Class / Patent application number | Description | Number of patent applications / Date published |
710114000 | Static bus prioritization | 13 |
20080270657 | Management of Transfer of Commands - An optical storage device that includes a memory and a controller. The memory includes a command queue to store advanced technology attachment (ATA) commands sent by a host device. The controller executes the commands, in which at least a subset of the commands are executed in a sequence that is different from a sequence in which the commands are sent by the host device. | 10-30-2008 |
20090187691 | Method for operation of a bus system - The disclosure relates to a method for operating a bus system, in which a plurality of subscribers communicate with one another over the same bus line and all subscribers are assigned a subscriber address from a limited address set. To avoid address conflicts, it is suggested that by each subscriber newly added to an existing bus system, the bus traffic will be monitored before the first send access to the bus with the current subscriber address, in order to form a list of already used subscriber addresses. The subscriber then assigns itself an address from the as yet unused address space according to a predefinable schema. | 07-23-2009 |
20090287869 | Bus Arbiter, Bus Device and System - A bus arbiter includes an arbitration stop determining unit and a transaction arbitrating unit. The arbitration stop determining unit generates an arbitration stop signal based upon transaction grouping request signals which indicate whether successive transactions are requested. The transaction arbitrating unit selectively performs an arbitration operation based upon the arbitration stop signal. | 11-19-2009 |
20100146178 | NEGATION-BASED FIXED-PRIORITY ARBITER - A device includes an M-bit input request for service bus, a NEGATE component that may perform a negation operation on the M-bit input bus, an AND component that may perform a Boolean AND operation on the M-bit input signal and the negated input, and an M-bit 1-HOT grant output bus that indicates which request for service is being granted. | 06-10-2010 |
20100318706 | BUS ARBITRATION CIRCUIT AND BUS ARBITRATION METHOD - Provided is a bus arbitration circuit including: a fixed priority determination circuit that grants a bus use right to an access request from a higher priority bus master among access requests from a plurality of bus masters; and a determination adjustment circuit that determines whether or not to assert the access request from the plurality of bus masters to the fixed priority determination circuit. The determination adjustment circuit masks an access request from a bus master which is granted the bus use right, for a given period of time, when the access request from the bus master which is granted the bus use right and an access request from a bus master which is not granted the bus use right compete with each other. | 12-16-2010 |
20110258354 | Methods of Bus Arbitration for Low Power Memory Access - Systems and method for arbitrating requests to a shared memory system for reducing power consumption of memory accesses, comprises determining power modes associated with memory channels of the shared memory system, assigning priorities to the requests based at least in part on the power modes, and scheduling the requests based on the assigned priorities. Latency characteristics and page hit rate are also considered for assigning the priorities. | 10-20-2011 |
20110320660 | INFORMATION PROCESSING DEVICE - To improve processing performance of an information processing device as a whole by controlling priority in units of processes. | 12-29-2011 |
20120117288 | Arbitration circuit and control method thereof - An arbitration circuit includes a use frequency setting block that sets a setting value for limiting a bus use frequency for each of a plurality of masters. A use request management section holds the bus use request from each of the plurality of masters and selects a use request that has not been granted from among the held use requests. A use frequency limitation block limits the use request selected by the use request management section such that the bus use frequency of each of the plurality of masters will not exceed its setting value. A use request grant block grants a use request of any one of the plurality of masters from among use requests not limited by the use frequency limitation block received from the plurality of masters. | 05-10-2012 |
20150039796 | ACQUIRING RESOURCES FROM LOW PRIORITY CONNECTION REQUESTS IN SAS - Systems and methods herein provide for managing connection requests through a Serial Attached Small Computer System Interface (SAS) expander. In one embodiment, the expander receives a low priority open address frame (OAF) that includes a source address and a destination address. The expander also receives a high priority OAF that includes a source address and a destination address. The high priority OAF requires at least a portion of a partial path acquired by the low priority OAF for which connection request arbitration is in progress. The expander determines whether the high OAF source address matches the low OAF destination address, and in response to a determination that the high OAF source address is different than the low OAF destination address, acquires pathway resources from the low priority OAF and forwards the high priority OAF in accordance with its destination address. | 02-05-2015 |
20160378694 | MANAGEMENT OF ALLOCATION FOR ALIAS DEVICES - Embodiments of the present invention provide systems, methods, and computer program products for managing computing devices to handle an input/output (I/O) request. In one embodiment, the I/O request may eligible for performance throttling based, at least in part, on the associated importance level for performing the received I/O request and one or more characteristics of the received I/O request. Embodiments of the present invention provide systems, methods, and computer program products for throttling the I/O request and transmitting the I/O request to a storage controller. | 12-29-2016 |
710115000 | Physical position bus prioritization | 3 |
20100023665 | MULTIPROCESSOR SYSTEM, ITS CONTROL METHOD, AND INFORMATION RECORDING MEDIUM - To provide a multiprocessor system in which data transmission efficiency is unlikely to be affected if a damaged processor should exist among a plurality of processors. The multiprocessor system has a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus for relaying data transmission among the respective processing modules, and specifies at least one damaged processor; selects as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus; and restricts data transmission by the communication restricted processor via the bus. | 01-28-2010 |
20100180057 | Data Structure For Implementing Priority Queues - Particular embodiments of the present invention are related to implementing a priority queue. | 07-15-2010 |
20110252170 | HIERARCHICAL TO PHYSICAL BUS TRANSLATION - In an embodiment, a translation of a hierarchical bus number to a physical bus number and a bridge identifier of a bridge are written to a north chip. A request is received that comprises an identifier of a destination. A determination is made that the identifier comprises the hierarchical bus number. In response to the determination, the identifier of the destination is replaced in the request with the physical bus number and the bridge identifier. The request is sent to the bridge identified by the bridge identifier. A south chip comprises the bridge, and the south chip is connected to the north chip via a point-to-point serial link. The physical bus number identifies a bus that connects the bridge to a device. The request comprises a configuration write request that requests a write of data to the device. | 10-13-2011 |