Entries |
Document | Title | Date |
20080235422 | DOWNSTREAM CYCLE-AWARE DYNAMIC INTERCONNECT ISOLATION - A device, method, and system are disclosed. In one embodiment, the device includes a data reception unit that receives data from an interconnect, and a data suppression unit that receives a target address from the interconnect, determines if the target address is local to the device, and, if the target address is not local to the device, the data suppression unit suppresses the interconnect from switching at the interconnect entry point into the data reception unit. | 09-25-2008 |
20080235423 | Data processing apparatus and method for arbitrating between messages routed over a communication channel - A data processing apparatus and method are provided for arbitrating between messages routed over a communication channel. The data processing apparatus has a plurality of processing elements, each processing element executing a process requiring messages to be issued to recipient elements, and a communication channel shared amongst those processing elements over which the messages are routed. Arbitration circuitry performs an arbitration process to arbitrate between multiple messages routed over the communication channel. Each processing element issues progress data for the process executing on that processing element, the progress data indicating latency implications for the process. Arbitration control circuitry is then responsive to the progress data from each processing element to perform a priority ordering process taking into account the latency implications of each process as indicated by the progress data in order to generate priority ordering data. That priority ordering data is then output to the arbitration circuitry in order to control the arbitration process. This enables quality of service to be determined and allocated automatically between the various processes, without the need to know the requirements of the processes in advance, and the prioritisation mechanism adapts dynamically to changes in communication between the processes. | 09-25-2008 |
20080244133 | Data processing apparatus and method for arbitrating access to a shared resource - A data processing apparatus and method are providing for arbitrating access to a shared resource. The data processing apparatus has a plurality of logic elements sharing access to the shared resource, and arbitration circuitry which is responsive to requests by one or more of the logic elements for access to the shared resource to perform a priority determination operation to select one of the requests as a winning request. The arbitration circuitry applies an arbitration policy to associate priorities with each logic element, the arbitration policy comprising multiple priority groups, each priority group having a different priority and containing at least one of the logic elements. Within each priority group, the arbitration circuitry applies a priority ordering operation to attribute relative priorities to the logic elements within that priority group. Responsive to a predetermined event, the arbitration circuitry re-applies the priority ordering operation within at least one priority group prior to a subsequent performance of the priority determination operation. Such an approach has been found to provide a particularly flexible mechanism for performing arbitration, allowing a wide variety of different arbitration schemes to be implemented using the same arbitration hardware. | 10-02-2008 |
20080288689 | Opportunistic granting arbitration scheme for fixed priority grant counter based arbiter - In one embodiment, an arbiter may provide for opportunistic granting of one or more grants to a requestor that has no available fixed grants remaining in a given arbitration round. In one embodiment, a method may detect that a target resource to be accessed by a requestor with a valid grant count is unavailable during an arbitration round, and opportunistically grant an access grant to another requestor to access a different target resource for a slot of the round. Other embodiments are described and claimed. | 11-20-2008 |
20080288690 | Image processing controller and image forming apparatus - An image processing controller performs transmission and processing of image data by connecting an engine and a CPU connected via a chipset. A first controller controls communication with the chipset via a first PCI-Express I/F. A second controller controls communication with the engine when it is connected via a second PCI-Express I/F. A third controller controls communication with the engine when it is connected via a PCI I/F. The first controller receives, on behalf of the engine, an access from the CPU to the engine and inhibits a reference by the CPU to a resource connected to the image processing controller. | 11-20-2008 |
20080294824 | DEVICE INFORMATION MANAGEMENT SYSTEMS AND METHODS - Device information management systems and methods for use in a computer system are provided. The system comprises an application device, a south bridge chip, a memory and an arbitrator. The application device and the south bridge chip couple to the arbitrator, and couple to the memory via the arbitrator. The arbitrator receives an access request from a specific device among the application devices and the south bridge chip. When data transmission between the arbitrator and the memory is idle, the arbitrator transmits a grant signal to the specific device. After receiving the grant signal, the specific device begins access from the memory. | 11-27-2008 |
20080320192 | FRONT SIDE BUS PERFORMANCE USING AN EARLY DEFER-REPLY MECHANISM - Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving the performance of a front side bus using an early defer-reply mechanism. In some embodiments, an integrated circuit receives a memory read request and accesses memory to obtain read data responsive to receiving the memory read request. The integrated circuit may initiate a defer-reply transaction corresponding to the memory read request N front side bus (FSB) clocks prior to receiving the read data from the memory. | 12-25-2008 |
20090006690 | PROVIDING UNIVERSAL SERIAL BUS DEVICE VIRTUALIZATION WITH A SCHEDULE MERGE FROM MULTIPLE VIRTUAL MACHINES - An apparatus, system, and method are disclosed. In one embodiment, the apparatus includes a virtualization engine on a computer platform. The virtualization engine can intercept multiple data transfer schedules from multiple virtual machines fetched from a memory by a physical Universal Serial Bus (USB) host controller on the computer platform. The virtualization engine also can merge the multiple fetched data transfer schedules into a merged data transfer schedule. The virtualization engine also can send the merged data transfer schedule to the physical USB host controller. | 01-01-2009 |
20090006691 | Bus width arbitration - There is provided a method and apparatus for bus arbitration. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device. | 01-01-2009 |
20090031066 | CAPACITY PLANNING BY TRANSACTION TYPE - Capacity planning is performed based on expected transaction load and the resource utilization for each expected transaction. Resource usage is determined for one or more transactions or URLs based on transaction specific and non-transaction specific resource usage. Once the resource usage for each transaction is known, the expected resource usage may be determined for an expected quantity of each transaction. The actual resources needed to meet the expected resource usage are then determined. Resources may include hardware or software, such as a central processing unit, memory, hard disk bandwidth, network bandwidth, and other computing system components. The expected resource usage for a transaction may based on the usage directly related to the transaction and usage not directly related to the transaction but part of a process associated with the performed transactions. | 01-29-2009 |
20090031067 | Spider Web Interconnect Topology Utilizing Multiple Port Connection - A data communications apparatus includes a central device and a plurality of communication devices. The central device includes a plurality of central port pairs, in which each central port pair includes an input port and an output port. The plurality of communication devices is arranged in a spoke and ring configuration, in which each communication device is part of a communication spoke. Each communication spoke is in communication with a different central port pair. Each communication device is also a part of a communication ring, so that each communication device in a selected communication ring belongs to a different communication spoke. | 01-29-2009 |
20090063740 | METHOD AND APPARATUS FOR ARBITRATION IN A WIRELESS DEVICE - A method and apparatus for traffic arbitration in a system are provided. In the system, a first module operating in a first protocol and a second module operating in a second protocol share one communication channel. An arbitration circuit schedules medium accesses thereof, in which a quota table maintains a utilization value updated in accordance with the amount of time slots consumed by a particular traffic type, and a time counter periodically resets the utilization value to a default value. When the arbitration circuit receives a request for medium access of the particular traffic type, the arbitration circuit grants the request according to the utilization value, such that the first module or the second module are not activated at the same time. | 03-05-2009 |
20090106465 | Method of Piggybacking Multiple Data Tenures on a Single Data Bus Grant to Achieve Higher Bus Utilization - An improved method, device and data processing system are presented. In one embodiment, the method includes a source device sending a request for a bus grant to deliver data to a data bus connecting a source device and a destination device. The device receives the bus grant and logic within the device determines whether the bandwidth of the data bus allocated to the bus grant will be filled by the data. If the bandwidth of the data bus allocated to the bus grant will not be filled by the data, the device appends additional data to the first data and delivers the combined data to the data bus during the bus grant for the first data. When the bandwidth of the data bus allocated to the bus grant will be filled by the first data, the device delivers only the first data to the data bus during the bus grant. | 04-23-2009 |
20090119432 | Starvation Prevention Scheme for a Fixed Priority PCE-Express Arbiter with Grant Counters using Arbitration Pools - Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams. When the resource buffer for the low priority stream becomes available and a corresponding request is arbitrated in the high priority arbitration pool, a grant for the request can be immediately made since grant counts for the stream already exist. | 05-07-2009 |
20090319708 | ELECTRONIC SYSTEM AND RELATED METHOD WITH TIME-SHARING BUS - An electronic system with time-sharing bus includes a controller, a storage element, a first electronic element, and a shared bus. The controller receives a command to generate a set of enable signals and a set of operation signals. The storage element has a first set of input ends coupled to the controller for receiving a first enable signal of the set of enable signals. The first electronic element has a first input end coupled to the controller for receiving a second enable signal of the set of enable signals. The shared bus is coupled between the controller and the storage element, and is coupled between the controller and the first electronic element. The shared bus provides the set of operation signals to the storage element while the first electronic element is disabled and provides the set of operation signals to the first electronic element while the storage element is disabled. | 12-24-2009 |
20100011140 | Ethernet Controller Using Same Host Bus Timing for All Data Object Access - An Ethernet controller has a host interface for coupling to a host processor and a physical layer transceiver for coupling to a data network and includes multiple data objects having different access times where the data objects communicate with the host interface over an internal data bus. The Ethernet controller includes a data object interface module coupled between the host interface and the internal data bus where the data object interface module has a first access time for handling data requests for the data objects received on the host interface from the host processor, and a control logic circuit coupled to control the operation of the data object interface module. Data requests from the host processor for accessing data stored in the multiple data objects are carried out through the data object interface module using the first access time, regardless of the different access times of the multiple data objects. | 01-14-2010 |
20100011141 | SIGNAL RELAY DEVICE AND METHOD FOR ACCESSING AN EXTERNAL MEMORY VIA THE SIGNAL RELAY DEVICE - A signal relay device for accessing an external memory is provided. The signal relay device includes a bus arbiter and a burst access engine. The bus arbiter performs bus arbitration among main masters on a bus. The burst access engine exchanges signals with the bus arbiter and an external memory controller. The signal relay device facilitates data transfer of large groups of read/write commands between the main masters and the external memory controller. | 01-14-2010 |
20100036985 | SYSTEM ARCHITECTURE FOR MOTOR VEHICLES WITH ENABLE INTERFACES FOR THE START-UP THEREOF - A system architecture for a motor vehicle has a control unit for identifying an authorized user and a gateway control unit for enabling at least one further data bus, and control units arranged on the at least one further data bus, following the identification of an authorized user. An external diagnostic interface contains a further identification unit and it is enabled and the data in the at least one further data bus system are thus accessible only after an authorized diagnostic tester has been identified. | 02-11-2010 |
20100057962 | ARBITRATION DEVICE, ARBITRATION METHOD, AND ELECTRONIC APPARATUS - An arbitration device and method including validating a second signal after a first signal is selected for a given number of times when the first signal and the second signal conflict, where the first signal has a first priority based on a priority order corresponding to a plurality of processes and the second signal has a second priority lower than the first priority. | 03-04-2010 |
20100082865 | Access Grants - Provided are, among other things, systems, methods, apparatuses and techniques for storing access grants. In one implementation, a blinding factor and access information for accessing a restricted object are obtained; blinded access information is generated for the restricted object based on the access information and the blinding factor; and an anchor node is stored into a data store, with the anchor node being accessible by submission of an identifier, the anchor node at least one of containing or referring to sufficient information to obtain access to the blinding factor and the blinded access information, and the identifier for the anchor node being independent of the blinding factor. | 04-01-2010 |
20100138578 | MEMORY ACCESS CONTROLLER, SYSTEM, AND METHOD - A memory access controller including a command analysis unit to receive write access request and command data and to analyze access to a memory, a command execution unit to output command and data control signals to the memory based on write data, and the analysis result, a mode setting unit to switch between a first operation mode in which a write access request is issued when both the command data and the corresponding write data are available, and a second operation mode in which a write access request is issued when the command data is available independently of availability of the write data corresponding to the command data, and a timing arbitration unit provided for each bus master to output the write access request and command data to the command analysis unit and output the write data to the command execution unit in accordance with the mode setting unit. | 06-03-2010 |
20100250808 | BUS ARBITRATION SYSTEM, A METHOD OF CONNECTING DEVICES OF AN IC EMPLOYING A BUS SYSTEM AND AN IC - A bus arbitration system, a method of connecting a master device and a peripheral over a bus system of an IC and an IC is provided. In one embodiment, the bus arbitration system includes: (1) a bus system configured to couple master devices to peripherals, port arbiters coupled to the bus system, wherein each of the port arbiters uniquely corresponds to one of the peripherals and is configured to manage access to the uniquely corresponding peripheral and a request splitter configured to receive connection requests from the master devices for the peripherals and direct the connection requests to a specific one of the port arbiters according to a port identifier associated with each of the connection requests. | 09-30-2010 |
20110016245 | Method and System for Addressing a Plurality of Ethernet Controllers Integrated into a Single Chip Which Utilizes a Single Bus Interface - A method for processing network data is disclosed and may include receiving data via a single bus interface to which each of a plurality of Ethernet controllers are coupled, where the Ethernet controllers are integrated within a single chip. A particular one of the integrated Ethernet controllers may be identified based on information within the received data. The particular one of the integrated Ethernet controllers may be granted access to a shared resource within the single chip. The access to the shared resource may be granted using at least one semaphore register within the shared resource. The particular one of the integrated Ethernet controllers may be granted access to the single bus interface. The information may include a bus identifier, a bus device identifier and/or a bus function identifier. The shared resource may include a nonvolatile memory (NVM). | 01-20-2011 |
20110099312 | CIRCUIT AND METHOD FOR PIPE ARBITRATION - Provided is an arbitration circuit included in a host controller that can be connected to a plurality of external devices via a plurality of pipe control circuits. The arbitration circuit includes an available state information storage unit that stores available state information. The available state information indicates an available state of the plurality of pipe control circuits and is updated by the pipe control circuit by a unit of data transfer of a predetermined communication size. The arbitration circuit further includes an arbitration unit that refers to the available state information storage unit, selects the arbitrary pipe control circuit from the available pipe control circuit, and allocates the selected pipe control circuit to the external device, while updating the available state information storage unit. | 04-28-2011 |
20110113172 | UTILIZATION-ENHANCED SHARED BUS SYSTEM AND BUS ARBITRATION METHOD - A utilization-enhanced shared bus system and bus arbitration method are disclosed. An arbiter arbitrates among multiple masters according to active requests sent from the masters. The arbiter sends a passive request to one of the masters in an idle period of the shared bus according to respective status of the masters. Accordingly, the master that receives the passive request may access a shared resource in the idle period. | 05-12-2011 |
20110125948 | MULTI-PROCESSOR SYSTEM AND CONTROLLING METHOD THEREOF - In order to control sub-processors in parallel without losing extensibility, an execution control circuit ( | 05-26-2011 |
20110138091 | PRE-MEMORY RESOURCE CONTENTION RESOLUTION - Techniques are disclosed relating to resource contention resolution in a pre-memory environment. Prior to system memory being accessible, a resource control processing element controls access to a hardware resource by a plurality of processing elements by granting received requests from the processing elements for access to the resource. The resource control processing element may prioritize requests based on a determined amount of utilization of the hardware resource by individual ones of the processing elements. In one embodiment, processing elements request for information from a bus controller (e.g., an SMBus controller) that is usable to initialize system memory. The resource control processing element may respond to the requests by retrieving the requested information from the controller and providing that information to the processing element or by retrieving the requested information from a cache and providing that information to the processing element. | 06-09-2011 |
20110145456 | ARBITRATION DEVICE, ARBITRATION METHOD, IMAGE PROCESSING DEVICE, AND IMAGE FORMING SYSTEM - An arbitration device includes an arbitration section, a counter, and a changing section. While write request signals and read request signals for a transfer path, are inputted from request sources, the arbitration section arbitrates an order that the write and read request signals use the transfer path, and when arbitration is settled, outputs use permission signals to the request sources. The changing section changes a time from outputting of the write request signals until inputting of the write request signals to the arbitration section, and/or a time from outputting of the use permission signals for the write request signals until inputting of the use permission signals to the request sources. | 06-16-2011 |
20110153892 | ACCESS ARBITRATION APPARATUS, INTEGRATED CIRCUIT DEVICE, ELECTRONIC APPARATUS, ACCESS ARBITRATION METHOD, AND PROGRAM - An access arbitration apparatus includes: a group setting information storage section; and an access control section, wherein the group setting information storage section stores group setting information that specifies which of the following groups each of a plurality of masters belongs to, a first group or a second group whose priority is lower than that of the first group, and the access control section identifies an access request source, based on an access request signal from each of the plurality of masters, and repeatedly performs a first group process and a second group process in an alternate manner, the first group process being a process of granting access rights valid for predetermined time to the entire first access request source set, the second group process being a process of granting access rights valid for predetermined time to part of the second access request source set. | 06-23-2011 |
20110185094 | DATA TRANSFER CONTROL DEVICE AND DATA TRANSFER CONTROL METHOD - A data transfer control device that selects one of a plurality of DMA channels and transfers data to or from memory includes a request holding section configured to hold a certain number of data transfer requests of the plurality of DMA channels and a request rearranging section configured to select and rearrange the data transfer requests that are held in a basic transfer order so that the data transfer requests of each of the plurality of DMA channels are successively outputted for a number of successive transfers set in advance. | 07-28-2011 |
20120005386 | METHOD, APPARATUS AND SYSTEM FOR MAINTAINING TRANSACTION COHERECY IN A MULTIPLE DATA BUS PLATFORM - Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests—e.g. between those requestors providing the access requests—the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus. | 01-05-2012 |
20120059962 | PROVIDING A FINE-GRAINED ARBITRATION SYSTEM - In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed. | 03-08-2012 |
20120089759 | Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s) - Devices, systems, methods, and computer-readable mediums for arbitrating stream transactions based on information related to the stream transactions are disclosed. A stream transaction is a superset of burst access types to facilitate efficient bulk transfers of data. In one embodiment, an arbiter is provided that arbitrates bus transactions between a plurality of devices coupled to a bus competing for resources accessible through the bus. To efficiently arbitrate stream transactions requested on the bus, the arbiter is configured to use information related to the stream transactions to provide a view of future bus traffic on the bus. The arbiter is configured to use this stream transaction information to apply bus arbitration policies for arbitrating stream transactions. In this example, the bus arbitration policy can be adjusted for stream transactions based on the stream transaction information, if necessary, for the arbiter to attempt to meet a parameter(s) for completing the stream transactions. | 04-12-2012 |
20120151109 | Method and apparatus to reduce serial bus transmission power - In some embodiments, a serial bus interface circuit includes at least two serial ports, a memory to store a relationship between serial bus addresses and the at least two serial ports, and a controller to control access to the at least two serial ports. The controller may be configured to receive an access request for a serial bus address, determine a first port of the at least two serial ports corresponding to the serial bus address using the relationships stored in the memory, and disable a second port of the at least two serial ports. Other embodiments are disclosed and claimed. | 06-14-2012 |
20120159027 | Techniques for accessing memory, system and bus arbitration - Techniques for accessing a memory are described. According to one embodiment, a method comprises: comparing priorities of N function modules accessing the memory to obtain location information of the function module with the highest priority; switching a bus of the function modules accessing the memory to the function module with the highest priority by performing logic operation on the location information and bus information of each function module. | 06-21-2012 |
20120179850 | METHOD AND APPARATUS FOR ARBITRATION ON A DATA BUS - A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means. | 07-12-2012 |
20120191891 | MULTI-MASTER BUS ARBITRATION AND RESOURCE CONTROL - The present invention discloses an arbitration mechanism for controlling access of a plurality of nodes external to a shared resource, to which accesses by the number of nodes must he restricted, is applicable to any shared source in a computer or computer-controlled system. The present design delivers the following advantageous features. It provides localized arbitration to obtain resource access and localized self-management of resource mastery; eliminates resource seizure locally; it allows equal access to the share resource, encapsulate all four above features with the same circuit/protocol. | 07-26-2012 |
20120311212 | AVOIDING NON-POSTED REQUEST DEADLOCKS IN DEVICES - Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations. | 12-06-2012 |
20120311213 | AVOIDING NON-POSTED REQUEST DEADLOCKS IN DEVICES - Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations. | 12-06-2012 |
20130042038 | NON-BLOCKING PROCESSOR BUS BRIDGE FOR NETWORK PROCESSORS OR THE LIKE - Described embodiments provide a system having a bridge for connecting two different processor buses. The bridge receives a request from a first bus, the request having an identification field having a value. The request is then entered into one of a plurality of buffers having requests therein with the same identification field values. Which buffer receives the request may be based on a variety of techniques, such as random, least recently used, most full, prioritized, or sequential. Next, the buffered request is transmitted over a second bus. A response to the request is eventually received from the second bus, the response is transmitted over the first bus, and the request is then removed from the buffer. By entering the received request to the buffer with request with the same identification value, there is a reduced possibility of head-of-line request blocking when compared to a single buffer implementation. | 02-14-2013 |
20130067131 | System and Method of Increasing Data Processing on a Diagnostic Tool - A method of processing J1850 requests using a scan tool having multiple processor systems is provided. The scan tool includes a first processor that processes data according to scan tool functions to assist with diagnosing and repairing a vehicle. A second processor receives data transmitted to the first processor and stores the data in a buffer. The second processor determines whether the data is complete to enable the first processor to make a determination regarding the data. | 03-14-2013 |
20130073763 | MEMORY ARBITRATION CIRCUITRY - An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed. | 03-21-2013 |
20130086288 | Supporting Multiple Channels Of A Single Interface - In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed. | 04-04-2013 |
20130145064 | Scalable Data Storage Architecture And Methods Of Eliminating I/O Traffic Bottlenecks - A Storage Area Network (SAN) system has host computers, front-end SAN controllers (FE_SAN) connected via a bus or network interconnect to back-end SAN controllers (BE_SAN), and physical disk drives connected via network interconnect to the BE_SANs to provide distributed high performance centrally managed storage. Described are hardware and software architectural solutions designed to eliminate I/O traffic bottlenecks, improve scalability, and reduce the overall cost of SAN systems. In an embodiment, the BE_SAN has firmware to recognize when, in order to support a multidisc volume, such as a RAID volume, it is configured to support, it requires access to a physical disk attached to a second BE_SAN; when such a reference is recognized it passes assess commands to the second BE_SAN. Further, the BE_SAN has firmware to make use of the physical disk attached to the second BE_SAN as a hot-spare for RAID operations. | 06-06-2013 |
20130179613 | NETWORK ON CHIP (NOC) WITH QOS FEATURES - Quality-of-Service (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC). | 07-11-2013 |
20130219095 | CIRCUIT AND METHOD FOR PIPE ARBITRATION USING AVAILABLE STATE INFORMATION AND ARBITRATION - Provided is an arbitration circuit included in a host controller that can be connected to a plurality of external devices via a plurality of pipe control circuits. The arbitration circuit includes an available state information storage unit that stores available state information. The available state information indicates an available state of the plurality of pipe control circuits and is updated by the pipe control circuit by a unit of data transfer of a predetermined communication size. The arbitration circuit further includes an arbitration unit that refers to the available state information storage unit, selects the arbitrary pipe control circuit from the available pipe control circuit, and allocates the selected pipe control circuit to the external device, while updating the available state information storage unit. | 08-22-2013 |
20130227186 | TRANSACTION ROUTING DEVICE AND METHOD FOR ROUTING TRANSACTIONS IN AN INTEGRATED CIRCUIT - A transaction routing device (e.g. an interconnect) for routing transactions in an integrated circuit includes arbitration circuitry for performing arbitration between a plurality of candidate transactions using attribute values associated with the candidate transactions. Candidate transactions are selected for routing to a destination device in dependence on the arbitration. In a cycle in which a new candidate transaction is received, the arbitration is performed using a default attribute value as the attribute value for the new transaction. Meanwhile, the actual attribute value is stored to an attribute storage unit. In a following processing cycle, if the new candidate transaction has not yet been selected for muting, then the arbitration is performed using the actual attribute value stored in the storage unit. | 08-29-2013 |
20130246677 | OPERATION ANALYSIS APPARATUS, OPERATION ANALYSIS METHOD, AND COMPUTER PROGRAM PRODUCT - An image forming apparatus includes a storage unit, an arbitration unit that controls access to the storage unit, and a plurality of image processing units that are connected to the arbitration unit and access the storage unit via the arbitration unit. And, an operation analysis apparatus includes: an access monitoring unit monitoring which of the image processing units the arbitration unit permits access to the storage unit; a log generation unit generating, in response to the fact that the access monitoring unit detects that the image processing unit with access permitted has been switched, information on the image processing unit with access permitted as a log; a log storage unit storing therein the generated log; and a remaining capacity determination unit determining whether the storage capacity of the log storage unit after storing the log has become equal to or smaller than a particular capacity. | 09-19-2013 |
20130262725 | DATA PROCESSING DEVICE AND METHOD FOR CONTROLLING DATA PROCESSING DEVICE - A data processing device includes a plurality of entries and a plurality of output ports, allocates the plurality of entries to a plurality of arbitration groups corresponding to the plurality of output ports respectively when a clock is inputted thereto, arbitrates the output ports for each of the allocated arbitration groups when data held in the entry is outputted from the output port, and outputs data held in the entry according to an arbitration result. | 10-03-2013 |
20130318268 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A distributed server system for handling multiple networked applications is disclosed. Systems can include at least one main processor; a plurality of offload processors connected to a memory bus; an arbiter connected to each of the plurality of offload processors, the arbiter configured to schedule resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter. | 11-28-2013 |
20130318269 | PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS - Methods of processing structured data are disclosed that can include providing a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules further providing an in-memory database; and connecting a central processing unit (CPU) in the first server to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules. | 11-28-2013 |
20140032803 | PREDICTION OF ELECTRONIC COMPONENT BEHAVIOR IN BUS-BASED SYSTEMS - Systems and methods for predicting electronic component behavior in bus-based systems are described. In some embodiments, a method may include identifying a first bus access request pending in a request queue, the first bus access request associated with a first master component operably coupled to a bus. The method may also include calculating a first wait time corresponding to the first bus access request, the first wait time indicative of a length of time after which the first master component is expected to be granted access to the bus. The method may further include, in response to the first wait time meeting a threshold value, issuing a command to the first master component. In some embodiments, various techniques disclosed herein may be implemented, for example, in a computer system, an integrated circuit, or the like. | 01-30-2014 |
20140129750 | BUS CONTROLLER, BUS CONTROL SYSTEM AND NETWORK INTERFACE - In a bus control system for a semiconductor circuit, data is transmitted between first and second nodes over a network of buses. The bus controller is connected directly to the first node and includes: a route load detector which detects loads on routes that form at least one of a group of forward routes leading from the first to the second node and a group of backward routes leading from the second to the first node; a candidate route extraction circuit which extracts a candidate route from the group of routes so that loads on the routes that form the group become uniform; a route determining circuit which determines the route to transmit the data based on the candidate route and a predetermined selection rule; and a data communication circuit which transmits the data between the first and second nodes based on header information including route information indicating the route. | 05-08-2014 |
20140136743 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device includes a master arbitrating unit assigning information to a command sent from a selected bus master, a data buffer, a write command buffer, a read command buffer, a write data reception completion notification control unit issuing a signal indicating that storing of write data is complete, and a command order determining unit selecting whichever of a first command and a second command coming earlier in an order identified with the information, the first information being information for which the completion is indicated by the signal and a second command being a read command. | 05-15-2014 |
20140149620 | Providing A Fine-Grained Arbitration System - In one embodiment, the present invention includes a method for selecting a requester to service during an arbitration round, and updating counters associated with the selected requester including a command unit counter and a data unit counter, determining if the counters are in compliance with corresponding threshold values, and if so granting a transaction for the selected requester, and otherwise denying the transaction. Other embodiments are described and claimed. | 05-29-2014 |
20140164660 | DEVICE PRESENCE DETECTION USING A SINGLE CHANNEL OF A BUS - The presence of devices attached to a bus are detected by a controller of a bus transmitting a signal on a channel of the bus, to cause each device to hold the channel to a first logical state for a duration of time that is unique to each device. The device that holds the channel to the first logical state for the longest duration of time is detected. Detected devices remain idle while undetected devices repeat holding the channel to the first logical state for the duration of time, until detected. All devices are detected when the channel returns to a second logical state. | 06-12-2014 |
20140173148 | APPROACH FOR WORKING AROUND STARVATION PROBLEMS IN A DATAPATH - A starvation control engine operable to monitor data transactions within a computer system potentially prevents or corrects starvation issues. The starvation control engine is programmed to generate one or more bubbles in a data path based on one or more trigger events. The trigger events or the criteria underlying the trigger events may be programmed or changed by at least one of a user or the starvation control engine. The starvation control engine determines when, for how long, and how often to generate the one or more bubbles based on the type of event. | 06-19-2014 |
20140258577 | Wire Level Virtualization Over PCI-Express - A network element (NE) comprising a processor configured to receive a resource request via a Peripheral Component Interconnect (PCI) Express (PCI-e) network from a first device, wherein the first device is external to the NE, and query an access control list to determine whether the first device has permission to access a resource. The disclosure also includes an apparatus comprising a memory comprising instructions, and a processor configured to execute the instructions by allocating a resource of a shared device for use by an external device over a PCI-e network by updating a resource allocation table. | 09-11-2014 |
20140258578 | Supporting Multiple Channels Of A Single Interface - In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed. | 09-11-2014 |
20140258579 | MULTIPLE PATH LOAD DISTRIBUTION FOR HOST COMMUNICATION WITH A TAPE STORAGE DEVICE - A multiple port host communicates with multiple tape drives by requesting information associated with a particular tape. Information of availability status of a plurality of host ports is provided. Traversing all host initiator ports finds a host port with no or the least traffic load for a tape reservation request. A host port's traffic load calculation uses instant and the updated historical traffic as primary and secondary factors. Every host port's traffic load is updated for every read/write command, and is used for path selection of reservation requests. The instant load is relatively sensitive but will be zero under light load. The historical load is aware of the light load though it is not sensitive enough when a burst I/O occurs. With the traffic load calculated from instant and historical loads, the distribution of tape tasks is spread evenly among host initiator ports under light load and burst I/O scenarios. | 09-11-2014 |
20140281084 | LOCAL BYPASS FOR IN MEMORY COMPUTING - Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network. | 09-18-2014 |
20150052272 | INFERRING PHYSICAL LAYER CONNECTION STATUS OF GENERIC CABLES FROM PLANNED SINGLE-END CONNECTION EVENTS - A work order is generated. The work order comprises a first work order step specifying that a port of a first network element is to be connected to a port of a second network element using a cable. The first and second network elements are configured to detect when connections are made at the specified ports of the first network element and the second network element. A management system is configured to update information it maintains to indicate that there is a connection between the specified port of the first network element and the specified port of the second network element if connections made at the specified ports of the first and second network elements are detected during a period in which the first work order step of the first work order is expected to be performed. A similar technique can be used for disconnecting a cable. | 02-19-2015 |
20150149675 | MEMORY CONTROLLER, INFORMATION PROCESSING APPARATUS, AND METHOD OF CONTROLLING MEMORY CONTROLLER - A memory controller has a request holding unit holding a write request and a read request; a transmission unit transmitting any one of the write request and the read request to a memory through a transmission bus; a reception unit receiving read data corresponding to the read request through a reception bus; and a request arbitration unit performing: a first processing of transmitting the write request before the read request, when a first reception time is not later than a second reception time, and a second processing of transmitting the read request before the write request, when the first reception time is later than the second reception time. The first reception time is when reception of the read data is started when the write request is transmitted first, and the second reception time is when the reception of the read data is started when the read request is transmitted first. | 05-28-2015 |
20160019170 | SYSTEMS AND METHODS FOR PRESERVING THE ORDER OF DATA - A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more corresponding locations in a second memory, causes the first data to be processed by the one processing engine, and stores the processed first data in one of the locations in the second memory. The output processing unit receives second data, assigns an entry address corresponding to a location in an output memory to the second data, transfers the second data and the entry address to one of a group of second processing engines, causes the second data to be processed by the second processing engine, and stores the processed second data to the location in the output memory. | 01-21-2016 |
20160070669 | MULTI-PORT TRANSMITTER DEVICE FOR TRANSMITTING AT LEAST PARTLY REDUNDANT DATA, AN ASSOCIATED CONTROL SYSTEM, AN ASSOCIATED METHOD AND AN ASSOCIATED COMPUTER PROGRAM PRODUCT - A multi-port transmitter device for transmitting at least partly redundant data is described. The multi-port transmitter device comprises at least two transmitters comprising respective transmitter buffers. One transmitter is a master transmitter that issues a request to the processor to provide a data block when the transmitter buffer of the master transmitter has free space to store a data block. The processor is arranged to copy at least one data block of data stored in an external memory from the external memory to respective positions in a local buffer. The processor is arranged to, in accordance with a predefined sequence, sequentially initiate transfer of the data block from the respective position of the data block in the local buffer to the transmitter buffers of the at least two transmitters in response to a request from the master transmitter to provide a data block. | 03-10-2016 |
20160124890 | Multicore Bus Architecture With Wire Reduction and Physical Congestion Minimization Via Shared Transaction Channels - The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction. | 05-05-2016 |
20160132438 | PROCESSING DEVICE, PROCESSING METHOD, STORAGE MEDIUM, AND ELECTRONIC MUSICAL INSTRUMENT - A processing device includes: a plurality of processing units that perform processes in accordance with data items read from a memory; a bus that connects the memory to the plurality of processing units; and a traffic monitor that monitors traffic on the bus with respect to the plurality of processing units, and when the traffic for one of the processing units that has been assigned access rights to the memory exceeds or reaches a prescribed upper limit, outputs a signal to the one of the processing units so as to reduce or suspend the traffic for the one of the processing units. | 05-12-2016 |
20160132446 | NETWORK SUBSCRIBER - A network subscriber comprises a plurality of individual functional units, each individual functional unit comprising an application interface. The network subscriber further comprises a network subscriber comprises at least a shared functional unit, a first interface for establishing a physical connection and a second interface for establishing a further physical connection. | 05-12-2016 |
20160140059 | MULTIPLE MEMORY MANAGEMENT UNITS - In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier. | 05-19-2016 |
20160147683 | BUS CONTROLLER AND DATA TRANSMISSION METHOD THEREOF - A data transmission method includes: determining a sum of first service proportions and a sum of second service proportions according to a first transmission rate of at least one first device, a second transmission rate of at least one second device, and a maximum bandwidth of a host transmission interface; determining at least one first service proportion of the first device according to the sum of the first service proportions, and determining at least one second service proportion of the second device according to the sum of the second service proportions; and transmitting at least one package of first transmission data of the first device and at least one package of second transmission data of the second device to a host via the host transmission interface according to the first service proportion and the second service proportion. | 05-26-2016 |
20160162424 | MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK - Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network. | 06-09-2016 |
20160179723 | COMMUNICATION SYSTEM, MANAGEMENT APPARATUS, AND CONTROLLING APPARATUS | 06-23-2016 |
20160188501 | Reordering Responses in a High Performance On-Chip Network - Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core. | 06-30-2016 |
20160188513 | Intelligent Network Fabric to Connect Multiple Computer Nodes with One or More SR-IOV Devices - This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device. | 06-30-2016 |
20160378703 | MANAGEMENT OF ALLOCATION FOR ALIAS DEVICES - An input/output (I/O) request is received that indicates a priority for performing the received I/O request by a storage controller. If a base device is not available to handle the received I/O request, whether the received I/O request is eligible for performance throttling is determined. The received I/O request is transmitted to the storage controller indicating whether the received I/O request is eligible for performance throttling. An alias device is allocated to the base device based on the priority for performing the received I/O request. If the throttling information received from the storage controller for the previous I/O request indicates that a request type of the received I/O request is not being throttled, and it is determined that the received I/O request is a new request, then a control block is representing the base device is flagged, indicating that the received I/O request is eligible for performance throttling. | 12-29-2016 |
20190146940 | METHOD FOR THE EMERGENCY SHUTDOWN OF A BUS SYSTEM, AND BUS SYSTEM | 05-16-2019 |