Class / Patent application number | Description | Number of patent applications / Date published |
375375000 | With frequency detector and phase detector | 24 |
20090074125 | TIME-INTERLEAVED CLOCK-DATA RECOVERY AND METHOD THEREOF - A clock-data recovery (CDR) that employs a time-interleaved scheme is disclosed. the circuit comprises: a time-interleaved sampler/phase-detector circuit for receiving an input voltage signal and a plurality of clock signals and outputting N-bit data and N phase signals, wherein N is an integer greater than 1; a control circuit, coupled to the time-interleaved sampler/phase-detector circuit, for receiving the N phase signals and converting the N phase signals into a control signal; and a controlled oscillator, coupled to the control circuit, for generating the plurality of clock signals under the control of the control signal. The CDR is used to relax circuit speed requirement by time-interleaving phase detection by using a multi-phase lower speed circuit. | 03-19-2009 |
20090122939 | Wide range and dynamically reconfigurable clock data recovery architecture - Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly. | 05-14-2009 |
20090147901 | Auto Frequency Acquisition Maintenance in a Clock and Data Recovery Device - A system and method are provided for automatic frequency acquisition maintenance in a clock and data recovery (CDR) device. In an automatic frequency acquisition (AFA) mode, the method uses a phase detector (PHD) to acquire the phase of a non-synchronous input communication signal having an initial first frequency. In the event of a loss of lock/loss of signal (LOL/LOS) signal being asserted, a frequency ratio value is retrieved from memory. Using a phase-frequency detector (PFD), the reference signal, and the frequency ratio value, a synthesized signal is generated. In response to using the PFD to generate the synthesized signal and the LOL/LOS signal being deasserted, a rotational frequency detector (RFD) is used to generate a synthesized signal having a frequency equal to the frequency of the input communication signal. With the continued deassertion of the LOL/LOS signal, the PHD is enabled and the phase of the input signal is acquired. | 06-11-2009 |
20090207961 | PHASE SYNCHRONIZATION CIRCUIT AND RECEIVER HAVING THE SAME - A phase synchronization circuit includes a controlled oscillator configured to generate a first oscillation signal and a second oscillation signal that have a common frequency but different phase controlled by a combination of a first control signal and a second control signal, a digital phase frequency detector configured to detect a frequency difference and a first phase difference between a reference signal and the first oscillation signal to generate the first control signal, an analog phase detector configured to detect a second phase difference between the second oscillation signal and the reference signal to generate the second control signal, and a lock detection unit configured to detect a lock of the first oscillation signal with the reference signal in terms of frequency and phase, in order to set the analog phase detector in an active state. | 08-20-2009 |
20090257542 | Dual loop clock recovery circuit - A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator. | 10-15-2009 |
20100034333 | Methods And Apparatus For Improved Phase Linearity In A Multi-Phase Based Clock/Timing Recovery System - Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements. | 02-11-2010 |
20100040185 | METHODS AND APPARATUS FOR DIGITAL CLOCK RECOVERY - A method and apparatus for clock recovery in synchronous digital systems. The apparatus includes a phase frequency detector, a loop filter, a compressor, and a clock generator. The phase frequency detector generates a phase error signal based on a difference between an input clock signal and an output clock signal. The loop filter multiplies the phase error signal and filters the multiplied phase error signal. The compressor divides the loop filter output. Based on the compressor output, the clock generator generates an output clock signal is provided as a feedback signal to the phase error detector. The apparatus may also include a glitch cleaner for deglitching the input clock signal. | 02-18-2010 |
20100061499 | PHASE/FREQUENCY DETECTOR FOR A PHASE-LOCKED LOOP THAT SAMPLES ON BOTH RISING AND FALLING EDGES OF A REFERENCE SIGNAL - A circuit comprises a first phase detector, a second phase detector, and combinational logic. The first phase detector is for detecting a phase difference between a rising edge of a first clock signal and a rising edge of a second clock signal, and for providing a first difference signal indicating the phase difference. The second phase detector is for detecting a phase difference at a time of a falling edge of the first clock signal and a time of a falling edge of the second clock signal, and for providing a second difference signal indicating the phase difference. The combinational logic is coupled to receive the first difference signal and the second difference signal, and for preventing the second difference signal from being provided when the first difference signal is being provided. | 03-11-2010 |
20100310030 | PHASE LOCKED LOOP DEVICE AND METHOD THEREOF - A phase locked loop device includes a phase detector that measures a difference in phase between a reference clock signal and an output clock signal provided to a device module. The phase detector provides a pulse having a width indicative of the phase difference. If the phase difference exceeds one of a plurality of threshold values, in indicator can be asserted. Based on the indicator, a control module can take remedial action, such as providing a different clock signal to the device module or triggering an interrupt at a processor device. | 12-09-2010 |
20130136220 | Clock and Data Recovery Employing Piece-Wise Estimation on the Derivative of the Frequency - A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock. | 05-30-2013 |
20130251084 | LOW JITTER CLOCK RECOVERY CIRCUIT - A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter. | 09-26-2013 |
20130329843 | SEMICONDUCTOR DEVICE - A frequency tracking loop receives a result from a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal, and conducts a control to reduce a frequency deviation between the input data and the extracted clock signal. A phase interpolator adjusts a phase of the clock signal subjected to spread-spectrum frequency modulation on the basis result of the frequency deviation in the frequency tracking loop, and outputs the extracted clock signal. In the frequency tracking loop, the frequency deviation between the data signal and the clock signal is corrected to offset a variation of the frequency of the clock signal, on the basis of the frequency modulation information related to the clock signal subjected to the spread-spectrum frequency modulation which is input to the phase interpolator. The frequency of the clock signal seemingly follows the frequency of the data signal. | 12-12-2013 |
20140016731 | Millimeter-Wave Band Radio Transceiver Device - Provided is a millimeter wavelength range transceiver device which can improve phase noise characteristics and which can also independently calibrate each respective local oscillator of a transmission unit and a reception unit. This millimeter wavelength range transceiver device comprises a transmission unit ( | 01-16-2014 |
20140029708 | DYNAMIC OPTIMIZATION OF CARRIER RECOVERY PERFORMANCE FOR COMMUNICATION SYSTEMS - Apparatuses, systems, and methods are directed to maintaining optimal carrier tracking performance in view of operating conditions that prevail. Such configurations employ a phase lock loop that configured to generate an estimated phase error value, a variance module configured to calculate a phase noise variance based on the estimated phase error value, and a loop control bandwidth module that calculates a loop bandwidth value based on a detected lower phase noise variance, generates modified loop filter values in accordance with the calculated loop bandwidth value, and updates the phase lock loop with the modified loop filter values. During subsequent iterations, the modified loop filter values are incrementally adjusted along a particular direction until the phase noise variance increases at which point the modified loop filter values are incrementally adjusted in an opposite direction to converge on an optimal loop bandwidth value. | 01-30-2014 |
20140126678 | ALL DIGITAL BURST-MODE CLOCK AND DATA RECOVERY (CDR) - The present invention relates to a clock and data recovery (CDR) unit comprising of a bang-bang phase detector to receive data and a recovered clock from a phase selector multiplexer. The phase detector produces a late and an early comparison output. A block (digital filter) receives the late and early input and produces a multiplexer selector control signal. The phase selector multiplexer selects a clock phase as the recovered clock signal using multiplexer selector control signal. | 05-08-2014 |
20140177771 | CLOCK DATA RECOVERY CIRCUIT, DATA RECEPTION APPARATUS, AND DATA TRANSMISSION AND RECEPTION SYSTEM - A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator. | 06-26-2014 |
20140362962 | System and Method For Adaptive N-Phase Clock Generation For An N-Phase Receiver - An N-phase clock generation circuit includes an input clock signal comprising a first phase signal, a phase interpolator configured to receive the input clock signal and generate a second phase signal, a first divider element configured to receive the first phase signal and generate an in-phase divided clock signal, a second divider element configured to receive the second phase signal and generate a quadrature divided clock signal, a first delay element configured to receive the in-phase divided clock signal and an in-phase control signal, the first delay element configured to generate a delayed in-phase divided clock signal, an a second delay element configured to receive the quadrature divided clock signal and a quadrature control signal, the second delay element configured to generate a delayed quadrature divided clock signal. | 12-11-2014 |
20140362963 | CORRECTING APPARATUS FOR TIMING RECOVERY OF RECEIVER AND METHOD THEREOF - A correcting apparatus for timing recovery of a receiver is provided. The receiver includes a timing recovery module that outputs a first symbol and a second symbol. The correcting apparatus includes: a channel impulse response module, configured to generate a first set of peak times and a second set of peak times according to the first symbol and the second symbol, respectively; and a calculation module, configured to calculate a correction signal according to a relationship between the first and second sets of peak times and to send the correction signal to the timing recovery module. | 12-11-2014 |
20150349786 | HIGH SPEED CURRENT MODE LATCH - A current mode logic (CML) latch that includes a first transistor coupled to a second transistor, a third transistor coupled to a fourth transistor, a first capacitor connected to the first, second, third, and fourth transistors, and a second capacitor cross-coupled with the first capacitor and connected to the third and fourth transistors. The first and second transistors are configured to receive a data signal. The third and fourth transistors are configured to receive a clock signal. | 12-03-2015 |
20150381341 | DATA RECEIVER AND DATA RECEIVING METHOD THEREOF - A data receiver includes a serial-data processing module, a null-frequency detecting unit, a data checking unit, a status control unit and a timeout checking unit. The serial-data processing module receives serial data, generates an operation clock, parallel data and required data, and determines whether the operation clock is correct for accordingly generating a first result. The null-frequency detecting unit receives the operation clock and determines whether the operation clock is locked or null for accordingly generating a second result. The data checking unit is enabled according to the first result and determines whether checking data of the required data is correct for accordingly generating a third result. The status control unit outputs a frequency-locked signal and changes the signal state of the frequency-locked signal according to the first to third results. The enabled timeout checking unit resets the serial-data processing module according to the signal state of the frequency-locked signal. | 12-31-2015 |
20160013929 | CDR CIRCUIT AND SEMICONDUCTOR DEVICE | 01-14-2016 |
20160043862 | Multi-channel timing recovery device - The present invention discloses a multi-channel timing recovery device capable of generating a common clock for processing a plurality of data channel signals, comprising: a first channel timing recovery circuit, and a second channel timing recovery circuit. The said first channel timing recovery circuit includes a first detecting circuit capable of detecting phase and/or frequency, an oscillation control circuit, an oscillator and a feedback circuit, and is operable to generate the common clock according to a first channel signal which could be a clock signal or a data signal. The said second channel timing recovery circuit includes a second phase detecting circuit, a second phase control circuit and a second clock output circuit, and is operable to generate a second clock according to the common clock and determine the phase of the second clock according to a second channel signal which is a data signal. | 02-11-2016 |
20160127122 | QUADRICORRELATOR CARRIER FREQUENCY TRACKING - Systems and methods are provided for correcting frequency drift in satellite receivers based on quadricorrelator carrier frequency tracking. An intermediate frequency corresponding to a received satellite signal may be converted to a digital baseband signal. Frequency related information may be obtained based on quadricorrelator carrier frequency tracking of the digital baseband signal, and the information may be used in generating a quadricorrelator corrected channel. The quadricorrelator corrected channel may converge to the centroid of its spectrum. Thus, the advanced quadricorrelator frequency tracking may allow tracking and correcting frequency drift during baseband signal processing. | 05-05-2016 |
20160191284 | CLOCK SIGNAL GENERATING APPARATUS, CLOCK SIGNAL GENERATING METHOD, AND MEDIUM - A clock signal generating apparatus detects a phase difference between an input reference clock signal and a feedback signal to output a control signal based on the phase difference, generates the clock signal with a frequency based on the output control signal, generates a pattern by switching, at a certain time interval, between a plurality of patterns of a second phase shift amount, adds a first phase shift amount to the second phase shift amount having the generated pattern, determines a phase to be selected, so that a cycle of the phase-shifted clock signal matches the cycle of a clock signal changed by the first phase shift amount to which the second phase shift amount is added, selects the determined phase from among a plurality of phases, and generates a phase-shifted clock signal whose signal level changes in the selected phase for output as the feedback signal. | 06-30-2016 |