Entries |
Document | Title | Date |
20080205569 | UWB Receiver scaling clock frequency by data rate and data reception method thereof - A method for demodulating an ultra-wide band (UWB) signal includes detecting a detecting a data rate of the UWB signal, selecting one from plurality of clock signals in response to the detected data rate, decoding the UWB signal in accordance with the selected clock signal, and outputting transmission data determined by a fast clock. The plurality of clock signals includes at least one frequency different from other frequencies. A receiver for an UWB signal includes an OFDM demodulating unit demodulating the UWB signal into an OFDM symbol, and a bit-level processing unit demodulating the OFDM symbol into bit-level data. The bit-level processing unit receives a scaled clock signal having a frequency corresponding to one of a plurality of data rates of the UWB signal. The method and apparatus may reduce static power consumption and improve performance of the receiver. | 08-28-2008 |
20080219392 | Data-Dependent Noise Predictor in Data-Aided Timing Recovery - A communication system includes a communication channel ( | 09-11-2008 |
20080226008 | Providing Accurate Time-Based Counters for Scaling Operating Frequencies of Microprocessors - The illustrative embodiments provide accurate time-based counters for scaling operating frequencies of microprocessors. A time-based counter circuit configuration in which a fixed frequency clock is derived from a PLL of the clock generation circuit of the microprocessor and is used to feed the external and internal timebase logic as well as a timebase accumulator counter. The timebase accumulator counter accumulates the tick events from the timebase logic between two core clocks. The accumulated value is transferred to the core clock domain on every clock edge of a scalable clock and the accumulator is then reset. Because the accumulated ticks are transferred to the core clock domain before the accumulator is reset, no ticks are ever lost using the circuitry of the illustrative embodiment. | 09-18-2008 |
20080232530 | ALTERING POWER CONSUMPTION IN COMMUNICATION LINKS BASED ON MEASURED NOISE - A method, circuit and system for altering the power consumption in communication links. A type of noise and an amount of jitter in a signal transmitted across a communication link is measured. Upon determining the contribution of the measured noise to the measured jitter in the signal, the measured noise is classified based on such contribution and the intensity of the measured jitter. The power consumption in a component(s) of the communication link may be adjusted based on the classification of the measured noise. For example, if the measured noise is classified as being a low amount of noise, then the power consumption of the component(s) may be reduced such as by lowering the voltage of the power supply and/or reducing the complexity of the circuitry. By reducing the power consumption when the communication link is not subject to the worst-case condition, a savings in power consumption may be made. | 09-25-2008 |
20080240325 | High-Speed Receiver Architecture - A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm. | 10-02-2008 |
20080253491 | Method and Apparatus for Reducing Jitter in Multi-Gigahertz Systems - An apparatus for generating an output signal that is analogous to an first signal from a first signal source that exhibits a first jitter, so that the output signal exhibits less jitter than the first jitter includes at least one second signal source generates a second signal that is analogous to and phase locked with the first signal. The second signal exhibits a second jitter that is uncorrelated with the first jitter. A signal averaging device is responsive to the first signal and the second signal. The signal averaging device averages the first signal and the second signal with respect to at least one parameter and thereby generates the output signal. | 10-16-2008 |
20080267331 | Method and Apparatus Adapted to Demodulate a Data Signal - The present invention relates to the field of receiving data and/or demodulating a data transmission signal. The present invention provides a method of and/or device for determining a data signal imposed on a phase jitter modulation signal. In one form, the invention relates to the field of Radio Frequency Identification (RFID), and the transmission of data between a tag and an interrogator. | 10-30-2008 |
20080267332 | METHOD AND SYSTEM FOR COMPENSATING FOR THE EFFECT OF PHASE DRIFT IN A DATA SAMPLING CLOCK - A method and system for compensating for the effect of phase drift in a data sampling clock during data transfer between sub-systems of an electronic device. The sub-systems of the electronic device transfer data frame by frame. Each frame includes multiple data windows. Each data window includes multiple data bits. The method includes sampling each of the one or more data bits of a data window at one or more early instances, a prompt instance, and one or more late instances. Further, the method includes calculating the phase-error value of the sampled data window, based on the data sampled. Furthermore, the method includes compensating for the effect of phase drift in the data sampling clock, based on the calculated phase error value. | 10-30-2008 |
20080273645 | METHODS AND APPARATUS FOR CRYSTAL OSCILLATOR DRIFT ESTIMATION AND COMPENSATION - In at least some disclosed embodiments, a method includes receiving a burst of data out of multiple bursts of data subject to long-term frequency drift and short-term frequency drift, determining an intercept of the long-term frequency drift based on, at most, the entire burst, and compensating for the long-term drift of a subsequent burst based on the intercept. The method further includes determining a slope of the short-term frequency drift, and compensating for the short-term frequency drift of a subsequent burst based on the slope. | 11-06-2008 |
20080273646 | SAMPLING CLOCK OFFSET TRACKING AND SYMBOL RE-TIMING - Systems, devices, and methods are described for sampling clock offset tracking and timing correction. Wireless signals are received, some of which include a control signal known at the receiver. A first received signal may be correlated with the control signal to produce a reference correlation. A second, later received signal may be correlated with the control signal to produce a second correlation. A difference measurement between the reference correlation and the second correlation may be calculated to estimate drift. The estimated drift may be corrected. | 11-06-2008 |
20080273647 | HIGH-SPEED COMMUNICATION SYSTEM WITH A FEEDBACK SYNCHRONIZATION LOOP - In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device. | 11-06-2008 |
20080279322 | Method and device for timing synchronization and neighbor scanning for cellular OFDM systems - An embodiment of a device for processing at least an incoming signal in a wireless communication system, said incoming signal being sent by a base station and comprising successive frames, each of which comprising at least a training symbol correlated to said base station, and a data symbol carrying message data. | 11-13-2008 |
20080285695 | Method and Arrangements for Link Power Reduction - Methods and arrangements to determine phase adjustments for a sampling clock of a clock and data recovery (CDR) loop based upon subsets of data samples, or values, derived from an incoming data signal are disclosed. In particular, embodiments extend the CDR loop by slowing the clock rate with respect to the sampling clock. For instance, the slower clock rate may be implemented by dividing the frequency of the sampling clock by a number such as 128, slowing a sampling clock frequency designed to handle multiple gigabits per second (Gbps) to a frequency of less than one kilohertz (Khz). In addition to the reduced power consumption realized by operating at a lower frequency, the slower clock rate allows components of the CDR loop circuitry to operate a lower operating voltage reducing power consumption by the CDR loop even more. | 11-20-2008 |
20080298530 | DATA-DEPENDENT JITTER PRE-EMPHASIS FOR HIGH-SPEED SERIAL LINK TRANSMITTERS - In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty. | 12-04-2008 |
20080298531 | Methods and Systems for Communicating Using Transmitted Symbols Associated with Multiple Time Durations - In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that permits interpretation of transmitted symbols associated with a first time duration. The system may further comprise one or more devices configurable to communicate according to a second protocol that permits interpretation of transmitted symbols associated with multiple time durations. The one or more devices configurable to communicate according to the second protocol are operable to communicate using transmitted symbols associated with the first time duration and to communicate using transmitted symbols associated with a time duration that is not supported by the one or more devices configured to communicate according to the first protocol. | 12-04-2008 |
20080304608 | TEST APPARATUS, AND DEVICE FOR CALIBRATION - The test apparatus includes a first comparator and a second comparator that measure a measured signal output from the device under test at a given sampling clock timing, a deciding section that decides a quality of the device under test on the basis of a measurement result in the first comparator and the second comparator, a control section that causes the first comparator and the second comparator to input an adjustment signal having a previously injected jitter and respectively sample the input signal, a skew computing section that computes a skew between the first comparator and the second comparator on the basis of sampling results, and a phase adjusting section that adjusts a phase of at least any one of the measured signal and the sampling clock in at least any one of the first comparator and the second comparator on the basis of the skew. | 12-11-2008 |
20080310572 | FRAME SYNCHRONIZATION APPARATUS AND ITS CONTROL METHOD - A frame synchronization apparatus for controlling a frame synchronization process carried out on an input signal, the frame synchronization apparatus including: a correlation-value computation section; an IQ component select section; and a synchronization-signal outputting section. | 12-18-2008 |
20090016476 | Method for shifting a phase of a clock signal and memory chip using the same - A memory chip includes a receiver, a clock phase shifter, an error detector, and a controller. The receiver receives a test signal having a plurality of random data bits. The clock phase shifter shifts the phase of a clock signal to one of first through nth phases (n is a natural number). The controller controls the clock phase shifter to sequentially increase the phase of the clock signal from the first phase when the error detector determines the data bit sampled in synchronization with the clock signal has an erro has an error. The controller controls the clock phase shifter to sequentially decrease the phase of the clock signal from the nth phase when none of the plurality of data bits sampled in synchronization with the clock signal having a kth phase (k is a natural number greater than 1 and smaller than n−1) have an error. | 01-15-2009 |
20090028279 | SYMBOL TIMING RECOVERY CIRCUIT - An A/D converter samples an input signal with a first clock. An FIR filter generates data at a zero-crossing point/data decision point from the sampled data. A decimation circuit decimates an output of the FIR filter | 01-29-2009 |
20090028280 | TRANSMITTER AND TRANSMITTER/RECEIVER - A clock control circuit | 01-29-2009 |
20090034673 | SYSTEM AND METHOD FOR ADAPTIVELY DESKEWING PARALLEL DATA SIGNALS RELATIVE TO A CLOCK - A system and method of reducing skew between a plurality of signals transmitted with a transmit clock is described. Skew is detected between the received transmit clock and each of received data signals. Delay is added to the clock or to one or more of the plurality of data signals to compensate for the detected skew. The delay added to each of the plurality of delayed signals is updated to adapt to changes in detected skew. | 02-05-2009 |
20090041172 | PHASE DETECTION CIRCUIT - A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values. | 02-12-2009 |
20090046821 | RECEIVING APPARATUS - A capsule endoscope | 02-19-2009 |
20090060108 | DEVICE FOR ESTIMATING SYMBOL TIMING OR FREQUENCY OFFSET WITH RELIABILITY OF DEMODULATED SIGNAL DETERMINED - A PHS mobile phone set is provided with an offset estimation device which estimates an offset of a signal received through digital communication and makes use of the estimated offset as correction information for offset correction. The received signal is corrected in offset by use of the estimated offset and then demodulated. In the offset estimation device, the estimated offset is updated on the basis of the control signal indicating whether or not the demodulated digital signal is reliable. | 03-05-2009 |
20090060109 | APPARATUS FOR GENERATING CLOCK SIGNAL IN MOBILE COMMUNICATION TERMINAL - Disclosed is an apparatus for generating a stable clock signal having a Long term jitter noise removed therefrom. In a mobile communication terminal having a power management chip for converting a sinusoidal wave oscillated in a crystal into a clock signal of square wave, the sinusoidal wave is converted into a square wave clock signal by the stabilized driving power having no alternating current components, and thus a power noise of the square wave clock signal is removed. Then, the square wave clock signal having the power noise removed therefrom is outputted after a predetermined delay time. Accordingly, it is possible to supply the clock signal having the Long term jitter noise removed therefrom and synchronized to each device in the mobile communication terminal. | 03-05-2009 |
20090067562 | DOPPLER TRACKING METHOD AND DEVICE FOR A WIDE BAND MODEM - A system and method for estimating and tracking the frequency offset for a transmission system whose bandwidth is not insignificant with respect to the central frequency, the system transmitting a waveform including fixed carriers whose level is substantially greater than that of the carriers transporting the information, the carriers having frequencies F | 03-12-2009 |
20090074124 | Determining a Time Interval Based on a First Signal, a Second Signal, and a Jitter of the First Signal - An apparatus including a circuit configured to determine a jitter of a first signal, and to determine a time interval between a feature in a second signal and a feature in the first signal based on the determined jitter. | 03-19-2009 |
20090080583 | ADAPTIVE CONTROL OF CLOCK SPREAD TO MITIGATE RADIO FREQUENCY INTERFERENCE - In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed. | 03-26-2009 |
20090080584 | SEMICONDUCTOR SYSTEM - A semiconductor system has a SerDes circuit for receiving serial data, and a reference SerDes circuit for receiving clock signals running in parallel. The SerDes circuit performs serial to parallel conversion of the serial data captured by the recovery clock whose phase is controlled by utilizing the phase control signal P_CS generated by the reference SerDes circuit. | 03-26-2009 |
20090086870 | ADAPTIVE DATA ALIGNMENT - An apparatus including a transmit circuit, a receive circuit, and a control circuit. The control circuit may be configured to present a plurality of transmit data lanes in response to (i) a plurality of transmit data sources and (ii) a plurality of first skew control signals. The receive circuit may be configured to generate a plurality of receive data lanes in response to (i) the plurality of transmit data lanes and (ii) a plurality of second skew control signals. The control circuit may be configured to generate the first skew control signals and the second skew control signals in response to an alignment of the plurality of receive data lanes. The control circuit may adjust a timing of the receive data lanes and the transmit data lanes to achieve arrival of the receive data lanes across a transmission medium within a skew parameter. | 04-02-2009 |
20090086871 | Apparatus for distributing a signal - An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal. | 04-02-2009 |
20090086872 | Method for binary clock and data recovery for fast acquisition and small tracking error - A novel method and system for clock and data recovery in high speed serial transceiver applications allowing for fast bit lock acquisition and small data tracking error is presented. The clock and data recovery method utilizes a variable bandwidth loop filter to generate a phase adjustment signal used by a phase interpolator in generating a clock signal at the same frequency and phase as the incoming digital data stream. The loop filter bandwidth may be adjusted to correspond with a plurality of clock and data recovery operating modes. In particular, the filter bandwidth may be set to either a high or a low value depending on whether the phase difference between the recovered clock signal and the incoming digital data stream is above or below a programmed threshold value. | 04-02-2009 |
20090086873 | Waveform Signal Generator with Jitter or Noise on a Desired Bit - Waveform data of selected bits having jitter or noise is generated wherein the waveform date represents a serial digital signal. A signal generator displays a jitter/noise setting area and a bit selection area on a display device where jitter or noise is set and the jitter or noise settings are applied to only the bit selected with the bit selection area. The bit is selected through various ways. A user may directly input a bit pattern to be selected. Box objects corresponding to the respective bits in the digital signal may be displayed and one or more of the bits can be selected by selecting one of the box objects. Frequently used bit patterns may be stored and provided using a menu-driven interface for selecting a bit pattern. An arbitrary number of consecutive bits may be designated for receiving jitter or noise and displayed. | 04-02-2009 |
20090092214 | CLOCK CIRCUIT WITH CLOCK TRANSFER CAPABILITY AND METHOD - An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock. | 04-09-2009 |
20090103672 | TRANSMISSION SYSTEM, TRANSMITTER, RECEIVER, AND TRANSMISSION METHOD - There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a data sequence is transferred, includes a transmitter that transmits a first transfer signal including an edge-present data waveform which has (i) a first timing edge indicating a timing to obtain data included in the data sequence and (ii) a level signal indicating a signal level corresponding to a value of the data, and a receiver that outputs the value of the data in accordance with the signal level which is detected at the timing indicated by the first timing edge of the edge-present data waveform. | 04-23-2009 |
20090103673 | SIGNAL POWER COMBINER WITH DYNAMIC PHASE COMPENSATION - The present invention relates to a signal power combiner with dynamic phase compensation, which uses a plurality of phase shifters to receive a first input signal and a second input signal, and shift the phases of the first and second input signals. A detection unit detects the phases of the first input signal and the second input signal, produces a compensation signal, and transmits to the plurality of phase shifters for shifting the phases of the first input signal and the second input signal. A combiner receives the compensated first and second input signals, combines the first input signal and the second input signal, and produces an output signal. Thereby, the transmission quality of signals is improved. | 04-23-2009 |
20090110134 | Noise Floor Independent Delay-Locked Loop Discriminator - A system and method for providing code tracking in a CDMA based communications receiver. In example systems and methods, a CDMA receiver, such as a GPS receiver, receives a signal and demodulates the signal to yield a digital IF signal. The digital IF signal is down-converted to a received code signal. Early, prompt and late correlation results are determined by correlating the received code signal with early, prompt and late duplicates of the received code signal. The early, prompt and late correlation results are used to calculate a code phase error using a noise-floor independent function of all three correlation results. | 04-30-2009 |
20090110135 | Methods for PRS-Based Symbol Timing Adjustment for OFDM Systems - This invention relates to methods for determining symbol timing shift for a received signal, comprising the steps of: demodulating a received signal; removing a phase reference sequence from the demodulated signal to generate a channel frequency response; converting said channel frequency response to the time domain to generate a channel impulse response; determining a detection threshold; determining a first path and a last path as a function of the detection threshold; and calculating a timing shift as a function of the first path and the last path. | 04-30-2009 |
20090116600 | PHASE DRIFT COMPENSATION FOR SAMPLED SIGNALS - Methods for processing a signal of interest in an electrical power system are provided, as well as systems and computer program products for carrying out the methods. The methods include obtaining a representative window of data points from the signal of interest; obtaining a window of interest containing data points from the signal of interest; and comparing a phase drift compensated window to the representative window, wherein the compensated window is calculated in accordance with the window of interest and a phase drift that is present in the window of interest relative to the representative window. | 05-07-2009 |
20090116601 | Clock data recovery circuit and method for operating the same - A clock data recovery (CDR) circuit occupies a small area required in a high-integration semiconductor device, electronic device and system and is easy in design modification. The CDR circuit includes a digital filter configured to filter phase comparison result signals received during predetermined periods and output control signals, a driver configured to control the digital filter by adjusting the predetermined periods, and an input/output circuit configured to recognize an input and output of data and clock in response to the control signals. | 05-07-2009 |
20090122938 | Method and System for Identifying Sources of Operating System Jitter - A method for tuning performance of an operating system, the method comprising identifying all sources of operating system jitter; measuring the impact of each of the operating system jitter source; and tuning performance of the operating system, preferably by use of different approaches/techniques, which could include removing the sources of operating system jitter and/or delaying their execution and/or smoothening their execution over a longer period of time. Computer program code and systems are also provided. | 05-14-2009 |
20090135976 | RESOLVING BUFFER UNDERFLOW/OVERFLOW IN A DIGITAL SYSTEM - In a digital system with more than one clock source, lack of synchronization between the clock sources may cause overflow or underflow in sample buffers, also called sample slipping. Sample slipping may lead to undesirable artifacts in the processed signal due to discontinuities introduced by the addition or removal of extra samples. To smooth out discontinuities caused by sample slipping, samples are filtered to when a buffer overflow condition occurs, and the samples are interpolated to produce additional samples when a buffer underflow condition occurs. The interpolated samples may also be filtered. The filtering and interpolation operations can be readily implemented without adding significant burden to the computational complexity of a real-time digital system. | 05-28-2009 |
20090135977 | DEVICE FOR AND METHOD OF SIGNAL SYNCHRONIZATION IN A COMMUNICATION SYSTEM - A device for signal synchronization in a communication system, the device comprising a first detector configured to perform a first sliding correlation for a received signal and a pseudo-random noise (PN) sequence to obtain information on symbol timing, a second detector configured to identify a fractional carrier frequency offset (FCFO) using the information on symbol timing and the cyclic extension property of the PN guard interval (GI), a first multiplier configured to provide a first product by multiplying the received signal with the FCFO, and a third detector comprising a set of second multipliers configured to provide a set of second products by multiplying the first product with each of a set of phases related to integral carrier frequency offsets (ICFOs), a set of sliding correlators each being configured to perform a second sliding correlation for the PN sequence and one of the set of the second products, the set of sliding correlators providing a set of peak values, and a peak detector configured to identify an ICFO by detecting an index number of a maximal value among the set of peak values. | 05-28-2009 |
20090135978 | Apparatus and method for estimating and compensating sampling frequency offset - An apparatus and method for estimating and compensating sampling frequency offset are disclosed. Particularly, a linear mathematical scheme is employed to calculate the related phase difference for saving use of multipliers and storage circuit used for sampling frequency offset estimation and compensation in the conventional art. The preferred embodiment of the invention has a first step to receive signals by the offset estimating circuit. Next, the phase value for each signal is calculated, and the pilot signal therein is retrieved. Next, a phase difference is obtained by subtraction operation between the received symbols and the delayed pilot symbols. And a circuit for storing the phase differences is incorporated. Next, a phase difference between the adjacent symbols is obtained by accumulating the phases and processing the least-error-sum-of-squares operation. Therefore, an estimation value of the sampling frequency offset of a communication system is obtained, and further to compensate the offset. | 05-28-2009 |
20090141843 | Method and Apparatus for Determining a Skew - The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words. | 06-04-2009 |
20090154628 | SCAN SIGNAL GENERATING CIRCUIT AND SCAN SIGNAL GENERATING METHOD THEREOF - The invention provides scan signal generating circuits and scan signal generating methods thereof. The scan signal generating circuit comprises a first, a second and a third switch and a capacitor, and generates a scan signal driving a pixel. The first switch is turned on to couple an input signal to a first node when a first clock signal is high. The second switch, controlled according to the voltage level at the first node, is turned on to couple a second clock signal that has an inverse phase of the first clock signal to an output terminal of the scan signal generating circuit when the voltage level at the first node is high. When the first clock signal is high, the third switch is turned on to couple the output terminal to a first voltage source. The first node is coupled to ground by the capacitor. | 06-18-2009 |
20090161808 | APPARATUS AND METHOD FOR DETECTING RECEPTION SIGNAL SYMBOL SYNCHRONIZATION IN WIRELESS COMMUNICATION SYSTEM - Provided is an apparatus and method for detecting reception signal symbol synchronization in a wireless communication system. The method, includes: calculating a channel power value in each of multiple antennas; selecting and averaging at least 2 channel power values; compensating carrier frequency offset for an average value; and determining a symbol boundary of a reception signal according to the size of the average value compensating the carrier frequency offset. | 06-25-2009 |
20090168940 | Methods and Apparatus for Improved Jitter Tolerance in an SFP Limit Amplified Signal - Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter. | 07-02-2009 |
20090168941 | Method and apparatus for duty cycle pre-distortion and two-dimensional modulation - In serial communications, jitter is an unwanted variation of one or more signal characteristics. Two-dimensional modulation circuits and methods incorporate an amplitude pre-emphasis scheme as well as a transmit duty cycle pre-distortion (pre-DCD) technique to reduce jitter. The pre-DCD technique directly addresses transition edges of the data signal and is combined with amplitude pre-emphasis to improved data transmission. | 07-02-2009 |
20090175396 | Signal processing unit - Since signal transmittance adjustment devices that can suppress transmittance of a receiving signal to a DSP as a receiving processing device from an antenna for reception and a signal transmittance control device configured to control the signal transmittance adjustment devices so that the transmittance of the receiving signal to the DSP from the antenna for reception is suppressed at least when a transmission signal including a modulation signal is transmitted from an antenna for transmission are provided, occurrence of a trouble in which a head portion of a reply signal is crushed by a wrap around signal from a transmission side can be suitably prevented, and particularly, favorable communication can be realized at start of a response from a RFID tag. That is, an apparatus for communicating with a RFID tag that can suitably suppress an influence of a transient response can be provided. | 07-09-2009 |
20090190705 | System And Method For In-Phase/Quadrature-Phase (I/Q) Time Delay Measurement And Compensation - A system for determining a time delay between an in-phase signal component and a quadrature-phase signal component includes an in-phase signal start time determination module coupled to an in-phase delay module, the in-phase signal start time determination module and the in-phase delay module configured to receive an in-phase signal component of a received signal. The in-phase signal start time determination module is configured to receive a reference signal. The system also includes a quadrature-phase signal start time determination module coupled to a quadrature-phase delay module, the quadrature-phase signal start time determination module and the quadrature-phase delay module configured to receive a quadrature-phase signal component of a received signal. The quadrature-phase signal start time determination module is configured to receive a reference signal, wherein the in-phase delay module is configured to develop an in-phase delay signal and the quadrature-phase delay module is configured to develop a quadrature-phase delay signal. | 07-30-2009 |
20090202030 | AUTOMATED CLOCK RELATIONSHIP DETECTION - Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or extended over multiple clock periods. Automated clock relationship detection between two clocks may comprise (a) a shift register synchronizer that reduces the possibility of metastability while capturing and temporarily storing samples of the first clock in response to cycles of the second clock and (b) an evaluator that processes the samples to determine the relationship. A clock relationship detector may also determine the relationship of two clocks by arbitrating a plurality of preliminary determinations of the relationship. Delays may be applied so that each of several detectors receives a clock at a different time, which may avoid metastability in the majority of detectors. The relationship may be used to reliably determine an operating mode of logic driven by one of the clocks. | 08-13-2009 |
20090202031 | Delay estimation for a timing advance loop - An apparatus includes a radio frequency receiver and a timing adjustment unit that contains at least two channel impulse response estimators. The at least two channel impulse response estimators include an on-time estimator and at least one of an early estimator and a late estimator. The apparatus also includes a calculation unit that is configurable to obtain a channel estimate for each measured channel impulse response and to average obtained channel estimates over a plurality of received signal events to determine a timing adjustment in accordance with residual signal power. | 08-13-2009 |
20090207960 | FRAME PULSE SIGNAL LATCH CIRCUIT AND PHASE ADJUSTMENT METHOD - While a phase of an output clock signal is varied, an input frame pulse is latched based on the output clock signal. Then, by using an output frame pulse, which is a result of the latching, generation of a racing state, which is caused by the phase relation between the output clock signal and the output frame pulse, is detected. Next, a phase adjustment amount is determined so that the phase of the output clock signal of the moment when the racing state is generated is shifted by a period corresponding to half a cycle of the output clock signal. | 08-20-2009 |
20090213972 | Apparatus and method to adjust a phase and frequency of a digital signal - An apparatus comprising at least two controllers each providing control information for controlling phase or frequency of a digital signal, a combiner for combining control information from the at least two controllers to combined control information and a phase rotator for adjusting, by using phase rotation, one or more of the phase and the frequency of the digital signal on the basis of the combined control information. | 08-27-2009 |
20090213973 | CLOCK REGENERATION CIRCUIT - A clock regeneration circuit according to the present invention that generates a clock signal that is synchronized to an input signal, includes: a detection section which detects points at which the input signal transitions; a histogram generation section which associates a plurality of partial periods with the transition points, and generates a first histogram indicating an incidence of the transition points for each of the partial periods, the partial periods being generated by dividing a reference period of the clock signal; a calculation processing section which generates a second histogram by calculation processing based on the first histogram, and calculates a phase adjustment value of the clock signal based on the second histogram; and a phase adjustment section which adjusts a phase of the clock signal based on the phase adjustment value. | 08-27-2009 |
20090232264 | LOW COMPLEXITY HIGH PERFORMANCE TMCC ACQUISITION IN ISDB-T AND ISDB-TSB RECEIVERS - A method of TMCC information acquisition in an ISDB-T/TSB receiver comprises detecting coarse frequency offset in the receiver to identify bins that have TMCC information; and acquiring TMCC and symbol number information from the identified bins. The detecting process may be conducted using different methods and the acquiring process may be conducted using different methods. The TMCC information acquisition method saves memory space and provides enhanced performance by using coarse frequency offset to identify the bins that have TMCC information and obtaining the TMCC and symbol number information from the identified bins. | 09-17-2009 |
20090232265 | Clock data recovery circuit - A clock data recovery circuit that supplies stable reproduction clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2π. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reproduction clock. | 09-17-2009 |
20090252270 | DATA DECISION APPARATUS AND ERROR MEASUREMENT APPARATUS - The object of the present invention is to provide a data decision apparatus and an error measurement apparatus which can set the phase of the clock to the optimum state with respect to the data signal without continuously sweeping of the phase, and can keep the state for a long time. The data decision apparatus according to the present invention comprises a delay device ( | 10-08-2009 |
20090257540 | Multi-Channel Timing Recovery System - The present invention discloses a novel multi-channel timing recovery scheme that utilizes a shared CORDIC to accurately compute the phase for each tone. Then a hardware-based linear combiner module is used to reconstruct the best phase estimate from multiple phase measurements. The firmware monitors the noise variance for the pilot tones and determines the corresponding weight for each tone to ensure that the minimum phase jitter noise is achieved through the linear combiner. Then a hardware-based second-order timing recovery control loop generates the frequency reference signal for VCXO or DCXO. A single sequentially controlled multiplier is used for all multiplications in the control loop. | 10-15-2009 |
20090257541 | Receiving Circuit with Adaptive Synchronization and Method Thereof - A circuit with adaptive synchronization and a method thereof is provided. The synchronous receiving circuit adaptively adjusts the timing of a clock signal generated therein for receiving data without accompanying a clock signal for synchronization. The synchronous receiving circuit includes a clock generator, an edge detector, a synchronization unit and a latch. The clock generator generates a first clock signal according to an input data signal. The edge detector detects edges to generate an indication signal. The synchronization unit is coupled to the clock generator and the edge detector, and adaptively adjusts the first clock signal according to the indication signal. The latch latches the input data signal according to the adjusted first clock signal. | 10-15-2009 |
20090274254 | DATA TRANSMITTING DEVICE AND DATA TRANSMITTING METHOD - The logic block | 11-05-2009 |
20090290671 | Data recovery system for source synchronous data channels - A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol interference, high-frequency loss, skew between the clock and data channels, and differential skew within a differential signal are compensated by analog circuits which are automatically tuned for best performance by observing the quality of the recovered analog signal. Oversampling is used to provide a 24-bit digital representation of the analog signal for determining the quality of the signal. | 11-26-2009 |
20090296866 | EFFICIENT MECHANISMS FOR LOCAL CLUSTER NETWORK SYNCHONIZATION - Embodiments of local cluster network synchronization in mechanisms are described generally herein. Other embodiments may be described and claimed. | 12-03-2009 |
20090296867 | ISI Pattern-Weighted Early-Late Phase Detector with Jitter Correction - An inter-symbol interference (ISI) pattern-weighted early-late phase detector is provided. I and Q clocks are generated. The I clock frequency is divided by n, creating a reference clock. A serial data stream is sequentially sampled with the I clock, and with Q clocks having fixed and varied phase delays from the I clock, creating digital I-bit and Q-bit values. The I-bit values and Q-bit values are segmented into n-bit digital words. I clock phase corrections are identified and a modulation factor is determined in response to comparing Q-bit values sampled by the varied delay Q clock. Also identified are bit sequence patterns associated with each I-bit value. Each I-bit value is weighted in response to the identified bit sequence pattern and the identified I clock phase correction. The modulation factor is applied to the weighted average, and I and Q clock phase error signal are generated. | 12-03-2009 |
20090310728 | IN-SITU JITTER TOLERANCE TESTING FOR SERIAL INPUT OUTPUT - According to some embodiments, a method and apparatus are provided to generate a sine wave via a jitter modulator to modulate a control voltage of a clock source. The jitter modulator is in-situ on a die. The sine wave is received at a clock and data recovery circuit comprising the clock source. The clock and data recovery circuit is in-situ on the die. | 12-17-2009 |
20090323879 | DATA ALIGNMENT AND DE-SKEW SYSTEM AND METHOD FOR DOUBLE DATA RATE INPUT DATA STREAM - Methods and apparatus are provided for a system for aligning data. The apparatus comprises a demultiplexing component adapted to bifurcate a double data rate (DDR) data stream into a first single data rate (SDR) data stream and a second SDR data stream, a bit detection component coupled to the demultiplexing component and adapted to compare bit values between the first and second SDR data streams and generate a first signal in response to detection of a predetermined arrangement of bits, a delay component adapted to receive the DDR data stream and perform a delay operation on the DDR data stream to create a delayed data stream, and a data alignment component coupled to the demultiplexing component, the delay component, and to the bit detection component, the data alignment component being adapted to place the delayed data stream in alignment in response to the first signal. | 12-31-2009 |
20100002822 | PHASE COMPARATOR, PHASE COMPARISON DEVICE, AND CLOCK DATA RECOVERY SYSTEM - A comparison period detecting unit ( | 01-07-2010 |
20100008458 | Methods and apparatuses for estimating time delay and frequency offset in single frequency networks - In one method, an uplink signal carrying at least one block of transmitted samples is transmitted, and a distorted copy of the uplink signal is received as a downlink signal. A plurality of blocks of received samples are generated based on the received downlink signal, and a time delay and frequency offset between the uplink and downlink signals are determined based on a correlation between the block of transmitted samples and at least one of the plurality of blocks of received samples. | 01-14-2010 |
20100008459 | Calibrating A Phase Detector And Analog-To-Digital Converter Offset And Gain - The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed. | 01-14-2010 |
20100014621 | Synchronization Determining Circuit, Receiver Including the Synchronization Determining Circuit, and Method of the Receiver - A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed. | 01-21-2010 |
20100020909 | SYNCHRONIZING APPARATUS AND METHOD IN PACKET NETWORK - Provided are a synchronizing apparatus and method for performing synchronization in a packet network. The synchronizing apparatus includes a sampling unit to measure a time difference using a plurality of time stamps included in a plurality of two-way message packets, an estimating unit to estimate a frequency offset by applying a baseline algorithm to the time difference, a verifying unit to verify the frequency offset to remove an error caused by network delay variation, and a synchronizing unit to remove the frequency offset from a local slave clock signal and generate a slave clock signal synchronized to a clock signal of a master device. | 01-28-2010 |
20100027729 | Fractional Interpolative Timing Advance and Retard Control in a Transceiver - Transmission of information between user equipment (UE) and base stations in a wireless network occurs using a stream of periodic data. A modem in the UE operates synchronized to a first clock source to produce the stream of periodic data at a chip rate. Transceiver circuitry is synchronized to a variable clock source to receive the stream of data from the first circuitry at a rate according to the variable clock source. A fixed phase relationship is maintained between the variable clock source and the first clock source while the data period is uniform by adjusting the variable clock in response to detected phase errors. Occasionally, one period of the periodic data is changed by a defined amount. The fixed phase relationship is restored over a number of periods in a gradual manner by changing the frequency of the variable clock by an amount. By restoring the phase relationship gradually, quality degradation of the transmitted signal is reduced. | 02-04-2010 |
20100034332 | JITTER BUFFER CONTROL - A method of controlling an adaptable jitter buffer in accordance with the present invention detects a context description of data handled by the adaptable jitter buffer. Thereafter it is determined whether the detected context description is equal to a predetermined context description. If not, jitter buffer adaptation proceeds as normal. Otherwise it is determined whether the current target buffer depth is too low for the detected context description. If not, the target buffer depth is frozen to the current value. Otherwise it is increased and frozen at a higher value that is compatible with the detected context description. | 02-11-2010 |
20100054383 | METHODS AND APPARATUS FOR GENERATING EARLY OR LATE SAMPLING CLOCKS FOR CDR DATA RECOVERY - Methods and apparatus are provided for a clock phase generator for CDR data sampling that generates early and/or late sampling clocks, relative to ideal transition and sample points. An early sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the transition clock signals to generate one or more early clock signals. A late sampling clock is generated by generating a plurality of transition and data sampling clock signals having a substantially uniform phase separation; and delaying at least one of the data sampling clock signals to generate one or more late clock signals. The early clock signals can be employed, for example, in a threshold-based decision feedback equalizer. The late clock signals can be employed, for example, in a classical decision feedback equalizer. | 03-04-2010 |
20100054384 | SIGNAL DELAY STRUCTURE IN HIGH SPEED BIT STREAM DEMULTIPLEXER - A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals. | 03-04-2010 |
20100061497 | METHOD AND APPARATUS FOR HANDLING OF CLOCK INFORMATION IN SERIVAL LINK PORTS - A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block. | 03-11-2010 |
20100061498 | DATA RECEIVING CIRCUIT - A receiving circuit includes a clock generation circuit that generates a clock signal, an integration filter that stores a signal potential of an input signal and generates a first storage potential in a period in which the clock signal indicates one logic, a first analog-to-digital circuit that converts the first storage potential into a first digital value, and a data determination circuit that determines a logic of the input signal on a basis of the first digital value. | 03-11-2010 |
20100067632 | LONG TERM EVOLUTION (LTE) RADIO LINK TIMING SYNCHRONIZATION - A method for performing a radio link timing estimation for synchronization to a wireless communications channel such as an uplink channel in a 3GPP Long Term Evolution (LTE) network in a mobile wireless device or wireless network base station is provided. A channel frequency response estimate from a received reference signal comprising multiple non-coherent Orthogonal Frequency Division Multiplexing (OFDM) symbols is obtained. A frequency response covariance matrix from the channel frequency response estimate is then generated. Timing offsets of the received reference signal using covariance matrix and timing offset estimation algorithms are then estimated. | 03-18-2010 |
20100074384 | RECEIVING DEVICE, RECEIVING METHOD, AND PROGRAM - A receiving device includes: a noise detecting means for detecting a noise, which is contained in a received signal, using the received signal which has undergone clock synchronization processing: a phase error detecting means for detecting a phase error of the received signal using the received signal which has undergone clock synchronization processing; and a calculation means for calculating a phase correction value on the basis of the phase error detected by the phase error detecting means, wherein, when the noise is detected by the noise detecting means, the calculation means modifies a parameter to be employed in the calculation of the phase correction value so as to decrease the phase correction value. | 03-25-2010 |
20100074385 | Digital Transmit Phase Trimming - A circuit has a phase adjustment circuit to generate an adjusted clock signal by adjusting a first clock signal in accordance with a control signal. A multiplexer receives input data signals on a plurality of first data lines and outputs onto at least one second data line output data signals in accordance with a plurality of second clock signals. A timing measurement circuit determines at least one timing parameter of at least one output data signal on at least the one second data line and generates the control signal in accordance with a deviation of at least the one timing parameter from a desired value. | 03-25-2010 |
20100074386 | JITTER CONTROL APPARATUS - A jitter control apparatus used in a multiplexing apparatus multiplexing a plurality of signals by asynchronous mapping, includes: a detection unit configured to detect a frequency of timing compensation processes in the asynchronous mapping for each of the plurality of signals; and a selection unit configured to select, on basis of a detection result by the detection unit, a clock signal to be used as a carrier clock for the plurality of signals, from a plurality of clock signals including clock signals extracted from at least one of the plurality of signals. | 03-25-2010 |
20100080333 | METHOD AND APPARATUS FOR PROCESSING RADIO FREQUENCY SIGNALS - A method and apparatus for processing a radio frequency (RF) signal is provided. The method includes generating a periodic square wave local oscillator (LO) signal of a first phase, a periodic square wave LO signal of a second phase, and a chopping signal. The method further includes coding the periodic square wave LO signal of the first phase and the periodic square wave LO signal of the second phase synchronously with the chopping signal to generate a first set of synchronized signals ( | 04-01-2010 |
20100091926 | PHASE CORRECTION CIRCUIT OF ENCODER SIGNAL - A position detector has a peak detector for detecting peak values of an A1 signal and a B1 signal serving as output signals of an analog to digital (AD) converter, an offset/amplitude correction section for generating an A2 signal and a B2 signal by correcting offsets and amplitude errors using the peak values detected by the peak detector, and a position data conversion section for converting the sinusoidal signals of an A phase and a B phase into position data. | 04-15-2010 |
20100098203 | DIGITAL PHASE INTERPOLATION CONTROL FOR CLOCK AND DATA RECOVERY CIRCUIT - This invention discloses a phase interpolation controller for a clock and data recovery circuit receiving an indication of a phase relationship between a first and a second signal, the phase interpolation controller comprises a plurality of serially coupled bi-directional shift-registers, wherein when the received indication indicates the first signal is ahead of the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in one of the bi-directions, and when the received indication indicates the first signal is behind the second signal in phase, the plurality of serially coupled bi-directional shift-registers shifts in the other of the bi-directions. | 04-22-2010 |
20100098204 | Systems and Methods for Regulating Clock Precision in Distributed Devices - Systems and methods for regulating clock precision are disclosed. One embodiment is a method including receiving a clock signal from an oscillator, maintaining a signal count based on the clock signal; receiving a message comprising timing information from a remote device, calculating a drift value based at least in part on the timing information, and determining whether the drift is greater than a targeted clock accuracy. While the drift value is greater than the targeted clock accuracy, adjusting the signal count by the targeted clock accuracy, reducing the drift value by the targeted clock accuracy, and waiting a partial correction interval. If the drift value is less than the targeted clock accuracy, adjusting the signal count by the drift value. Then determining a receive time for a network message based at least in time on the signal count, and activating a wireless receiver based on the receive time to receive a message. | 04-22-2010 |
20100119024 | METHOD AND APPARATUS FOR MULTI-MODE CLOCK DATA RECOVERY - The disclosed invention is a technology for producing a recovered clock signal using a multi-mode clock data recovery (CDR) circuit that accommodates a flexible range operating frequencies F and consecutive identical digit requirements CID. In a first mode of operation, a controlled oscillator produces the recovered clock signal, and in a second mode of operation, a phase interpolator produces the recovered clock signal. The multi-mode CDR circuit operates in the first mode if (CID/F) is less than a threshold time value and in the second mode if (CID/F) is greater than the threshold time value. | 05-13-2010 |
20100135449 | CORRECTION OF QUADRATURE ERRORS - Embodiments of the invention are concerned with correction of quadrature errors associated with digital communications systems, and in particular in a wireless transmit chain in which an up-converter and a down-converter both have a direct conversion architecture. One embodiment comprises a correction network for correcting a difference between a transmission characteristic of an in-phase signal path and a transmission characteristic of a quadrature signal path, said quadrature signal path being for the transmission of in-phase and quadrature parts of a signal and the signal comprising frequency components within a base band, wherein the correction network comprises an in-phase input port, a quadrature input port, an in-phase output port and a quadrature output port, wherein each input port is connected to each output port by a digital filter network, the digital filter network comprising a set of filter tap coefficients and configuration means for configuring values of said set of filter tap coefficients. Since each input port is connected to each output port by a digital filter network comprising a set of filter tap coefficients and having configuration means for configuring values of said set of filter tap coefficients, frequency dependent quadrature impairments, for example due to the analogue components of a quadrature up-converter or down-converter, may be corrected by suitable control of the coefficients. | 06-03-2010 |
20100150289 | CLOCK REPRODUCING APPARATUS AND METHOD - A common mode of a waveform of a duobinary transmission signal (IN) is set to 0 and the size of a data eye is set to Veye; and reference potentials Vref_H and Vref_L are set to the following values: | 06-17-2010 |
20100150290 | Clock-Data Recovery ("CDR") Circuit, Apparatus And Method For Variable Frequency Data - A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time. | 06-17-2010 |
20100158180 | High jitter tolerant phase comparator - Aspects of the disclosure provide a method and an apparatus for clock and data recovery. The method and apparatus can increase jitter tolerance, and can provide recovered data with reduced jitter amplitude. The method for recovering data transmitted over a channel can include detecting a phase of a data transition within a full unit interval that includes an active zone and an inactive zone that are set based on a jitter characteristic for the channel, generating a phase directive when the phase of the data transition is located within the active zone, and adjusting a data sampling phase based on the phase directive, so that the data transmitted over the channel is sampled at a data transition edge free location. | 06-24-2010 |
20100158181 | Frequency Synchronization with Compensation of Phase Error Accumulation Responsive to a Detected Discontinuity - An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery module further comprises a discontinuity detector configured to detect a delay discontinuity in timing messages received in the slave device from the master device, and a loop controller operative to place the clock recovery loop in a particular state responsive to the detected discontinuity. The particular state comprises a state in which a normal operating mode of the loop is interrupted and a compensating drive signal is applied to a clock source of the slave device to at least partially offset phase error accumulation associated with the detected discontinuity. | 06-24-2010 |
20100166131 | Method and apparatus for detecting clock frequency deviation - The embodiment of the present disclosure discloses a method and apparatus for detecting frequency deviation of a clock. The method includes: counting the clock to be detected to acquire current counting information; filtering the current counting information to acquire filtered data; and acquiring the frequency deviation of the clock to be detected from the filtered data. According to the embodiments of the present disclosure, the detection accuracy of frequency deviation is improved by filtering the counting information acquired by counting the clock to be detected, and appropriately increasing an amount of information after the filtering, so as to perceive the occurrence of any abnormal dithering, and avoid neglecting of any abnormal condition in periodic or aperiodic queries. | 07-01-2010 |
20100172456 | METHOD FOR ADJUSTING TRANSMISSION JITTER IN A RECEPTION TERMINAL - The invention aims to resolve the problems with jitter in a system for receiving real-time data in packets by a jitter regulation method based on the calculation of a curve representing the minimum filling rate of the buffer and by the triggering of a correction operation according to the change in this curve over time. This invention is applicable to all systems for receiving real-time data streams using a reception buffer. It is however particularly advantageous when the transmission jitter has a pseudoperiodic character. | 07-08-2010 |
20100189207 | RECOVERING DATA SAMPLES - An apparatus recovers synchronous data samples from an asynchronously over-sampled stream of data samples derived from an input signal the spectral characteristic of which is subject to variation. The apparatus comprises an FIR filter having an input for receiving the asynchronously over-sampled stream of data samples and for producing equalised asynchronous samples. A signal sample reconstruction means reconstructs the synchronous data samples from the equalised asynchronous data samples. An automatic gain control loop is responsive to the reconstructed data samples to apply gain control for producing gain controlled reconstructed samples. A timing recovery means is responsive to the gain controlled reconstructed samples to provide timing information to the signal sample reconstruction means. A coefficient adaptation control loop is responsive to equalised reconstructed asynchronous data samples substantially unaffected by the automatic gain control for adapting the FIR filter coefficients to the variations in the spectral characteristics of the input signal. | 07-29-2010 |
20100189208 | System and method for clock jitter compensation in direct RF receiver architectures - Systems and methods that provide clock jitter compensation architectures that improve the performance of direct radio frequency (RF) receivers by injecting a calibration tone into the received radio frequency (RF) signals in order to help identify and then compensate for the clock jitter noise. After injecting the tone, the jitter noise going through the direct RF bandpass sampling receiver is estimated using a narrow bandwidth filter, and the received signals are further processed and demodulated depending on the Nyquist zone of the received signal. The relative modulation factor for the modulation is computed and then applied to the Nyquist zone to de jitter that particular Nyquist zone. | 07-29-2010 |
20100195778 | Jitter reduction device and method - A method for reducing the effect of jitter in sampled data is presented. The invention is based on the modelling of jitter as a phase modulation that acts on all the frequencies component of the sampled record in correlated manner. | 08-05-2010 |
20100202578 | CLOCK GENERATION CIRCUIT AND SYSTEM - A clock generation circuit includes: a first determination circuit that detects an input signal at a first phase position based on first frequency signal; a second determination circuit that detects the input signal at a second phase position based on second frequency signal; a phase detector that compares output of the first determination circuit and output of the second determination circuit; a first summing circuit which sums comparison result and first control signal; a second summing circuit which sums comparison result and second control signal; a first voltage controlled oscillation circuit which receives output of the first summing circuit and outputs the first frequency signal; a second voltage controlled oscillation circuit which received output of the second summing circuit and outputs the second frequency signal; and a phase adjustment circuit which generates first control signal and second control signal based on first frequency signal and second frequency signal. | 08-12-2010 |
20100208856 | Stream Data Recording Device, Stream Data Editing Device, Stream Data Reproducing Device, Stream Data Recording Method, and Stream Data Reproducing Method - When recording stream data, index information and time correction information are recorded in correspondence with the stream data. The index information specifies a position of an invalid section in the stream data. The time correction information specifies a time which, supposing that a PCR included in the invalid section was able to be got, a time clock would have shown in synchronization with the PCR. When reproducing the stream data recorded together with the time correction information and the index information, at a position where the invalid section ends, the time clock can be set to a time intended by a broadcasting system, by referencing the index information and the time correction information. | 08-19-2010 |
20100239058 | WIRELESS APPARATUS - The present invention has an object to provide a wireless apparatus which is capable of correctly sampling a waveform of a pulse even when a shape of the pulse is varied. | 09-23-2010 |
20100239059 | TRANSMISSION METHOD AND TRANSMISSION APPARATUS - A data transmission circuit transmits transmission data to a receiving apparatus. The clock transmission circuit transmits a transmission clock to the receiving apparatus when the transmission data is transmitted by the data transmission circuit. The phase control circuit varies a phase of the transmission clock to a phase different from that of the transmission data after the transmission clock is transmitted from the clock transmission circuit. | 09-23-2010 |
20100246738 | SYNCHRONIZATION APPARATUS FOR ACCURATELY DEMODULATING SIGNAL INPUT TO PJM TAG AND PJM TAG INCLUDING THE SYNCHRONIZATION APPARATUS - A passive phase jitter modulation (PJM) tag is charged with power in a continuous wave (CW) section. When receiving a command from a reader, the passive PJM tag must recognize the command and determine exactly when to begin demodulating the command. Only then can the passive PJM tag demodulate the command. To this end, a synchronization apparatus for accurately demodulating a signal input to a PJM tag includes a plurality of correlators correlating a received phase jitter-modulated signal with a template of an internal matched filter which is in the same form as at least a portion of a modified frequency modulation (MFM) flag. | 09-30-2010 |
20100260299 | DESKEWING METHOD AND APPARATUS, AND DATA RECEPTION APPARATUS USING THE DESKEWING METHOD AND APPARATUS - Deskewing method and apparatus, and a data reception apparatus using the deskewing method and apparatus, in which the deskewing apparatus includes an up/down detection unit, a lower limit detection unit, an upper limit detection unit, a phase detection unit, and a buffer unit. The up/down detection unit samples a received data signal in response to a data sampling clock signal, a first edge sampling clock signal, and a second edge sampling clock signal and determines in which of first through third areas of the data signal the logic level of the data signal transitions by using the result of the sampling, wherein the data sampling clock signal, the first edge sampling clock signal, and the second edge sampling clock signal are sequentially activated. The lower limit detection unit detects a lower limit of the first area if the logic level of the data signal transitions in the first area. The upper limit detection unit detects an upper limit of the third area if the logic level of the data signal transitions in the third area. The phase detection unit determines a delay amount indicating the amount by which the data signal is to be delayed according to the upper limit detected by the upper limit detection unit and the lower limit detected by the lower limit detection unit. The buffer unit delays the data signal by the delay amount determined by the phase detection unit. The deskewing apparatus can optimize data sampling by efficiently reducing data skew. In addition, the deskewing apparatus can minimize data restoration errors by reducing an accumulation of jitter. | 10-14-2010 |
20100266081 | System and Method for Double Rate Clocking Pulse Generation With Mistrack Cancellation - A method for generating a dual rate clock circuit the method including coupling the output terminal of a first local clock buffer to the input of a second local clock buffer through at least one inverter circuit and driving the first local clock buffer with a base signal. The method also includes generating an early clock signal with the first local clock buffer based on the base signal and generating a delayed early clock signal by delaying the first local clock signal with the at least one inverter. The method also includes generating a later clock signal by driving the second local clock buffer with the delayed early clock signal wherein the second local clock buffer and the late clock signal generated by the second local clock buffer are synchronized and correlated with the first local clock buffer and the early clock signal generated by the first local clock buffer. | 10-21-2010 |
20100266082 | RECEIVING APPARATUS AND METHOD WITH CLOCK DRIFT ESTIMATION AND COMPENSATION - The present invention relates to a receiving apparatus | 10-21-2010 |
20100290573 | METHOD AND APPARATUS FOR CLOCK DRIFT COMPENSATION DURING ACQUISITION IN A WIRELESS COMMUNICATION SYSTEM - A method of wireless communication is disclosed that includes receiving a plurality of samples from a transmission of a known sequence; identifying a peak position in the known sequence based on a correlation of the plurality of samples and the known sequence; and adjusting the identified peak position based on an offset. An apparatus for performing the method is also disclosed herein. | 11-18-2010 |
20100310029 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR OPERATING THE SAME - A semiconductor memory apparatus includes a clock input unit configured to receive a system clock and a data clock, a data clock phase regulation unit configured to regulate a frequency of the data clock, and delay the data clock by a delay varied in accordance with a training information signal, and a clock phase comparison unit configured to compare a phase of an output clock of the data clock phase regulation unit with a phase of the system clock, and generate the training information signal according to a result of the comparison. | 12-09-2010 |
20100329405 | TIME-FREQUENCY SYNCHRONIZATION AND FRAME NUMBER DETECTION FOR DMB-T SYSTEMS - A DMB-T receiver supports a single carrier (SC) form of modulation and a multi-carrier form of modulation such as orthogonal frequency division multiplexing (OFDM). Upon receiving a broadcast signal, the DMB-T receiver downconverts the received broadcast signal to a received base-band signal and determines frame timing synchronization from the received signal as a function of frame header mode | 12-30-2010 |
20110019787 | Method and Apparatus Synchronizing Integrated Circuit Clocks - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device. | 01-27-2011 |
20110019788 | CLOCK REGENERATION CIRCUIT AND RECEIVER USING THE SAME - Provided are a clock regeneration circuit and a receiver, wherein difference values (V | 01-27-2011 |
20110026656 | CLOCK SWITCHING CIRCUITS AND METHODS - For use in systems having multiple potential clock sources, circuitry and methods are used for selecting from among multiple clock sources and for preventing switching to an inactive clock source. Such clock switching circuitry and methods are used to detect an activity-status indication of the clock sources, generate a selection based update-enable signal responsive to the detected activity-status indication of the selected clock source, update a clock select input signal in response to a clock switch request for switching to the selected clock source and based on the generated selection based update-enable signal, and control switching to the selected clock source based on the updated clock select input signal. | 02-03-2011 |
20110064178 | JITTER DIGITIZER - A circuit and method for digitizing jitter in a high speed digital signal receives a digital signal using a comparator and supplies a clock signal to a counter. The circuit and method determine the frequency of the digital signal using the clock signal and the counter, and calculate the period of the digital signal based on the frequency (using a logic element). The method and circuit provide a linearized delay for jitter analysis based on the period of the digital signal (using a delay shift circuit) and output a delayed digital signal from the digital signal based on the linearized delay (using a measure delay circuit). The circuit and method supply the digital signal and the delayed digital signal to a programmable unit. The programmable unit comprises flip flops. The circuit and method count transitions of the flip flops within the programmable unit using the counter. The flip flops transition when the digital signal differs from the delayed digital signal. The circuit and method repeat the counting of the transitions of the flip flops for different time intervals to generate a jitter histogram of the digital signal using the logic element. | 03-17-2011 |
20110069799 | REDUNDANT COMMUNICATION TIMING FOR REMOTE NODES - A system and method for redundant synchronizing to a reference clock for data communications. A determination is made whether a first data stream and a second data stream are available. The first data stream and the second data stream are received through opposing directions of a communications ring. A first data packet and second data packet are received at a remote node in response to the first data stream and second data stream being available. A timing characteristic of the first data packet and the second data packet correspond to a tick of a reference clock. The tick of the reference clock is extracted utilizing a timing characteristic of the first data packet or second data packet in response to the first data stream or the second data stream being available. A secondary clock is disciplined with the reference clock by adjusting the secondary clock based on a difference between times measured by the reference clock and the secondary clock to generate a clock signal. The clock signal is communicated to one or more interfaces for distribution. | 03-24-2011 |
20110069800 | TIMING ADJUSTMENT METHOD, USER EQUIPMENT, BASE STATION, AND MOBILE COMMUNICATION SYSTEM - In response to receiving second transmission timing adjustment information during connection processing while the user equipment is performing the connection processing to the base station based on first transmission timing adjustment information, the first transmission timing adjustment information is applied to transmission timing adjustment for transmission processing until a valid term of the first transmission timing adjustment information; and the second transmission timing adjustment information is applied to transmission timing adjustment for transmission processing after the valid term of the first transmission timing adjustment information. | 03-24-2011 |
20110090999 | STREAM DATA RECORDING DEVICE, STREAM DATA EDITING DEVICE, STREAM DATA REPRODUCING DEVICE, STREAM DATA RECORDING METHOD, AND STREAM DATA REPRODUCING METHOD - When recording stream data, index information and time correction information are recorded in correspondence with the stream data. The index information specifies a position of an invalid section in the stream data. The time correction information specifies a time which, supposing that a PCR included in the invalid section was able to be got, a time clock would have shown in synchronization with the PCR. When reproducing the stream data recorded together with the time correction information and the index information, at a position where the invalid section ends, the time clock can be set to a time intended by a broadcasting system, by referencing the index information and the time correction information. | 04-21-2011 |
20110103534 | Frequency Synchronization Methods and Apparatus - Methods and apparatus for have frequency offset estimation and cell search in radio communication systems take into account the time-frequency correlation properties of reference and synchronization signals in such systems. This reduces the probability of misdetection of the physical layer cell ID and frequency offset by accounting for time-frequency ambiguities and evaluating correlation signal peaks in the frequency domain, saving signal processing time and making initial cell search considerably faster. Also, lower-grade and hence cheaper oscillators can be used without causing problems in the user's experience with a receiver, such as a cellular telephone. | 05-05-2011 |
20110110474 | TRANSFER APPARATUS, AND JITTER CONTROL METHOD OF TRANSMISSION SIGNAL - A transfer apparatus includes a receiver to receive an input signal and to extract a clock signal from the input signal, an input signal interruption detector to detect whether an input signal is input, an oscillator, and a frequency setter to set an oscillation frequency of the oscillator such that a difference between the oscillation frequency of the oscillator and a frequency of a frequency division signal into which a clock signal extracted from the input signal is frequency-divided falls out of a passband width of a filter when the input signal interruption detector detects the input of the input signal. | 05-12-2011 |
20110129048 | SYNCHRONIZED SYSTEM FOR DISTRIBUTING AND PROCESSING SIGNALS, IN PARTICULAR AUDIO SIGNALS IN A WIRELESS LOUDSPEAKER NETWORK - The system comprises a master device ( | 06-02-2011 |
20110158366 | Clock Recovery Apparatus - A clock recovery apparatus includes a mask generator configured to generate a plurality of time masks using a multi-phase clock signal and a clock recovery unit configured to select one of the time masks to recover a clock from a data stream. | 06-30-2011 |
20110182390 | Methods and Apparatuses of Serial Link Transceiver Without External Reference Clock - A representative method of serial link transceiver without external reference clock is disclosed. The method includes: receiving an incoming signal; generating a local timing under control of a control code; generating a temperature sensor code by sensing a local temperature; generating a logical signal by detecting a presence of the incoming signal; adjusting the control code in a closed loop manner to make the local timing match that of the incoming signal and recording the control code and a value of the temperature sensor code as part of a template when the logical signal is asserted; and synthesizing the control code in accordance with the template when the logical signal is not asserted. | 07-28-2011 |
20110182391 | Adaptive Filter Using Shifted Reverse Interpolation - In one embodiment, an apparatus comprises an adaptive filter, a timing recovery unit, and a reverse interpolation filter. The adaptive filter has adaptive filter coefficients that are adjusted based on a first error signal at a first sample rate and filters a first signal at the first sample rate to obtain a second signal at the first sample rate. The timing recovery unit interpolates the second signal at the first sample rate to obtain a third signal at a second sample rate; and estimates a partial response signal at the second sample rate corresponding to the third signal. The a reverse interpolation filter interpolates a second error signal at the first sample rate, which is a difference between the third signal and the partial response signal, to obtain the first error signal at the first sample rate for feeding back to the adaptive filter. | 07-28-2011 |
20110216862 | Synchronous Sequential Processing of Multi-Sampled Phase - The synchronous sequential processing of multi-sampled phase (SSP MSP) includes a method, a system and an apparatus for implementing programmable algorithms for analyzing a very wide range of low and high frequency wave-forms. | 09-08-2011 |
20110216863 | RECEIVING APPARATUS AND METHOD FOR SETTING GAIN - A receiving apparatus includes: a clock-data recovery circuit to generate a clock based on receive data and a setting circuit to set a gain of a filtering process to filter a phase difference between the receive data and the clock. | 09-08-2011 |
20110216864 | VARIABLE DELAY CIRCUIT AND DELAY-LOCKED LOOP INCLUDING THE SAME - The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal. | 09-08-2011 |
20110216865 | SYSTEM, APPARATUS, AND METHOD OF FREQUENCY OFFSET ESTIMATION AND CORRECTION FOR MOBILE REMOTES IN A COMMUNICATION NETWORK - A frequency offset estimation and correction apparatus including a frame averaging unit to average a plurality of frequency offset values to obtain a frame offset average for each of a plurality of frames, a re-sampling unit to produce a plurality of interpolated frequency offset values uniformly distributed over a time period of a frame of the plurality of frames based on the frame offset average of the frame and a frame offset average of at least one frame that precedes the frame, and an exponential averaging unit to calculate the estimated frequency offset based on the plurality of interpolated frequency offset values weighted by an exponential averaging coefficient. | 09-08-2011 |
20110228888 | MEDIA CLOCK RECOVERY - A system recovers a local media clock from a master media clock based on time-stamped packets received from a transmitter. The packets may include audio, video, or a combination of both, sampled at a rate determined by the master media clock at the transmitter. Timestamps in the packets may be based on values of a remote real-time counter at the transmitter that is synchronized with a local real-time counter at a receiver. The local media clock may be syntonized with the master media clock through the clock periods. The clocks may be synchronized by syntonizing the clocks and adjusting the phase of the local media clocks based on timestamps and a real-time counter. | 09-22-2011 |
20110243289 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR. | 10-06-2011 |
20110249782 | CLOCK RECOVERY - A clock and data recovery circuit injects a noise waveform into the control loop to offset the data sampling point artificially in order to induce errors. The amplitude of the injected waveform can be varied to ascertain the effect on the bit error rate (BER) so as to be able to evaluate the temporal noise margin. | 10-13-2011 |
20110255643 | Digital Second-Order CDR Circuits - A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases. | 10-20-2011 |
20110261917 | Time Synchronization Using Packet-Layer and Physical-Layer Protocols - In certain embodiments, a slave node in a packet network achieves time synchronization with a master node by implementing a packet-layer synchronization procedure, such as the IEEE1588 precision timing protocol (PTP), to set the slave's local time based on the master's time. The slave's local time is then maintained by implementing a physical-layer syntonization procedure, such as synchronous Ethernet, without relying on the packet-layer synchronization procedure. The packet-layer synchronization procedure may be selectively employed to adjust the slave's local time (if needed) after significant periods of time (e.g., substantially greater than one second). Both the packet-layer synchronization procedure and the physical-layer syntonization procedure are traceable to a common reference timescale (e.g., UTC). Depending on the implementation, the packet-layer synchronization procedure can be, but does not have to be, terminated when not being employed to adjust the slave's local time. | 10-27-2011 |
20110286562 | RECEIVER HAVING CLOCK RECOVERY UNIT BASED ON DELAY LOCKED LOOP - A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal. | 11-24-2011 |
20110293054 | ADAPTIVE CONTROL OF CLOCK SPREAD TO MITIGATE RADIO FREQUENCY INTERFERENCE - In some embodiments an adaptive clocking controller determines a clock spread of a system clock that would result in a lowest total interference between a channel received by a radio receiver and the system clock. A clock generator modifies a spread of the system clock in response to the determined clock spread. Other embodiments are described and claimed. | 12-01-2011 |
20110299643 | Timing Recovery Controller and Operation Method Thereof - A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock detector. The timing error detector includes a first delay unit and a second delay unit, for delaying a data sequence to output a first delay data sequence and a second delay data sequence, respectively, and a timing error calculating module, for generating a timing error value, to adjust a time base. The timing lock detector includes a third delay unit, for delaying the data sequence to output a third delay data sequence, and a timing lock determination module, for generating a timing lock determination result. | 12-08-2011 |
20110311011 | Method and Apparatus for Emulating Stream Clock Signal in Asynchronous Data Transmission - A method and apparatus for emulating stream clock signal in asynchronous data transmission. The inventive subject matter proposes a system consisting of a transmitter module, a receiver module, and a link or network in between. A scheme to generate the emulated stream clock across a wide frequency range is also proposed with the property of controllable deviation from the original stream frequency to meet jitter requirement and fast frequency convergence (minimal number of converging steps). The scheme includes an optional first step to derive a frequency estimation of the stream clock and a second step of continuous adjusting the emulated clock frequency to keep the average frequency equals that of the original stream clock. | 12-22-2011 |
20110317793 | WAVEFORM GENERATOR IN A MULTI-CHIP SYSTEM - In one aspect, an integrated circuit (IC) system includes a receiver IC configured to receive a first clock signal and includes a feedback circuit configured to provide a feedback signal to a driver IC. The IC system also includes the driver IC configured to receive a second clock signal and includes a waveform generator configured to provide synthesized waveforms from DC to K-band, a serializer/deserializer (SERDES) to receive data from the waveform generator and to provide the signal to the receiver IC and a phase selection circuit to provide a phase selection signal to the first integrated circuit based on the feedback signal. The phase selection signal calibrates the signal from the SERDES and provides phase correction to the SERDES. | 12-29-2011 |
20120008725 | TIMING RECOVERY APPARATUS AND METHOD THEREOF - A multimedia processing system for processing a program stream containing a program clock reference information. The system comprises a clock generator, a timer, a modifier, a processing unit, a parser and a compensator. The clock generator generates a clock signal. The timer receives the clock signal and generates a time information. The modifier incorporates a timing reference information into the program stream, wherein the timing reference information is provided according to the time information and the program clock reference information. The processing unit processes the program stream to generate a data stream incorporated with the timing reference information. The parser extracts the timing reference information from the data stream. And, the compensator generates a control signal according to the timing reference information. Wherein the clock generator receives the control signal and adjusts the clock signal. | 01-12-2012 |
20120033773 | Phase Interpolation-Based Clock and Data Recovery for Differential Quadrature Phase Shift Keying - In one embodiment, a method includes receiving N input streams; generating a recovered clock signal based on the input data bits in the N input streams, the recovered clock signal having a clock frequency and a recovered clock phase; generating a clock signal for each one of the N input streams based on the recovered clock signal having the clock frequency and a respective phase at a respective phase offset relative to the recovered clock phase; detecting a phase difference between each of the N input bit streams and the respective N clock signals; and adjusting the phases of the N clock signals to eliminate the respective phase differences, the adjusting comprising shifting the N respective clock phase offsets such that each of the N clock signals is locked to the input data bits in the respective one of the N input streams. | 02-09-2012 |
20120033774 | CDR circuit, reception apparatus, and communication system - Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider. | 02-09-2012 |
20120039427 | Output signal adjustment system - An output signal adjustment system includes a signal adjustment unit, a reference slope generating unit, a slope detecting unit, a voltage-to-current conversion unit, and a control unit. The slope detecting unit compares the slope of the rising and falling edges of the output signal of the reference slope generating unit with that of the signal adjustment unit and outputs a voltage signal. The voltage-to-current conversion unit converts the voltage signal into a current signal. Based on the current signal, the control unit outputs a control signal for controlling the adjustment of the signal adjustment unit to the slope of the rising and falling edges of the output signal. The output signal adjustment system can automatically adjust the slope of the rising and falling edges of the output signal, so that the output signal is insensitive to the packaging, the printed circuit board, the transmission line and other sender loads. | 02-16-2012 |
20120045028 | FEED-FORWARD CARRIER RECOVERY SYSTEM AND METHOD - A method of feedforward phase recovery on a data stream is described. Phase estimation base points are calculated, at a phase detector, for each block of the received data stream. A current phase, at a phase interpolator, between two phase estimation base points. Data stream delays within the phase detector are matched with delays within the phase interpolator. | 02-23-2012 |
20120045029 | RELATIVE TIME MEASUREMENT SYSTEM WITH NANOSECOND LEVEL ACCURACY - A system for instantaneous and continuous nanosecond-level accuracy determination of a relative time offset between at least two non-collocated timing units, the system comprising at least two non-collocated timing units located at known positions, each timing unit comprising a frequency source and a collocated receiver, each frequency source being disciplined at a frequency domain using a time source to generate corrections of the relative frequency drift between the frequency source and the time source. | 02-23-2012 |
20120063556 | Techniques for Varying a Periodic Signal Based on Changes in a Data Rate - A circuit includes a phase detection circuit, a phase adjustment circuit, and a sampler circuit. The phase detection circuit compares a phase of a first periodic signal to a phase of a second periodic signal to generate a control signal. The phase adjustment circuit causes the phase of the second periodic signal and a phase of a third periodic signal to vary based on a variation in the control signal. The sampler circuit samples a data signal to generate a sampled data signal in response to the third periodic signal. The circuit varies a frequency of the third periodic signal to correspond to changes in a data rate of the data signal between at least three different data rates that are based on at least three data transmission protocols. | 03-15-2012 |
20120063557 | Phase adjustment circuit, receiving apparatus and communication system - A phase adjustment circuit includes: a serial-to-parallel conversion section configured to convert serial data including a synchronization pattern inserted into a predetermined position into parallel data in response to a clock; a synchronization-pattern-position detection section configured to detect the position of the synchronization pattern in the parallel data generated by the serial-to-parallel conversion section; and an adjustment section configured to adjust the phases of the parallel data and the clock to conform to a position detected by the synchronization-pattern-position detection section as the position of the synchronization pattern in accordance with information on the position of the synchronization pattern. | 03-15-2012 |
20120069943 | BASE STATION AND CLOCK SYNCHRONIZATION METHOD THEREOF - An enhanced base station and clock synchronization method are provided. The method includes scanning to discover a satellite transmitting a satellite signal and a master base station providing clock synchronization signal, entering, when a satellite having a signal that fulfills predetermined conditions is found, a master mode for receiving the satellite signal to acquire clock synchronization and transmitting a clock synchronization signal to at least one slave base station, and entering, when no satellite having a signal that fulfills the predetermined conditions is found, a slave mode for receiving the clock synchronization signal from the master base station to acquire clock synchronization. The method allows the base station to switch between the master and slave modes dynamically according to variation of the communication environment, resulting in efficient clock synchronization. | 03-22-2012 |
20120099689 | Detection of Jitter in a Communication Network - The present invention is concerned with a method, a network entity and computer program for detecting occurrence of transmission resynchronizations in a network carrying packets subject to variable delays. The present invention is further concerned with adaptively varying the play out time of data packets. According to a method embodying the invention, the packets are received at a network entity and forwarded by the network entity by delaying them of a jitter protection time. The method comprises determining (S | 04-26-2012 |
20120106688 | Data Recovery Architecture (CDR) For Low-Voltage Differential Signaling (LVDS) Video Transceiver Applications - The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links. | 05-03-2012 |
20120121052 | PHASE SELECTOR CAPABLE OF TOLERATING JITTER AND METHOD THEREOF, AND CLOCK AND DATA RECOVERY CIRCUIT - A phase selector capable of tolerating jitters is applied in a clock and data recovery circuit. The phase selector includes a comparing module, a weighting circuit, and a predictor. The comparing module compares a phase-detecting signal and a phase-selecting signal corresponding to the last cycle so as to generate an error signal. The weighting circuit calculates a weighting error signal according to the error signal and a weighting parameter. The phase predictor compares the weighting error signal and predetermined threshold values so as to generate the phase-selecting signal corresponding to the present cycle. When the received input data stream of the clock and data recovery circuit has a small jitter, the phase selector rapidly locks the phase so as to generate the correct phase-selecting signal. When the received input data stream of the clock and data recovery circuit has a large jitter, the phase selector stably generates the phase-selecting signal. | 05-17-2012 |
20120134458 | Frequency detector and method for detecting frequencies - A frequency detector includes a multi-phase clock generation unit, a sampling unit connected to the multi-phase clock generation unit and a digital logic unit connected to the sampling unit. An inputted single-phase clock is received by the multi-phase clock generation unit and transformed into a multi-phase clock. Inputted random data are received by the sampling unit and sampled by the multi-phase clock. Each data bit of the random data is divided into several sampling intervals according to a phase number of the multi-phase clock. The digital logic unit analyses sampling values logically, judges the corresponding sampling interval of each sampling value and outputs signals for indicating that a frequency of the random data is higher or lower than the frequency of the single-phase clock based on differences in the corresponding sampling intervals of the sampling values at two adjacent times. A method for detecting frequencies is further provided. | 05-31-2012 |
20120148002 | PULSE-SIGNAL RECOVERING DEVICE WITH TIME-INTERLEAVING SCHEME - Disclosed is a pulse-signal recovering device with a time-interleaving scheme. Exemplary embodiments of the present invention can improve receive performance of a radar so as to shorten pre-scanning time for roughly determining presence and absence of objects and time consumed to recover received pulse signals in the radar receiver with the sub-sampling scheme by simultaneously sensing signal levels of the received pulse signals at several positions and improve a signal to noise ratio by increasing an averaging rate with respect to the number of same received pulses. | 06-14-2012 |
20120177161 | CALIBRATION OF SYNTHESIZER PHASE USING REFERENCE HARMONIC - Arbitrary phase variations of a shared frequency synthesizer can be calibrated using a reference harmonic each time the shared frequency synthesizer is allocated to a network device to enable one frequency synthesizer to be shared between multiple network devices. On determining that the shared frequency synthesizer has been allocated to the network device, an output frequency of the shared frequency synthesizer can be aligned with a predetermined reference frequency that is associated with an operating frequency band of the network device. A phase correction factor associated with the shared frequency synthesizer can be calculated from a signal calculated based, at least in part, on the output frequency of the shared frequency synthesizer and the predetermined reference frequency. The phase correction factor is applied to a signal received at the network device to correct a phase error associated with the shared frequency synthesizer. | 07-12-2012 |
20120189086 | SERDES JITTER TOLERANCE BIST IN PRODUCTION LOOPBACK TESTING WITH ENHANCED SPREAD SPECTRUM CLOCK GENERATION CIRCUIT - A system for controllably generating jitter in a serial data stream includes a frequency generator and first and second mixers. The frequency generator is configured to output in-phase and quadrature local oscillator signals with a local oscillator frequency of at least about 5 MHz. The local oscillator frequency varies between a selectable minimum frequency and a selectable maximum frequency. The first mixer is configured to mix a fixed frequency clock signal with the in-phase local oscillator signal to output a first mixer output. The second mixer is configured to mix the fixed frequency clock signal with the quadrature local oscillator signal to output a second mixer output. An adder is configured to add the first and second mixer outputs to produce a frequency-modulated clock signal with a frequency that is about the sum of the fixed frequency and the local oscillator frequency and includes a periodic jitter. | 07-26-2012 |
20120207259 | SYNCHRONIZED CLOCK PHASE INTERPOLATOR - A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise. | 08-16-2012 |
20120230457 | CLOCK AND DATA RECOVERY USING LC VOLTAGE CONTROLLED OSCILLATOR AND DELAY LOCKED LOOP - A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. A delay locked loop (DLL) is configured to receive the clock signal from the LCVCO and generate multiple clock phases. A charge pump is configured to control the LCVCO. A phase detector is configured to receive a data input and the multiple clock phases from the DLL, and to control the first charge pump in order to align a data edge of the data input and the multiple clock phases. | 09-13-2012 |
20120250811 | FAST LOCK CLOCK-DATA RECOVERY FOR PHASE STEPS - A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals. | 10-04-2012 |
20120314825 | FAST LOCK SERIALIZER-DESERIALIZER (SERDES) ARCHITECTURE - A serializer-deserializer (SERDES) includes a clock-data recovery block, a control block, and a low-pass filter. The control block contains a state machine that includes a fast convergence mode utilizing an unstable operating point and a slow tracking mode utilizing a stable operating point. The control block is configured to start in the fast convergence mode to allow quickly locking the recovered clock to the incoming data stream by replicating movement commands resulting in multiple phase adjustments for each transition. To facilitate proper operation of the SERDES, the fast convergence mode is exited after N-bits and a slow tracking mode is entered to provide stable operation. The control block accepts filtered transition-data and data-transition phase state signals and converges to a phase aligned state in less than 2N-bits where N represents the number of phases in one data bit. | 12-13-2012 |
20120328063 | Low Latency High Bandwidth CDR Architecture - Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies. | 12-27-2012 |
20120328064 | Phase Tracking in Communications Systems - The present invention includes a method of determining a phase estimate for an input signal having pilot symbols. The method includes receiving a plurality of pilot symbols, and then multiplying two or more pilot symbol slots by corresponding correlator coefficients to correct a phase estimate of the input signal. | 12-27-2012 |
20130003906 | METHOD AND SYSTEM FOR JITTER REDUCTION - Embodiments relate to systems and methods for reducing jitter caused by frequency modulation of a clock signal including modulating the frequency of the clock signal based on a predetermined modulation signal m(t), and compensating an accumulated jitter J(t) caused by the frequency modulation of the clock signal such that an absolute value of the accumulated jitter J(t) never exceeds a predetermined jitter limit J | 01-03-2013 |
20130129025 | METHOD AND APPARATUS FOR JITTER BUFFERING WITHIN A COMMUNICATION SYSTEM - A method and apparatus for performing jitter buffering is provided herein. During operation, a system will utilize variable-length jitter buffers within each receiver. Each receiver will then be assigned an appropriate jitter-buffer size based upon system constraints. In one embodiment of the present invention jitter-buffer size is adjusted on a per call (or even per call/speech segment) basis and is based on both the source and destination capabilities. | 05-23-2013 |
20130129026 | CHIRP RECEIVER UTILIZING PHASE PRECESSED CHIRP SIGNALS - A chirp receiver processes broadcast chirp signals in the frequency domain to distinguish direct path signals from multipath signals. The receiver processes received chirp signals consisting of respective pulsed frequency sweeps by combining the signals with a synchronized local chirp signal and phase adjusting and concatenating the results over multiple sweeps based on estimated clock phase errors and expected phase rotations of the direct path signals, and produces a sine wave. The phase adjustment and concatenation allows the use of longer Fast Fourier Transforms, which provide increased accuracy of frequency estimation and separate component signals that are very close in frequency. The frequency corresponding to the direct path signal is identified by the lowest frequency bin in which power is above a predetermined noise threshold. The receiver then determines a time delay based on the identified frequency and uses the time delay to calculate accurate clock phase error and position. | 05-23-2013 |
20130136219 | CLOCK FREQUENCY ERROR DETECTING DEVICE - A clock frequency error detecting device includes a system storage portion which stores a synchronization system based on at least one of several types of frame synchronization signals included in a received signal in which a frame synchronization signal in each frame includes a part obtained by shifting of a frame synchronization signal of another frame by a symbol by using a predetermined rule; a pattern matching portion which performs pattern matching between the received signal and the synchronization system; a symbol counter which outputs a symbol number; a timing detection portion which detects the frame synchronization signal of each frame based on a pattern matching processing result and to output the symbol number at the detection timing; and a frequency error detection portion which detects a change of the symbol number and to detect a clock frequency error of the symbol period based on the detection. | 05-30-2013 |
20130188762 | Clock Data Recovery With Out-Of-Lock Detection - The disclosed clock-data recovery architecture includes out-of-lock (including false lock) detection. Out-of-lock detection is accomplished by sampling retimed/recovered data with positive and negative edges of the received data. In example embodiments, an out-of-lock condition is determined either by detecting the occurrence of, or counting, missed edges corresponding to the failure of received data sampling to detect corresponding positive/negative edges of the retimed/recovered data. | 07-25-2013 |
20130202072 | Data Transfer Clock Recovery for Legacy Systems - The present invention provides method and apparatus for adapting a relatively high data rate second order serdes receiver to receive relatively low data rate serial data, the receiver having jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the serdes receiver for frame realignment; and supplying to an output of the serdes receiver one of the bits of said same value from each frame at the low data rate. | 08-08-2013 |
20130208839 | Clocking Scheme for a Wireless Communication Device - The invention relates to a method and a system for generating clock signals in a wireless communication device. The method includes generating an uncorrected reference clock signal, generating at least one frequency correction value corresponding to a frequency error in the uncorrected reference clock signal, and generating at least one radio frequency clock signal based on the uncorrected clock signal and the at least one frequency correction value, for receiving and transmitting radio frequency signals. The method further comprise generating, independently of the at least one radio frequency clock signal, a baseband timing signal based on the uncorrected reference clock signal and the at least one frequency correction value, for clocking base-band signal processing circuits. | 08-15-2013 |
20130235962 | MIMO ANTENNA CALIBRATION DEVICE, INTEGRATED CIRCUIT AND METHOD FOR COMPENSATING PHASE MISMATCH - A multiple input multiple output (MIMO) calibration device ( | 09-12-2013 |
20130279637 | Method and System for A Reference Signal (RS) Timing Loop for OFDM Symbol Synchronization and Tracking - Aspects of a method and system for a reference signal (RS) timing loop for OFDM symbol synchronization and tracking may include tracking symbol timing in an Orthogonal Frequency Division Multiplexing (OFDM) signal based on at least a reference symbol set. A receiver timing may be adjusted based on at least the symbol timing. The symbol timing may be tracked by generating an output signal as a function of a guard time Δt | 10-24-2013 |
20130294555 | METHOD AND APPARATUS FOR DESKEWING DATA TRANSMISSIONS - The present invention discloses a method and apparatus for addressing the issue of clock skew in a data signal while making efficient use of space on an integrated chip (IC) by utilising a physical delay line controlled by a state machine in conjunction with pre-requisite chip architecture. The pre-requisite chip architecture samples the incoming data signal in response to a clocking signal input from the physical delay line; the physical delay line responds to commands from the state machine to increment the delay of the physical delay line to produce samples which describe the incoming data signal and delineate its data valid window. | 11-07-2013 |
20140044225 | CLOCK AND DATA RECOVERY USING LC VOLTAGE CONTROLLED OSCILLATOR AND DELAY LOCKED LOOP - A clock and data recovery (CDR) circuit includes an inductor-capacitor voltage controlled oscillator (LCVCO) configured to generate a clock signal with a clock frequency. The CDR circuit further includes a delay locked loop (DLL) configured to receive the clock signal from the LCVCO and generate multiple clock phases and a first charge pump configured to control the LCVCO. The CDR circuit further includes a phase detector configured to receive a data input and the multiple clock phases from the DLL, and to align a data edge of the data input and the multiple clock phases. | 02-13-2014 |
20140064422 | CDR CIRCUIT AND TERMINAL - Embodiments of the present invention disclose a CDR circuit and a terminal, where the CDR circuit is configured to perform clock synchronization in a terminal with EEE function, and the CDR circuit includes: a phase detector, a first phase signal selector, a loop filter, a numerical controlled oscillator, a second phase signal selector, a phase signal generator, and a state machine. In the embodiments of the present invention, after the terminal enters a REFRESH state from a QUIET state, the CDR circuit can implement clock synchronization with a peer end without waiting for the loop filter and the numerical controlled oscillator to be converged, but the phase signal generator generates a phase signal satisfying a preset clock synchronization condition, and the second phase signal selector selects the phase signal satisfying the preset clock synchronization condition as the phase selection signal of the CDR. | 03-06-2014 |
20140079170 | Method and apparatus for controlling the data rate of a data transmission between an emitter and a receiver - A method of controlling the data rate of a data transmission between an emitter and a receiver, wherein data rate adaptation control commands may be sent using a return path from the receiver to the emitter, which comprises monitoring at least one receiving condition at the receiver; determining at least one threshold on said receiving conditions to trigger data rate adaptation control commands; estimating the transmission time of the data rate adaptation control commands from the receiver to the emitter and adjusting the threshold on these receiving conditions to trigger data rate adaptation control commands based on said estimation of the transmission time from the receiver to the emitter. | 03-20-2014 |
20140105343 | CIRCUIT, METHOD AND MOBILE COMMUNICATION DEVICE - A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is configured to operate in a free-running mode of operation. The variable phase adjuster is configured to provide a phase adjusted signal, a phase of which is shifted with respect to a phase of an output signal of the oscillator, or with respect to a phase of a signal derived from the output signal of the oscillator. The feedback loop is configured to provide a control value for controlling the variable phase adjuster based on the phase adjusted signal and a reference oscillator signal to counteract a phase error of the phase adjusted signal. | 04-17-2014 |
20140105344 | METHOD AND APPARATUS FOR RADIO FREQUENCY (RF) PULSE SYNCHRONIZATION IN SUPER REGENERATIVE RECEIVER (SRR) - A method for radio frequency (RF) pulse synchronization in a super regenerative receiver (SRR), includes receiving an input signal including an asymmetric preamble, and estimating a phase difference between the input signal and a quench signal based on the asymmetric preamble. The method further includes compensating for the phase difference. | 04-17-2014 |
20140133615 | REAL-TIME CLOCK FREQUENCY CORRECTION DEVICES - A real-time clock frequency correction device includes: a quartz oscillator outputting an oscillating signal including a plurality of oscillating pulses with a frequency; a control unit setting a first integer, a second integer, a first number corresponding to the first integer, and a second number corresponding to the second integer according to the frequency, wherein the first integer is a minimum integer that is larger than the frequency, and the second integer is a maximum integer that is smaller than the frequency; a multiplexer outputting the first integer for the first number of times and the second integer for the second number times; and a counter, coupled to the multiplexer and the quartz oscillator, for counting the number of oscillating pulses according to one of the first integer and the second integer and thereby outputting a pulse. | 05-15-2014 |
20140140458 | Digital Second-Order CDR Circuits - A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases. | 05-22-2014 |
20140140459 | SYSTEM AND METHOD FOR PERFORMING TIMING CONTROL - A timing control apparatus includes an adder and a comparator. The adder adds unused time error in each of a plurality of periods to form a cumulative value, and the comparator compares the cumulative value to a reference value. The unused time error is computed during operation of a first clock, and a control signal is generated to switch from the first clock to a second clock based on an output of the comparator. The frequency of the first clock is greater than a frequency of the second clock. | 05-22-2014 |
20140146932 | LOW POWER DIGITAL PHASE INTERPOLATOR - Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs. | 05-29-2014 |
20140153680 | MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT - A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use. | 06-05-2014 |
20140153681 | INTER-INTEGRATED CIRCUIT-SLAVE INTERFACE, AND METHOD FOR OPERATING AN INTER-INTEGRATED CIRCUIT-SLAVE INTERFACE | 06-05-2014 |
20140153682 | DIGITAL PHASE DETECTOR WITH ZERO PHASE OFFSET - An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal. | 06-05-2014 |
20140161215 | DEVICE AND METHOD FOR ESTIMATING CARRIER FREQUENCY OFFSET OF OFDM SIGNALS TRANSMITTED AND RECEIVED THROUGH PLURALITY OF POLARIZED ANTENNAS - Provided are a device and method for estimating carrier frequency offset of OFDM signals transmitted and received through a plurality of polarized antennas that may accurately estimate carrier frequency offset used for carrier frequency synchronization acquisition when there is interference between polarized waves. | 06-12-2014 |
20140161216 | Apparatus and Method for Reducing Jitter in Periodic Signals - The present invention provides an apparatus and method for reducing jitter in a periodic signal. The apparatus comprises: a frequency discriminator configured to receive the periodic signal and feedback of an output signal of the apparatus and calculate an estimate value for a length of a current period of the periodic signal; a phase discriminator configured to receive the periodic signal and determine an adjustment factor for the length of the current period of an input signal according to the input signal in a previous period of the periodic signal and the output signal in the previous period of the apparatus; and an adjustor configured to determine the period length of the output signal in the current period according to the estimate value for the length of the current period and the adjustment factor for the length of the current period. | 06-12-2014 |
20140185725 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 07-03-2014 |
20140211898 | PHASE INTERPOLATION CIRCUIT AND RECEIVER CIRCUIT - A phase interpolation circuit includes: a first circuit configured to generate a first intermediate signal by weighting first reference signals having different phases with a first ratio and combining weighed first reference signals; a second circuit configured to generate a second intermediate signal by weighing second reference signals having phases different from the phases of the first reference signals by a certain value with a second ratio equal to the first ratio and combining weighted second reference signals; and a third circuit configured to generate an output signal by combining the first intermediate signal and the second intermediate signal. | 07-31-2014 |
20140270030 | EYE WIDTH MEASUREMENT AND MARGINING IN COMMUNICATION SYSTEMS - Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected. | 09-18-2014 |
20140270031 | PHASE INTERPOLATOR WITH LINEAR PHASE CHANGE - Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes. | 09-18-2014 |
20140286468 | METHOD AND APPARATUS FOR COMPENSATING FOR VARIABLE SYMBOL TIMING USING CYCLIC PREFIX IN NON-SYNCHRONIZED OFDM SYSTEM - Disclosed are a method and apparatus for estimating symbol timing in a non-synchronized OFDM system. The present invention includes synchronizing a frame of a received signal, estimating the symbol timing of each symbol of the frame based on the synchronization, compensating for the symbol timing using a phase difference attributable to a Symbol Timing Offset (STO), variably changing within a Cyclic Prefix (CP) interval due to the frequency offset of a sampling clock and thermal noise, and performing channel equalization using a preamble based on output including corrected phase rotation. | 09-25-2014 |
20140301515 | CLOCK AND DATA RECOVERY TOLERATING LONG CONSECUTIVE IDENTICAL DIGITS - A high performance CDR circuit. The circuit includes a first and second sampler, a first and second charge-pump coupled to the first and the second sampler, a capacitor coupled to the first charge pump, and a filter coupled to the second charge pump. A VCO circuit is coupled to the first charge pump and the second charge pump, wherein a path for setting a frequency is provided by the first charge pump and the capacitor, and wherein a path for phase is provided by the second charge pump, wherein a voltage of the capacitor is stable to enable the VCO to tolerate CIDs. | 10-09-2014 |
20140301516 | ORTHOGONAL TRANSFORM ERROR CORRECTOR - A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal. | 10-09-2014 |
20140314191 | DISTRIBUTED PHASE-CORRECTION CIRCUIT - A distributed phase-correction circuit is described. This distributed phase-correction circuit reduces jitter in a delay line by averaging edge delay through local feedback of signals internal to the delay line. In particular, the distributed phase-correction circuit includes a delay line with multiple cascaded first phase-alignment elements that each delay the input signal by a fraction of the period (i.e., that perform distributed phase correction) based on feedback signals from a second delay line. | 10-23-2014 |
20150010122 | TRANSMITTER, RECEIVER AND SYSTEM INCLUDING THE SAME - A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal. | 01-08-2015 |
20150016580 | POINT TO MULTI-POINT CLOCK-FORWARDED SIGNALING FOR LARGE DISPLAYS - A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter. | 01-15-2015 |
20150023460 | INTERFEROMETRIC PRECISE TIMING DISTRIBUTION WITH A PRECISION PHASE DETECTOR - A method distributing data in a network is provided. The method comprises measuring the path lengths between a reference clock and a plurality of remote destinations and sending a timing signal from the reference clock to the plurality of remote destinations. The method further comprises measuring the phase between the reference clock and a return signal from each of the plurality of remote destinations and adjusting the phase of the data such that each remote destination receives the data within a skew tolerance. | 01-22-2015 |
20150030113 | Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets - A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offset in phase from one another to the respective clock inputs of the edge sampler 105 and the data sampler 145. The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals. | 01-29-2015 |
20150036775 | METHODS AND CIRCUITS FOR REDUCING CLOCK JITTER - A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly. | 02-05-2015 |
20150043697 | Delay Compensation for Variable Cable Length - The present application discloses a time distribution device capable of providing a synchronized time signal to a plurality of end devices connected to the time distribution device with cables of various lengths. The time distribution device may receive a time signal, generate a time reference based on the received time signal, compensate the time reference for hardware delay, and overcompensate the time reference for a delay caused by a maximum cable length. Prior to being distributed to various end devices, each being connected with the time distribution device by cables of varying length, this overcompensated time reference may then be delayed by an amount based on the cable length connecting each respective end device such that the arrival of each of the synchronized time references at the various end devices is synchronized. | 02-12-2015 |
20150071395 | COMPLEXITY REDUCED FEED FORWARD CARRIER RECOVERY METHODS FOR M-QAM MODULATION FORMATS - The present disclosure provides a method of carrier phase error removal associated with an optical communication signal. The method includes estimating and removing a first phase angle associated with an information signal using coarse phase recovery, the information symbol being associated with a digital signal, the digital signal representing the optical communication signal; estimating a carrier frequency offset between a receiver light source and a transmitter light source by using the estimated first phase angle, the carrier frequency offset being associated with the information signal; removing carrier phase error associated with the carrier frequency offset; and estimating and removing a second phase angle associated with the information signal, the estimated second phase angle being based on the estimated first phase angle and the estimated carrier frequency offset. | 03-12-2015 |
20150078500 | METHOD OF CORRECTING TIME MISALIGNMENT BETWEEN ENVELOPE AND PHASE COMPONENTS - Provided is a method of correcting a time misalignment between envelope and phase components in a transmitting apparatus which separates envelope and phase components of a signal, processes them, and then recombines them to transmit the recombined signal. For this, in a method of correcting a time misalignment between envelope and phase components according to an embodiment of the present invention, a time misalignment is corrected by applying a time delay to at least one of envelope and phase components in digital and analog signal processing operations, or applying a time delay to an envelope or phase component by a pre-processing operation. | 03-19-2015 |
20150103964 | CDR CIRCUIT AND SERIAL COMMUNICATION INTERFACE CIRCUIT - The CDR circuit | 04-16-2015 |
20150103965 | TEMPERATURE COMPENSATED CARRIER OFFSET CORRECTION OF A RECEIVED SIGNAL - Apparatuses, methods and systems for mitigating carrier offset of a received signal are disclosed. One embodiment of a receiver includes a controller operative to determine that a communication signal being received is from a desired transmitter, and to determine a carrier offset correction based on prior reception of communication signals from the desired transmitter, comprising retrieving a carrier offset of the desired transmitter from one or more stored carrier offsets based on previous communication with the desired transmitter and a temperature of the receiver. The receiver further includes a receiver chain operative to receive the communication signal from the desired transmitter, and to generate a carrier offset corrected received signal based on the retrieved carrier offset by applying the carrier offset correction to the received communication signal. The receiver is operative to synchronize to the carrier offset corrected received communication signal. | 04-16-2015 |
20150110232 | USING DECISION FEEDBACK PHASE ERROR CORRECTION - Methods and systems are provided for using decision feedback phase error correction during signal processing. When an input signal comprises a plurality of sub-carriers, each of the plurality of sub-carriers may be processed separately, wherein the processing may comprise determining for each one of the plurality sub-carriers error related information; and the determined error related information may be applied as separate feedback, such as to allow separately adjusting subsequent processing of the corresponding one of the plurality of sub-carriers. The error related information may comprise phase error related information. At least part of the error related information based on data carried by the corresponding one of the plurality of sub-carriers. The plurality of sub-carriers comprises orthogonal frequency-division multiplexing (OFDM) based sub-carriers. Error related information obtained from processing of at least some of the plurality of sub-carriers may be shared. | 04-23-2015 |
20150117581 | RECEPTION APPARATUS, RECEPTION METHOD, AND PROGRAM - Provided is a reception apparatus including: a correction unit that corrects phase compensation for each one of multiple phase-compensated segments that are connected one after another, in which the correction unit includes a timing generation unit that, based on a phase of a known signal, generates a timing at which an amount of the phase compensation is initialized, an amount-of-correction generation unit that, based on the phase of the known signal, generates an amount of correction for correcting the amount of the phase compensation, and a phase correction unit that performs phase correction on the phase compensation using the amount of the correction that is generated by the amount-of-correction generation unit. | 04-30-2015 |
20150124918 | METHOD FOR COMPENSATING TIMING ERRORS OF REAL-TIME CLOCKS - The present invention relates to a method for compensating timing errors of real-time clocks, which comprises a compensating step, wherein in step 1, assign CNT to be 0 and execute step two; in step 2, assign FLAG to be 1 when a rising edge of 1 Hz clock is arrived and execute step 3; in step 3, judge FLAG and M3, if FLAG=1 and M3<0, execute step 4 while waiting until CNT=S4; if FLAG=1, CNT=0 and M3>0, execute step 5; otherwise execute step 2; in step 4, execute an assignment operation, CNT=0, M3=M3+S4, FLAG=0 and restart step 2; in step 5, execute an assignment operation, CNT=S4, M3=M3−S4, FLAG=0, and restart step 2. A sampling frequency of relative errors ERR of the present invention is adjustable, and a compensatory accuracy is much higher. | 05-07-2015 |
20150139376 | SIGNAL PROPAGATION SYSTEM AND METHOD OF REDUCING ELECTROMAGNETIC RADIATION EMISSIONS CAUSED BY COMMUNICATION OF TIMING INFORMATION - A signal propagation system for communicating timing information comprises a processing resource ( | 05-21-2015 |
20150139377 | LOW POWER DIGITAL PHASE INTERPOLATOR - Described herein is an apparatus, method and system corresponding to relate to a low power digital phase interpolator (PI). The apparatus comprises: a digital mixer unit to generate phase signals from a series of input signals, the phase signals having phases which are digitally controlled; a poly-phase filter, coupled to the digital mixer unit, to generate a filtered signal by reducing phase error in the phase signals; and an output buffer, coupled to the poly-phase filter, to generate an output signal by buffering the filtered signal. The low power digital PI consumes less power compared to traditional current-mode PIs operating on the same power supply levels because the digital PI is independent of any bias circuit which are needed for current mode PIs. | 05-21-2015 |
20150146832 | Main Clock High Precision Oscillator - A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator. | 05-28-2015 |
20150146833 | METHOD AND APPARATUS FOR CONTROLLING SUPPLY VOLTAGE OF CLOCK AND DATA RECOVERY CIRCUIT - The present invention relates to a method and apparatus for controlling supply voltage of clock and data recovery circuit. According to an embodiment, there is provided an apparatus for controlling supply voltage of clock and data recovery circuit comprising a frequency lock detector configured to compare a frequency of a recovered clock signal with a frequency of a reference clock signal periodically and output a digital value corresponding to the result determined as that the frequency of recovered clock signal is higher than, lower than, or equal to the frequency of a reference clock signal; a digital counter configured to receive the digital value from the frequency lock detector and convert to a counter value based on the digital value; a digital-to-analog converter configured to receive the counter value from the digital counter and generate analog reference voltage corresponding to the counter value; a DC-DC converter configured to receive the analog reference voltage from the digital-to-analog converter and output supply voltage corresponding to the analog reference voltage; and a clock and data recovery circuit configured to receive the supply voltage from the DC-DC converter and generate the recovered clock signal and recovered digital data from a received digital input signal by using the supply voltage. | 05-28-2015 |
20150295704 | RF Carrier Synchronization and Phase Alignment Methods and Systems - A method comprising generating a baseband information signal by mixing a received modulated carrier signal with a local oscillator (LO) signal having an LO frequency; obtaining baseband signal samples of the baseband information signal having a baseband signal magnitude and a baseband signal phase; determining a cumulative phase measurement associated with baseband signal samples having a baseband signal magnitude greater than a threshold; and, applying a correction signal to compensate for an LO frequency offset of the LO frequency based on the cumulative phase. | 10-15-2015 |
20150304098 | MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT - A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use. | 10-22-2015 |
20150304099 | Inter-Signal Delay Processing Method and Device - Disclosed are an intra-signal delay processing method and device. The method includes: a bit error rate of each path of serial digital signal of a plurality of paths of serial digital signals is determined at N sampling clocks, wherein the each sampling clock in the N sampling clocks is a sum of a recovered clock and N interpolation phases, and the N interpolation phases are within one preset clock unit; an interpolation phase corresponding to the each path of serial digital signal is determined according to the bit error rate, wherein the sampling clock position is within one preset clock unit; and a clock of the each path of serial digital signal is adjust by using the interpolation phase corresponding to the each path of serial digital signal. The disclosure improves the reliability of data transmission. | 10-22-2015 |
20150312023 | Time Signal Propagation Delay Correction - Disclosed herein are a variety of systems and methods for correcting for propagation delay in time signals used in connection with an electric power generation and delivery system. According to various embodiments, a device consistent with the present disclosure may determine an estimated propagation delay between an accurate time source and a receiving device. The propagation delay may be determined based on a variety of transmission parameters including, for example, communication channel type and/or length. A corrected time signal may be generated by advancing a reference incitation such as an “on-time” reference and/or “start-of-second” reference included in the time signal by an amount associated with the propagation delay. The corrected time signal may then be transmitted to the receiving device. | 10-29-2015 |
20150318978 | CLOCK AND DATA RECOVERY WITH HIGH JITTER TOLERANCE AND FAST PHASE LOCKING - Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal. | 11-05-2015 |
20150333902 | DATA TRANSFER CLOCK RECOVERY FOR LEGACY SYSTEMS - The present disclosure provides methods and apparatus for adapting a relatively high data rate second order SERDES receiver to receive relatively low data rate serial data, the receiver having a jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the SERDES receiver for frame realignment; and supplying to an output of the SERDES receiver one of the bits of said same value from each frame at the low data rate. | 11-19-2015 |
20150349944 | CIRCUIT ARRANGEMENT AND METHOD FOR CLOCK AND/OR DATA RECOVERY - In order to provide a circuit arrangement ( | 12-03-2015 |
20150358146 | DESIGN APPARATUS AND DESIGN METHOD - A correlation between noise injection time at which a power supply noise signal is applied to a clock path and a path delay of the clock path at the time of the power supply noise signal being applied is acquired. Furthermore, noise injection time width based on a clock signal inputted from a circuit arranged before the clock path to the clock path is set. The differences between path delays within the set noise injection time width are calculated by the use of the acquired correlation and the maximum value of the differences is estimated to be clock jitter of the clock path. The estimated clock jitter is smaller than the worst value and overestimation is prevented. | 12-10-2015 |
20150365094 | LOW POWER LOSS OF LOCK DETECTOR - A loss of lock detector that includes a logic gate, a voltage-to-current converter coupled to the logic gate, a capacitor coupled to the converter, and a comparator coupled to the capacitor. The logic gate is configured to receive a first error signal and a second error signal from a phase detector, perform an AND function of the first and second error signals, and generate a gate output signal. The converter is configured to receive the gate output signal and generate a stream of current pulses representative of the gate output signal. The capacitor is configured to receive the stream of current pulses and generate a DC signal representative of the stream of current pulses. The comparator is configured to compare the DC signal to a reference signal and output a lock signal. | 12-17-2015 |
20160013927 | HYBRID CLOCK AND DATA RECOVERY CIRCUIT AND SYSTEM INCLUDING THE SAME | 01-14-2016 |
20160028536 | METHOD AND SYSTEM FOR MODULATION-INDEPENDENT CARRIER PHASE RECOVERY - A system for carrier phase recovery, including a receiver for receiving one or more frames of L symbols. A phase estimator performs carrier phase estimation for the received frames of L symbols, and the resulting carrier phase estimates are stored in a non-transitory computer-readable storage medium. One or more rotators de-rotates the received frames of L symbols by one or more of the carrier phase estimates, and a data processor calculates a sum of the outputs of the L de-rotated signals raised to an n | 01-28-2016 |
20160036583 | SYNCHRONIZATION METHOD, AND CORRESPONDING DEVICE AND INTEGRATED CIRCUIT - The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a sync signal by applying to the sync signal a digital delay, which can add to the delay that is subject to time spread. | 02-04-2016 |
20160043860 | CLOCK AND DATA RECOVERY APPARATUS - A clock and data recovery apparatus which includes a voltage controlled delay line (VCDL), a phase detector (PD) and a control voltage generating circuit is provided. The VCDL generates a plurality of clock signals with different phases according to a reference clock signal and a control voltage. The PD detects the phase relationship between a first input signal and a second input signal, and produces a detection result. A data signal or one of the clock signals is used as the first input signal, and one or more of the clock signals is/are used as the second input signal. The control voltage generating circuit generates the control voltage to the VCDL according to the detection result of the PD. | 02-11-2016 |
20160043861 | Phase Control Block for Managing Multiple Clock Domains in Systems with Frequency Offsets - A circuit for performing clock recovery according to a received digital signal | 02-11-2016 |
20160050064 | Method, Apparatus, Mobile Communication Terminal, Computer Program and Storage Medium for Adjusting Frequency Error of Terminal - Handling a frequency error (FEQ) of a terminal which includes a plurality of modems using a same clock source includes: obtaining the FEQ, which is a difference between a carrier frequency of a received signal and a nominal frequency for each modem; obtaining a FEQ threshold of the received signal in a current service based on the FEQ; obtaining an adjusted value of the clock source corresponding to each modem based on the FEQ and the FEQ threshold; obtaining a synthesized adjusted value of the clock source based on the adjusted values of all the moderns; and adjusting the frequency of the clock source based on the synthesized adjusted value of the clock source. The FEQ of the mobile communication terminal can be quickly corrected by adjusting the clock source's frequency, and, by considering the FEQ of all the modems, the modems' performances may be balanced. | 02-18-2016 |
20160065359 | USING DECISION FEEDBACK PHASE ERROR CORRECTION - Methods and systems are provided for using decision feedback phase error correction during signal processing. When an input signal comprises a plurality of sub-carriers, each of the plurality of sub-carriers may be processed separately, for each one of the plurality sub-carriers error related information may be determined separately, based on the processing of that sub-carrier. Subsequent processing of at least one of the plurality of sub-carriers may then be adjusted based on determined error related information corresponding to one or more sub-carriers. In this regard, the subsequent processing of the at least one sub-carrier may be adjusted based on determined error related information for that sub-carrier, based on determined error related information for at least one other sub-carrier, or based on determined error related information corresponding to all of the sub-carriers. The error related information may comprise phase error related information. | 03-03-2016 |
20160065360 | RADIO COMMUNICATION APPARATUS - A radio communication apparatus includes an adjustment unit, a transmitting unit, a correction unit, and a control unit. The adjustment unit adjusts a first frequency of a clock signal to generate a second clock signal having a second frequency using an adjustment value. The transmitting unit transmits the second clock signal having the second frequency. The correction unit corrects the second frequency of the second clock signal that is transmitted by the transmitting unit, which results in a third frequency, using a correction value. The control unit sets the adjustment value according to a receive frequency of a receive signal, obtains the correction value from the adjustment value, and sets the correction value. | 03-03-2016 |
20160065394 | SERIALIZER/DESERIALIZER WITH INDEPENDENT EQUALIZATION ADAPTATION FOR REDUCING EVEN/ODD EYE DISPARITY - A method for reducing a disparity between even and odd eye characteristics in recovered data includes: receiving an input serial data stream; performing independent data slicing of even and odd components in the serial data stream to generate corresponding even and odd discrete-time data samples, respectively; performing independent error slicing of even and odd components in the serial data stream to generate corresponding even and odd discrete-time error samples, respectively; deserializing the even and odd discrete-time data and error samples to generate the recovered data and recovered error, respectively; and controlling respective offsets for error slicing of the even and odd components independently so as to reduce the disparity between even and odd eye characteristics in the recovered data. | 03-03-2016 |
20160080139 | RECEIVERS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The receiver includes a first buffer configured to buffer a data to generate a first internal data, a first delay unit configured to retard the first internal clock signal by a first delay period to generate a first delayed internal clock signal, and a second buffer configured to buffer the first internal data to generate a first input data. | 03-17-2016 |
20160094333 | DATA RECOVERY CIRCUIT - In a data recovery circuit, the position of an edge is detected from parallel data acquired by oversampling data received through serial communication, the position of a next edge is estimated, the estimated position of the edge is compared with the detected position of the actual edge, and the sampling position of the parallel data is adjusted based on a result of the comparison. As a result, an oversampling clock can be set to a maximum frequency, and accordingly, the precision of the data recovery circuit can be improved. | 03-31-2016 |
20160112183 | SIGNAL SAMPLING TIMING DRIFT COMPENSATION - Method and apparatus for signal sampling timing drift compensation are provided. Raw time values or deviations between clock and data are measured and filtered to generate filtered time information, and the filtered time information is compared to an upper bound and a lower bound. If the filtered time information is outside the upper and lower bounds, then an amount of timing compensation for the clock is computed. A signal is sent to reset the clock based on the amount of timing compensation. | 04-21-2016 |
20160112184 | CLOCK AND DATA RECOVERY CIRCUIT AND METHOD - A clock and data recovery (CDR) circuit is provided, and includes a sampling module, an error sampler, a phase detect module, and a phase adjust module. The sampling module generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect module receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect module stops transmitting the corrective signal. The phase adjust module generates and adjusts the first and the second clock signal according to the corrective signal. | 04-21-2016 |
20160119111 | System and Apparatus for Clock Retiming with Catch-Up Mode and Associated Methods - An apparatus includes analog or mixed-signal circuitry that operates in response to a first signal, and digital circuitry that operates in response to a second signal. The apparatus further includes a signal retiming circuit. The signal retiming circuit retimes an output signal of a digital signal source to reduce interference between the digital circuitry and the analog or mixed-signal circuitry by retiming edges of the output signal of the digital signal source to fall on cycle boundaries of the first signal. | 04-28-2016 |
20160127119 | OUTDOOR UNIT RESONATOR CORRECTION - A system comprises a microwave backhaul outdoor unit having a first resonant circuit, phase error determination circuitry, and phase error compensation circuitry. The first resonant circuit is operable to generate a first signal characterized by a first amount of phase noise and a first amount of temperature stability. The phase error determination circuitry is operable to generate a phase error signal indicative of phase error between the first signal and a second signal, wherein the second signal is characterized by a second amount of phase noise that is greater than the first amount of phase noise, and the second signal is characterized by a second amount of temperature instability that is less than the first amount of temperature instability. The phase error compensation circuitry is operable to adjust the phase of a data signal based on the phase error signal, the adjustment resulting in a phase compensated signal. | 05-05-2016 |
20160142199 | HIGH-SPEED INTERFACE APPARATUS AND DESKEW METHOD THEREOF - A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode. | 05-19-2016 |
20160164666 | CLOCK AND DATA RECOVERY CIRCUIT AND SYSTEM USING THE SAME - A clock and data recovery circuit may include a phase detection unit, a first filtering unit, a second filtering unit, and a phase interpolation unit. The phase detection unit compares a clock signal with data and generates a plurality of early phase detection signals and a plurality of late phase detection signals. The first filtering unit generates an early enable signal and a late enable signal based on the number of early phase detection signals and the number of late phase detection signals that have been generated. The second filtering unit generates an up signal and a down signal based on a difference between the number of times that the early enable signal has been generated and the number of times that the late enable signal has been generated. The phase interpolation unit controls the phase of the clock signal according to the up signal and the down signal. | 06-09-2016 |
20160164667 | CLOCK AND DATA RECOVERY CIRCUIT AND SYSTEM USING THE SAME - A clock and data recovery circuit may include: a phase detection unit configured to generate an early phase detection signal and a late phase detection signal by comparing a clock signal and data; a filtering unit configured to generate an up signal and a down signal based on a number of generation times of the early phase detection signal and a number of generation times of the late phase detection signal; a phase information summing unit configured to receive an output of the filtering unit at each cycle of the clock signal, and generate first and second phase control signals by summing up numbers of the up signals and the down signals received from the filtering unit during a summing-up time; and a phase interpolator configured to adjust a phase of the clock signal according to the first and second phase control signals. | 06-09-2016 |
20160183211 | FREQUENCY DEVIATION COMPENSATION SCHEME, FREQUENCY DEVIATION COMPENSATION METHOD, AND STORAGE MEDIUM | 06-23-2016 |
20160254903 | CIRCUIT FOR DYNAMICALLY ADAPTIVE BIT-LEVELING BY INCREMENTAL SAMPLING, JITTER DETECTION, AND EXCEPTION HANDLING | 09-01-2016 |