Entries |
Document | Title | Date |
20080218986 | Increased Stand-Off Height Integrated Circuit Assemblies, Systems, and Methods - Disclosed are integrated circuit assemblies with increased stand-off height and methods and systems for their manufacture. Methods of the invention provide for assembling a semiconductor device by aligning a die with a substrate and interposing solder between corresponding substrate and die bond pads. A lifting force is applied to the die during heating of the solder to a liquescent state, thereby increasing the stand-off height of the die above the substrate. The lifting force is maintained during cooling of the solder to a solid state, thereby forming increased stand-off height solder connections. | 09-11-2008 |
20080239686 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR STRUCTURE BODIES ON UPPER AND LOWER SURFACES THEREOF, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an upper circuit board which has a plurality of upper-layer wirings including a plurality of first upper-layer wirings, and has a plurality of first and second lower-layer wirings. A first semiconductor structure body is provided on an upper side of the upper circuit board and is electrically connected to the first upper-layer wirings. A lower circuit board which is provided on a peripheral part of a lower side of the upper circuit board, the lower circuit board including a plurality of external connection wirings that are electrically connected to the first lower-layer wirings, and an opening portion which exposes the second lower-layer wirings. A second semiconductor structure body which is disposed in the opening portion of the lower circuit board, second semiconductor structure body including a plurality of external connection electrodes that are electrically connected to the second lower-layer wirings of the upper circuit board. | 10-02-2008 |
20080259581 | Circuitized substrates utilizing smooth-sided conductive layers as part thereof - A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided. | 10-23-2008 |
20080285247 | Low Exothermic Thermosetting Resin Compositions Useful As Underfill Sealants and Having Reworkability - This invention relates to the thermosetting resin compositions useful for mounting onto a circuit board semiconductor devices, such as chip size or chip scale packages (“CSPs”), ball grid arrays (“BGAs”), land grid arrays (“LGAs”) and the like, each of which having a semiconductor chip, such as large scale integration (“LSI”), on a carrier substrate. Similarly, the compositions are useful for mounting onto circuit board semiconductor chips themselves. Reaction products of the compositions of this invention are controllably reworkable when subjected to appropriate conditions. And significantly, unlike many commercial rapid curing underfill sealants (“snap cure underfills”), the inventive compositions possess an exotherm under 300 J/g or demonstrate package stability at 55° C. for 7 days, and therefore do not require special packaging to be transported by air courier, or special approval from international transportation authorities, such as the U.S. Department of Transportation, to permit such air transport. The inventive compositions possess an exotherm under 300 J/g and/or demonstrate package stability at 55° C. for 7 days and therefore do not require special packaging to be transported by air courier, or special approval from international transportation authorities, such as the U.S. Department of Transportation, to permit such air transport. | 11-20-2008 |
20080291652 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME, PRINTED CIRCUIT BOARD, AND ELECTRONIC DEVICE - Provided are a semiconductor package and a method for forming the same, and a PCB (printed circuit board). The semiconductor package comprises: a PCB including a slit at a substantially central portion thereof, the PCB including an upper surface and a lower surface; a semiconductor chip mounted on the upper surface of the PCB; an upper molding layer disposed on the upper surface and covering the semiconductor chip; and a lower molding layer filling the slit and covering a portion of the lower surface of the PCB, wherein the PCB comprises a connecting recess at a side surface thereof, and the upper molding layer and the lower molding layer are in contact with each other at the connecting recess. | 11-27-2008 |
20080298034 | PRINTED CIRCUIT BOARD AND SEMICONDUCTOR MODULE HAVING THE SAME - A printed circuit board (PCB) includes a substrate having a first group of at least two via holes and a second group of at least two via holes formed therein, a first pad set of terminal pads and a second pad set of terminal pads formed on the substrate, and a first group of conductive connection members and a second group of conductive connection members formed in the substrate. The first group of the via holes are surrounded by the first pad set of the terminal pads and the second group of the via holes are surrounded by the second pad set of the terminal pads. The first and the second groups of conductive connection members fill up the first and second groups of the via holes. The first group of the conductive connection members are connected to the first pad set of the terminal pads and the second group of the conductive connection members are connected to the second pad set of the terminal pads. | 12-04-2008 |
20080316726 | MULTI-LAYER SUBSTRATE AND MANUFACTURE METHOD THEREOF - Disclosed are a multi-layer substrate and a manufacture method thereof. The multi-layer substrate of the present invention comprises a surface dielectric layer and at least one bond pad layer. The surface dielectric layer is located at a surface of the multi-layer substrate. The bond pad layer is embedded in the surface dielectric layer to construct the multi-layer substrate with the surface dielectric layer of the present invention. The manufacture method of the present invention forms at least one bond pad layer on a flat surface of a carrier and then forms the surface dielectric layer to cover the bond pad layer where the bond pad layer is embedded therein. After the multi-layer substrate is separated from the carrier, the bond pad layer and the surface dielectric layer construct a flat surface of the multi-layer substrate. | 12-25-2008 |
20090046441 | WIRING BOARD FOR MOUNTING SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME, AND WIRING BOARD ASSEMBLY - A wiring board for mounting semiconductor device, includes at least a dielectric film | 02-19-2009 |
20090109642 | SEMICONDUCTOR MODULES AND ELECTRONIC DEVICES USING THE SAME - Semiconductor devices and electronic devices using the same. The semiconductor module may include a first semiconductor chip, and a module substrate having a top surface on which the first semiconductor chip is mounted and a second surface opposite the top surface, wherein the module substrate includes a first buffer layer to relieve stress occurring due to a difference of thermal expansions between the first semiconductor chip and the module substrate. | 04-30-2009 |
20090109643 | THIN SEMICONDUCTOR DEVICE PACKAGE - A thin semiconductor device package, comprising a thin substrate at least one thin die coupled with the substrate and having a perimeter dimension less than that of the substrate a mold material provided at a surface of the substrate adjacent to the perimeter of the die so that a surface of the mold material is coplanar with a surface of the die, and at least one electrically conductive pathway having at least one first terminal end configured to provide electrical continuity with the conductive element and at least one second terminal end formed at a surface of the mold material, the pathway extending from the first terminal end to the second terminal end. | 04-30-2009 |
20090116205 | MOUNTED STRUCTURE - A plurality of semiconductor elements is adjacently mounted on a substrate by a solder with a melting point of 200° C. or lower, an electronic part other than the semiconductor elements is mounted on the substrate between the adjacently mounted semiconductor elements by a solder with a melting point of 200° C. or lower, and spaces between the plurality of semiconductor elements and the substrate, spaces between the electronic part and the substrate, and spaces between the plurality of semiconductor elements and the electronic part are integrally molded with a molding resin. | 05-07-2009 |
20090129040 | Circuit board having power source - A circuit board having a power source is provided, including: a carrier board having a first dielectric layer disposed on at least a surface thereof and a first circuit layer disposed on the first dielectric layer, wherein the first circuit layer has at least an electrode pad; a first electrode plate disposed on the electrode pad; an insulating frame member disposed on the first electrode plate, with a portion of the first electrode plate being exposed from the insulating frame member, wherein electrolyte is received in the insulating frame member and in contact with the first electrode plate; and a porous second electrode plate disposed on the insulating frame member and the electrolyte, the second electrode plate being in contact with the electrolyte, so as to provide the power source for the circuit board. | 05-21-2009 |
20090147490 | SUBSTRATE FOR WIRING, SEMICONDUCTOR DEVICE FOR STACKING USING THE SAME, AND STACKED SEMICONDUCTOR MODULE - In a stacked semiconductor module, a test covering connecting terminals is easily conducted and high reliability is achieved. | 06-11-2009 |
20090154128 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate | 06-18-2009 |
20090168382 | SEMICONDUCTOR MODULE - A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals. | 07-02-2009 |
20090196002 | PRINTED WIRING BOARD UNIT - A printed wiring board unit includes an electronic circuit component, a printed wiring board, a plurality of first conductive terminals disposed between the electronic circuit component and the printed wiring board, at least one of the first conductive terminals arranged along a quadrangular outline, and a plurality of second conductive terminals disposed between the electronic circuit component and the printed wiring board, the second conductive terminals arranged at a corner of the quadrangular outline, and the second conductive terminals contacting at least one of the printed wiring board and the electronic circuit component in a relatively displaceable manner. | 08-06-2009 |
20090196003 | WIRING BOARD FOR SEMICONDUCTOR DEVICES, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND MOTHERBOARD - In a wiring board according to the present invention, a substrate, a solder resist provided on the substrate, a land, a wiring line, and a connection portion connecting the wiring line and the land, the connection portion is provided with a recess as a non-flat portion, and is formed to comprise a width greater than a width of the wiring line and smaller than a width (diameter) of the land, the width of the connection portion being gradually increased from the wiring line toward the land. | 08-06-2009 |
20090201657 | WIRING SUBSTRATE FOR USE IN SEMICONDUCTOR APPARATUS, METHOD FOR FABRICATING THE SAME, AND SEMICONDUCTOR APPARATUS USING THE SAME - On a printed-wiring board | 08-13-2009 |
20090231823 | Tape wiring substrate and semiconductor chip package - A second output wiring and a third output wiring enter into a chip mounting portion while coming across a second side and a third side of the chip mounting portion. The other end portions of the second output wiring and the third output wiring enter into the chip mounting portion are bent toward a fourth side of the chip mounting portion, and are connected to an output pad and an output pad provided along a fourth side of the semiconductor chip. An input wiring extends along the fourth side of the chip mounting portion, is bent from a midstream to enter into the chip mounting portion while coming across the fourth side of the chip mounting portion, and is connected to an input pad provided along the fourth side of the semiconductor chip. | 09-17-2009 |
20090244867 | METHODS OF FABRICATING MULTICHIP PACKAGES AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a discontinuous sealant on a substrate, wherein an opening is formed at an integrated heat spreader gap region, wherein the substrate comprises a portion of a multi chip microelectronic package. A thermal interface material is placed on a top surface of a high power die disposed on the substrate, and then an integrated heat spreader lid is placed on top of the sealant and on top of the thermal interface material. A molding compound is flowed within an integrated heat spreader cavity through the opening directly on a top surface of a low power die disposed on the substrate. | 10-01-2009 |
20090244868 | Semiconductor device and bonding material - The present invention is directed to enhancing the bonding reliability of a bonding portion between an Al electrode of a semiconductor device and a bonding material having metal particles as a main bonding agent. In the semiconductor device, a semiconductor element and an Al electrode are connected to each other with a bonding layer made of Ag or Cu interposed therebetween, and the bonding layer and the Al electrode are bonded to each other with an amorphous layer interposed therebetween. It is possible to obtain excellent bonding strength to the Al electrode by performing a bonding process in atmospheric air by using a bonding material including a metal oxide particle with an average diameter of 1 nm to 50 μm, an acetic acid- or formic acid-based compound, and a reducing agent made of an organic material. | 10-01-2009 |
20090244869 | Semiconductor device having wiring formed on wiring board and electric conductor formed in wiring board and conductor chip formed over wiring - A semiconductor device has a wiring board having a wiring, a semiconductor chip that is mounted on the wiring board, and an electric conductor reference plane provided in the inside of the wiring board, in which in top view. The wiring includes a first region that overlaps the electric conductor reference plane and a second region that is the whole region except for the first region. A conductor chip is mounted above the second region. | 10-01-2009 |
20090251876 | PRINTED CIRCUIT BOARD - A printed circuit board is disclosed. The printed circuit board comprises a substrate having a top surface and a bottom surface. A ground plane is on the bottom surface. A signal trace is on the top surface along a first direction. At least two isolated power planes are on the top surface adjacent to opposite sides of the signal trace, respectively. A conductive connection along a second direction couples to the two power planes, across the signal trace without electrically connecting to the signal trace, wherein the signal trace doesn't directly pass over any split of the ground plane. | 10-08-2009 |
20090284942 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device fabrication method includes: forming an elongated hole | 11-19-2009 |
20090284943 | WIRING BOARD, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE - In a wiring board, a plurality of wiring layers and a plurality of insulating layers are alternately stacked. The wiring layers are electrically connected to one another through via holes formed in the insulating layers. The wiring board includes: a connection pad which is disposed on one of the wiring layers that is on the inner side of an outermost wiring layer; and an external connection terminal which is disposed on the connection pad, and which is projected from the surface of the wiring board. The external connection terminal is passed through the outermost wiring layer. | 11-19-2009 |
20090296361 | Integrated circuit module with temperature compensation crystal oscillator - An integrated circuit module with temperature compensation crystal oscillator (TCXO) applying to an electronic device comprises: one substrate having one top surface; one temperature compensation crystal oscillator (TCXO) disposed on the top surface; at least one chip disposed on the top surface; one encapsulating piece formed on the top surface for covering the TCXO and the chip. As above-described structure, TCXO is prevented from exchanging heat due to the temperature difference so that the stability of the TCXO is improved. | 12-03-2009 |
20090310321 | PRINTED CIRCUIT BOARD AND ELECTRONIC APPARATUS - According to an aspect of the present invention, there is provided a printed circuit board including: a semiconductor package having a surface and a plurality of solder bumps arranged on the surface; a wiring board having electrodes provided at positions respectively corresponding to the solder bumps and configured to mount the semiconductor package; and a reinforcing member formed continuously along the surface and configured to fix the semiconductor package to the wiring board; wherein the reinforcing member is configured to define an opening portion between the surface and the wiring board. | 12-17-2009 |
20090310322 | Semiconductor Package - A substrate includes a number of protruding contact elements. An electrical circuit with electrical contact elements is provided on the substrate. A layer of substrate adhesive is provided on the substrate, the substrate adhesive being in contact with the substrate, with the electrical circuit and with the protruding contact elements. Wiring elements are connected between the protruding contact elements and the electrical contact elements. | 12-17-2009 |
20100014264 | PRINTED CIRCUIT BOARD FOR ACCOMPLISHING NARROW SCRIBE LANE AND SEMICONDUCTOR PACKAGE INCLUDING THE PRINTED CIRCUIT BOARD - A PCB (printed circuit board) for manufacturing a semiconductor package. The PCB includes a plurality of semiconductor package unit frames; a scribe lane dividing the plurality of semiconductor package unit frames; and a printed circuit pattern for plating directly connected to a plurality of bond fingers on the semiconductor package unit frames and disposed to cross the scribe lane between adjacent semiconductor package unit frames. | 01-21-2010 |
20100053923 | SEMICONDUCTOR DEVICE AND CIRCUIT BOARD ASSEMBLY - A semiconductor device that includes a semiconductor element, a package substrate, and a plurality of bonding members. The semiconductor element is fixed on the front surface of the package substrate. The package substrate has a first region and a second region on the back surface. The plurality of bonding members is arranged in a grid pattern on the first region of the back surface of the package substrate. The second region of the package substrate defines a bonding prohibition region corresponding with the periphery of the semiconductor element in a plan view. | 03-04-2010 |
20100079966 | MEMORY MODULE - A memory module includes a printed circuit board (PCB), and a plurality of semiconductor packages and a multi-functional package mounted to the PCB. The multi-functional package may have a data processing function and an error correcting function. Thus, the packages may occupy a relatively small area of the PCB in terms of the number of functions that they provide. Thus, the module may be highly integrated. | 04-01-2010 |
20100097775 | Electronic control device - In an electronic control device, an electrically-conductive adhesive is arranged on an outer edge portion of a first surface of a circuit board as a stress reducing portion for reducing stress of the circuit board received by a molding resin. An elastic modulus of the electrically-conductive adhesive is lower than that of the circuit board. The electrically-conductive adhesive is covered by an adhesion improving member. When peeling stress is applied to the circuit board from the molding resin, the electrically-conductive adhesive and the adhesion improving member receive the peeling stress to be deformed. Therefore, the peeling stress to the circuit board is reduced. | 04-22-2010 |
20100110651 | Integrated Circuit Coating For Improved Thermal Isolation - During manufacture of an electronic device, an aerogel coating is applied to a first side of an IC substrate of a first IC. A bonding procedure is initiated, during which IC interconnects are either placed on the coated side of the substrate or on the opposite side of the substrate. The first IC is connected on a carrier to a second IC with the coated side of the first IC facing the second IC to reduce heat transmission to the second IC during operation of the first IC. The aerogel coating reduces thermal stress to the circuit board and surrounding components, reduces the risk of overheating of critical circuit components, provides chemical and mechanical insulation from contamination during subsequent wafer handling operations, and provides a thermal isolator between IC regions of dissimilar power dissipation, which isolator facilitates efficient thermal extraction from localized hotspots. | 05-06-2010 |
20100110652 | ANISOTROPIC CONDUCTIVE ADHESIVE COMPOSITION, ANISOTROPIC CONDUCTIVE FILM, CIRCUIT MEMBER CONNECTING STRUCTURE AND METHOD FOR MANUFACTURING COATED PARTICLES - The anisotropically conductive adhesive composition according to the present invention is an anisotropically conductive adhesive composition to connect a first circuit member where a first circuit electrode is formed on the principal surface of a first substrate and a second circuit member where a second circuit electrode is formed on the principal surface of a second substrate with the first circuit electrode and the second circuit electrode placed opposite, wherein the anisotropically conductive adhesive composition comprises an adhesive and a coated particle where at least part of the surface of a conductive particle is coated with an insulating material containing a polymer electrolyte and an inorganic oxide fine particle. | 05-06-2010 |
20100124037 | THERMOSETTING COMPOSITION AND PRINTED CIRCUIT BOARD USING THE SAME - A thermosetting composition including an organic solvent, a liquid crystalline thermoset oligomer, and either a crosslinking agent or an epoxy resin or both is disclosed. A printed circuit board which includes the thermosetting composition is also disclosed. The printed circuit board is produced by impregnating the thermosetting composition into a reinforcing material. | 05-20-2010 |
20100134994 | POWER SEMICONDUCTOR MODULE - A power semiconductor module is disclosed, comprising: a substrate mounted with a power semiconductor device and formed with a pattern; and an integrated terminal unit integrally assembled with a power terminal for applying power to the substrate and a body in which a signal terminal for inputting a signal to or outputting the signal from the substrate is made of an insulated resin material, wherein the integrated terminal unit can be mounted to the substrate to allow the power terminal and the signal terminal to be simultaneously connected to the substrate. | 06-03-2010 |
20100149773 | INTEGRATED CIRCUIT PACKAGES HAVING SHARED DIE-TO-DIE CONTACTS AND METHODS TO MANUFACTURE THE SAME - Integrated circuit packages having shared die-to-die contacts and methods to fabricate the same are disclosed. A disclosed example integrated circuit package comprises a leadframe, a first die pad and a second die pad associated with the leadframe, and first and second integrated circuits associated with the first and second die pads, respectively. The package also includes a shared die-to-die contact externally exposed by a recess that extends laterally across a bottom surface of the leadframe between the first and second die pads. The first integrated circuit is electrically coupled to a first portion of the shared contact. The second integrated circuit is electrically coupled to a second portion of the shared contact. | 06-17-2010 |
20100149774 | SEMICONDUCTOR DEVICE - A semiconductor device includes a terminal case containing a semiconductor element, a plurality of pin terminals of equal length mounted in the terminal case and electrically connected to the semiconductor element, the plurality of pin terminals projecting outward from a predetermined surface of the terminal case in the same direction, and at least one protruding pin terminal mounted in the terminal case and projecting outward from the predetermined surface of the terminal case in the same direction farther than the plurality of pin terminals. | 06-17-2010 |
20100149775 | Tape circuit substrate with reduced size of base film - A tape circuit substrate includes a base film with first wiring and second wiring disposed on the base film. The first wiring extends into a chip mount portion through a first side and bends within the chip mount portion toward a second side. The second wiring extends into the chip mount portion through a third side and bends within the chip mount portion toward the second side. The first, second, and third sides are different sides of the chip mount portion. Thus, size and in turn cost of the base film are minimized by arranging wirings within the chip mount portion for further miniaturization of electronic devices, such as a display panel assembly, using the tape circuit substrate. | 06-17-2010 |
20100149776 | PRESSURE CONDUCTIVE SHEET - A pressure conductive sheet includes a connector body formed of a thin plate of insulation material, an elastic body deposited as one body with the connector body, pluralities of connection terminals provided with a given interval to pass through the elastic body and the connector body, and a ground plate constituting a matching circuit, the ground plate being buried by a given width in between the connector body and the elastic body. The ground plate is coupled to a ground terminal among the connection terminals and is separated from an outer circumference face of a signal terminal. The connector body, the elastic body, the connection terminals and the ground plate are combined with one another to substantially reduce an interference between signal terminals through the matching circuit formed based on capacitance of a gap between a ground face of the ground plate and the signal terminal, and to improve electrical characteristics. | 06-17-2010 |
20100157559 | PRINTED CIRCUIT BOARD AND METHOD FOR MOUNTING ELECTRONIC COMPONENTS - In a case where the first component and the third component are mountable on the first circuit board pattern of the first individual board and the second component is mountable on the second circuit board pattern of the first individual board, or in a case where the first component is mountable on the first circuit board pattern of the second individual board, and the second component and the third component are mountable on the second circuit board pattern of the second individual board, in the first and second individual boards, traces for the third component are provided so that electrical connections between the third component and the other components are identical between the case where the third component is mounted on the first circuit board pattern, and the case where the third component is mounted on the second circuit board pattern. | 06-24-2010 |
20100172113 | METHODS FOR FORMING PACKAGED PRODUCTS - An apparatus and methods for packaging semiconductor devices are disclosed. The apparatus is applicable to many types of contemporary packaging schemes that utilize a sacrificial metal base strip. Tunnels formed through an encapsulation area surrounding the device and associated bond wires are filled with a metallic conductor by, for example, electroplating, and extend bottom contact pads to an uppermost portion of the encapsulated area. The sacrificial metal base strip serves as a plating bus and is etch-removed after plating. The filled tunnels allow components to be stacked in a three-dimensional configuration. | 07-08-2010 |
20100202125 | SEMICONDUCTOR MODULE - A top panel, which is disposed to face a module board with an electronic component therebetween, includes a resin layer and a metal layer, and has an insulating characteristic. The metal layer includes a metal layer formed at a front side of the resin layer and a metal layer formed at a rear side of the resin layer. With this structure, in reflow soldering performed in mounting a semiconductor module on a main board, warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the front side of the resin layer is cancelled by warp which is caused, under temperature change, in the top panel due to difference in coefficient of thermal expansion between the resin layer and the metal layer formed at the rear side of the resin layer, whereby warp of the top panel is eliminated. This helps prevent the electronic component adhered to the top panel with adhesive from being pressed down to or pulled up from the module board due to warp of the top panel. | 08-12-2010 |
20100208442 | WIRING BOARD ASSEMBLY AND MANUFACTURING METHOD THEREOF - A wiring board assembly includes a rectangular plate-shaped wiring board having a plurality of resin insulation layers and conduction layers alternately laminated together to define opposite first and second main surfaces and a plurality of connection terminals arranged on the first main surface for surface contact with terminals of a chip and a rectangular frame-shaped reinforcing member fixed to the first main surface of the wiring board with the connection terminals exposed through an opening of the reinforcing member. The reinforcing member has a plurality of structural pieces separated by slits extending from an inner circumferential surface to an outer circumferential surface of the reinforcing member. | 08-19-2010 |
20100208443 | SEMICONDUCTOR DEVICE - A semiconductor device reduces the impedance of a wiring for supplying the circuit excluding a data output circuit with a power source voltage or a ground voltage and of speedup of data signal transmission in the data output circuit. Additional substrates | 08-19-2010 |
20100214753 | Pb-free solder-connected structure and electronic device - Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength. | 08-26-2010 |
20100214754 | RIBBON BONDING IN AN ELECTRONIC PACKAGE - A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher throughput due to less areas to bond and test. | 08-26-2010 |
20100226110 | Printed wiring board, printed IC board having the printed wiring board, and method of manufacturing the same - A printed IC board has a multilayer printed wiring board and one or more bare IC chips. The multilayer printed wiring board has insulation layers made of PTFE, and wiring patterns formed on the insulation layers which are stacked to make a lamination structure. Electrode parts as parts of the wiring patterns are electrically connected to the bare IC chip. A copper member which serves as a reinforcing member is laid in a region formed in the insulation layers other than a first insulation layer. the region is formed directly below the electrode parts. The region is formed in a direction Z along a thickness of the stacked insulation layers. The region formed directly below the electrode parts in the insulation layers in the insulation layers other than the first insulation layer has a higher rigidity than the insulation layers. | 09-09-2010 |
20100232127 | WIRING BOARD COMPOSITE BODY, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE WIRING BOARD COMPOSITE BODY AND THE SEMICONDUCTOR DEVICE - A wiring board composite body includes a supporting substrate, and wiring boards formed on each of the upper and the lower surfaces of the supporting substrate. The supporting substrate includes a supporting body, and a metal body arranged on each of the upper and the lower surfaces of the supporting body. The wiring board comprises at least an insulation layer insulating upper and lower wirings, and a via connecting the upper and the lower wirings. The wiring board mounted on the metal body constitutes a wiring board with the metal body. Thus, the supporting body supporting the metal body is effectively used in a process of forming the wiring board on the metal body, and the wiring board composite body, which has advantageous structural and production characteristics, is provided. A semiconductor device and a method for manufacturing such wiring board composite body and the semiconductor device are also provided. | 09-16-2010 |
20100232128 | MICROELECTRONIC ASSEMBLY WITH IMPEDANCE CONTROLLED WIREBOND AND REFERENCE WIREBOND - A microelectronic assembly can include a microelectronic device, e.g., semiconductor chip, connected together with an interconnection element, e.g., substrate, the latter having signal contacts and reference contacts. The reference contacts can be connectable to a source of reference potential such as ground or a voltage source other than ground such as a voltage source used for power. Signal conductors, e.g., signal wirebonds can be connected to device contacts exposed at a surface of the microelectronic device. Reference conductors, e.g., reference wirebonds can be provided, at least one of which can be connected with two reference contacts of the interconnection element. The reference wirebond can have a run which extends at an at least substantially uniform spacing from a signal conductor, e.g., signal wirebond that is connected to the microelectronic device over at least a substantial portion of the length of the signal conductor. In such manner a desired impedance may be achieved for the signal conductor. | 09-16-2010 |
20100232129 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A method of making a microelectronic assembly includes providing a microelectronic package having a substrate, a microelectronic element overlying the substrate and at least two conductive elements projecting from a surface of the substrate, the at least two conductive elements having surfaces remote from the surface of the substrate. The method includes compressing the at least two conductive elements so that the remote surfaces thereof lie in a common plane, and after the compressing step, providing an encapsulant material around the at least two conductive elements for supporting the microelectronic package and so that the remote surfaces of the at least two conductive elements remain accessible at an exterior surface of the encapsulant material. | 09-16-2010 |
20100246152 | INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY - Integrated circuit chips and chip packages are disclosed that include an over-passivation scheme at a top of the integrated circuit chip and a bottom scheme at a bottom of the integrated circuit chip using a top post-passivation technology and a bottom structure technology. The integrated circuit chips can be connected to an external circuit or structure, such as ball-grid-array (BGA) substrate, printed circuit board, semiconductor chip, metal substrate, glass substrate or ceramic substrate, through the over-passivation scheme or the bottom scheme. Related fabrication techniques are described. | 09-30-2010 |
20100259910 | Circuit Board and Mounting Structure - The invention relates to a circuit board having high density circuit and excellent connection reliability and lamination reliability. A resin fabric cloth ( | 10-14-2010 |
20100259911 | MAGNETIC MICROINDUCTORS FOR INTEGRATED CIRCUIT PACKAGING - Magnetic microinductors formed on semiconductor packages are provided. The magnetic microinductors are formed as one or more layers of coplanar magnetic material on a package substrate. Conducting vias extend perpendicularly through the plane of the magnetic film. The magnetic film is a layer of isotropic magnetic material or a plurality of layers of anisotropic magnetic material having differing hard axes of magnetization. | 10-14-2010 |
20100265683 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip | 10-21-2010 |
20100265684 | INTERPOSER SUBSTRATE AND INCLUDING CAPACITOR FOR ADJUSTING PHASE OF SIGNAL TRANSMITTED IN SAME INTERPOSER SUBSTRATE - In an interposer substrate, a plating stub conductor and a ground conductor form a capacitor, and a plating stub conductor and the ground conductor form a capacitor. Capacitances of the capacitors are adjusted so that a phase difference between signals transmitted by a differential transmission using a signal line including a connection wiring conductor and a signal line including a connection wiring conductor is equal to 180 degrees. | 10-21-2010 |
20100290205 | ADHESIVE FILM - An adhesive film is provided that can ensure reliable continuity even if a filler and a binder composition are not sufficiently removed from between a wiring board and a semiconductor chip during flip-chip mounting of the semiconductor chip. The adhesive film is formed from a binder composition including an epoxy compound, a curing agent, and the filler. The amount of a filler contained with respect to a total amount of an epoxy compound, a curing agent, and the filler is 10 to 70 mass %. The filler includes first non-conductive inorganic particles having an average particle size of 0.5 to 1.0 μm, and conductive particles formed by subjecting second non-conductive inorganic particles having an average particle size of 0.5 to 1.0 μm. An average particle size of the conductive particles does not exceed 1.5 μm. The conductive particles is contained in an amount of 10 to 60 mass % of the filler. | 11-18-2010 |
20100302749 | Controlling Warpage in BGA Components in a Re-flow Process - A method of manufacturing an integrated circuit package includes providing a ball grid array (BGA) module including BGA balls on a side of the BGA module; providing a base substrate; and placing the BGA module on the base substrate. The BGA balls are placed between the BGA module and the base substrate. An adhesive is applied between and contacting the BGA module and the base substrate. The adhesive is then cured. The BGA balls are re-flowed after the step of curing the adhesive. | 12-02-2010 |
20100309641 | INTERPOSER SUBSTRATE, LSI CHIP AND INFORMATION TERMINAL DEVICE USING THE INTERPOSER SUBSTRATE, MANUFACTURING METHOD OF INTERPOSER SUBSTRATE, AND MANUFACTURING METHOD OF LSI CHIP - A method of forming narrow-pitch flip-chip bonding electrodes and wire bonding electrodes at the same time is provided so as to reduce the cost of a substrate. In addition, a low-cost solder supply method and a flip-chip bonding method to a thin Au layer are provided. A stacked layer of a Cu layer | 12-09-2010 |
20100315796 | CONDUCTIVE MATERIAL, CONDUCTIVE PASTE, CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE - A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal. | 12-16-2010 |
20100321912 | DISPLAY PANEL - A display panel includes a substrate and many driving chips. The substrate has many pad regions located in a non-display region of the substrate. Each pad region has many first pins with the same length disposed therein, and a pin pitch between two adjacent first pins, a width of each of the first pins, or both the pin pitch and the width vary with the positions where the first pins are disposed in the corresponding pad region. The driving chips are disposed in the non-display region of the substrate. Each driving chip has many second pins, and each second pin is electrically connected to each first pin correspondingly. | 12-23-2010 |
20100321913 | MEMORY CARD - A memory card and method for fabricating the same are disclosed, which includes mounting and electrically connecting at least a chip to a circuit board unit having a predefined shape of a memory card; attaching a thin film to the surface of the circuit board unit opposed to the surface with the chip mounted thereon; covering the circuit board unit and the thin film by a mold so as to form a mold cavity having same shape as the circuit board unit but bigger size; filling a packaging material in the mold cavity so as to form an encapsulant encapsulating the chip and outer sides of the circuit board unit, thus integrally forming a memory card having the predefined shape. The present invention eliminates the need to perform a shape cutting process by using water jet or laser as in the prior art, thus reducing the fabricating cost and improving the fabricating yield. | 12-23-2010 |
20100321914 | MULTILAYER PRINTED WIRING BOARD - A multilayer printed wiring board in which interlayer insulation layer and conductive layer are formed on a multilayer core substrate composed of three or more layers, having through holes for connecting the front surface with the rear surface and conductive layers on the front and rear surfaces and conductive layer in the inner layer to achieve electric connection through via holes, the through holes being composed of power source through holes, grounding through holes and signal through holes connected electrically to a power source circuit or a grounding circuit or a signal circuit of an IC chip, when the power source through holes pass through the grounding conductive layer of the inner layer in the core substrate, of the power source through holes, at least a power source through hole just below the IC having no conductive circuit extending from the power source through hole in the grounding conductive layer. | 12-23-2010 |
20100328916 | SEMICONDUCTOR DEVICE - A protection circuit used for a semiconductor device is made to effectively function and the semiconductor device is prevented from being damaged by a surge. A semiconductor device includes a terminal electrode, a protection circuit, an integrated circuit, and a wiring electrically connecting the terminal electrode, the protection circuit, and the integrated circuit. The protection circuit is provided between the terminal electrode and the integrated circuit. The terminal electrode, the protection circuit, and the integrated circuit are connected to one another without causing the wiring to branch. It is possible to reduce the damage to the semiconductor device caused by electrostatic discharge. It is also possible to reduce faults in the semiconductor device. | 12-30-2010 |
20100328917 | MULTICHIP MODULE, PRINTED CIRCUIT BOARD UNIT, AND ELECTRONIC APPARATUS - A multichip module includes a package substrate, a first semiconductor device, a second semiconductor device and a conductive bump. The first semiconductor device is flip-chip bonded to the package substrate. The first semiconductor device includes a first chip pad on a surface thereof. The second semiconductor device is mounted on the first semiconductor device. The second semiconductor device includes a second chip pad facing the first chip pad. The conductive bump connects the first chip pad to the second chip pad. The conductive bump includes a first metallic body that has a first diffusion rate and a second metallic body that has a second diffusion rate lower than the first diffusion rate. | 12-30-2010 |
20100328918 | COMPOSITE STRUCTURE OF ELECTRONIC COMPONENT AND SUPPORTING MEMBER - A composite structure includes an electronic component and a supporting member. The electronic component includes a main body and a plurality of pins extended outwardly from the main body. The supporting member includes a first supporting part and a second supporting part. The first supporting part is foldable with respect to the second supporting part. The main body of the electronic component is accommodated within the first supporting part of the supporting member. The pins are accommodated with the second supporting part of the supporting member. The first supporting part is folded with respect to the second supporting part such that the pins are bent to define a bent structure. | 12-30-2010 |
20100328919 | METHOD OF MAKING A FIBER REINFORCED PRINTED CIRCUIT BOARD PANEL AND A FIBER REINFORCED PANEL MADE ACCORDING TO THE METHOD - A method of making a printed circuit board panel, a printed circuit board panel made according to the method, and a system incorporating a printed circuit board provided onto the panel. The printed circuit board panel has a panel top edge, a panel bottom edge parallel to the panel top edge, and two parallel panel side edges, and further includes a first set of fiber bundles extending at the predetermined angle with respect to the panel side edges, and a second set of fiber bundles extending at the predetermined angle with respect to the panel top edge. | 12-30-2010 |
20110007489 | EPOXY RESIN COMPOSITION, RESIN SHEET, PREPREG, MULTILAYER PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE - An object of the present invention is to provide an epoxy resin composition that provides, when used for an insulation layer of a multilayer printed wiring board, a multilayer printed wiring board which is excellent in plating adhesion, heat resistance and moisture resistance reliability and capable of forming fine wiring. Another object of the present invention is to provide a resin sheet, a prepreg, a method for producing a multilayer printed wiring board, a multilayer printed wiring board and a semiconductor device. | 01-13-2011 |
20110019379 | Printed wiring board, semiconductor device, and method for manufacturing printed wiring board - A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area. | 01-27-2011 |
20110019380 | METHOD AND DEVICE FOR MODULATING LIGHT - Improvements in an interferometric modulator that has a cavity defined by two walls. | 01-27-2011 |
20110019381 | ELECTRONIC CIRCUIT BOARD AND POWER LINE COMMUNICATION APPARATUS USING IT - A highly reliable electronic circuit board for suppressing propagation of noise and a power line communication apparatus using it are provided. An electronic circuit board of the invention is connected to a different electronic circuit board and including a first board having a first face and a second face opposed to the first face and a second board having a third face and a fourth face opposed to the third face. The electronic circuit board includes a first circuit mounted on one end of the first face for performing analog signal processing; a second circuit mounted on another end of the first face for performing digital signal processing; a junction layer provided between the second face and the third face for jointing the first board and the second board; a built-in electronic component built into the junction layer; a connection part mounted on the fourth face and to be connected to the different electronic circuit board; and a first conducting path for electrically connecting the second circuit and the connection part, wherein the connection part is mounted at a position overlapping projection projecting the second circuit onto the fourth face from a vertical direction relative to the first face. | 01-27-2011 |
20110051385 | HIGH-DENSITY MEMORY ASSEMBLY - High-density memory assemblies and related methods for manufacturing and using such memory assemblies are included in the present disclosure. According to one exemplary embodiment, a high-density memory assembly includes stacked first and second panels. The first and second panels each comprise a substrate and at least one chip disposed on the substrate. The first and second panels each further comprise connecting tabs extending from the substrates of the first and second panels. | 03-03-2011 |
20110051386 | Circuit Board, Mounting Structure, and Method for Manufacturing Circuit Board - A circuit board ( | 03-03-2011 |
20110051387 | METHOD FOR ELECTROLESS NICKEL-PALLADIUM-GOLD PLATING, PLATED PRODUCT, PRINTED WIRING BOARD, INTERPOSER AND SEMICONDUCTOR APPARATUS - An object of the present invention is to provide an electroless nickel-palladium-gold plating method which is able, when performed on a plating target surface such as terminals of a printed wiring board, terminals of other electronic components, and other resin substrates with a fine metal pattern, to prevent abnormal metal deposition on a resin surface which is an undercoat and to provide a high-quality plated surface. Another object of the present invention is to provide a plated product with a high-quality plated surface, particularly such as an interposer and motherboard, and a semiconductor apparatus using the same. These objects were achieved by the electroless nickel-palladium-gold plating method of the present invention, which is a method for plating target objects such as terminals of a printed wiring board and in which at least one surface treatment selected from a treatment with a solution of pH 10 to 14 and a plasma treatment is performed at an optional step after the step of providing a palladium catalyst and before the step of performing electroless palladium plating. | 03-03-2011 |
20110051388 | PRINTED CIRCUIT BOARD WITH A FUSE AND METHOD FOR THE MANUFACTURE OF A FUSE - Some invention embodiments relate to a method for forming a fuse which electrically connects two metal surfaces ( | 03-03-2011 |
20110058346 | Bonding Metallurgy for Three-Dimensional Interconnect - A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate. | 03-10-2011 |
20110063812 | ELECTRONIC DEVICE, METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC EQUIPMENT - An electronic device includes a circuit board having a first electrode formed on a main surface thereof, a semiconductor device disposed toward the main surface of the circuit board, the semiconductor device having a second electrode formed on a surface thereof opposed to the main surface, and a connection member electrically connecting between the first and second electrodes. The connection member includes a hollow cylindrical member and a conductive member disposed within the hollow cylindrical member. | 03-17-2011 |
20110069464 | Memory module, memory system having the memory module, and method for manufacturing the memory module - Provided is a memory module, a system using the memory module, and a method of fabricating the memory module. The memory module may include a printed circuit board and a memory package on the printed circuit board. The printed circuit board may include an embedded optical waveguide and a first optical window extending from the optical waveguide to a first surface of the printed circuit board. The memory package may also include a memory die having an optical input/output section and a second optical window. The optical input/output section, the second optical window, and the first optical window may be arranged in a line and the first optical window and the second optical window may be configured to at least one of transmit an optical signal from the optical waveguide to the optical input/output section and transmit an optical signal from the optical input/output section to the optical waveguide. | 03-24-2011 |
20110075390 | PAD LAYOUT STRUCTURE OF DRIVER IC CHIP - A pad layout structure of a driver IC chip of a liquid crystal display device includes dummy power pads and dummy ground pads, which are disposed in corners of the driver IC chip and are connected to main power pads and main ground pads by metal lines in a chip-on-film (COF) package. Accordingly, it is possible to reduce the resistance of power supply lines and ground lines, to minimize a power dip of a block located far away from the main power pads and main ground pads, and to prevent a failure in power application, which may occur due to a decrease of adhesive strength at a specific position, by dispersing the adhesion positions of the power pads and ground pads. | 03-31-2011 |
20110103031 | PACKAGE SUBSTRATE, SEMICONDUCTOR PACKAGE HAVING THE PACKAGE SUBSTRATE - A package substrate may include an insulating substrate, first circuit patterns, second circuit patterns and a test pattern. The first circuit patterns may be arranged on the insulating substrate. The second circuit patterns may be arranged on the insulating substrate. The second circuit patterns may be arranged between the first circuit patterns. The test pattern may be electrically connected between same polar terminals of the first circuit patterns and the second circuit patterns. Thus, electrical connections between the semiconductor chip and the circuit patterns may be tested before performing a process for cutting the package substrate. | 05-05-2011 |
20110110061 | Circuit Board with Offset Via - Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first interconnect layer of a circuit board. The first interconnect layer includes first and second conductor structures in spaced apart relation, a first via in ohmic contact with the first conductor structure and a second via in ohmic contact with the second conductor structure. A second interconnect layer is formed on the first interconnect layer. The second interconnect layer includes third and fourth conductor structures in spaced apart relation and offset laterally from the first and second conductor structures, a third via in ohmic contact with the third conductor structure and a fourth via in ohmic contact with the fourth conductor structure. | 05-12-2011 |
20110110062 | Stack-type semiconductor device having chips having different backside structure and electronic apparatus including the same - A stack-type semiconductor device including semiconductor chips having different backside structures and an electronic apparatus including the stack-type semiconductor device include: a base frame for a semiconductor device; a first semiconductor chip that is mounted on the base frame and has a bottom surface having a first surface roughness; and a second semiconductor chip that is mounted on the first semiconductor chip and has a bottom surface having a second surface roughness, wherein the second surface roughness is greater than the first surface roughness by 1.2 nm or more. The stack-type semiconductor device is manufactured to be thin while cracking of the first semiconductor chip is prevented. In addition, changes in data caused by charge loss resulting from diffusion of metal ions, which can occur when a stack-type semiconductor device is a memory device, is prevented. | 05-12-2011 |
20110116247 | SEMICONDUCTOR PACKAGE HAVING MULTI PITCH BALL LAND - A semiconductor device having a printed circuit board and a semiconductor chip. The printed circuit board includes a chip region, a plurality of first ball lands adjacent to the chip region, and at least one second ball land adjacent to the first ball lands. The semiconductor chip is mounted on the chip region. The first ball lands are arranged to have a first pitch. One of the first ball lands which is nearest to the second ball land, and the second ball land have a second pitch greater than the first pitch. | 05-19-2011 |
20110128712 | COMPACT MEDIA PLAYER - An electronic device such as a media player may be formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts may be used to play audio and to convey digital signals. Electrical components for the device may be mounted to a substrate. The components may be encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons may remain uncovered by encapsulant during the encapsulation process. Integrated circuits may be entirely encapsulated with encapsulant. The integrated circuits may be packaged or unpackaged integrated circuit die. The substrate may be a printed circuit board or may be an integrated circuit to which components are directly connected without interposed printed circuit board materials. | 06-02-2011 |
20110134619 | High power device module - A high power device module includes a substrate carrying multiple chips on the top side and having stepped through holes around the chips, copper plates and connectors connected to the chips, fastening members each having a shoulder respectively fitted into the through holes of the substrate, a head connected to one end of the shoulder fitted into the expanded bottom end of the associating stepped through hole, and a shank connected to the other end of the shoulder and protruding over the top side of the substrate, and packaging members directly molded from resin on the shanks of the fastening members and the chips and the copper plates and the connectors to seal the component parts to the substrate. | 06-09-2011 |
20110134620 | MEMORY CARDS AND ELECTRONIC MACHINES - Provided is a memory card. The memory card includes interconnection terminals for electric connection with an external electronic machine. The interconnection terminals may be spaced from the front side of the memory card by a distance greater than the lengths of the interconnection terminals. Alternatively, the memory card may include other interconnection terminals between its front side and the former interconnection terminals. The former and latter interconnection terminals may be used for electric connection with different kinds of electronic machines. | 06-09-2011 |
20110149540 | METHOD FOR ASSEMBLING AT LEAST ONE CHIP WITH A WIRE ELEMENT, ELECTRONIC CHIP WITH A DEFORMABLE LINK ELEMENT, FABRICATION METHOD OF A PLURALITY OF CHIPS, AND ASSEMBLY OF AT LEAST ONE CHIP WITH A WIRE ELEMENT - A first step of the method for assembling a wire element with an electronic chip comprises arranging the wire element in a groove of the chip delineated by a first element and a second element, joined by a link element comprising a plastically deformable material, and a second step then comprises clamping the first and second elements to deform the link element until the wire element is secured in the groove. | 06-23-2011 |
20110149541 | HEAT CURABLE ADHESIVE AND RESIN LAMINATED-TYPE IC CARD - Provided is a heat curable adhesive that can strongly bond a base material formed of a crystalline polyester resin, can freely regulate the thickness of an adhesive layer, has excellent chemical resistance, and, at the same time, has excellent storage stability. Furthermore, provided is a resin laminated-type IC card, in which a liquid heat curable adhesive of which use has been difficult in the past can be used, and the liquid heat curable adhesive can be coated with a good accuracy by a printing method without the need to perform molding into a hot-melt sheet to bond a base material formed of a crystalline polyester resin. Accordingly, the resin laminated-type IC card can have a high degree of freedom in design of the thickness of an IC card. The heat curable adhesive comprises (a) a hydroxyl group-containing non-crystalline polyester resin, (b) a resin containing a carboxylic acid anhydride, and (c) a solvent for dissolving (a) the hydroxyl group-containing non-crystalline polyester resin. | 06-23-2011 |
20110157853 | FAN-OUT WAFER LEVEL PACKAGE WITH POLYMERIC LAYER FOR HIGH RELIABILITY - A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit. | 06-30-2011 |
20110157854 | SELECTIVE SPACER FORMATION ON TRANSISTORS OF DIFFERENT CLASSES ON THE SAME DEVICE - A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class. | 06-30-2011 |
20110157855 | INTEGRATED CIRCUITS HAVING LEAD CONTACTS AND LEADLESS CONTACT PADS CONNECTED TO A SURFACE OF A PRINTED WIRING BOARD, AND METHODS FOR CONNECTING THE SAME - A method is provided for connecting an integrated circuit to a surface of a printed wiring board. The integrated circuit includes lead contacts and leadless contact pads. A first solder paste is applied to the leadless contact pads of the integrated circuit, and preformed conductive pieces are placed on the first solder paste. The preformed conductive pieces are slugs that have, for example, a cylindrical shape or a rectangular cross-section. The preformed conductive pieces are heated and brought into electrical contact with the leadless contact pads. The lead contacts are formed into gull wings. The bases of the preformed conductive pieces are generally aligned in a plane, and the bases of the gull wings are substantially coplanar with the plane such that they collectively generally define a contact plane. A second solder paste is applied on the surface, and the bases of the gull wings and the preformed conductive pieces are soldered to the second solder paste on the surface so that the integrated circuit is in electrical contact with the surface through both the leadless contact pads and the lead contacts. The preformed conductive pieces comprise a conductive material (e.g., a copper alloy) that has a higher melting point than the first solder paste and the second solder paste such that the preformed conductive pieces do not melt during heating or soldering that is described above. | 06-30-2011 |
20110170274 | CIRCUIT SUBSTRATE AND DISPLAY DEVICE - Provided is a circuit substrate which can integrate circuit elements without degrading wiring characteristics, and a display device including the circuit substrate. The circuit substrate of the present invention includes a transistor substrate ( | 07-14-2011 |
20110176285 | Interconnection structure, interposer, semiconductor package, and method of manufacturing interconnection structure - There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities. | 07-21-2011 |
20110176286 | LEAD PIN AND WIRING SUBSTRATE WITH LEAD PIN - A lead pin includes a shaft portion, and a connection head portion which is provided on a top end side of the shaft portion and has a diameter larger than a diameter of the shaft portion, and whose whole outer surface is formed of a spherical surface. The connection head portion is formed of a ball shape, an oval spherical shape, or a teardrop-like shape, and also the connection head portion of the lead pin is connected to a wiring substrate by the reflow soldering. | 07-21-2011 |
20110188219 | CIRCUIT BOARD ASSEMBLY - A circuit board assembly includes a circuit board having a first side and a second side opposite to the first side. A chip module is connected to the first side of the circuit board. The chip module includes a substrate and a chip disposed on the substrate. The first clamping member defines a recess and a contact portion around the recess. The chip is received in the recess, and the contact portion abuts the substrate. A second clamping member abuts the second side of the circuit board. A plurality of stress adjusting members extends through the second clamping member and engages the first clamping member. | 08-04-2011 |
20110199746 | ELECTRONIC SYSTEM WITH A COMPOSITE SUBSTRATE - A composite substrate made of a circuit board mounted on a lead frame is used for an electronic system package. High heat generated electronic components are adapted to mount on the lead frame and relatively low heat generated electronic components are adapted to mount on the circuit board. Metal lines are used for electrical coupling between the circuitry of the IC chip and the circuit board. An electronic system with the composite substrate gains both advantages—good circuitry arrangement capability from the circuit board and good heat distribution from the lead frame. | 08-18-2011 |
20110205721 | RESIN COMPOSITION, RESIN SHEET, PREPREG, LAMINATE, MULTILAYER PRINTED WIRING BOARD, AND SEMICONDUCTOR DEVICE - Disclosed is a resin composition having a low thermal expansion coefficient and a high glass transition temperature used for the insulating layer of a multilayer printed wiring board, capable of forming an insulating layer having fine roughened shapes and imparting sufficient plating peel strength. Also disclosed are a resin sheet, a prepreg, a laminate, a multilayer printed wiring board and a semiconductor device, all of which comprising the resin composition. The resin composition is a resin composition comprising (A) an epoxy resin, (B) a cyanate ester resin, (C) an aromatic polyamide resin containing at least one hydroxyl group and (D) an inorganic filler, as essential components. | 08-25-2011 |
20110211322 | ELECTRONIC DEVICE - An electronic device includes a printed circuit board, conductive portions coated with a solder paste, a chip module installed on the printed circuit board, contact portions formed at the bottom of the chip module and corresponding to the conductive portions respectively, and at least one support portion formed between the chip module and the printed circuit board and having an end coupled to the printed circuit board and another end coupled to the contact portion of the chip module. When the chip module and printed circuit board are deformed in a high-temperature process, the contact portions will still be in contact with the solder paste. Since the printed circuit board is warped upward at the middle and downward at the periphery in a soldering process, the support portion maintains a specific distance between the two to prevent excessive melted solder pastes from flowing towards the periphery or causing short circuits. | 09-01-2011 |
20110211323 | CIRCUIT BOARD, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to one embodiment, a circuit board includes: a substrate on which circuit patterns are formed, a first surface of the substrate being formed substantially flat; and a solder resist film that covers the first surface of the substrate. The solder resist film assumes, as a whole, a convex shape in which the thickness of the solder resist film in the center of the substrate is larger than the thickness of the solder resist film in the periphery of the substrate. | 09-01-2011 |
20110216516 | Semiconductor Module, Socket For The Same, And Semiconductor Module/Socket Assembly - A semiconductor module, a socket for the same, and a semiconductor module/socket assembly are disclosed. The semiconductor module includes a printed circuit board including a plurality of semiconductor devices, a plurality of insulating layers and a plurality of metal layers, the plurality of insulating layers and the plurality of metal layers are alternately stacked. Exposed portions of the metal layers are exposed to the outside of the semiconductor module at a first and a second ends of the printed circuit board. The first end and the second end are at opposite ends of the printed circuit board. | 09-08-2011 |
20110216517 | ELECTRICAL CONNECTION INTERFACES AND METHODS FOR ADJACENTLY POSITIONED CIRCUIT COMPONENTS - Electrical components, such as packaged integrated circuit devices that are mountable on a substrate surface, are provided with at least one exposed electrical contact on a side surface of the component that will be substantially perpendicular to the substrate surface when the component is mounted. Two such components can be mounted side-by-side on the substrate surface with the above-mentioned contacts close to one another between the above-mentioned side surfaces. An electrical connection between the contacts can be made (or perfected) by depositing an electrically conductive connector material in contact with both of the contacts between the above-mentioned side surfaces. | 09-08-2011 |
20110222256 | CIRCUIT BOARD WITH ANCHORED UNDERFILL - Various circuit boards and methods of manufacturing using the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a solder mask to a side of a circuit board and forming at least one opening in the solder mask leading to the side. An underfill is placed on the solder mask so that a portion thereof projects into the at least one opening. | 09-15-2011 |
20110222257 | INVERTER UNIT, INTEGRATED CIRCUIT CHIP, AND VEHICLE DRIVE APPARATUS - A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed. | 09-15-2011 |
20110235296 | Integrated circuit package component with ball conducting joints - The present invention relates to an integrated circuit package component with ball conducting joints, includes a substrate and a plurality of solder joints. The solder joints are installed on one surface of the substrate. The solder joints are arranged to form a concentric array having a first zone and a second zone, the second zone encircles the first zone. The soldering area of any solder joint in the first zone of the concentric array is smaller than that of any solder joint in the second zone of the concentric array. | 09-29-2011 |
20110235297 | Integrated circuit package component with lateral conductive pins - An integrated circuit package component with lateral conductive pins includes a package body having a middle conductive pin, an initial conductive pin and a final conductive pin. The middle conductive pin, the initial conductive pin and the final conductive pin are all disposed on a lateral side of the package body and respectively have a first soldering portion, a second soldering portion, and a third soldering portion, in which the middle conductive pin is arranged between the initial conductive pin and the final conductive pin, and an area of the middle conductive pin is smaller than that of the second soldering portion area and the third soldering portion in size. | 09-29-2011 |
20110235298 | Wiring substrate and method of manufacturing the wiring substrate - A wiring substrate includes a side-wall electroconduction layer and a land. The side-wall electroconduction layer is formed on the side-wall of a through hole formed in the substrate. The land is an electroconduction layer connected with the side-wall electroconduction layer in which only the land portion as a minimum necessary portion used for wiring is formed to the surface of the substrate. Unnecessary portion of the land other than the land portion is eliminated. | 09-29-2011 |
20110242782 | SUBSTRATE FOR AN ELECTRICAL DEVICE - Substrate for electrical devices is disclosed. An embodiment for the substrate comprised of an insulator and a conductive element(s), wherein the conductive element embedded in the insulator, said conductive element also enables to be comprised of an upper portion(s) and a lower portion(s) which are unitary and stack; wherein the surfaces of said conductive element contacted with said insulator enables to be increased, then said conductive layer can be held by said insulator more securely, in this manner, it enables to be prevented said conductive element from peeling off said insulator, and then the reliability of said substrate in accordance with the present invention enables to be enhanced; meanwhile, said substrate can further include a chip which is embedded therein, in order that said substrate being capable of affording a thinner electrical device thickness and enhanced reliability. | 10-06-2011 |
20110255258 | RESIN COMPOSITION, PREPREG, RESIN SHEET, METAL-CLAD LAMINATE, PRINTED WIRING BOARD, MULTILAYER PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE - Disclosed is a resin composition exhibiting a low thermal expansion coefficient, as well as higher heat resistance, flame resistance and insulation reliability than ever before when used in a multilayer printed wiring board that requires fine wiring work. Also disclosed are a prepreg, a resin sheet, a metal-clad laminate, a printed wiring board, a multilayer printed wiring board and a semiconductor device, all of which comprising the resin composition. The resin composition of the present invention comprises (A) an epoxy resin, (B) a cyanate resin and (C) an onium salt compound as essential components. | 10-20-2011 |
20110267791 | CIRCUIT CONNECTION MATERIAL, AND CONNECTION STRUCTURE OF CIRCUIT MEMBER AND CONNECTION METHOD OF CIRCUIT MEMBER USING THE CIRCUIT CONNECTION MATERIAL - A circuit connection material | 11-03-2011 |
20110267792 | DISPLAY APPARATUS AND DRIVING CHIP MOUNTING FILM IN THE DISPLAY APPARATUS - A display apparatus and a driving chip mounting film in the display apparatus, capable of simplifying a manufacturing process and reducing a process time. The display apparatus includes an insulating substrate; a display device formed on the insulating substrate and for defining an image display unit; pads formed on the insulating substrate and electrically connected to the display device; a first circuit substrate disposed at and separate from a first side of the insulating substrate; and a number of driving chip mounting films including one-side ends electrically connected to the first circuit substrate, and other-side ends electrically connected to the pads. A number of driving chips are mounted on each of the number of driving chip mounting films. | 11-03-2011 |
20110273857 | CONTACT SPRINGS FOR SILICON CHIP PACKAGES - A method for manufacturing a silicon chip package for a circuit board assembly is provided with a package substrate having a silicon chip and an array of contact pads provided by conductive material. A plurality of conductive springs are affixed to the array of contact pads for providing conductive contact with the corresponding array of contacts on a circuit board assembly. | 11-10-2011 |
20110286190 | Enhanced Modularity in Heterogeneous 3D Stacks - Enhanced modularity in heterogeneous three-dimensional computer processing chip stacks includes a method of manufacture. The method includes preparing a host layer and integrating the host layer with at least one other layer in the stack. The host layer is prepared by forming cavities on the host layer for receiving chips pre-configured with heterogeneous properties relative to each other, disposing the chips in corresponding cavities on the host layer, and joining the chips to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips. | 11-24-2011 |
20110286191 | Printed circuit board and semiconductor package with the same - Disclosed herein is a printed circuit board. The printed circuit board includes a base substrate including a first region on which a semiconductor chip is mounted and a second region positioned outside the first region, first insulating patterns covering the base substrate and including trenches formed on the second region, and second insulating patterns protruding from the first insulating patterns on the second region. The trench and the second insulating pattern may be used as a structure defining an underfill forming material in a preset shape during the process of forming an underfill. | 11-24-2011 |
20110286192 | PRINTED WIRING BOARD AND METHOD OF SUPPRESSING POWER SUPPLY NOISE THEREOF - Disclosed is a printed wiring board having signal layers each interposed between a power supply layer and a ground layer, wherein the signal layer includes at least one of a wiring region for a ground potential and a wiring region for a power supply potential. | 11-24-2011 |
20110292628 | ANTI-ULTRAVIOLET MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides an anti-UV electronic device and fabrication method thereof. The anti-ultraviolet (anti-UV) electronic device includes an integrated circuit die, wherein the integrated circuit die has an ultraviolet (UV) light erasable memory; and an anti-UV light layer is formed on and covers the ultraviolet (UV) light erasable memory. | 12-01-2011 |
20110304998 | Package Substrate - In accordance with an embodiment, a substrate layout comprises a ground plane of a first power loop on a layer of a substrate, a first trace rail on the layer extending along a first periphery of the ground plane, and a first perpendicular trace coupled to the first trace rail. The ground plane is between the first trace rail and a die area, and the first perpendicular trace extends perpendicularly from the first trace rail. The first trace rail and the first perpendicular trace are components of a second power loop. | 12-15-2011 |
20110304999 | Interposer-on-Glass Package Structures - A device includes an interposer including a substrate, and a first through-substrate via (TSV) penetrating through the substrate. A glass substrate is bonded to the interposer through a fusion bonding. The glass substrate includes a second TSV therein and electrically coupled to the first TSV. | 12-15-2011 |
20110317388 | ELECTRONIC DEVICE HAVING A WIRING SUBSTRATE - A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer. | 12-29-2011 |
20120008295 | WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A wiring board has a first resin insulation layer, a first conductive pattern formed on the first resin insulation layer, a second resin insulation layer formed on the first conductive pattern and having an opening portion exposing at least a portion of the first conductive pattern, a second conductive pattern formed on the second resin insulation layer, and a via conductor formed in the opening portion of the second resin insulation layer and electrically connecting the first conductive pattern and the second conductive pattern. The via conductor has a side surface extending between the first conductive pattern and the second conductive pattern and a bent portion where an inclination of the side surface of the via conductor changes in a depth direction of the via conductor. | 01-12-2012 |
20120020044 | ELECTRONIC MODULE WITH VERTICAL CONNECTOR BETWEEN CONDUCTOR PATTERNS - The present invention generally relates to a new structure to be used with electronic modules such as printed circuit boards and semiconductor package substrates. Furthermore there are presented herein methods for manufacturing the same. According to an aspect of the invention, the aspect ratio of through holes is significantly improved. Aspect ratio measures a relationship of a through hole or a micro via conductor in the direction of height divided width. According to the aspect of the invention, the aspect ratio can be increased over that of the prior art solution by a factor of ten or more. | 01-26-2012 |
20120026708 | CARRIER SUBSTRATE AND METHOD FOR MAKING THE SAME - A carrier substrate includes a substrate having a chip side and a PCB side, a plurality of bond pads disposed on the chip side for bonding a chip, a plurality of land grid array (LGA) pads disposed on the PCB side, and a plurality of resilient flanges installed on the PCB side in an array manner. The plurality of resilient flanges electrically connects with the LGA pads correspondingly. | 02-02-2012 |
20120063107 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes stacked semiconductor die. In accordance with embodiments, the semiconductor component includes a substrate having a component receiving area and a plurality of bond pads. A semiconductor chip is attached to the component receiving area. An electrical connector is coupled to the semiconductor chip and the substrate. A second semiconductor chip is mounted or attached to one of the ends of the electrical connector such that this end is positioned between the semiconductor chips. A second electrical connector is coupled between the second semiconductor chip and the substrate. A third semiconductor chip is mounted over or attached to the second electrical connector such that a portion is between the second and third semiconductor chips. | 03-15-2012 |
20120063108 | CIRCUIT BOARD AND SEMICONDUCTOR MODULE INCLUDING THE SAME - In one embodiment, a circuit board is disclosed. The circuit board includes a first metal core; a second metal core spaced apart from the first metal core in a first direction when viewed as a cross section, such that a first side of the first metal core faces a first side of the second metal core; a first electrode electrically connected to the first side of the first metal core; a second electrode electrically connected to the first side of the second metal core facing the first metal core; and a dielectric layer between the first and second electrodes. | 03-15-2012 |
20120075821 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A SHIELD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a first integrated circuit over the substrate; forming an encapsulant around the first integrated circuit and over the substrate; and forming a shield structure within and over the encapsulant while simultaneously forming a vertical interconnect structure. | 03-29-2012 |
20120075822 | ORGANIC PRINTED CIRCUIT BOARD HAVING REINFORCED EDGE FOR USE WITH WIRE BONDING TECHNOLOGY - Disclosed herein are electronic devices, such as, for example, televisions, stereo systems, diagnostic equipment, cell phones, desktop or laptop PCs, medical pulse generators, or etc., including an integrated circuit including a printed circuit board including multiple layers and a wire bond pad. The multiple layers are sandwiched together in a planar unitary structure including a top surface, a bottom surface and a structure edge extending between the top surface and the bottom surface. The multiple layers include a first organic substrate layer joined to a second organic substrate layer. Each organic substrate layer includes a layer edge and a peripheral surface adjacent the layer edge. Each layer edge forms part of the structure edge. The wire bond pad includes an outer face, an inner face generally opposite the outer face, and a first rib. The inner face extends along the structure edge. The first rib projects generally perpendicular from the inner face between the first organic substrate layer and the second organic substrate layer and extends along the peripheral surface of at least one of the first organic substrate layer or the second organic substrate layer. | 03-29-2012 |
20120081871 | WARP REACTIVE IC PACKAGE - An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of a layer of material bonded to the top of the integrated circuit package. The layer of material may have a generally planar-convex or a generally planar-concave cross-section. By appropriate choice of temperature coefficient and degree of concavity or convexity, the layer of material can compensate for either convex or concave warpage. In some embodiments the layer of material has apertures therein allowing compensation for more complex warpages. The apparatus provides an alternative to apparatus for dealing with IC package warpage known in the art. | 04-05-2012 |
20120081872 | THERMAL WARP COMPENSATION IC PACKAGE - An apparatus and method for temperature induced warpage compensation in an integrated circuit package is disclosed. The apparatus consists of bonded layers of material having different thermal coefficients of expansion. The bonded layers are bonded to the top of the integrated circuit package. By appropriate choice of temperature coefficients the layers of material can compensate for either convex or concave warpage. In some embodiments the layers of material have apertures therein allowing compensation for more complex warpages. As well, in some embodiments the top layer of material does not have a planar cross-section. A method is also disclosed for manufacturing an integrated circuit package assembly. The apparatus and method provide an alternative to methods of dealing with IC package warpage known in the art. | 04-05-2012 |
20120087099 | Printed Circuit Board For Board-On-Chip Package, Board-On-Chip Package Including The Same, And Method Of Fabricating The Board-On-Chip Package - Provided is a printed circuit board for a board-on-chip package prepared with a strip level of a plurality of unit substrates and including a reject marking portion for determining whether there is a defective unit substrate, wherein the reject marking portion is in each unit substrate. | 04-12-2012 |
20120106111 | ANISOTROPIC ELECTRICALLY AND THERMALLY CONDUCTIVE ADHESIVE WITH MAGNETIC NANO-PARTICLES - A composition of matter comprising a plurality of nanoparticles in a non-conductive binder, wherein, the type of nanoparticles form isolated parallel electrically and thermally conductive columns when cured in the presence of the magnetic field. Also wherein the plurality of nanoparticles are Paramagnetic or Ferromagnetic magnetic. Wherein the nano particles are coated, and of a particular shape. Wherein the particles are selected from the group consisting of; Al, Pt, Cr, Mn, crown glass, Fe, Ni, and Co, Ni—Fe/SiO | 05-03-2012 |
20120106112 | Method for Producing an Electrical Circuit and Electrical Circuit - A method for producing an electrical circuit includes providing a main printed circuit board having a plurality of metalized plated-through holes through the main printed circuit board along at least one separating line between adjacent printed circuit board regions of the main printed circuit board. Each printed circuit board region has electrical contact connection pads on at least the main surface of the printed circuit board region that is to be populated, electrical lines for connection between the plurality of plated-through holes and the contact connection pads, and at least one semiconductor chip electrically contact-connected by means of the contact connection pads. The main printed circuit board is covered with a potting compound across the printed circuit board regions with the semiconductor chips. | 05-03-2012 |
20120120624 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate | 05-17-2012 |
20120127683 | ELECTRONIC DEVICE, RESONATOR, OSCILLATOR AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device includes a substrate, a functional structural body formed on the substrate and a covering structure for defining a cavity part having the functional structural body disposed therein, wherein the covering structure is provided with a side wall provided on the substrate and comprising an interlayer insulating layer surrounding the cavity part and a wiring layer; a first covering layer covering an upper portion of the cavity part and having an opening penetrating through the cavity part and composed of a laminated structure including a corrosion-resistant layer; and a second covering layer for closing the opening. | 05-24-2012 |
20120127684 | INSULATION CIRCUIT BOARD, AND POWER SEMICONDUCTOR DEVICE OR INVERTER MODULE USING THE SAME - The invention relates to a high-voltage insulation circuit board which is used in an electric power apparatus such as an electric power converter or the like such as power semiconductor device, inverter module, or the like and provides an insulation circuit board in which electric field concentration at the end sections of a wiring pattern is reduced, partial discharging is suppressed, and a reliability is high. According to the invention, there is provided an insulation circuit board having: a metal base substrate; and wiring patterns which are formed onto at least one of the surfaces of the metal base substrate through an insulation layer, characterized in that between two adjacent wiring patterns in which an electric potential difference exists among the wiring patterns, at least one or more wiring patterns or conductors which are in contact with the insulation layer and have an electric potential in a range of the electric potential difference between the adjacent wiring patterns are arranged. According to the invention, the electric field concentration at the end sections of the wiring pattern to which a high voltage is applied is reduced and partial-discharge-resistant characteristics are improved. | 05-24-2012 |
20120155044 | ELECTRONIC CIRCUIT BOARD AND A RELATED METHOD THEREOF - An apparatus includes a set of first metal contact pads disposed on a low temperature co-fired ceramic substrate. A plurality of metalized interconnectors extend between a digital electronic component and the low temperature co-fired ceramic substrate. The apparatus is configured to operate at a temperature greater than 250 degrees Celsius. | 06-21-2012 |
20120155045 | CLIP FOR BIOS CHIP - A clip for a basic input/output system (BIOS) chip includes a main body, two spindles, two clipping elements, and two torsion springs. The main body includes a number of connecting pins mounted on a bottom of the main body, and a number of signal pins mounted on a top of the main body and electrically and correspondingly connected to the number of the connecting pins. The clipping elements are rotatably mounted to opposite ends of the main body through the spindles. The torsion springs are mounted between the clipping members and the main body. The connecting pins of the main body respectively electrically contacts a number of chip pins of the BIOS chip in response to the clipping elements clipping the BIOS chip. | 06-21-2012 |
20120155046 | PRINTED CIRCUIT BOARD - A printed circuit board (PCB) includes a top layer, a memory controller, two gaps, and two connectors. The memory controller is located on the top layer. A number of golden fingers are respectively set on the top layer near each gap and electrically connected to the memory controller. Each connector includes a first slot to hold the gold fingers near a corresponding one of the gaps and a second slot to hold a number of gold fingers of a corresponding one of two memory chips. The first slot is electrically connected to the second slot. Each memory chip and the PCB are coplanar. | 06-21-2012 |
20120155047 | PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a package and a method for manufacturing the same. The package includes: a first package including a first printed circuit board having a first surface and a second surface and having a first die mounted on the first surface, the first die having a through silicon via; a second package including a second printed circuit board having a first surface and a second surface and having a second die mounted on the first surface, the second die having a through silicon via; first external connecting terminals electrically interconnecting the first surface of the first printed circuit and the first surface of the second printed circuit disposed to be opposite to each other; and first connecting bumps electrically interconnecting the first and second dice. Therefore, power signals are independently applied to each of the dice, thereby making it possible to improve power stability of each of the dice. | 06-21-2012 |
20120155048 | WIRING BOARD, SEMICONDUCTOR APPARATUS AND METHOD OF MANUFACTURING THEM - There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step. | 06-21-2012 |
20120162947 | VERTICALLY INTEGRATED SYSTEMS - Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer. | 06-28-2012 |
20120162948 | SENSOR MODULE - A sensor module. One embodiment provides a cap whose perimeter defines a rim. A first semiconductor chip is attached to the cap. The first semiconductor chip includes first connection elements. The rim and the first connection elements define a common plane. | 06-28-2012 |
20120170240 | METHOD OF MANUFACTURING A MULTILAYER PRINTED WIRING BOARD FOR PROVIDING AN ELECTRONIC COMPONENT THEREIN - A multilayer printed wiring board and method for manufacturing a multilayer printed wiring board. One method include a method for manufacturing a multilayer printed wiring board having an electronic component housed therein. The method includes forming a conduction circuit on a core substrate and forming an alignment mark on the core substrate separate from the conduction circuit. Also included is forming a concavity in the core substrate, the concavity being formed in an area of the core substrate not including the conductor circuit and alignment mark, and inserting the electronic component into the concavity in the core substrate by using the alignment mark on the core substrate to align the electronic component with the concavity. | 07-05-2012 |
20120170241 | PRINTING INK, METAL NANOPARTICLES USED IN THE SAME, WIRING, CIRCUIT BOARD, AND SEMICONDUCTOR PACKAGE - Disclosed is a printing ink comprising Cu- and/or CuO-containing metal nanoparticles, which obtains excellent dispersion properties and successive dispersion stability without using additives such as dispersing agents. Specifically disclosed is a printing ink that comprises Cu- and/or CuO-containing metal nanoparticles and has no more than 2,600 ppm of ionic impurities in the total solid content. The printing ink is obtained by dispersing the Cu- and/or CuO-containing metal nanoparticles, which have no more than 2,600 ppm of ionic impurities in the total solid content, in a dispersion medium. | 07-05-2012 |
20120188737 | MOTHERBOARD AND MEMORY CONNECTOR THEREOF - A motherboard includes a printed circuit board (PCB) and a memory connector. The PCB includes top and bottom layers. A number of pads are set on the sides of the top and bottom layers and connected to a memory controller. A number of metal pins are set on a first sidewall of the memory connector. A socket slot is defined in a second sidewall opposite to the first sidewall. Top and bottom sidewalls bounding the socket slot define a number of grooves. First ends of the metal pins are soldered on the pads of the top layer and the bottom layer of the PCB. Second ends of the metal pins are extended to the socket slot through the memory connector and exposed through the grooves of the memory connector, to be electrically connected to the golden fingers of a memory when the memory is inserted in the socket slot. | 07-26-2012 |
20120206891 | CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE HAVING COMPONENT MOUNTED ON CIRCUIT BOARD - A circuit board H | 08-16-2012 |
20120218728 | Carrier Device, Arrangement Comprising such a Carrier Device, and Method for Patterning a Layer Stack Comprising at Least One Ceramic Layer - A method for patterning a layer stack with at least one ceramic layer includes providing the ceramic layer, which has at least one plated-through hole. An electrically conductive layer is applied above the ceramic layer, such that the electrically conductive layer is electrically coupled to the at least one plated-through hole. A further layer is deposited onto the electrically conductive layer in the region of the at least one plated-through hole, wherein the further layer includes nickel. The electrically conductive layer is removed outside the region of the at least one plated-through hole. A carrier device patterned in this way can be electrically and mechanically coupled to an electronic component. | 08-30-2012 |
20120224346 | ARRANGEMENT WITH CHIP AND CARRIER - An apparatus includes chip and a carrier of the chip. A ridge is positioned between the chip and the carrier. The ridge is adapted to increase thermal contact between the chip and the carrier. The chip is attached to a contact surface on the carrier by an adhesive member. | 09-06-2012 |
20120229999 | CIRCUIT BOARD CLAMPING MECHANISM - Methods and apparatus for clamping a first circuit board against a member are provided where the first circuit board has a first side and a second side opposite the first side. The method includes engaging an elastomeric member of a clamping member with the first side of the first circuit board to compliantly bear against the first side of the first circuit board whereby the second side of the circuit board is clamped against the member. | 09-13-2012 |
20120236524 | STACKED INTEGRATED COMPONENT DEVICES WITH ENERGIZATION - This invention discloses a device comprising multiple functional layers formed on substrates, wherein at least one functional layer comprises an electrical energy source. In some embodiments, the present invention includes a component for incorporation into ophthalmic lenses that has been formed by the stacking of multiple functionalized layers. | 09-20-2012 |
20120250282 | FASTENING AND ELECTROCONDUCTIVE CONNECTING OF A CHIP MODULE TO A CHIP CARD - For manufacturing a chip card, a chip module ( | 10-04-2012 |
20120268909 | Enhanced Modularity in Heterogeneous 3D Stacks - A three-dimensional computer processing chip stack that includes a host layer disposed on at least one other layer in the stack. The host layer includes cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other. The cavities are formed to accommodate the heterogeneous properties of the chips. The chips are joined to respective surfaces of the cavities, thereby forming an element having a smooth surface with respect to the host layer and the chips. | 10-25-2012 |
20120287589 | ELECTRONIC MODULE AND COMMUNICATION APPARATUS - An electronic module with excellent electrical characteristics includes an electronic component, a mount board, signal electrodes, a ground electrode, and an insulating layer. The electronic component is mounted on a first main surface of the mount board. The signal electrodes and the ground electrode are located on a second main surface of the mount board. The insulating layer is arranged so as to cover a portion of the second main surface of the mount board. The insulating layer is arranged so as not to cover end portions of the signal electrodes that face the ground electrode. | 11-15-2012 |
20120293973 | MULTILAYERED WIRING BOARD AND METHOD FOR FABRICATING THE SAME - In a multilayered wiring board constituted by laminating to form pluralities of layers of wiring layers | 11-22-2012 |
20120307470 | WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a substrate body formed of an inorganic material and including a first surface and a second surface, a first trench formed in a first surface side of the substrate body, a second trench formed in a second surface side of the substrate body, a penetration hole penetrating through the substrate body, a first plane layer filling the first trench, a second plane layer filling the second trench, and a penetration wiring filling the penetration hole. The first plane layer is a reference potential layer. The second plane layer is a power supply layer. | 12-06-2012 |
20120327626 | WIRING SUBSTRATE, ITS MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE - One embodiment provides a wiring substrate including: a core substrate having an insulative base member, the insulative base member having a first surface and a second surface, a plurality of linear conductors penetrating through the insulative base member from the first surface to the second surface; an inorganic material layer joined to at least one of the first surface and the second surface of the insulative base member; and a penetration line penetrating through the inorganic material layer, wherein one end of the penetration line is electrically connected to a corresponding part of the linear conductors, without intervention of a bump. | 12-27-2012 |
20130003335 | CORELESS MULTI-LAYER CIRCUIT SUBSTRATE WITH MINIMIZED PAD CAPACITANCE - A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers. | 01-03-2013 |
20130010446 | LAMINATE ELECTRONIC DEVICE - A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 μm. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip. | 01-10-2013 |
20130021767 | DOUBLE-SIDED PRINTED CIRCUIT BOARD - A double-sided PCB includes a circuit plate, a first chip, and a second chip. The circuit plate includes a spacer layer having a first surface and an opposing second surface, a first multilayer structure, and a second multilayer structure. The first multilayer structure includes a first wire layer, a first middle layer, and a second wire layer having a first grounding portion and first conductive pattern portions, that are stacked on each other on the first surface. The second multilayer structure on the second surface is either a mirror image of the first multilayer structure, or is very similar thereto. The first and second chips are each arranged on a grounding portion and are each electrically connected to their respective conductive pattern portions. | 01-24-2013 |
20130021768 | CHIP-ON-FILM PACKAGES AND DEVICE ASSEMBLIES INCLUDING THE SAME - Chip-on-film packages are provided. A chip-on-film package includes a film substrate having a first surface and a second surface opposite to each other, a semiconductor chip on the first surface, and a thermal deformation member adjacent to the second surface. The thermal deformation member has a construction that causes its shape to transform according to a temperature. Related devices and device assembles are also provided. | 01-24-2013 |
20130021769 | MULTICHIP MODULE, PRINTED WIRING BOARD, METHOD FOR MANUFACTURING MULTICHIP MODULE, AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD - A multichip module includes an arithmetic element that is a semiconductor element that executes arithmetic processing and a memory element that is arranged opposite the arithmetic element and that is a semiconductor element that stores therein data. Then, the multichip module includes the arithmetic element mounted thereon and includes a package board that includes, on a surface on which the arithmetic element is mounted, an external terminal that connects another part. Furthermore, the multichip module includes a reinforcing part on a surface at the opposite side from the surface of the package board on which the external terminal and that is arranged such that the reinforcing part covers an area from outside the peripheral portion of the arithmetic element to a predetermined position located on the central side of the package board. | 01-24-2013 |
20130033839 | ELECTRIC DEVICE AND PRODUCTION METHOD THEREFOR - An electric device includes a support substrate 12, an electric circuit 14 provided in a sealing region set on the support substrate 12, an electric wiring provided on the support substrate 12 for electrically connecting an external electrical signal input/output source with the electric circuit 14, a sealing member 16 provided on the support substrate 12 to surround the sealing region, and a sealing substrate 17 bonded to the support substrate 12 with the sealing member 16 interposed therebetween. the electric circuit 14 includes an electronic element 24 having an organic layer, and a width of the sealing member 16 differs between an intersection region in which the electric wiring 15 and the sealing member 16 intersect each other and a non-intersection region excluding the intersection region. | 02-07-2013 |
20130033840 | TRANSFER METHOD FOR MANUFACTURING CONDUCTOR STRUCTURES BY MEANS OF NANO-INKS - A method for equipping a film material with at least one electrically conductive conductor structure, wherein a dispersion containing metallic nanoparticles in the form of a conductor structure is applied to a thermostable transfer material and the metallic nanoparticles are sintered to form an electrically conductive conductor structure. The electrically conductive conductor structure of sintered metallic nanoparticles is then transferred from the thermostable transfer material to the non-thermostable film material. A method for producing a laminate material using the film material using at least one electrically conductive conductor structure, and to the corresponding film material and laminate material are described. | 02-07-2013 |
20130044450 | MOTHERBOARD ASSEMBLY HAVING SERIAL ADVANCED TECHNOLOGY ATTACHMENT DUAL IN-LINE MEMORY MODULE - A motherboard assembly includes a motherboard and a serial advanced technology attachment dual-in-line memory module (SATA DIMM) module with a circuit board. The motherboard includes an expansion slot and a storage device interface. An edge connector is set on a bottom edge of the circuit board to be detachably engaged in the expansion slot, and a notch is set on a bottom edge of the circuit board to engage in a protrusion of the expansion slot. A SATA connector of the circuit board is connected to the storage device interface of the motherboard. | 02-21-2013 |
20130050968 | CIRCUIT BOARD WITH HIGHER CURRENT - A circuit board includes a plurality of conductive layers, at least one group of vias, a number of second vias, at least one power supply element, and at least one electronic element. Each conductive layer includes a conductive portion. Both the first vias and the second vias are defined through the conductive layers and electrically connected each conductive layers. The at least one group of first vias surrounds the at least one power supply element. The second vias are arranged along the side of the conductive portion, and positioned between the power supply element and the electronic element. Current from a power supply element flows to the inner conductive layers through the group of surrounding first vias. Current transmission on each conductive layer continuously flows to another conductive layer having a lower resistance through the second vias during transmission. | 02-28-2013 |
20130058062 | METHOD FOR MANUFACTURING BASE MATERIAL HAVING GOLD-PLATED METAL FINE PATTERN, BASE MATERIAL HAVING GOLD-PLATED METAL FINE PATTERN, PRINTED WIRING BOARD, INTERPOSER, AND SEMICONDUCTOR DEVICE - A method for manufacturing a base material having a gold-plated metal fine pattern is disclosed, comprising the steps of preparing a base material having a supporting surface made of a resin; forming a primer resin layer having surface roughness of 0.5 μm or less on the supporting surface, and forming a metal fine pattern thereon by an SAP process to obtain a base material having a metal fine pattern; and applying a gold-plating treatment to at least one part of a surface of the metal fine pattern; wherein the base material having a metal fine pattern is subjected to a palladium removal treatment in an optional stage before carrying out the gold-plating treatment. | 03-07-2013 |
20130077275 | ELECTRONIC DEVICE, WIRING SUBSTRATE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - Even in an electronic device where electrodes are coupled electrically using a solder, sections to which electrodes of an electronic component are coupled are switched by a method other than changing circuits of the electronic component or changing circuits of a wiring substrate. | 03-28-2013 |
20130083503 | PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE - A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided. | 04-04-2013 |
20130083504 | ELECTRONIC DEVICE - An electronic device includes: a first plate; a wiring board arranged on the first plate and configured to have a plurality of first terminals on a surface opposite to a surface facing the first plate; an electronic component arranged above the wiring board and configured to have a plurality of second terminals on a surface facing the wiring board; a connecting unit arranged between the wiring board and the electronic component and configured to electrically couple the first terminals and the second terminals; a second plate arranged on the electronic component; a fixing unit arranged in an area outside of an area where the electronic component is placed and configured to pressurize the first plate and the second plate; and a pressing unit arranged below the area where the electronic component is placed and configured to press the wiring board toward the electronic component. | 04-04-2013 |
20130088842 | PREPREG, METAL-CLAD LAMINATE, PRINTED WIRING BOARD, AND SEMICONDUCTOR DEVICE - A prepreg that yields a semiconductor device which, even when using Cu wire, exhibits excellent reliability under conditions of high temperature and high humidity (heat-resistant and moisture-resistant reliability), a metal-clad laminate and a printed wiring board that use the prepreg, and a semiconductor device that uses the printed wiring board. Specifically disclosed are a prepreg comprising a substrate and a B-staged resin composition comprising (a) a thermosetting resin, (b) a hydrotalcite compound having a specific composition, (c) zinc molybdate, and (d) lanthanum oxide. | 04-11-2013 |
20130100624 | CIRCUIT BOARD CONTACT PADS - The present disclosure provides a circuit board with a first via and a second via, the first and second vias providing an electrical path from a top surface of the circuit board to a bottom surface of the circuit board. The circuit board also includes a first contact pad electrically coupled to the first via and a second contact pad electrically coupled to the second via. The first contact pad is disposed at an angle with respect to a reference line crossing through the center of the first and second vias, and the second contact pad is disposed on an opposite side of the reference line at the angle with respect to the reference line, such that a footprint that encompasses an area between the first and second contact pads does not cover the first and second vias. | 04-25-2013 |
20130100625 | WIRING BOARD, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING WIRING BOARD - A wiring board includes a resin substrate in which reinforcement members are arranged horizontally, a through electrode filled in a through hole penetrating the substrate in a thickness direction, and wiring layers respectively formed on both surfaces of the substrate and electrically connected to each other via the through electrode. The reinforcement members are arranged such that reinforcement members arranged in a middle region of the substrate in the thickness direction has higher density than reinforcement members arranged in the regions other than the middle region of the substrate. | 04-25-2013 |
20130100626 | WIRING SUBSTRATE AND MANUFACTURING METHOD OF THE SAME - Embodiments of the present invention provide a wiring substrate having a structure where a plurality of projection electrodes are arranged within an electrode formation region on a substrate main surface. At least one among a plurality of the projection electrodes is a variant projection electrode which has a recess portion on an upper surface, an outer diameter at the upper end that is larger than an outer diameter at the lower end, and a reverse trapezoidal cross-section shape. Embodiments of the present invention also provide methods for manufacturing wiring substrates having one or more of said variant projection electrode. | 04-25-2013 |
20130114226 | COF Packaging Unit and COF Packaging Tape - The invention discloses a COF packaging unit and a COF packaging tape. The COF packaging unit comprises COF baseband(s), IC Die(s) packaged on the COF baseband(s), and input end wires and output end wires connected with the IC Die(s); the input end wires and the output end wires are respectively provided with input terminals and output terminals at two edges of the COF baseband. In the invention, because the input terminals and the output terminals are pitched along the edges of the COF baseband, the length of the single COF packaging unit is set in accordance with the pitching requirement of the input end wires and the output end wires, so that the COF baseband can have sufficient area for wiring, to adapt to the requirement of large LCD panels. Thus, resources are reasonably integrated and used, equipment utilization rate is increased, material purchasing cost is saved, and economic benefits are increased. | 05-09-2013 |
20130114227 | Efficient electronics module - An efficient electronics package comprising an integrated circuit, a transistor case packaging, a power supply, an actuation segment and a sensor segment, wherein engagement of the integrated circuit causes the actuation segment to be activated. The integrated circuit may be engaged, for example, by a level-hold trigger or the sensor segment. | 05-09-2013 |
20130114228 | ELECTROMAGNETIC INTERFERENCE SHIELDING TECHNIQUES - Methods and apparatuses are disclosed for fabricating a printed circuit board (PCB) having electromagnetic interference (EMI) shielding and also having reduced volume over conventional frame-and-shield approaches. Some embodiments include fabricating the PCB by mounting an integrated circuit to the PCB, outlining an area corresponding to the integrated circuit with a number of grounded vias, selectively applying an insulating layer over the PCB such that at least one of the grounded vias are exposed, and selectively applying a conductive layer over the PCB such that the conductive layer covers at least a portion of the integrated circuit and such that the conductive layer is coupled to the at least one of the grounded vias that are exposed. | 05-09-2013 |
20130120951 | STACKED CMOS CHIPSET HAVING AN INSULATING LAYER AND A SECONDARY LAYER AND METHOD OF FORMING SAME - A chipset includes a sheet of glass, quartz or sapphire and a first wafer having at least one first circuit layer on a first side of a first substrate layer. The first wafer is connected to the sheet such that the at least one first circuit layer is located between the first substrate layer and the sheet. A second wafer having at least one second circuit layer on a first side of a second substrate layer is connected to the first substrate layer such that the at least one second circuit layer is located between the second substrate layer and the first substrate layer. Also a method of forming a chipset. | 05-16-2013 |
20130120952 | SUBSTRATE AND ELECTRONIC DEVICE INCLUDING THE SUBSTRATE - A substrate and an electronic device including the substrate are described. The substrate includes a first surface configured such that a semiconductor package or a semiconductor die is installable thereon, and a second surface facing the first surface, wherein, with respect to a central plane disposed between the first surface and the second surface at equal distances therefrom, a coefficient of thermal expansion in a first portion between the first surface and the central plane is configured to be higher than a coefficient of thermal expansion in a second portion between the second surface and the central plane configured to be. By using the substrate, undesirable overall shape deformation during semiconductor installation may be reduced or relieved. | 05-16-2013 |
20130170167 | PRINTED CIRCUIT BOARD - A multi-layer printed circuit board includes an embedded capacitor substrate composed of a power source conductor layer and a ground conductor layer, the layers being disposed close to each other. The power source conductor layer has a first power source plane to supply power to a circuit element, and a second power source plane that is separated from the first power source plane by a gap and functions as a main power source. The first power source plane is partially connected to the second power source plane by a connecting line. The ground conductor layer has an opening at a position overlapping with a projected image when the connecting line is projected on the ground conductor layer. This structure suppresses propagation of the noise caused at the circuit element and reduces radiation noise in the printed circuit board. | 07-04-2013 |
20130208434 | FLIP-CHIP MOUNTED MICROSTRIP MONOLITHIC MICROWAVE INTEGRATED CIRCUITS (MMICs) - A microstrip MMIC chip flip-chip mounted to a printed circuit board with conductive vias passing through the chip to electrical connect a ground plane of the microstrip MMIC chip to a ground conductor of the printed circuit board. | 08-15-2013 |
20130215587 | MULTILAYER WIRING BOARD AND ELECTRONIC DEVICE - Provided is a multilayer wiring board including a plurality of signal layers and ground layers. The multilayer wiring board includes: a first differential wiring wired to a third signal layer; and a second differential wiring wired to a ninth signal layer disposed above the third signal layer. The multilayer wiring board includes a first differential signal via and a second differential signal via that are connected to the first differential wiring. The multilayer wiring board includes a third differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer. The multilayer wiring board includes a fourth differential signal via which is connected to the second differential wiring and a stub of which is terminated above the third signal layer, the first differential wiring wired to pass between the fourth differential signal via and the third differential signal via. | 08-22-2013 |
20130215588 | MULTILAYERED WIRING SUBSTRATE AND ELECTRONIC APPARATUS - A multilayered wiring substrate that includes at least one signal layer and at least one ground layer is provided. The multilayered wiring substrate includes a first signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to one of a pair of differential signaling wires provided in the signal layer, and is formed on a first grid point; and a second signal via that extends in a direction substantially perpendicular to the layers of the multilayered wiring substrate, is conductively connected to the other of the pair of differential signaling wires, and is formed on a second grid point that is positioned diagonally adjacent with respect to the first signal via. | 08-22-2013 |
20130229777 | CHIP ARRANGEMENTS AND METHODS FOR FORMING A CHIP ARRANGEMENT - A chip arrangement is provided: the chip arrangement including: a carrier; a chip disposed over the carrier; a ceramic layer formed over the chip and on at least a portion of the carrier; wherein the chip is surrounded by the carrier and the ceramic layer. | 09-05-2013 |
20130235544 | INTEGRATED CIRCUIT STACK - In some examples, an integrated circuit system includes a plurality of integrated circuit layers. At least one of the integrated circuit layers includes an integrated circuit die, which may not include any through-silicon vias that provide a pathway to an adjacent integrated circuit layer, and an interposer portion, which includes electrically conductive through-vias. The interposer portion may facilitate communication of the integrated circuit die with other integrated circuit layers of the integrated circuit system. In some examples, the stacked integrated circuit system may include more than one integrated circuit die, which may be in the same integrated circuit layer as at least one other integrated circuit die, or may be in a different integrated circuit layer. | 09-12-2013 |
20130235545 | MULTILAYER WIRING BOARD - In a multilayer wiring board | 09-12-2013 |
20130242520 | INSULATING SUBSTRATE, METAL-CLAD LAMINATE, PRINTED WIRING BOARD AND SEMICONDUCTOR DEVICE - The present invention provides: an insulating substrate or metal-clad laminate able to sufficiently reduce or prevent negative warping of a semiconductor device; a printed wiring board that uses the insulating substrate or metal-clad laminate; and a semiconductor device. The insulating substrate is composed of a cured product of a laminate including one or more fibrous base material layers and two or more resin layers, in which the outermost layers on both sides is the resin layers. At least one of the fibrous base material layers is shifted towards the first side or a second side on the opposite side thereof with respect to the reference position, namely the dividing position at which a total thickness of the insulating substrate is equally divided by the number of the fibrous base material layers and each divided region having the thickness is further equally divided by two. The fibrous base material layers are not shifted in different directions. It is possible to produce a printed wiring board by using, as a core substrate, a metal-clad laminate containing the insulating substrate. Also, it is possible to produce a semiconductor device by mounting a semiconductor element onto the printed wiring board. | 09-19-2013 |
20130250535 | SEMICONDUCTOR DEVICE - Aspects of the invention are directed to a power module including a metal base, an insulating substrate which is attached to the metal base, a semiconductor chip and a control terminal which are attached to a circuit pattern of the insulating substrate, and a resin case which is attached to the metal base. The control terminal can include a penetration portion which penetrates a cover of the resin case, an L-shaped processed portion which is connected to the penetration portion, and a connection portion which is connected to the L-shaped processed portion. A protrusion portion can be installed in a portion of the control terminal, which penetrates the cover. The protrusion portion can be in contact with a protrusion receiving portion which is configured with a front surface of the cover. The L-shaped processed portion can be in contact with a convex portion in a rear surface of the cover. | 09-26-2013 |
20130250536 | ELECTRONIC DEVICE - An electronic device comprising a laminate comprising pluralities of insulator layers each provided with conductor patterns, and an amplifier-constituting semiconductor device mounted to a mounting electrode formed on an upper surface of the laminate, a first ground electrode being formed on an insulator layer near an upper surface of the laminate; a second ground electrode being formed on an insulator layer near a lower surface of the laminate; the first ground electrode being connected to the mounting electrode through pluralities of via-holes; conductor patterns constituting the first circuit block being disposed in a region below the amplifier-constituting semiconductor device between the first ground electrode and the second ground electrode; and at least part of a conductor pattern for a line connecting the first circuit block to the amplifier-constituting semiconductor device being disposed on an insulator layer sandwiched by the mounting electrode and the first ground electrode. | 09-26-2013 |
20130258628 | POWER CONVERTER - A power module includes a power module body portion and a wiring board. The power module body portion includes P-side semiconductor elements and N-side semiconductor elements, and a P-side terminal connection portion, a U-phase terminal connection portion, and an N-side terminal connection portion which establish electrical connection with the wiring board on an upper surface of the power module body portion and into which a current flows from the wiring board and from which a current flows to the wiring board. | 10-03-2013 |
20130265734 | INTERCHIP COMMUNICATION USING EMBEDDED DIELECTRIC AND METAL WAVEGUIDES - An apparatus is provided. There is a circuit assembly with a package substrate and an integrated circuit (IC). The package substrate has a microstrip line, and the IC is secured to the package substrate and is electrically coupled to the microstrip line. A circuit board is also secured to the package substrate. A dielectric waveguide is secured to the circuit board. The dielectric waveguide has a dielectric core that extends into a transition region located between the dielectric waveguide and the microstrip line, and the microstrip line is configured to form a communication link with the dielectric waveguide. | 10-10-2013 |
20130265735 | METAL NANOPARTICLE PASTE, ELECTRONIC COMPONENT ASSEMBLY USING METAL NANOPARTICLE PASTE, LED MODULE, AND METHOD FOR FORMING CIRCUIT FOR PRINTED WIRING BOARD - Disclosed is a metal nanoparticle paste that uses the low-temperature sintering characteristics of metal nanoparticles to easily obtain a metal bond with excellent conductivity and mechanical strength, and which can form a wiring pattern with excellent conductivity. The metal nanoparticle paste is characterized by containing (A) metal nanoparticles, (B) a protective film that coats the surface of the metal nanoparticles, (C) a carboxylic acid, and (D) a dispersion medium. | 10-10-2013 |
20130265736 | WIRING BOARD AND ELECTRONIC APPARATUS - The present disclosure provides a wiring board including a thin film member configured to include an inorganic dielectric film formed over an overall area of a mounting face thereof for an electronic part, a first conductive film formed over an overall area of one of faces of the inorganic dielectric film and including a plurality of patch electrode portions disposed in a predetermined pattern corresponding to a predetermined electromagnetic band gap structure in at least part of the area, and a second conductive film formed over an overall area of the other face of the inorganic dielectric film. | 10-10-2013 |
20130286620 | Package with Integrated Pre-Match Circuit and Harmonic Suppression - A package is connected at a first side to a printed circuit board and with a die fixed to it on a second side opposite to the first side. The package has an integrated pre-match circuit to provide an impedance match for a signal to be sent to a circuit external to the package. The signal has a predetermined main frequency component. The pre-match circuit has a pair of transmission lines and a pair of stubs on a predetermined layer of the package and connected to the pair of transmission lines. The pair of stubs have a length such as to form a short circuit for an harmonic frequency of the main frequency component in the signal. | 10-31-2013 |
20130286621 | Pb-FREE SOLDER-CONNECTED STRUCTURE - Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength. | 10-31-2013 |
20130308287 | POWER DEVICE AND PACKAGE FOR POWER DEVICE - The present invention addresses the problem of providing a power device comprising a terminal-holding member excellent in insulating properties. The present invention relates to a power device having a power element, a terminal, and a terminal-holding member composed of a liquid crystalline polyester, wherein the liquid crystalline polyester is a liquid crystalline polyester having a repeating unit (1) derived from an aromatic hydroxycarboxylic acid, a repeating unit (2) derived from an aromatic dicarboxylic acid, and a repeating unit (3) derived from an aromatic diol, and the content of a repeating unit derived from isophthalic acid in the liquid crystalline polyester is 0 to 7 mol % relative to the total amount of all repeating units of the liquid crystalline polyester. | 11-21-2013 |
20130329390 | SEMICONDUCTOR DEVICES - A semiconductor device includes a package board having a front side and a back side opposite to each other. A first memory device has data pins and is mounted on the front side of the package board, and a second memory device has data pins and is mounted on the back side of the package board. The data pins of the first and second memory devices have a same arrangement. A controller provides data signals to the first and second memory devices, with the same data signal provided from the controller to one data pin of the first memory device and one data pin of the second memory device. | 12-12-2013 |
20130329391 | PRINTED WIRING BOARD, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - An electronic device comprises: a printed wiring board that comprises a substrate, pads formed on the substrate, and an insulating film layer covering a surface of the substrate on which the pads are formed; and an electronic element that comprises external terminals electrically connected to the pads and that is mounted on the printed wiring board. The insulating film layer comprises at least one connecting opening section each exposing at least part of one of the pads. At least part of an inner wall of the connecting opening section comprises at least one step section. | 12-12-2013 |
20130335940 | ELECTRONIC CIRCUIT SUBSTRATE, DISPLAY DEVICE, AND WIRING SUBSTRATE - A wiring substrate ( | 12-19-2013 |
20130343024 | PRINTED CIRCUIT BOARD AND PRINTED WIRING BOARD - On a surface layer of a printed wiring board, main power supply patterns to be applied with different DC voltages are disposed in a second region. Power supply patterns are disposed on the surface layer, and the power supply patterns are led from the main power supply patterns to a first region. The power supply patterns connect power supply terminals of terminal groups in the second region. The power supply patterns connect the power supply terminals between the terminal groups in the first region. Power supply terminals of the terminal groups of a semiconductor package are electrically connected to the main power supply patterns by the power supply patterns. Thus, potential fluctuations are reduced and radiation noise is suppressed, and the number of layers of the printed wiring board is reduced. | 12-26-2013 |
20140003017 | ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREFOR | 01-02-2014 |
20140003018 | WIRING BOARD, MANUFACTURING METHOD FOR WIRING BOARD, AND IMAGE PICKUP APPARATUS | 01-02-2014 |
20140016289 | NETWORK COMMUNICATION DEVICE - A network communication device is disclosed. The network communication device includes a circuit board, a network connector, a network chip and a plurality of network magnetic assemblies. The network connector, the network chip and the network magnetic assemblies are disposed on the circuit board. The network magnetic assemblies are electrically connected with the network connector and the network chip, respectively. Each of the network magnetic assemblies includes an Ethernet transformer and at least one inductor. The Ethernet transformer is electrically connected in series with the inductor via a conductive trace of the circuit board. The spaced distance or a path length of the conductive trace between the Ethernet transformer and the inductor of the at least one network magnetic assembly is less than a first specific length. | 01-16-2014 |
20140022751 | ELECTRIC CIRCUIT APPARATUS AND MANUFACTURING METHOD THEREFOR - An electric circuit apparatus includes: a first-circuit board that includes a first-through-hole, and a first-electrode disposed on a front side of the first-circuit-board; a second-circuit-board that is disposed on a back side of the first-circuit-board, the second-circuit-board including on the front side of the second-circuit-board a second-electrode associated with the first-through-hole; a semiconductor device that is disposed on the front side of the first-circuit-board, the semiconductor device including on a back side a third-electrode-associated with the first-electrode, and a fourth-electrode-associated with the second-electrode; a first-bonding-material that bonds the first-electrode and the-third-electrode; a second-bonding-material that bonds the second-electrode and the fourth-electrode while passing through the first-through-hole; and a support body that is disposed between the first-electrode and the second-circuit-board and that supports the first-circuit-board. | 01-23-2014 |
20140029227 | ELECTRONIC CIRCUIT AND SEMICONDUCTOR COMPONENT - A circuit board according to an embodiment is one in which a plurality of electronic components is mounted on a printed wiring board. The circuit board includes a semiconductor component that is mounted on the printed wiring board, and the semiconductor component includes a semiconductor device and a first EBG structure formed on or above the semiconductor device. An operating frequency of the semiconductor device exists outside a cutoff band of the first EBG structure, and the first EBG structure is connected to a ground or a power supply of the printed wiring board. | 01-30-2014 |
20140036467 | CERAMIC MULTILAYER SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - A ceramic multilayer substrate includes stacked ceramic layers; internal conductors which are stacked with one of the ceramic layers therebetween, and are arranged such that at least a portion of the internal conductors overlap each other in a stacking direction; and a constraining layer which is arranged on a layer different from layers on which the internal conductors are located. The constraining layer overlaps, in the stacking direction, an internal conductor-overlapping region where at least two of the internal conductors overlapping each other in the stacking direction, has a planar area not more than twice the planar area of the internal conductor-overlapping region, and contains an unsintered inorganic material powder. The constraining layer has a planar area not more than one-half the planar area of the ceramic layers. The constraining layer is arranged so as to entirely cover the internal conductor-overlapping region. | 02-06-2014 |
20140049930 | MOUNTED STRUCTURE AND MANUFACTURING METHOD OF MOUNTED STRUCTURE - In a case where a first mounted substrate to which a semiconductor element is bounded by solder is mounted on a second substrate, connection strength becomes low, when the first mounted substrate is bonded to the second substrate by using a solder having a low melting point. A mounted structure, in which a first mounted substrate on which a semiconductor element is bonded by using a first solder having a melting point of 217° C. or more, is mounted on a second substrate, includes plural bonding parts bonding the first mounted substrate to the second substrate; and a reinforcing member formed around the bonding part. Each of the bonding parts contains a second solder having a melting point, that is lower than the melting point of the first solder, and a space exists, in which the reinforcing members do not exist, between the bonding parts neighboring each other. | 02-20-2014 |
20140055969 | BOARD ASSEMBLIES WITH MINIMIZED WARPAGE AND SYSTEMS AND METHODS FOR MAKING THE SAME - Board assemblies with minimized warpage and systems and methods for making the same are disclosed. A board may be pre-conditioned by designing the board to mount components in selected areas of the board and by selectively copper flooding certain regions of the board. Pre-conditioning of the board may assist in preventing board warpage. A reflow fixture may fix a board during solder pasting and reflow processing thereof. After reflow, an underfill fixture may fix the board during underfill processing. Each of these fixtures may include respective clamp members that may hold various portions of the board to correct and/or prevent warpage of the board. | 02-27-2014 |
20140055970 | CO-SUPPORT COMPONENT AND MICROELECTRONIC ASSEMBLY - A component may be configured for connection with a microelectronic assembly having terminals and a microelectronic element connected with the terminals. The component may include a support structure bearing conductors configured to carry command and address information, and a plurality of contacts coupled to the conductors and configured for connection with the terminals. The contacts may have address and command information assignments arranged according to a first predetermined arrangement for connection with a first type of microelectronic assembly in which the microelectronic element is configured to sample command and address information coupled thereto through the contacts at a first sampling rate, and according to a second predetermined arrangement for connection with a second type of microelectronic assembly in which the microelectronic element is configured to sample the command and address information coupled thereto through a subset of the contacts at a second sampling rate greater than the first sampling rate. | 02-27-2014 |
20140055971 | SURFACE MOUNT ACTUATOR - A silicon MEMS device can have at least one solder contact formed thereupon. The silicon MEMS device can be configured to be mounted to a circuit board via the solder contact(s). The silicon MEMS device can be configured to be electrically connected to the circuit board via the solder contact(s). | 02-27-2014 |
20140063766 | LATERAL ELEMENT ISOLATION DEVICE - Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier. | 03-06-2014 |
20140063767 | CIRCUIT DEVICE - A circuit device according to one exemplary embodiment includes a ceramic substrate, a first conductive pattern provided on one face of the ceramic substrate, a second conductive pattern, formed mainly of Cu, which is provided on the other face of the ceramic substrate, and a semiconductor element provided on an island that constitutes the second conductive pattern. An electrode, whose outermost surface is formed mainly of Cu, is provided in the semiconductor element, and the interface between the island and the electrode is directly fixed by solid-phase bonding. | 03-06-2014 |
20140071647 | INTEGRATED CIRCUIT RETENTION MECHANISM WITH RETRACTABLE COVER - A computer processor retention device comprises a load frame, a load plate, and a pair of retractable cover members. The load frame may be secured to a circuit board around a processor mounting site. The load plate is pivotally coupled to the load frame and is pivotable between being open for receiving a processor at the processor mounting site and closed in engagement with a periphery of the received processor. The load plate has a window that is open to the processor mounting site when the load plate is closed. The retractable cover members span the window and are alternately movable along a track toward one another to cover the processor mounting site and away from one another to expose the processor mounting site. | 03-13-2014 |
20140085853 | DISPLAY APPARATUS - A display apparatus including a display and a waveguide plate is provided. The display panel includes multiple rows of display units and multiple rows of solar cell units. The display units and the solar cell units are substantially parallel to a first direction and alternately arranged along a second direction perpendicular to the first direction. The waveguide plate is disposed at one side of the display panel. A first side of the waveguide plate adjacent to the display panel includes multiple microstructures. First and second structure surfaces of each microstructure respectively correspond to one row of the display units and one row of the solar cell units. When the display apparatus is disposed such that the second direction is perpendicular to a ground surface, an inclination of the first structure surface makes a thickness of the waveguide plate gradually decrease along an upward direction from the ground surface. | 03-27-2014 |
20140085854 | CIRCUIT BOARD INCORPORATING SEMICONDUCTOR IC AND MANUFACTURING METHOD THEREOF - Disclosed herein is a manufacturing method of a circuit board. The manufacturing method includes a first step for preparing a prepreg in which a core material is impregnated with an uncured resin. The prepreg has a through-hole surrounded by the core material and the resin so as to penetrate through the core material and the resin. The manufacturing method further includes a second step for housing a semiconductor IC in the through-hole, and a third step for pressing the prepreg so that a part of the resin flows into the through-hole to allow the semiconductor IC housed in the through-hole to be embedded in the resin. | 03-27-2014 |
20140092576 | FILM INTERPOSER FOR INTEGRATED CIRCUIT DEVICES - In one embodiment, a stack device comprising a film interposer of a polyimide film material, for example, is assembled. In accordance with one embodiment of the present description, a front side of the film interposer is attached to a first element of the stack device, which may be an integrated circuit package, an integrated circuit die, a substrate such as a printed circuit board, or other structure used to fabricate electronic devices. In addition, a back side of the film interposer is attached to a second element which like the first element, may be an integrated circuit package, an integrated circuit die, a substrate such as a printed circuit board, or other structure used to fabricate electronic devices. Other aspects are described. | 04-03-2014 |
20140098507 | PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR MANUFACTURING THE PRINTED CIRCUIT BOARD AND THE SEMICONDUCTOR PACKAGE - The present invention relates to a printed circuit board, a semiconductor package using the same, and a method for manufacturing the printed circuit board and the semiconductor package. The method for manufacturing a semiconductor package in accordance with the present invention includes: forming a circuit of a predetermined pattern on a PCB substrate; applying a first insulating material on the substrate; removing the first insulating material in the remaining portion except a predetermined portion by exposing and developing the substrate; forming a solder bump in the circuit portion exposed; molding a certain region of an upper surface portion of the PCB substrate including the solder bump by filling a second insulating material on the PCB substrate including the circuit portion; mounting a semiconductor chip on the PCB substrate; and completing one package in which the semiconductor chip and the PCB substrate are integrated. | 04-10-2014 |
20140104802 | SEMICONDUCTOR DEVICE AND CIRCUIT BOARD - A semiconductor device includes a semiconductor chip, a plurality of external terminals, and a board. The board includes a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed, a second main surface in which a plurality of second electrodes electrically connected to the plurality of external terminals are formed, and a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality of signal paths that electrically connect the first electrode and the second electrode corresponding thereto. The interconnect layer includes a plurality of metal members which are dispersedly disposed at a distance shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal path, in the vicinity of a portion in which a structure of an interconnect for forming the signal path is changed. | 04-17-2014 |
20140104803 | CIRCUIT BOARD INCORPORATING ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF - Disclosed herein is a circuit board that includes a resin substrate including a substrate wiring layer, and an electronic component embedded in the resin substrate and having a plurality of external electrodes. The resin substrate includes a plurality of via holes that expose the external electrodes and a plurality of via conductors embedded in the via holes to electrically connect the substrate wiring layer to the external electrodes. At least some of the via holes are different in planar shape from each other. | 04-17-2014 |
20140118978 | PACKAGE SUBSTRATE AND CHIP PACKAGE USING THE SAME - A package substrate is disclosed. The package substrate includes a base layer and a dam structure or a dent structure on at least one side of the base layer. The base layer may be a CCL core, a molding compound, or an epoxy base. | 05-01-2014 |
20140118979 | Display Panel Integrating A Driving Circuit - A display panel includes a periphery area, an active display area adjacent to the periphery, a driving chip disposed out of the active display area for driving the active display area, and a plurality of wires electrically connecting the driving chip and the active display area. The width of at least one wire at a portion adjacent to the driving chip is smaller than the width of the at least one wire at the other portion adjacent to the active display area. | 05-01-2014 |
20140140029 | DISPLAY PANEL AND BONDING APPARATUS FOR MANUFACTURING THE SAME - A display panel that includes: a display substrate; a driving chip bonded onto the display substrate; an anisotropic conductive film provided between the display substrate and the driving chip; and a protection film attached to a bottom of the display substrate, and the protection film is provided with a bending prevention means. | 05-22-2014 |
20140140030 | CONDUCTIVE MATERIAL, CONDUCTIVE PASTE, CIRCUIT BOARD, AND SEMICONDUCTOR DEVICE - A conductive material includes a first metal part whose main ingredient is a first metal; a second metal part formed on the first metal part and whose main ingredient is a second metal, the second metal having a melting point lower than a melting point of the first metal, which second metal can form a metallic compound with the first metal; and a third metal part whose main ingredient is a third metal, which third metal can make a eutectic reaction with the second metal. | 05-22-2014 |
20140146506 | HIGH FREQUENCY DEVICE - A high frequency device includes a base plate having a main surface, a dielectric on the main surface, along a first side of the base plate, a signal line on the dielectric and extending from the first side toward a central portion of the main surface, an island pattern of a metal on the dielectric, a metal frame having a contact portion contacting the main surface and a bridge portion on the signal line and the island pattern, together enclosing the central portion, a lead frame connected to an outside signal line of the signal line and which is located outside the metal frame, a semiconductor chip secured to the central portion, and a wire connecting the semiconductor chip to an inside signal line of the signal line and which is enclosed within the metal frame. | 05-29-2014 |
20140146507 | CIRCUIT BOARD AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - In a circuit board for a semiconductor package, the contact pad of the circuit board is partially exposed through a contact hole and a subsidiary pad is provided around the contact hole in such a way that the contact hole is defined by the subsidiary pad. A subsidiary film having the subsidiary pad is provided on a mask pattern for protecting an internal circuit pattern and the contact pad from their surroundings. A contact terminal is provided on the subsidiary film in such a way that the contact hole is at least partially filled with the contact terminal and the subsidiary pad is covered with the contact terminal and an external body is bonded to the contact terminal. The contact area between the circuit board and the contact terminal is enlarged due to the subsidiary pad, thereby increasing the contact reliability of the semiconductor package. | 05-29-2014 |
20140192500 | Method of Electrophoretic Depositing (EPD) a Film on an Exposed Conductive Surface and an Electric Component Thereof - A system, a packaged component and a method for making a packaged component are disclosed. In an embodiment a system comprises a component carrier, a component disposed on the component carrier and an insulating layer disposed on an electrically conductive surface of at least one of the component carrier or the component, wherein the insulating layer comprises a polymer and an inorganic material comprising a dielectric strength of equal or greater than 15 ac-kv/mm and a thermal conductivity of equal or greater than 15 W/m*K. | 07-10-2014 |
20140192501 | MODIFIED SILOXANE COMPOUND HAVING AROMATIC AZOMETHINE, THERMOSETTING RESIN COMPOSITION INCLUDING THEREOF, PREPREG, FILM HAVING RESIN, LAMINATE, MULTI-LAYER PRINTED WIRING BOARD, AND SEMICONDUCTOR PACKAGE - A siloxane compound containing structures represented by the following general formulae (1) and (2): | 07-10-2014 |
20140211441 | WIRELESS APPARATUS AND METHOD FOR MANUFACTURING SAME - A wireless apparatus has a board, a power amplifier high-frequency IC chip, and a process variations detector. The process variations detector monitors a circuit characteristic variation amount due to process variations. An underfill having a parameter value calculated using the monitored circuit characteristic variation amount is applied between the board and the high-frequency IC chip and the mounting board. As a result, the wireless apparatus exhibits a desired circuit characteristic even with process variations and influence of the underfill. | 07-31-2014 |
20140211442 | PRE-SOLDERED LEADLESS PACKAGE - Consistent with an example embodiment, a semiconductor device comprises a patterned conductive layer defining contact pads for being connected to terminals of a semiconductor chip. The semiconductor chip comprises the terminals at a first side and an adhesive layer at a second side opposite to the first side; wherein, the semiconductor chip is mounted with an adhesive layer on a patterned conductive layer such that the semiconductor chip part of each respective contact pad leaves part thereof uncovered by the chip for wire bonding. Wire bonds connect respective terminals of the semiconductor chip and respective contact pads at the first side thereof. A molding compound covers the semiconductor chip, the wire bonds and the contact pads; wherein, the molding compound is also located on the second side of the semiconductor device, separating the contact regions that are located directly on a backside of the contact pads. | 07-31-2014 |
20140233201 | CARRIER BOARD FOR ATTACHMENT OF INTEGRATED CIRCUIT TO CIRCUIT BOARD - An electronics system includes a main circuit board; main circuitry located on the main circuit board; a carrier board located on top of the main circuit board; an integrated circuit (IC) located on the carrier board, wherein the IC is electrically connected to the main circuitry on the main circuit board; and a layer of adhesive located between the carrier board and the main circuit board. | 08-21-2014 |
20140268618 | PRINTED BOARD, PRINTED BOARD UNIT, AND METHOD OF MANUFACTURING PRINTED BOARD - A printed-board includes a first conductor-layer, a second conductor-layer provided to a layer different from the first conductor-layer, an insulation-layer provided between the first conductor-layer and the second conductor-layer, a plurality of through-holes that pass through the first conductor-layer, the second conductor-layer, and the insulation-layer, and a plurality of vias that are formed in the plurality of through-holes, respectively, and couple the first conductor-layer and the second conductor-layer, each of the plurality of vias including a conductor portion that occupies part of an internal space of the through-hole, and a non-conductor portion that occupies remaining part of the internal space, wherein in a given pair of vias adjacent to each other, the conductor portion of one of the pair of vias is arranged so as to face the non-conductor portion of another one of the pair of vias. | 09-18-2014 |
20140268619 | Method of Manufacturing Substrate for Chip Packages and Method of Manufacturing Chip Package - Provided are a method of manufacturing a substrate for chip packages and a method of manufacturing a chip package, the method of manufacturing the substrate including: forming a lower adhesive layer in a lower part of an insulation film; forming an upper adhesive layer in an upper part of the insulation film to form a base material; forming via holes in the base material; and forming a circuit pattern layer on the upper adhesive layer, so it is effective to improve adhesion power between the molding resin and the insulation film at the time of manufacturing a chip package later. | 09-18-2014 |
20140301058 | WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes a first insulation layer, a first wiring layer formed on the first insulation layer, and a second insulation layer stacked on the first insulation layer. The second insulation layer covers the first insulation layer and includes a filler. A third insulation layer is stacked on the second insulation layer. The third insulation layer is filler-free. A through electrode extends through the second and third insulation layers in a thicknesswise direction. A second wiring layer is stacked on the third insulation layer and the through electrode. The through electrode electrically connects the second wiring layer to the first wiring layer. | 10-09-2014 |
20140313686 | MULTI-CHIP SOCKET - A multi-chip socket including multiple cavities. The multiple cavities include support surfaces. The support surfaces may be disposed at different heights relative to a reference plane. A first thermal interface is to thermally contact a top surface of the first component, and a second thermal interface is to thermally contact a top surface of the second component. | 10-23-2014 |
20140321091 | PACKAGE SUBSTRATE WITH HIGH DENSITY INTERCONNECT DESIGN TO CAPTURE CONDUCTIVE FEATURES ON EMBEDDED DIE - Embodiments of the present disclosure are directed towards techniques and configurations for interconnect structures embedded in a package assembly including a bridge. In one embodiment, a package assembly may include a package substrate, a bridge embedded in the package substrate and including a bridge substrate, and an interconnect structure including a via extending through the package substrate into a surface of the bridge substrate and configured to interface with a conductive feature disposed on or beneath the surface of the bridge substrate. The interconnect structure may be configured to route electrical signals between the conductive feature and a die mounted on the package substrate. Other embodiments may be described and/or claimed. | 10-30-2014 |
20140347838 | ELECTRONIC DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - An electronic device includes first to third terminals and a clip. The clip includes first to third joint portions and a connection portion. The first to third joint portions correspond to and are bonded to the first to third terminals, respectively. The connection portion connects the first to third joint portions. One terminal in the first to third terminals has a depressed portion depressed to one side in a predetermined direction to store a conductive bonding material. A variation in positions of the first to third terminals in the predetermined direction is absorbed by deformation of the conductive bonding material when one joint portion in the first to third joint portions corresponding to the one terminal is bonded to the one terminal through the conductive bonding material. | 11-27-2014 |
20140362552 | INTERPOSER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - There is provided an interposer for cooling an electronic component. The interposer includes: a substrate body having a hollow cooling channel therein, wherein a cooling medium flows through the cooling channel, the cooling channel including: a plurality of main cooling channels extending in a certain direction and separated from each other; an inflow channel which is communicated with one end of the respective main cooling channels; and an outflow channel which is communicated with the other end of the respective main cooling channels, and a plurality of through electrode groups each comprising a plurality of through electrodes arranged in a line. Each of the though electrodes is formed through the substrate body to reach the first and second surfaces of the substrate body. The respective through electrode groups are partitioned by at least corresponding one of the main cooling channels. | 12-11-2014 |
20150016082 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - A printed circuit board includes an insulating layer; a via in the insulating layer, a first circuit layer formed at a first side of the insulating layer and having a portion buried in the via; a second circuit layer formed at a second side of the insulating layer and electrically connected with the portion of the first circuit layer in the via. | 01-15-2015 |
20150022989 | UTILIZING CHIP-ON-GLASS TECHNOLOGY TO JUMPER ROUTING TRACES - A chip-on-glass device comprises a chip-on-glass substrate, a metal layer, and a plurality of chip-on-glass connection bumps. The metal layer comprises a plurality of passive jumper routing traces. The plurality of chip-on-glass connection humps is coupled with passive jumper routing traces of the plurality of passive jumper routing traces. | 01-22-2015 |
20150036309 | ELECTRONIC DEVICE COMPRISING A SUBSTRATE BOARD EQUIPPED WITH A LOCAL REINFORCING OR BALANCING LAYER - A substrate board includes an electrical connection network on a face thereof. An integrated-circuit chip is mounted to the face of the substrate board in electrical contact with the electrical connection network. A local reinforcing or balancing layer made of a non-metallic material is mounted to the face of the substrate board in at least one local zone free of the face which is free of metal portions of the electrical connection network. | 02-05-2015 |
20150055312 | INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is an interposer substrate, including: a core layer and a through core via (TCV) penetrating through the core layer; circuit wirings formed on both surfaces of the core layer and a TCV upper pad and a TCV lower pad which are each bonded to upper and lower surfaces of the TCV formed on both surfaces of the core layer; upper insulating layers covering the TCV upper pad and the circuit wiring formed on one surface of the core layer and having the circuit wirings formed on upper surfaces thereof; a stack via penetrating through the upper insulating layers of each layer and having one end connected to the TCV upper pad; and a lower insulating layer covering the TCV lower pad and the circuit wiring formed on the other surface of the core layer and provided with an opening which exposes the TCV lower pad. | 02-26-2015 |
20150070865 | Package-on-Package Structure with Through Molding Via - Disclosed herein is a device comprising a first package having a first side with a plurality of connectors disposed thereon and a second package mounted on the first package by the connectors. A molding compound is disposed on the first side of the first package and between the first package and the second package. A plurality of stress relief structures (SRSs) are disposed in the molding compound, the plurality of SRSs each comprising a cavity free of metal in the molding compound and spaced apart from each of the plurality of connectors. | 03-12-2015 |
20150092378 | DIRECT CHIP ATTACH USING EMBEDDED TRACES - A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices. | 04-02-2015 |
20150092379 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin. | 04-02-2015 |
20150092380 | Semiconductor Module Comprising Printed Circuit Board and Method for Producing a Semiconductor Module Comprising a Printed Circuit Board - A semiconductor module includes a printed circuit board, a ceramic substrate and a semiconductor chip. The printed circuit board includes an insulating material, a cutout formed in the insulating material, and a first metallization layer, which is partly embedded into the insulating material. The first metallization layer includes a conductor track projection projecting into the cutout. The ceramic substrate includes a dielectric, ceramic insulation carrier, and an upper substrate metallization applied to a top side of the insulation carrier. The semiconductor chip is arranged on the upper substrate metallization, and the first metallization layer is mechanically and electrically conductively connected to the upper substrate metallization at the conductor track projection. | 04-02-2015 |
20150092381 | PADLESS VIA - One disclosed embodiment comprises formation of a padless via in a substrate. The padless via includes a hole through a metal layer blanketing the substrate, as well as the underlying substrate. An inner wall of the padless via hole receives a seed layer of a conductive material. Electrolytic differential plating is then performed, resulting in a preferential accumulation of a conductive plating material on the via inner wall, relative to that deposited on a surface of the substrate. In one embodiment, the differential plating is performed by addition of an organic suppressant to a plating bath. | 04-02-2015 |
20150124423 | METHOD OF MANUFACTURING CIRCUIT BOARD, METHOD OF MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC DEVICE - A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring. | 05-07-2015 |
20150131254 | PRINTED CIRCUIT BOARD, SEMICONDUCTOR PACKAGE HAVING THE SAME AND METHOD FOR MANUFACTURING THE SAME - The present invention discloses a printed circuit board, a semiconductor package having the same, and a method for manufacturing the same. A printed circuit board according to an aspect of the present invention includes: a package board including a mounting area and a peripheral area, the mounting area having a semiconductor chip mounted therein, the peripheral area surrounding the mounting area; a first central circuit pattern formed in the mounting area on one surface of the package board; a second central circuit pattern formed in the mounting area on the other surface of the package board and having a greater thickness than the first central circuit pattern; a first peripheral circuit pattern formed in the peripheral area on the one surface of the package board; and a second peripheral circuit pattern formed in the peripheral area on the other surface of the package board and having a greater thickness than the second peripheral circuit pattern. | 05-14-2015 |
20150131255 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor package may include: a substrate including a core layer having a first surface and a second surface which is opposite to the first surface, a wiring layer formed over the first and second surfaces and in an inside of the core layer, and having a first electrode disposed in the inside of the core layer and exposed from the core layer and a second electrode disposed over the first surface, and a passivation layer formed over the first and second surface of the core layer such that the first and the second electrodes are exposed; a first semiconductor chip disposed over the first surface of the core layer; a second semiconductor chip stacked over the first semiconductor chip; a first connection member for connecting the first semiconductor chip with the first electrode; and a second connection member for connecting the second semiconductor chip with the second electrode. | 05-14-2015 |
20150311135 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device includes: a substrate; a semiconductor chip mounted over the substrate and having a solder bump coupled by soldering with an electrode over the substrate; and a heating unit for locally generating heat in a corner part within the horizontal plane of the semiconductor chip when an operating temperature of the semiconductor chip is equal to or less than a prescribed temperature. | 10-29-2015 |
20150319848 | PRINTED WIRING BOARD, SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD - A printed wiring board includes a core laminate including insulating layers and conductor layers, a first build-up layer formed on first surface of the laminate and including first interlayer resin and conductor layers, and a second build-up layer formed on second surface of the core laminate on the opposite side and including second interlayer resin and conductor layers. The conductor layers in the laminate include first and second conductor layers such that the first conductor layer is embedded in one of the insulating layers forming the first surface of the laminate and has an exposed surface exposed from the insulating layer and that the second conductor layer is formed on one of the insulating layers forming the second surface of the laminate, and the first interlayer resin layer has thickness greater than thickness of the second interlayer resin layer. | 11-05-2015 |
20150327388 | Electrically Bonded Arrays of Transfer Printed Active Components - An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed. | 11-12-2015 |
20150329371 | OXIDE, SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE - The oxide includes indium, an element M, and zinc. The oxide includes a first region and a second region. A peak of diffraction intensity derived from a crystal structure is not observed in the first region using X-ray. An electron diffraction pattern including a third region with high luminance in a ring pattern and a spot in the third region is observed by transmission of an electron beam having a probe diameter of 0.3 nm or more and 3 nm or less through the second region. The oxide includes a crystal part when being observed with a transmission electron microscope. | 11-19-2015 |
20150332995 | ELECTRONIC DEVICE INCLUDING COMPONENTS IN COMPONENT RECEIVING CAVITY AND RELATED METHODS - An electronic device may include a surface mount integrated circuit (IC) package to be attached to a printed circuit board (PCB). The surface mount IC package may include at least one IC and an encapsulating material surrounding the at least one IC and having a component receiving cavity defined therein on a bottom surface thereof to be positioned adjacent the PCB. The surface mount IC package may also include electrical leads coupled to the at least one IC and extending outwardly from the encapsulating material to be coupled to the PCB. The electronic device may also include at least one electronic component carried within the component receiving cavity and that includes electrical contacts to be coupled to the PCB. | 11-19-2015 |
20150333043 | SEMICONDUCTOR DEVICE - A first diode having a front surface anode region is mounted on a P pattern, and a second diode having a front surface cathode region is mounted on an N pattern. At this time, the first diode and the second diode are formed such that a cathode region of a front surface anode region in a first vertical relationship and an anode region of a front surface cathode region in a second vertical relationship are always located as upper portions. The front surface anode region is electrically connected to the front surface cathode region with wires provided thereover. | 11-19-2015 |
20150334823 | SUBSTRATE COMPONENTS FOR PACKAGING IC CHIPS AND ELECTRONIC DEVICE PACKAGES OF THE SAME - Substrate components for packaging IC chips and electronic device packages are disclosed. A substrate component for packaging IC chips comprises: a glass core base with at least one conductive through via connecting a combination of metallization and dielectric structures on both an upper surface and a lower surface of the glass core base; and, tapered edges created at a peripheral region of the glass core base; wherein dielectric layers are disposed over the tapered edges at the peripheral region of the glass core base. In accordance with an embodiment of the invention, the dielectric layers have a substantial planar upper surface, a lower surface conformably interfaced with the tapered edges at peripheral region of the glass core base, and a steep cutting face with the tapered edges of the glass core base. Alternatively, the tapered edges at peripheral region of the glass core base are not covered by the dielectric layers, and an encapsulated material sealing the tapered edges at peripheral region of the glass core base. | 11-19-2015 |
20150351225 | METAL-BASED MOUNTING BOARD AND METHOD OF MANUFACTURING METAL-BASED MOUNTING BOARD - A metal-based mounting board according to the present invention includes: a metal-based circuit board including a metal substrate through which a through-hole is provided along a thickness direction thereof, an insulating film provided on the metal substrate and a metal film provided on the insulating film, wherein the through-hole opens on a surface of the metal film on the opposite side of the metal substrate via the insulating film and the metal film; an electronic component connected to the metal film, the electronic component including an electronic component main body and a conductive leg portion electrically connected to the electronic component main body and inserted into the through-hole; and an insulating portion provided at least between the leg portion locating inside the through-hole and the metal substrate, and having a function of preventing them from making contact with each other. | 12-03-2015 |
20150357276 | WIRING SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING WIRING SUBSTRATE - A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end. | 12-10-2015 |
20150359100 | INTEGRATED CIRCUIT ASSEMBLIES WITH MOLDING COMPOUND - Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed. | 12-10-2015 |
20150364408 | PACKAGE SUBSTRATE AND FLIP-CHIP PACKAGE CIRCUIT INCLUDING THE SAME - This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer. | 12-17-2015 |
20150366054 | METAL FOIL-CLAD SUBSTRATE, CIRCUIT BOARD AND ELECTRONIC-COMPONENT MOUNTING SUBSTRATE - A metal foil-clad substrate used for forming a circuit board mounting and electrically connecting an electronic component is provided. The metal foil-clad substrate includes a metal foil having a one surface, a resin layer formed on the one surface of the metal foil; an insulating part formed on a surface of the resin layer opposite to the metal foil; and at least one bending portion in which the metal foil, the resin layer and the insulating part are bended to a side of the metal foil or the insulating part. The insulating part is constituted of a cured material of a first resin composition containing a first thermosetting resin. The resin layer is constituted of a cured material or solidified material of a second resin composition containing a resin material. | 12-17-2015 |
20150373834 | MOUNTING BLOCK AND A MOUNTING ASSEMBLY THAT INCORPORATES THE MOUNTING BLOCK - A mounting block is provided that has a multi-level upper surface that is used to mount one or more IC chips and the printed circuit board (PCB) thereon at heights that allow the lengths of the bond wires interconnecting the chips with the PCB and/or with the other IC chips to be reduced. The distances between the levels of the multi-level surface are preselected based at least in part on the known height of the PCB and the known height of at least one of the IC chips such that when the chip and the PCB are mounted on the mounting block, the distance between the contact pads of the PCB and the contact pads of the IC chip is very small, thereby allowing the lengths of the bond wires to be kept very short. | 12-24-2015 |
20150373836 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including a mounting substrate, a semiconductor element mounted on the mounting substrate, a laminated body laminated by a positive terminal plate and a negative terminal plate with a first insulating layer interposed therebetween, and a shield plate bonded to the laminated body with a second insulating layer interposed therebetween on the side of the laminated body that is opposite from the mounting substrate. The positive terminal plate and the negative terminal plate are electrically connected to the semiconductor element. | 12-24-2015 |
20150380332 | Substrate Design with Balanced Metal and Solder Resist Density - A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1. | 12-31-2015 |
20150380374 | SEMICONDUCTOR DEVICE - The semiconductor device includes an insulating substrate including an insulating plate and a circuit plate; a semiconductor chip having a front surface formed with an electrode and a rear surface fixed to the circuit plate; a printed circuit board including a metal layer, and facing the insulating substrate; a conductive bonding material disposed on the electrode; and a conductive post having a leading end portion electrically and mechanically connected to the electrode through the bonding material, a base portion electrically and mechanically connected to the metal layer, and a central portion. In the conductive post, a wetting angle of a surface of the leading end portion with respect to the molten bonding material is less than the wetting angle of a surface of the central portion. | 12-31-2015 |
20150382465 | SYSTEMS AND METHODS FOR IMPLEMENTING DISPLAY DRIVERS - A device includes a first substrate formed of a first material and a plurality of electromechanical devices formed upon a surface of the first substrate. The device also includes an integrated circuit (IC) chip bonded to the surface of the first substrate where the integrated circuit chip is formed of a material selected from a group consisting of the first material or a material having a coefficient of thermal expansion (CTE) that is substantially similar to the CTE of the first material. | 12-31-2015 |
20160007453 | HIGH THERMAL CONDUCTIVITY PREPREG, PRINTED WIRING BOARD AND MULTILAYER PRINTED WIRING BOARD USING THE PREPREG, AND SEMICONDUCTOR DEVICE USING THE MULTILAYER PRINTED WIRING BOARD - Problem: To prepare a prepreg having high thermal conductivity and a low thermal expansion coefficient. Resolution Means: The prepreg of the present disclosure is composed of a composite layer including an alumina-containing cloth including ceramic fibers and a thermosetting resin composition impregnated into the alumina-containing cloth and having a thermal conductivity coefficient greater than or equal to 1.0 W/(mK). | 01-07-2016 |
20160007460 | WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE - A wiring substrate includes a core layer, a first wiring layer, a first insulating layer, a first via wiring, a second wiring layer, a second insulating layer, a second via wiring, a third wiring layer, a third insulating layer, a third via wiring, and a through-wiring. The through-wiring includes upper and lower end surfaces. The upper end surface has an area that is smaller than an area of the lower end surface. The upper surface of the first insulating layer is more flat than the lower surface of the third insulating layer. The second wiring layer has a wiring density that is higher than a wiring density of the first wiring layer. | 01-07-2016 |
20160007464 | ELECTRONIC DEVICE AND MOUNTING STRUCTURE OF THE SAME - An electronic device includes an electronic element, a plurality of first sub-electrodes arrayed in a first direction, a plurality of second sub-electrodes arrayed in a second direction that is orthogonal to the first direction, a dummy electrode, and a sealing resin. The sealing resin has a resin back surface from which the plurality of first sub-electrodes, the plurality of second sub-electrodes and the dummy electrode are exposed. The plurality of second sub-electrodes are located further in the first direction than any of the plurality of first sub-electrodes. The plurality of first sub-electrodes are located further in the second direction than any of the plurality of second sub-electrodes. The dummy electrode is located further in the first direction than any of the plurality of first sub-electrodes, and is located further in the second direction than any of the plurality of second sub-electrodes. | 01-07-2016 |
20160029477 | WIRING SUBSTRATE, SEMICONDUCTOR DEVICE, PRINTED BOARD, AND METHOD FOR PRODUCING WIRING SUBSTRATE - A wiring substrate, to be interposed when an electronic component including an integrated circuit is mounted on a printed wiring board, includes a signal wire transmitting a signal from the electronic component, and a power supply wire supplying a power voltage to the electronic component, and the power supply wire is coated directly with a magnetic thin coat, and the magnetic thin coat is not provided on the signal wire so that the magnetic thin coat is arranged to be separated from the signal wire. | 01-28-2016 |
20160037641 | ELECTRICAL COMPONENT - An electrical component having a first package part of a first plastic compound. The first package part has a first trench-shaped formation. A first semiconductor body with an integrated circuit is disposed in the first trench-shaped formation. At least two traces, which run on an outer side of the first package part, are provided on a surface of the first trench-shaped formation, wherein the at least two traces are connected to the integrated circuit. The first trench-shaped formation is filled at least partially with a filling material of a second plastic compound to cover the first semiconductor body. | 02-04-2016 |
20160039052 | SOLDER MATERIAL AND BONDED STRUCTURE - Solder material used in soldering of an Au electrode including Ni plating containing P includes Ag satisfying 0.3≦[Ag]≦4.0, Bi satisfying 0≦[Bi]≦1.0, and Cu satisfying 0<[Cu]≦1.2, where contents (mass %) of Ag, Bi, Cu and In in the solder material are denoted by [Ag], [Bi], [Cu], and [In], respectively. The solder material includes In in a range of 6.0≦[In]≦6.8 when [Cu] falls within a range of 0<[Cu]<0.5, In in a range of 5.2+(6−(1.55×[Cu]+4.428))≦[In]≦6.8 when [Cu] falls within a range of 0.5≦[Cu]≦1.0, In in a range of 5.2≦[In]≦6.8 when [Cu] falls within a range of 1.0<[Cu]≦1.2. A balance includes only not less than 87 mass % of Sn. | 02-11-2016 |
20160043024 | PRINTED WIRING BOARD AND SEMICONDUCTOR PACKAGE - A printed wiring board includes a wiring conductor layer having first surface, conductor posts formed on second surface of the wiring layer, and an insulating layer embedding the wiring layer such that the first surface of the wiring layer is exposed on first surface of the insulating layer and covering side surfaces of the posts such that end surface of each conductor post is exposed from second surface of the insulating layer. The first surface of the wiring layer is recessed with respect to the first surface of the insulating layer and the end surface of each conductor post is recessed with respect to the second surface of the insulating layer such that distance between the end surface of each conductor post and the second surface of the insulating layer is greater than distance between the first surface of the wiring layer and the first surface of the insulating layer. | 02-11-2016 |
20160043488 | VERTICAL SOCKET CONTACT WITH FLAT FORCE RESPONSE - An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element. | 02-11-2016 |
20160050748 | SEMICONDUCTOR DEVICE - One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates. | 02-18-2016 |
20160057864 | SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor module includes: a substrate; a first interconnect layer provided on the substrate; a plurality of first semiconductor elements provided on the first interconnect layer, each of the first semiconductor elements having a first electrode, a second electrode, and a third electrode, and the second electrode being electrically connected to the first interconnect layer; a plurality of first rectifying elements provided on the first interconnect layer, each of the first rectifying elements having a fourth electrode and a fifth electrode, and the fifth electrode being electrically connected to the first interconnect layer; and a second interconnect layer provided on the substrate, and the second interconnect layer being electrically connected to the first electrode and the fourth electrode. The second interconnect layer includes a corrugated surface or the first interconnect layer includes a corrugated surface. | 02-25-2016 |
20160064315 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the conductive trace comprises a width W | 03-03-2016 |
20160073490 | DEVICES AND METHODS RELATED TO METALLIZATION OF CERAMIC SUBSTRATES FOR SHIELDING APPLICATIONS - Devices and method related to metallization of ceramic substrates for shielding applications. In some embodiments, a ceramic assembly includes a plurality of layers, the assembly including a boundary between a first region and a second region, the assembly further including a selected layer having a plurality of conductive features along the boundary, each conductive feature extending into the first region and the second region such that when the first region and the second region are separated to form their respective side walls, each side wall includes exposed portions of the conductive features capable of forming electrical connection with a conductive shielding layer | 03-10-2016 |
20160079220 | SEMICONDUCTOR PACKAGE ASSEMBLY - The invention provides a semiconductor package assembly. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die having first pads thereon. First vias are disposed on the first semiconductor die, coupled to the first pads. A first dynamic random access memory (DRAM) die is mounted on the first semiconductor die, coupled to the first vias. A second semiconductor package is stacked on the first semiconductor package. The second semiconductor package includes a body having a die-attach surface and a bump-attach surface opposite to the die-attach surface. A second dynamic random access memory (DRAM) die is mounted on the die-attach surface, coupled to the body through the bonding wires. The number of input/output (I/O) pins of first DRAM die is different from the number of input/output (I/O) pins of the second DRAM die. | 03-17-2016 |
20160088727 | PRINTED WIRING BOARD AND SEMICONDUCTOR PACKAGE - A printed wiring board includes a core laminate body including insulating layers, conductor layers including first and second conductor layers, and via conductors having smaller end surfaces connected to the first conductor layer, a first build-up layer formed on the core body and including an interlayer, a conductor layer on the interlayer, and via conductors having smaller end surfaces connected to the first conductor layer, and a second build-up layer formed on the core body and including an interlayer and a conductor layer on the interlayer. The first conductor layer is embedded such that the first conductor layer has exposed surface on the surface of the core body, the second conductor layer is formed on the other surface of the core body, and the first conductor layer has wiring pattern having the smallest minimum width of wiring patterns of the conductor layers in the core body and build-up layers. | 03-24-2016 |
20160095221 | INTEGRATION OF ELECTRONIC ELEMENTS ON THE BACKSIDE OF A SEMICONDUCTOR DIE - Systems and methods include a first semiconductor die with a substrate having a first side and a second side opposite to the first side. A first set of electronic elements is integrated on the first side. A second set of electronic elements is integrated on the second side. One or more through-substrate vias through the substrate are used to couple one or more of the first set of electronic elements and one or more of the second set of electronic elements. The through-substrate vias may be through-silicon vias (TSVs) or a through-glass vias (TGVs). The first semiconductor die may be stacked with a second semiconductor die, with the first side or the second side of the first semiconductor die interfacing an active side of the second semiconductor die. | 03-31-2016 |
20160104651 | POWER SEMICONDUCTOR DEVICE - A power semiconductor device includes an insulating substrate, a semiconductor element, a case, and a wiring member. The case forms a container body having a bottom surface defined by a surface of the insulating substrate, to which said semiconductor element is bonded. The wiring member has a bonding portion positioned above an upper surface electrode of the semiconductor element. The bonding portion of the wiring member is provided with a projection portion projecting toward the upper surface electrode of the semiconductor element and bonded to the upper surface electrode with a solder, and a through hole passing through the bonding portion in a thickness direction through the projection portion. | 04-14-2016 |
20160105955 | CIRCUIT SUBSTRATE AND ELECTRONIC DEVICE - A circuit substrate includes: a plurality of signal wirings formed at different positions of the circuit substrate in a thickness direction and extending in parallel in the circuit substrate; and ground layers or power supply layers formed at both sides of the circuit substrate in the thickness direction by interposing the plurality of the signal wirings between the ground layers or between the power supply layers, wherein the plurality of signal wirings are electrically coupled with each other by a plurality of conductors formed at an interval narrower than an interval by which a resonance is caused. | 04-14-2016 |
20160111803 | OPTOELECTRONIC ARRANGEMENT - An optoelectronic arrangement includes a first circuit board, a second circuit board, and an optoelectronic semiconductor chip arranged on the first circuit board, wherein a first electrical contact surface and a second electrical contact surface are formed on a surface of the first circuit board, a first mating contact surface and a second mating contact surface are formed on a surface of the second circuit board, and the first circuit board and the second circuit board connect to one another such that the surface of the first circuit board faces toward the surface of the second circuit board, and the first mating contact surface electrically conductively connects to the first contact surface and the second mating contact surface electrically conductively connects to the second contact surface. | 04-21-2016 |
20160113107 | POWER MODULE - The disclosure discloses a power module. The power module includes a substrate, a power chip, a bonding material, and at least one spacer. The substrate includes a circuit-patterned layer. The power chip bonded to the circuit-patterned layer by the bonding material. The spacer is located between the circuit-patterned layer and the power chip, so as to keep the power chip away from the circuit-patterned layer in a distance. | 04-21-2016 |
20160113112 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first ceramic substrate, a second ceramic substrate, an inter-ceramic metal having an intermediate portion interposed between an upper surface of the first ceramic substrate and a lower surface of the second ceramic substrate, a first surmounting portion formed on an upper surface of the second ceramic substrate, a second surmounting portion formed on the upper surface of the second ceramic substrate, a first connection portion abutting on an outer edge of the second ceramic substrate and connecting the intermediate portion and the first surmounting portion, and a second connection portion abutting on an outer edge of the second ceramic substrate and connecting the intermediate portion and the second surmounting portion, a circuit pattern formed on the second ceramic substrate, and a semiconductor element provided on the circuit pattern. | 04-21-2016 |
20160120031 | SEMICONDUCTOR PACKAGE WITH DUAL SECOND LEVEL ELECTRICAL INTERCONNECTIONS - A semiconductor package such as a multi-chip package is disclosed. The semiconductor package may be configured for dual second level interconnection onto a printed circuit board of a host device. Thus, a single semiconductor package may be used on host printed circuit boards having different configurations. | 04-28-2016 |
20160126170 | SOLID STATE CONTACTOR WITH IMPROVED INTERCONNECT STRUCTURE - A printed circuit board for selectively communicating power from a power source to a use has an input bus for receiving a power supply. A transistor is connected to the input bus and is positioned on one side of the input bus in a first direction. An output bus is connected to the transistor on an opposed side of the transistor relative to the input bus. The transistor is intermediate at the first input and output buses in the first dimension. A power supply system is also disclosed. | 05-05-2016 |
20160135298 | CIRCUIT PACKAGE - A circuit package having a first semiconductor body with a first monolithic integrated circuit having a first signal output that is interconnected with a bonding surface, and a first signal input that is interconnected with a bonding surface. The circuit package also has a second semiconductor body with a second monolithic integrated circuit having a second signal output that is interconnected with a bonding surface, and a second signal input that is interconnected with a bonding surface. The circuit package further features a contact element with at least one bonding surface, and a carrier element, wherein the bonding surface of the first signal output and the bonding surface of the second signal input are interconnected with the contact element so that an electrical connection exists between the first signal output and the second signal input, and a portion of the contact element penetrates the circuit package. | 05-12-2016 |
20160135300 | PRINTED CIRCUIT BOARD - A printed circuit board has a printed wiring board and a semiconductor package mounted on the printed wiring board. The printed wiring board has a signal conductor pattern and a resonance portion resonating with a plurality of resonance frequencies. The resonance portion has a plurality of conductor patterns aligned while separated each other to oppose to the ground conductor pattern through an insulating layer. The plurality of conductor patterns are arranged so as to oppose to the ground conductor pattern which is connected to a ground terminal of the semiconductor package. The resonance portion has a connecting conductor connecting the conductor patterns adjacent to each other. The resonance portion has a via conductor connecting the conductor pattern with the signal conductor pattern. The printed circuit board can reduce an exclusive region of the resonance portion interrupting a plurality of harmonic components, and can reduce EMI originating in a digital signal. | 05-12-2016 |
20160149318 | MATABLE AND DEMATABLE ELECTRICAL CONNECTING STRUCTURE AND CONNECTOR FOR ELECTRICAL CONNECTION WHICH INCLUDES SAME, SEMICONDUCTOR PACKAGE ASSEMBLY, AND ELECTRONIC DEVICE - The present invention discloses a matable and dematable electrical connecting structure characterized by comprising: a female coupling member having a first connecting portion; a male coupling member having a second connecting portion; and a connecting unit coupling the female coupling member and the male coupling member and electrically connecting the first and second connecting portions, wherein the connecting unit includes an inner conductive material which is electrically connected to the first connecting portion and is provided on the inner wall of an insert hole formed in the female connecting member, a column including a conductive material which is electrically connected to the second connecting portion, protruding from the male connecting member, and can be inserted in the insert hole, and one or more elastic pin including a surface of a conductive material which is extending in an outward direction from the column and elastically contacting the inner conductive material. | 05-26-2016 |
20160150642 | WIRING BOARD AND MOUNTING STRUCTURE USING SAME - A wiring board includes: an inorganic insulating layer having a via hole formed so as to penetrate the inorganic insulating layer in a thickness direction thereof; a conductive layer disposed on the inorganic insulating layer; and a via conductor which adheres to an inner wall of the via hole and is connected with the conductive layer. The inorganic insulating layer includes a first section including a plurality of inorganic insulating particles partly connected to each other, and a resin portion located in gaps between the inorganic insulating particles, and a second section which is interposed between the first section and the via conductor, including a plurality of inorganic insulating particles partly connected to each other, and a conducting portion composed of part of the via conductor which is located in gaps between the inorganic insulating particles. | 05-26-2016 |
20160163443 | EMBEDDED THIN FILM MAGNETIC CARRIER FOR INTEGRATED VOLTAGE REGULATOR - An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece. | 06-09-2016 |
20160163617 | CERAMIC CIRCUIT BOARD AND ELECTRONIC DEVICE - A ceramic circuit board includes a ceramic substrate, a first metal plate bonded to a front surface of the ceramic substrate, and a member bonded to a front surface side of the metal plate. The member is made up from a material which exhibits a lower coefficient of thermal expansion than that of the first metal plate, and which exhibits a higher Young's modulus than that of the first metal plate. | 06-09-2016 |
20160172288 | INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES | 06-16-2016 |
20160172290 | INTERPOSER WITH LATTICE CONSTRUCTION AND EMBEDDED CONDUCTIVE METAL STRUCTURES | 06-16-2016 |
20160183376 | ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME | 06-23-2016 |
20160183383 | Method for Contacting and Rewiring an Electronic Component Embedded into a Printed Circuit Board | 06-23-2016 |
20160192495 | SEMICONDUCTOR DEVICE - A semiconductor device including: a plurality of semiconductor units each constituting a three-level inverter circuit; and a connection unit electrically connecting the plurality of semiconductor units in parallel, wherein each of the semiconductor units includes: a multi-layer substrate including an insulating plate and circuit plates disposed on a primary surface of the insulating plate; a plurality of semiconductor elements each having a back surface thereof fixed to one of the circuit plates and a front surface thereof having primary electrodes; and wiring members electrically connected to the primary electrodes of the semiconductor elements, and wherein in each of the semiconductor units, the multi-layer substrate, the plurality of semiconductor elements, and the wiring members are configured in such a way as to constitute the three-level inverter circuit. | 06-30-2016 |
20160205780 | PRINTED CIRCUIT BOARD, PACKAGE AND METHOD OF MANUFACTURING THE SAME | 07-14-2016 |
20160255717 | MULTILAYER WIRING BOARD | 09-01-2016 |