Entries |
Document | Title | Date |
20080197493 | Integrated circuit including conductive bumps - One embodiment provides an integrated circuit including an electrical contact and a conductive bump elongated via centrifugal forces. The conductive bump has a base and a top. The base is attached to the electrical contact and the top remains unattached. | 08-21-2008 |
20080203566 | Stress buffer layer for packaging process - A semiconductor package structure is provided. The semiconductor package structure includes a first module; a second module, wherein the first and the second modules each are selected from the group consisting essentially of a package substrate, a die and a package module; and an elastic die-attaching film having a hardness of less than about 150 MPa interposed between the first and the second modules. | 08-28-2008 |
20080203567 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor package includes a print substrate which has a plurality of wiring layers. The print substrate has a wiring for connect pins extending internally across the plurality of wiring layers from one surface of the print substrate; a wiring for a non connect pin insulated in the thickness direction of the plurality of wiring layers by a void formed to an intermediate wiring layer as one of the plurality of wiring layers; and a surge absorption wiring facing the wiring for the non connect pin across the void. The interval of the void between the wiring for the non connect pin and the surge absorption wiring is set smaller than the interval between a non connect pin to be disposed and a connect pin adjacent to the connect pin. | 08-28-2008 |
20080203568 | Semiconductor device - An improved reliability in a region of a junction between a bonding wire and an electrode pad at higher temperature is achieved. A semiconductor device | 08-28-2008 |
20080203569 | Semiconductor device and manufacturing method thereof - A semiconductor device comprising: a semiconductor substrate which has a plurality of connection pads on a top surface thereof; an insulating film which is provided on the semiconductor substrate and which has a plurality of openings formed at portions corresponding to the connection pads; a plurality of re-wirings each of which is provided to be connected to one of the connection pads via one of the openings of the insulating film; a re-wiring upper layer insulating film which is filled between the re-wirings on a top surface of the insulating film, and which is provided such that a top surface thereof is as high as or higher than a top surface of the re-wirings; and a plurality of columnar electrodes each of which is provided to be connected to a top surface-side connection pad section of each of the re-wirings. | 08-28-2008 |
20080211093 | Semiconductor device having conductive bumps and fabrication method thereof - A semiconductor device having conductive bumps and a fabrication method thereof is proposed. The fabrication method includes the steps of forming a first metallic layer on a substrate having solder pads and a passivation layer formed thereon, and electrically connecting it to the solder pads; applying a second covering layer over exposed parts of the first metallic layer; subsequently, forming a second metallic layer on the second covering layer, and electrically connecting it to the exposed parts of the first metallic layer; applying a third covering layer, and forming openings for exposing parts of the second metallic layer to form thereon a conductive bump having a metallic standoff and a solder material. The covering layers and the metallic layers can provide a buffering effect for effectively absorbing the thermal stress imposed on the conductive bumps to prevent delamination caused by the UBM layers. | 09-04-2008 |
20080217773 | Removal of integrated circuits from packages - Packaging is substantially entirely removed from an integrated circuit die. The method allows the batch processing of several integrated circuit dies, such that packaging is removed from each die approximately simultaneously. | 09-11-2008 |
20080217774 | Semiconductor device - When a BGA package device is mounted to another substrate and tested for packaging strength, solder balls ( | 09-11-2008 |
20080224312 | DEVICE HAVING A BONDING STRUCTURE FOR TWO ELEMENTS - A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding. | 09-18-2008 |
20080230901 | STRUCTURE FOR CONTROLLED COLLAPSE CHIP CONNECTION WITH DISPLACED CAPTURED PADS - A structure, for controlled collapse chip connection (C4) between an integrated circuit (IC) and a substrate, that alleviates the adverse effects resulting from induced stresses in C4 solder joints, the structure includes: a first and second array defined on the ball limiting metallurgy (BLM) side of the IC; a first and second array of surface mount (SM) pads arranged on the substrate placement side; and wherein the reduction of the adverse effects resulting from the induced stress in the solder joints is facilitated by varying the relative alignment of the first and second arrays of SM pads to the first and second arrays of solder balls. | 09-25-2008 |
20080230902 | Method of Forming Solder Bump on High Topography Plated Cu - A solder bump is formed on a high-topography, electroplated copper pad integrating a first and second passivation layer. A sacrifice layer is deposited over the second passivation layer. The sacrifice layer is lithographically patterned. A via is etched in the sacrifice layer. A solder bump is formed in the via. A portion of the sacrifice layer is removed using the solder bump as a mask. A semiconductor device includes a substrate, an input/output (I/O) pad disposed over the substrate, a first passivation layer disposed over a portion of the I/O pad, a first conductive layer disposed over the first passivation layer, a second passivation layer disposed over the first conductive layer, a sacrifice layer disposed over the second passivation layer, the sacrifice layer having a via, and a solder bump formed in the via, the solder bump used as a mask to remove a portion of the sacrifice layer. | 09-25-2008 |
20080230903 | SEMICONDUCTOR CHIP, SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor chip constitutes a semiconductor device in which a plurality of semiconductor chips are laminated. The semiconductor chip includes a plurality of terminals which are to be connected to another semiconductor chip. At least one terminal of the terminals has a higher height than that of another terminal. | 09-25-2008 |
20080237854 | METHOD FOR FORMING CONTACT PADS - First, a substrate having a conductor therein is provided. Next, a first dielectric layer is disposed on the conductor and the substrate and a first opening is formed in the first dielectric layer for exposing the conductor. A first metal layer is deposited over the surface of the first dielectric layer and into the first opening. Next, an etching stop layer and a second metal layer are deposited over the surface of the first metal layer, and a pattern transfer process is performed by using a second dielectric layer as a mask to remove a portion of the first metal layer, the etching stop layer, and the second metal layer for exposing the first dielectric layer. A passivation layer is disposed on the second metal layer and the first dielectric layer and a second opening is formed in the passivation layer to expose a portion of the second metal layer. | 10-02-2008 |
20080237855 | Ball grid array package and its substrate - A BGA package and a substrate for the package are disclosed. A chip is disposed on a top surface of the substrate. A plurality of solder balls are disposed on a plurality of ball pads formed on a bottom surface of the substrate. The substrate has at least a core layer with a plurality of corner cavities filled with low-modulus materials as stress buffer. Additionally, some of the ball pads at the corners of the substrate are disposed under the corner cavities. | 10-02-2008 |
20080237856 | Semiconductor Package and Method for Fabricating the Same - A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip in the semiconductor package. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. The central electrode pads and the conductor plate may also be connected together using gold stud bumps. Preferably, the conductor plate is composed of a multilayer structure of two or more layers, and each conductor plate is used in power-supply wiring or ground wiring. | 10-02-2008 |
20080246147 | Novel substrate design for semiconductor device - A novel design and method of fabricating a semiconductor device. In a preferred embodiment, the present invention is a flip chip package including a BT substrate. On the side of the substrate facing the die, thin traces are formed of an enhanced conductive material. Conductive bumps such as eutectic solder balls are then mounted on the traces, and the die mounted to the bumps. The die then packaged and mounted to a printed circuit board using, for example, a ball grid array. | 10-09-2008 |
20080251916 | UBM structure for strengthening solder bumps - A novel UBM structure for improving the strength and performance of individual UBM layers in a UBM structure is disclosed. In one aspect, a UBM structure for disposal onto an electrically conductive element comprised of aluminum is disclosed. In one embodiment, the UBM structure comprises a tantalum layer disposed over the aluminum electrically conductive element, and a copper layer disposed over the tantalum layer, where the UBM structure is configured to receive a solder ball thereon. | 10-16-2008 |
20080251917 | SOLDER PAD AND METHOD OF MAKING THE SAME - A solder pad structure includes a first metal layer disposed on an insulation layer, wherein the first metal layer is electrically connected with an underlying interconnection circuit layer through a conductive through hole disposed in the insulation layer. A solder resist layer having an opening exposing a central portion of the first metal layer is disposed on the insulating layer. A pillar-shaped second metal layer is disposed within the opening directly on the first metal layer. A solder ball filled into the opening is in contact with the pillar-shaped second metal layer. | 10-16-2008 |
20080251918 | Wire Bonds Having Pressure-Absorbing Balls - A semiconductor device with a chip having at least one metallic bond pad ( | 10-16-2008 |
20080272488 | Semiconductor Device - A semiconductor device according to the present invention includes a semiconductor chip having a functional surface formed with a functional element, an electrode pad provided directly on the functional element on the functional surface of the semiconductor chip, a protective resin layer laminated on the functional surface of the semiconductor chip, an external connection terminal provided on the protective resin layer in opposed relation to the electrode pad, and a post extending through the protective resin layer in a direction in which the electrode pad and the external connection terminal are opposed to each other for connection between the electrode pad and the external connection terminal. | 11-06-2008 |
20080272489 | Package substrate and its solder pad - A semiconductor chip substrate with solder pad includes: a core layer and at least one conductive structure formed on the surface of the core layer; an insulation layer with at least one patterned opening covering the conductive structure, wherein the patterned opening has a center portion and a plurality of wing portions on the peripheral edge of the center portion to define the exposed area of the conductive structure as the solder pad. The solder pad with wing will improve the adhesion effect between the solder pad and the solder ball. | 11-06-2008 |
20080277786 | Semiconductor package substrate - A semiconductor package substrate includes a body having an upper surface and a lower surface opposite to one another, a plurality of circuit layers formed in the body, a plurality of solder pads formed on the upper surface of the body, and a plurality of solder ball pads formed on the lower surface of the body. Each of the solder pads is electrically connected to one of the solder ball pads via the circuit layers and conductive structures disposed between the circuit layers, wherein the circuit layers and conductive structures are configured to expand outwardly in a fan-out manner so as to provide more space between the circuit layers closer to the lower surface of the body such that part of the solder pad-solder ball pad electrical connections can comprise a plurality of parallel connected conductive structures formed in the space, thereby enhancing the heat conducting passageway and the effect of heat-dissipation without having to dispose more solder pads on surface of the substrate. | 11-13-2008 |
20080284017 | METHODS OF FABRICATING CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE, AND CIRCUIT BOARD AND SEMICONDUCTOR PACKAGE FABRICATED USING THE METHODS - Provided are methods of fabricating a circuit board and a semiconductor package, and a circuit board and a semiconductor package fabricated using the methods. The circuit board comprises: a lower wiring pattern disposed on an upper surface of a resin substrate comprising a filler; a resin layer disposed on the lower wiring pattern; an upper wiring pattern comprising a bonding pad disposed on the resin layer; and a passivation layer comprising an upper opening exposing the bonding pad. The resin substrate comprises a substrate opening exposing a lower surface of the lower wiring pattern. | 11-20-2008 |
20080284018 | INTEGRATED CHIP CARRIER WITH COMPLIANT INTERCONNECTS - An electronic device includes: at least one electronic chip comprising a first coefficient of thermal expansion (CTE); and a carrier including a top surface connected to the bottom surface of the chip by solder bumps. The carrier further includes a second CTE that approximately matches the first CTE, and a plurality of through vias from the bottom surface of the carrier to the top surface of the carrier layer. Each through via includes a collar exposed at the top surface of the carrier, a pad exposed at the bottom surface of the carrier, and a post disposed between the collar and the pad. The post extends thorough a volume of space. | 11-20-2008 |
20080290513 | SEMICONDUCTOR PACKAGE HAVING MOLDED BALLS AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor package having molded balls on a bottom surface of a PCB and a method of manufacturing the semiconductor package. The semiconductor package includes: a semiconductor chip mounting member comprising circuit patterns on a first surface, an insulating layer defining openings exposing at least portions of the circuit patterns, and external contact terminals arranged on the portions of circuit patterns exposed by the openings; a semiconductor chip formed on a second surface of the semiconductor chip mounting member and electrically connected to the semiconductor chip mounting member; a first sealing portion coating the second surface of the semiconductor chip mounting member and the semiconductor chip; and a second sealing portion arranged on the insulating layer and the external contact terminals such that at least portions of the external contact terminals are exposed. | 11-27-2008 |
20080290514 | Semiconductor device package and method of fabricating the same - In a semiconductor device, a package including the semiconductor device and a method of forming the same, the semiconductor device package includes a semiconductor device, a wiring board, and an underfill material layer. The semiconductor device includes a semiconductor chip, a metal layer, and solder balls for bump contacts. The semiconductor chip includes an active surface having bonding pads and a rear surface opposite the active surface and having concave portions corresponding to the bonding pads. The metal layer fills the concave portions and covers the rear surface. The solder balls for bump contacts are provided on the bonding pads. The wiring board includes an upper surface to which the semiconductor device is mounted and a lower surface opposite the upper surface. The underfill material layer fills a space between the active surface of the semiconductor device and the upper surface of the wiring board. The semiconductor device and the wiring board are electrically connected to each other by the solder balls for bump contacts of the semiconductor device and bonding electrodes included in the upper surface of the wiring board. | 11-27-2008 |
20080296763 | Multi-Die Wafer Level Packaging - A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration. | 12-04-2008 |
20080296764 | Enhanced copper posts for wafer level chip scale packaging - An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint. | 12-04-2008 |
20080296765 | Semiconductor element and method of manufacturing the same - A semiconductor element ( | 12-04-2008 |
20080296766 | REDUCED INDUCTANCE IN BALL GRID ARRAY PACKAGES - Techniques are described for reducing inductance in ball grid array (BGA) packages for integrated circuits (ICs). The BGA package comprises a set of contacts disposed near an outer edge of the BGA package that receives signal lines and isolated power and ground lines. One area of excess parasitic inductance within the BGA package is in the wire bonds that couple the set of contacts to the IC. The techniques described herein shorten the wire bonds in order to reduce the amount of parasitic inductance. The techniques include extending traces from a subset of the contacts inward into the BGA package toward the IC mounted. The wire bonds then couple the traces to the IC, thereby electrically coupling the subset of contacts to the IC. The presence of the traces substantially reduces lengths of the wire bonds relative to wire bonds that directly couple the set of contacts to the IC. | 12-04-2008 |
20080303149 | Electronic Component - An electronic component including, on one surface of a substrate ( | 12-11-2008 |
20080303150 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line circuit structure mainly includes: a first semiconductor device, an insulated layer on the same surface, an outer circuit layer above the first semiconductor device, and a solder mask formed on the outer circuit layer. The surface which is not covered by the solder mask can be made to be a pad, and electrically connected with a second semiconductor device. The fine line circuit layer, which is exposed, is to be a tin ball pad where a tin ball is filled. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 12-11-2008 |
20080303151 | Method of Packaging a Microchip - A method of packaging an integrated circuit singulates a wafer to form an integrated circuit, positions the integrated circuit on a carrier, and passivates the integrated circuit after the positioning the integrated circuit on the carrier. At this point, the integrated circuit is secured to the carrier. The method also electrically connects the integrated circuit to a plurality of exposed conductors. | 12-11-2008 |
20080303152 | Contact pad and method of forming a contact pad for an integrated circuit - A contact pad in an integrated circuit is disclosed. The contact pad comprises a flat portion comprising a base of the contact pad; a plurality of projections extending from and substantially perpendicular to the flat portion; and a solder ball attached to the projections and the flat portion. A method of forming a contact pad is also disclosed. | 12-11-2008 |
20080303153 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE PRODUCT - In a semiconductor device, a semiconductor element is built into a resin molded part molded in a flat plate shape. A wiring is electrically connected to the semiconductor element and is disposed on one surface of the resin molded part so that an inner surface side of the wiring is sealed with the resin molded part and an outer surface of the wiring is exposed flush with the one surface of the resin molded part. An electrode is disposed on the wiring in an outside of a plane area of the semiconductor element and extends through the resin molded part in a thickness direction. A tip part of the electrode protrudes from the other surface of the resin molded part. | 12-11-2008 |
20080308932 | SEMICONDUCTOR PACKAGE STRUCTURES - A semiconductor structure includes a plurality of solder structures between a first substrate and a second substrate. A first encapsulation material is substantially around a first one of the solder structures and a second encapsulation material is substantially around a second one of the solder structures. The first one and the second one of the solder structures are near to each other and a gap is between the first encapsulation material and the second encapsulation material. | 12-18-2008 |
20080308933 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH DIFFERENT CONNECTION STRUCTURES - An integrated circuit package system is provided including forming an external interconnect having a tip without a die-attach paddle; mounting a first integrated circuit device structure having a conductive ball over the tip; connecting a first wire between the first integrated circuit device structure and under the tip; and encapsulating the first integrated circuit device structure, the first wire, and the external interconnect with the external interconnect partially exposed. | 12-18-2008 |
20080308934 | SOLDER BUMP INTERCONNECT FOR IMPROVED MECHANICAL AND THERMO-MECHANICAL PERFORMANCE - An apparatus and method for a semiconductor package including a bump on input-output (IO) structure are disclosed involving a device pad, an under bump metal pad (UBM), a polymer, and a passivation layer. The shortest distance from the center of the device pad to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.5:1 to 0.95:1. Also, the shortest distance from the center of the polymer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.85:1. Additionally, the shortest distance from the center of the passivation layer to its outer edge, and the shortest distance from the center of the UBM to its outer edge are in a ratio from 0.35:1 to 0.80:1. | 12-18-2008 |
20080308935 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP PACKAGE, AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter. | 12-18-2008 |
20080315416 | A SEMICONDUCTOR PACKAGE WITH PASSIVE ELEMENTS EMBEDDED WITHIN A SEMICONDUCTOR CHIP - A semiconductor package includes a semiconductor chip having bonding pads formed on a top surface and a first via hole and a second via hole formed on both-side edges; a passive element formed within the first via hole; a via wiring formed within the second via hole; a first wiring connected to the bonding pad at one end and connected to the passive element and the via wiring on a top surface of the semiconductor chip; a second wiring formed on a back surface of the semiconductor chip and formed to connect with the passive element and the via wiring; a first passivation film formed in such a way to expose one portion of the first wiring on a top surface of the semiconductor chip; and a second passivation film formed in such a way to expose one portion of the second wiring on a bottom surface of the semiconductor chip. | 12-25-2008 |
20080315417 | CHIP PACKAGE - A chip package includes a patterned conductive layer, a first solder resist layer, a second solder resist layer, a chip, bonding wires and a molding compound. The patterned conductive layer has a first surface and a second surface opposite to each other. The first solder resist layer is disposed on the first surface. The second solder resist layer is disposed on the second surface, wherein a part of the second surface is exposed by the second solder resist layer. The chip is disposed on the first solder resist layer, wherein the first solder resist layer is disposed between the patterned conductive layer and the chip. The bonding wires are electrically connected to the chip and the patterned conductive layer exposed by the second solder resist layer. The molding compound encapsulates the pattern conductive layer, the first solder resist layer, the second solder resist layer, the chip and the bonding wires. | 12-25-2008 |
20090001573 | Structure and method for wire bond integrity check on BGA substrates using indirect electrical interconnectivity pathway between wire bonds and ground - An invention providing improvement in integrity testing of wire bonds between an IC die and a BGA substrate. | 01-01-2009 |
20090001574 | Multi-chips Stacked package structure - A multi-chips Stacked package structure, wherein a plurality of chips are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each chip on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality of metal pads on the plurality of chips with the plurality metallic ends on the substrate in one wire bonding process; then an encapsulate is provided for covering the plurality of stacked chips, a plurality of metal wires and the plurality of metallic ends on the substrate. | 01-01-2009 |
20090001575 | Printed Circuit Board, Mounting Method of Electronic Component, and Electronic Apparatus - According to one embodiment, there is provided a printed circuit board includes a printed wiring board having a component mounting surface, a semiconductor package which is mounted on the component mounting surface of the printed wiring board by solder bonding using solder balls, and reinforcement portions which locally reinforce portions of the solder bonding of the semiconductor package at a plurality of locations on the component mounting surface of the printed wiring board, the reinforcement portions being formed of a resin material having parts entering the solder balls of the portions of the solder bonding. | 01-01-2009 |
20090008777 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF THE SAME - An interconnecting structure for a semiconductor die assembly, comprising: a substrate with pre-formed wiring circuit formed therein; a die having contact pads on an active surface; an adhesive material formed over the substrate to adhere the die over the substrate, wherein the substrate includes a via through the substrate and the adhesive material; and conductive material refilled into the via to couple the contact pads of the die to the wiring circuit of the substrate. | 01-08-2009 |
20090008778 | Structure and manufactruing method of chip scale package - A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure. | 01-08-2009 |
20090014875 | BONDING PAD FOR PREVENTING PAD PEELING AND METHOD FOR FABRICATING THE SAME - A bonding pad includes multiple metal layers, insulation layers filled between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer, where a bonding is performed, and the underlying metal layers. Peeling of the bonding pad can be prevented during the ball bonding by forming the fixing pin coupled to the edges of the bonding pad. The upper portion of the fixing pin is formed in a disk shape and a ball portion of the fixing pin is fixed by slits such that the peeling of the bonding pad can be further prevented. | 01-15-2009 |
20090014876 | Wafer level stacked package having via contact in encapsulation portion and manufacturing method thereof - Provided are a wafer level stacked package with a via contact in an encapsulation portion, and a manufacturing method thereof. A plurality of semiconductor chips and encapsulation portions may be vertically deposited and electrically connected through a via contact that may be vertically formed in the encapsulation portion. Thus, an effective fan-out structure may be produced, vertical deposition may be available regardless of the type of a semiconductor device, and productivity may be improved. | 01-15-2009 |
20090026612 | SEMICONDUCTOR PACKAGE HAVING AN IMPROVED CONNECTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package having an improved connection structure and a method for manufacturing the same is described. The semiconductor package includes a substrate having a substrate body, connection pads that are located on one surface of the substrate body, and ball lands that are located on the other surface of the substrate body opposite the one surface. The ball lands are electrically connected to the connection pads. A semiconductor chip having bumps that are formed to correspond to the connection pads is connected to the substrate. An anisotropic conductive member having an insulation element is interposed between the substrate and the semiconductor chip to connect the substrate and the semiconductor chip. Electrically flowable conductive particles within the insulation element flow in the insulation element according to applied electric fields so as to arrange the electrically flowable conductive particles between the connection pads and the bumps. | 01-29-2009 |
20090026613 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern. | 01-29-2009 |
20090026614 | SYSTEM IN PACKAGE AND METHOD FOR FABRICATING THE SAME - A system device package that includes a semiconductor substrate, a metal line formed on the semiconductor substrate, a passivation film formed over the semiconductor substrate including the metal line, wherein the passivation film includes first and second openings, a pad formed over the passivation film and covering the first and second openings for connection to the metal line through the first opening, a via conductor extending through the pad, the passivation film and the semiconductor substrate such that the via conductor is in direct contact with the pad. The via conductor includes a first exposed end protruding from the pad and which serves as a first bump and a second exposed end protruding from the substrate that serves as a second bump. As a result, it is possible to reduce the total number of processes and fabrication costs and thus to improve fabrication efficiency. | 01-29-2009 |
20090026615 | SEMICONDUCTOR DEVICE HAVING EXTERNAL CONNECTION TERMINALS AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device has a semiconductor element made up of a semiconductor chip, first solder balls provided on the semiconductor chip and a BGA substrate on which the semiconductor chip is mounted via the first solder balls. Furthermore, the semiconductor device has external terminals on a surface of the BGA substrate opposing to a surface on which the semiconductor chip is mounted. The external terminals include oxide films provided with through holes. | 01-29-2009 |
20090032946 | INTEGRATED CIRCUIT - Integrated circuits and methods for making integrated circuits having a base layer, a side substrate, a circuit substrate and a connection. A bottom face of the base layer is disposed on the side substrate. The side substrate includes a first contact field, at least a second contact field, and a signal line. The first contact field is arranged on the bottom face in an area of an opening of the base layer, the second contact field is arranged on another face of the side substrate, and the signal line connects the first contact field to the second contact field. The circuit substrate is disposed on the base layer and alongside the side substrate. The connection connects the circuit substrate to the second contact field of the side substrate. | 02-05-2009 |
20090032947 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device has a semiconductor die having at least one bond pad formed on a first surface thereof. A substrate has at least one bond finger formed on a first surface thereof. A second surface of the semiconductor die is attached to the first surface of the substrate. A conductive wire connects the bond pad of the semiconductor die and the bond finger of the substrate wherein at least one end of the conductive wire has a stack bump. An encapsulant is provided to encapsulate the semiconductor die and the conductive wire. | 02-05-2009 |
20090032948 | SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR DESIGNING THE SAME - A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array. | 02-05-2009 |
20090039508 | LARGER THAN DIE SIZE WAFER-LEVEL REDISTRIBUTION PACKAGING PROCESS - Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes an integrated circuit die, a layer of insulating material, a redistribution interconnect on the layer of insulating material, and a ball interconnect. The integrated circuit die has a plurality of terminals on a first surface. The insulating material covers the first surface of the die and fills a space adjacent to one or more sides of the die. The redistribution interconnect has a first portion coupled to a terminal of the die through the first layer, and a second portion that extends away from the first portion over the insulating material filling the space adjacent to the die. The ball interconnect is coupled to the second portion of the redistribution interconnect. | 02-12-2009 |
20090039509 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided which can prevent contacts between thin metal wires for electrically connecting the electrodes of a substrate with the electrodes of a semiconductor element. The semiconductor device of the present invention includes metal protrusions formed on the electrodes of the semiconductor element, the metal protrusions having lower hardness than the hardness of the thin metal wires. The metal protrusions are bonded to the thin metal wires. | 02-12-2009 |
20090039510 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor construct constructed by a semiconductor substrate and a plurality of external connection electrodes provided under the semiconductor substrate. A lower insulating film is provided under and outside the semiconductor construct. A sealing film is provided on the lower insulating film to cover a periphery of the semiconductor construct. A plurality of lower wiring lines are provided under the lower insulating film and connected to the external connection electrodes of the semiconductor construct, respectively. | 02-12-2009 |
20090045511 | INTEGRATED CIRCUIT INCLUDING PARYLENE MATERIAL LAYER - An integrated circuit includes a substrate including a contact pad, a redistribution line coupled to the contact pad, and a dielectric material layer between the substrate and the redistribution line. The integrated circuit includes a solder ball coupled to the redistribution line and a parylene material layer sealing the dielectric material layer and the redistribution line. | 02-19-2009 |
20090045512 | CARRIER SUBSTRATE AND INTEGRATED CIRCUIT - A carrier substrate comprising a through contact connecting a first contact field on a top face of the carrier substrate to a second contact field on a bottom face of the carrier substrate and a substrate material being provided around the through contact. | 02-19-2009 |
20090045513 | SEMICONDUCTOR CHIP PACKAGE, ELECTRONIC DEVICE INCLUDING THE SEMICONDUCTOR CHIP PACKAGE AND METHODS OF FABRICATING THE ELECTRONIC DEVICE - A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other. | 02-19-2009 |
20090051030 | SEMICONDUCTOR PACKAGE WITH PAD PARTS ELECTRICALLY CONNECTED TO BONDING PADS THROUGH RE-DISTRIBUTION LAYERS - The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards. | 02-26-2009 |
20090051031 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure comprises a carrier, a chip, at least one wire, a molding compound, at least one first solder ball and at least one second solder ball. The carrier has a chip chamber passing through the first surface and the second surface. The chip is disposed in the chip chamber, and an active surface of the chip is coplanar with the first surface. During packaging, the first surface and the active surface are both tightly pasted on a carrier tape to facilitate the subsequent wire bonding and sealing process. Afterwards, the carrier tape is removed for exposing the active surface and the first surface, and the active surface of the chip is coplanar with the first surface of the carrier, hence simplifying the packaging process and reducing the thickness of the package structure. | 02-26-2009 |
20090057896 | Nail-Shaped Pillar for Wafer-Level Chip-Scale Packaging - A wafer-level chip-scale packaging feature for a semiconductor device is disclosed which has a substrate, a plurality of nail-shaped conducting posts extending from a surface of the substrate, and a plurality of solder balls, where each of the solder balls is connected to one of the nail-shaped conducting posts. When a different-sized solder ball is desired for use, the device can be re-processed by only removing and replacing the cross-members of the nail-shaped conducting posts, which cuts down on the re-processing expense. | 03-05-2009 |
20090057897 | High strength solder joint formation method for wafer level packages and flip applications - A Micro SMDxt package is provided that configured for mounting to a circuit board. The SMDxt package includes a silicon-based IC having an array of contact pads on one side of thereof, and a die electrically attached to the silicon-based IC. A plurality of solder balls is included, each of which has a polymeric core surrounded by a metallic shell that in turn is surrounded by a layer of solder material. Further, each solder ball is positioned in contact with a corresponding contact pad of the package. An intertwined intermetallic fusion layer is formed through the fusion between material components of the contact pads and the solder material, via heat treatment. The intermetallic fusion extends between and from an outer surface of the metallic shell of each solder to an outer surface of a corresponding contact pad to form a high strength intermetallic solder joint therebetween. | 03-05-2009 |
20090057898 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An insulating layer having an opening from which an electrode pad of a device is exposed is formed on the surface of a semiconductor substrate having the device fabricated therein, and an external terminal pad defined by a portion of a conductor layer formed on the insulating layer is connected to the electrode pad by means of a bonding wire. Further, a conductor post is formed on the external terminal pad, and an encapsulation resin layer is formed to coat a region on the semiconductor substrate in which the conductor post is formed, and to expose a top portion of the conductor post. An external connecting terminal is bonded to the top portion of the conductor post. | 03-05-2009 |
20090057899 | Semiconductor integrated circuit device and method of fabricating the same - A semiconductor integrated circuit device includes a semiconductor substrate including a main chip region and a pad region, a multi-layer pad structure on the pad region of the semiconductor substrate, a redistribution pad through the semiconductor substrate and in contact with a bottom surface of the multi-layer pad structure, the redistribution pad being electrically connected to the multi-layer pad structure, a trench belt through the semiconductor substrate and surrounding the redistribution pad, the trench belt electrically isolating the redistribution pad and a portion of the semiconductor substrate adjacent to the redistribution pad, and a connection terminal on the redistribution pad, the connection terminal electrically connecting the redistribution pad to an external source. | 03-05-2009 |
20090057900 | Stacked Chip Package With Redistribution Lines - A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate. | 03-05-2009 |
20090057901 | STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD - A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump. | 03-05-2009 |
20090065935 | SYSTEMS AND METHODS FOR BALL GRID ARRAY (BGA) ESCAPE ROUTING - A ball grid array (BGA) package and its corresponding printed circuit board incorporate an improved escape routing scheme. The substrate includes a plurality of conductive pads having a periphery defined by a predetermined edge pattern forming routing channels therebetween. A plurality of signal lines connected to a subset of the conductive pads extends beyond the periphery through the routing channels. The predetermined pattern may, for example, be a right triangle repeating with a periodicity along the periphery of the array, wherein the right triangle has a first side defined by a number of rows in the array, and a second side, perpendicular to the first, defined by a number of layers in the array. | 03-12-2009 |
20090065936 | SUBSTRATE, ELECTRONIC COMPONENT, ELECTRONIC CONFIGURATION AND METHODS OF PRODUCING THE SAME - A substrate for an electronic component comprises a dielectric body having an upper surface including a plurality of inner contact pads and a lower surface including a plurality of outer contact pads. Each outer contact pad has an inner face and an outer face. An insulating layer covers the lower surface of the dielectric body and the peripheral regions of the plurality of outer contact pads. A depression is located in the approximate lateral centre of the outer face of each of the plurality of outer contact. | 03-12-2009 |
20090065937 | STRUCTURE OF HIGH PERFORMANCE COMBO CHIP AND PROCESSING METHOD - A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump. | 03-12-2009 |
20090072397 | REDISTRIBUTION LAYER FOR WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD THEREFOR - In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern ( | 03-19-2009 |
20090079070 | Semiconductor Package with Passivation Island for Reducing Stress on Solder Bumps - A flip chip style semiconductor package has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. An under bump metallization (UBM) layer is in electrical contact with the contact pad. A passivation layer is formed over the substrate. In one case, the UBM layer is disposed above the passivation layer. Alternatively, the passivation layer is disposed above the UBM layer. A portion of the passivation layer is removed to create a passivation island. The passivation island is centered with respect to the contact pad with its top surface devoid of the UBM layer. A solder bump is formed over the passivation island in electrical contact with the UBM layer. The passivation island forms a void in the solder bump for stress relief. The UBM layer may include a redistribution layer such that the passivation island is offset from the contact pad. | 03-26-2009 |
20090079071 | STRESS RELIEF STRUCTURES FOR SILICON INTERPOSERS - An electronic device and method of making the device. The device includes: a carrier; a silicon interposer connected to a top surface of the carrier, the interposer having wires extending from a top surface of the interposer, through the interposer, to a bottom surface of the interposer, the wires at the bottom surface of the interposer electrically connected to wires in a top surface of the carrier; an integrated circuit chip connected to the top surface of the interposer, wires at a surface of the integrated circuit chip electrically connected to the wires in the top surface of the interposer; and a stress relief structure attached to the interposer, the stress relief structure either (i) not electrically connected to the wires of the interposer or integrated circuit chip or (ii) electrically connected to ground by wires of the interposer or wires of the integrated circuit chip. | 03-26-2009 |
20090079072 | Semiconductor device having low dielectric insulating film and manufacturing method of the same - A semiconductor device includes a semiconductor substrate having an integrated circuit. A low dielectric film wiring line laminated structure portion is provided on the semiconductor substrate except a peripheral portion thereof, and is constituted by low dielectric films and wiring lines. The low dielectric film has a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the laminated structure portion. A connection pad portion is arranged on the insulating film and connected to a connection pad portion of an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film is provided on the insulating film which surrounds the pump electrode and on the peripheral portion of the semiconductor substrate. The side surfaces of the laminated structure portion are covered with the insulating film or the sealing film. | 03-26-2009 |
20090079073 | Semiconductor device having low dielectric insulating film and manufacturing method of the same - A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film. | 03-26-2009 |
20090079074 | Semiconductor device having decoupling capacitor formed on substrate where semiconductor chip is mounted - A semiconductor device includes a substrate having a first surface and a second surface opposing to the first surface, a semiconductor chip mounted on the first surface of the substrate, a first pad formed on the first surface of the substrate to electrically connect to a first terminal of the semiconductor chip, a second pad formed on the second surface of the substrate to electrically connect to a second terminal of the semiconductor chip, and a decoupling capacitor formed on the first surface and including the first and second pads serving as electrodes of the decoupling capacitor. | 03-26-2009 |
20090085206 | METHOD OF FORMING SOLDER BUMPS ON SUBSTRATES - A method of forming solder bumps on a substrate is disclosed. The method includes forming a plurality of contact points on the substrate. The method further includes depositing a layer of surface finish material on the plurality of contact points. Furthermore, the method includes disposing a plurality of solder balls on the layer of surface finish material. Each solder ball of the plurality of solder balls has conductive material including a solder alloy and Phosphorus. Thereafter, the method includes applying a solder reflow process to the plurality of solder balls to configure a plurality of solder bumps on the substrate layer. The concentration of the Phosphorus in the solder material is based on target performance characteristic of the substrate having the plurality of solder bumps. | 04-02-2009 |
20090085207 | Ball grid array substrate package and solder pad - The invention provides ball grid array assemblies and methods for their manufacture, with improved characteristics favoring the formation of secure metallurgical solder pad to solder ball joints. In disclosed preferred embodiments of ball grid array assemblies, substrates, and methods according to the invention, solder pads are provided with metal blocks comprising a layer primarily of nickel plated with an outer metal layer comprising primarily gold. | 04-02-2009 |
20090085208 | Semiconductor device - A semiconductor device ( | 04-02-2009 |
20090091032 | Bond Pad Design for Fine Pitch Wire Bonding - A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad. | 04-09-2009 |
20090096098 | INTER-CONNECTING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF THE SAME - The interconnecting structure for a semiconductor die assembly comprises a build-up layers having RDL formed therein formed over a die having die pads formed thereon, wherein the RDL is coupled to the die pads; an isolation base having ball openings attached over the build-up layer to expose ball pads within the build-up layers; and conductive balls placed into the ball openings of the isolation base and attached on the ball pads within the build-up layers. | 04-16-2009 |
20090096099 | PACKAGE SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer. | 04-16-2009 |
20090102050 | SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE - A solder ball disposing surface structure of a package substrate is disclosed, wherein a package substrate has a chip disposing surface with a first circuit layer, an opposed solder ball disposing surface with a second circuit layer, and a first insulative protection layer formed on the chip disposing surface and the first circuit layer. The solder ball disposing surface structure includes: metal pads integral to the second circuit layer; metal flanges formed around the metal pads; and a second insulative protection layer formed on the solder ball disposing surface, the second insulative protection layer having second openings each with a size smaller than an outer diameter of each of the metal flanges so as to expose a part of surfaces of the metal flanges, thereby increasing contact area of the surface for mounting conductive elements and preventing detachment of the conductive elements from the surface due to poor bonding force. | 04-23-2009 |
20090108447 | SEMICONDUCTOR DEVICE HAVING A FINE PITCH BONDPAD - A semiconductor device is provided, including a semiconductor chip having fine pitch bond pads, dummy bond pads, and ball bonds formed on the semiconductor chip, and electrically connected to circuits of the semiconductor chip, where the width of each fine pitch bond pad is less than the diameter of each ball bond. The dummy bond pads are formed between adjacent bond pads and have a plurality of lands not connected to each other. The ball bonds may be connected to the bond pads in a zigzag configuration and are partially connected to the dummy bond pads. Accordingly, the pitch between bond pads is reduced while preventing short circuits between adjacent ball bonds. | 04-30-2009 |
20090108448 | METAL PAD OF SEMICONDUCTOR DEVICE - A metal pad of a semiconductor device that prevents cracking during a ball bonding process in a metal pad applied to a wafer level package (WLP). The metal pad includes a main metal pad formed on and/or over a semiconductor substrate and electrically connected to a contact plug, and a dummy metal pad electrically isolated from the main metal pad and formed at a peripheral portion of the main metal pad to surround the main metal pad. | 04-30-2009 |
20090115058 | Back End Integrated WLCSP Structure without Aluminum Pads - An integrated circuit structure includes a passivation layer; a via opening in the passivation layer; a copper-containing via in the via opening; a polymer layer over the passivation layer, wherein the polymer layer comprises an aperture, and wherein the copper-containing via is exposed through the aperture; a post-passivation interconnect (PPI) line over the polymer layer, wherein the PPI line extends into the aperture and physically contacts the copper-via opening; and an under-bump metallurgy (UBM) over and electrically connected to the PPI line. | 05-07-2009 |
20090140423 | UNDERBUMP METALLURGY EMPLOYING SPUTTER-DEPOSITED NICKEL TITANIUM ALLOY - A a metallic adhesion layer is formed on a last level metal plate exposed in an opening of a passivation layer. A Ni—Ti alloy in which the weight percentage of Ti is from about 6.5% to about 30% is deposited by sputtering onto the metallic adhesion layer to form an underbump metallic layer. A wetting layer comprising Cu or Ag or Au is deposited on top of Ni—Ti layer by sputtering. A C4 ball is applied to a surface of the wetting layer for C4 processing. The sputter deposition of the Ni—Ti alloy offers economic and performance advantages relative to known methods in the art since the Ni—Ti alloy in the composition of the present invention is non-magnetic and easy to sputter, and the consumption of the inventive Ni—Ti alloy is limited during C4 processing. Also, Sn in the solder reacts uniformly with both Ni and Ti and the consumption of Ni—Ti by Sn solder is less than that for pure Ni. | 06-04-2009 |
20090140424 | WAFER LEVEL SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A wafer level semiconductor package includes a semiconductor chip having a circuit part. A bonding pad group is disposed in the semiconductor chip and included in the bonding pad group is a power pad that is electrically connected to the circuit part. An internal circuit pattern is disposed at a side of the bonding pad group. An additional power pad is disposed at a side of the bonding pad group, and the additional power pad is electrically connected to the circuit part. An insulation layer pattern is disposed over the semiconductor chip, and the insulation layer includes openings that expose the power pad, the internal circuit pattern, and the additional power pad. A redistribution is disposed over the insulation layer pattern, and the redistribution is electrically connected to at least two of the power pad, the internal circuit pattern, and the additional power pad. | 06-04-2009 |
20090140425 | Chip Package - The present provides the improved structure of a chip package, comprising an electrical contact surface of at least a chip configured with a under fill layer, the first solder mask layer, the first metal layer, dielectric material layer, the second metal layer, the second solder mask layer, and metal ball layer, characterized in the electrical contact surfaces among the first metal layer, the second metal layer, and the chip accomplish the electrical connection by employing the contacts of the surfaces of the conducting layers | 06-04-2009 |
20090146299 | SEMICONDUCTOR PACKAGE AND METHOD THEREOF - A ball grid array (BGA) structure package includes: a circuit board including a top surface and a bottom surface, and the top surface includes a patterned metal point disposed thereon and the bottom surface includes a metal point corresponding to the patterned conductive point; a semiconductor die includes an active surface, and the active surface includes a plurality of pads disposed thereon and the pads is electrically connected to the patterned metal point; a package body used to encapsulate the semiconductor die and the top surface of the circuit board; and a plurality of conductive elements electrically connected to the bottom surface of the circuit board. | 06-11-2009 |
20090146300 | Semiconductor packages and electronic products employing the same - Example embodiments of a semiconductor package are provided. In accordance with an example embodiment, a semiconductor package may include an external terminal connected to a concave surface of a bottom pad, wherein the bottom pad is recessed into a substrate. In accordance with another example embodiment, a semiconductor package may include at least one external terminal, a flexible substrate having a first surface with a plurality of convex portions and a second surface opposite the first surface having a plurality of concave portions, wherein the at least one terminal is recessed into the substrate and at least one of the concave portions surrounds a portion of the at least one external terminal. | 06-11-2009 |
20090146301 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode | 06-11-2009 |
20090152717 | METHOD OF FORMING STACKED DIE PACKAGE - A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer. An electrical distribution layer is formed over the active side of the first IC and the conductive layer and conductive balls are attached to the electrical distribution layer. The conductive balls allow electrical interconnection to the first and second integrated circuits. | 06-18-2009 |
20090152718 | STRUCTURE WITH DIE PAD PATTERN - A structure includes a semiconductor die that has an arrangement of die pads on a surface of the semiconductor die. A first row of die pads consists of a first group of four die pads and run in a first direction. A second row of die pads are adjacent to the first row and consist of a second group of four die pads running in the first direction. The second row begins at a first offset in the first direction from where the first row begins. A third row of die pads are adjacent to the second row and comprise a third group of four die pads that run in the first direction. The third row begins at a second offset in the first direction from where the second row begins. This allows for relatively easy access to all of the die pads. | 06-18-2009 |
20090152719 | METHODS OF FLUXLESS MICRO-PIERCING OF SOLDER BALLS, AND RESULTING DEVICES - A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate. | 06-18-2009 |
20090152720 | MULTILAYER CHIP SCALE PACKAGE - A resin coated copper foil is used to fabricate a multilayer Chip Scale Package (CSP). A CSP package base has a first electrical routing layer. A resin coated copper foil is hot pressed onto the CSP package base and then patterned to form a second electrical routing layer. Conductive vias are then formed between the electrical routing layers. An Organic Solder Preservative (OSP) is used a surface finish for solder balls of the CSP. | 06-18-2009 |
20090152721 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer. | 06-18-2009 |
20090160052 | UNDER BUMP METALLURGY STRUCTURE OF SEMICONDUCTOR DEVICE PACKAGE - The under bump metallization (UBM) structure of semiconductor device comprises a substrate having a bonding pad disposed on an active surface; a UBM adhered on the bonding pad, wherein the UBM includes lateral embedded portions and the size of the UBM is larger than the size of the bonding pad; a dielectric layer over the UBM having opening that is smaller than the size of the UBM so as to allow the lateral embedded portions being embedded into the dielectric layer with a desired dimension; and a conductive ball melted on the UBM within the opening defined by the dielectric layer. | 06-25-2009 |
20090160053 | METHOD OF MANUFACTURING A SEMICONDUCOTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips. | 06-25-2009 |
20090166862 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulation layer that is formed on the wafer and has an exposure hole exposing the electrode pad; a redistribution layer that is formed on the insulation layer and the exposure hole of the insulation layer and has one end connected to the electrode pad; a conductive post that is formed at the other end of the redistribution layer; an encapsulation layer that is formed on the redistribution layer and the insulation layer such that the upper end portion of the conductive post is exposed; and a solder bump that is formed on the exposed upper portion of the conducive post. | 07-02-2009 |
20090166863 | Semiconductor device and method of manufacturing the same - A semiconductor-device manufacturing method includes: forming terminals on a wafer and across each of dicing lines along which the wafer is cut into a plurality of semiconductor chips; preparing a plurality of pre-cut substrates each including a substrate body capable of being cut along corresponding one of cutting lines into a pair of same structured substrate pieces, connection pads provided on a top surface of the substrate body, and external terminals formed on a bottom surface of the substrate body and connected to the connection pads; mounting the pre-cut substrates onto the wafer while the cutting lines of the pre-cut substrates match the dicing lines; and simultaneously dicing the wafer and the pre-cut substrates along the dicing lines matching the cutting lines. | 07-02-2009 |
20090174072 | SEMICONDUCTOR SYSTEM HAVING BGA PACKAGE WITH RADIALLY BALL-DEPOPULATED SUBSTRATE ZONES AND BOARD WITH RADIAL VIA ZONES - A printed circuit board has contact lands ( | 07-09-2009 |
20090174073 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE HAVING COATING FILM AND METHOD FOR MANUFACTURING THE SAME - A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the 1o ball land. The coating film includes a high molecular compound having metal particles. In the substrate having the ball land with the coating film formed thereon, it is not necessary to subject the substrate to a UBM formation process. | 07-09-2009 |
20090174074 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device exhibiting an improved reliability of a bump coupling section. A semiconductor device is provided, which comprises: an interconnect layer; a stress-relaxing layer, covering the interconnect layer and provided with an opening exposing at least a portion of the interconnect layer; a post, covering the opening and provided so as to overlap with the stress-relaxing layer disposed around the opening; and a resin layer, provided around the post to cover the stress-relaxing layer, wherein a value of 2A/C is within a range of from 0.1 to 0.5, wherein C is a diameter of the post and 2A is a width of an overlapping region of the stress-relaxing layer with the post. | 07-09-2009 |
20090184420 | Post bump and method of forming the same - A post bump and a method of forming the post bump are disclosed. The method of forming the post bump can include: forming a resist layer, in which an aperture is formed in correspondence to a position of an electrode pad, over a substrate, on which the electrode pad is formed; forming a metal post by filling a part of the aperture with a metallic material; filling a remaining part of the aperture with solder; reflowing the solder by applying heat; and removing the resist layer. This method can be utilized to prevent deviations in the plated solder and prevent the unnecessary flowing of the solder over the sides of the metal post during reflowing, so that the amount of solder used can be minimized. | 07-23-2009 |
20090194872 | DEPOPULATING INTEGRATED CIRCUIT PACKAGE BALL LOCATIONS TO ENABLE IMPROVED EDGE CLEARANCE IN SHIPPING TRAY - Methods, systems, and apparatuses for integrated circuit packages, transport containers, and for transporting integrated circuit packages are provided. A transport container for an integrated circuit package includes a body and a plurality of mounting features. The body has a surface that includes a package receiving region. The plurality of mounting features is positioned in the package receiving region. A first mounting feature is positioned on a first inner surface of the package receiving region and a second mounting feature is positioned on a second inner surface of the package receiving region. The package receiving region is configured to receive an integrated circuit package such that the received package is supported by the plurality of mounting features. The first and second mounting features coincide with respective spaces in first and second edges of an array of solder balls on a surface of the package. | 08-06-2009 |
20090194873 | INTEGRATED CIRCUIT DEVICE AND A METHOD OF MAKING THE INTEGRATED CIRCUIT DEVICE - An integrated circuit device comprises a first semiconductor chip on a first substrate and a second semiconductor chip on a second substrate. A side surface of the first semiconductor chip is facing a side surface of the second semiconductor chip. At least one electric cable is provided to be connecting the first substrate to the second substrate. | 08-06-2009 |
20090194874 | SEMICONDUCTOR CHIP PACKAGE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor chip package and a method for manufacturing thereof includes sequentially forming upper dielectric layer patterns and lower dielectric patterns over a substrate to expose an underlying metal line such that the lower dielectric layer patterns overlap the metal line, positioning a solder ball over and contacting the lower dielectric layer patterns such that the solder ball does not contact the metal line, and then placing the solder ball in a contacting position over the metal line by performing an etching process on the lower dielectric layer patterns. Therefore, no cracks occur on the chip pads so that there is no concern of short phenomenon generated in the terminal. | 08-06-2009 |
20090200666 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device is provided which comprises a semiconductor chip having wire bonding pads and a package encapsulating the semiconductor chip and connected via bonding wires to the wire bonding pads, wherein wire bonding pads on the semiconductor chip are arranged in two rows in a staggered manner along a periphery of the semiconductor chip, and of the wire bonding pads, power supply pads are arranged in a rear row located close to a semiconductor integrated circuit unit as an active area on the semiconductor chip and in a front row, only signal pads are arranged. Because the power supply pads are provided in the rear row, the line width of a power supply line led out from each power supply pad can be made equal to the width of the pad, thus reducing the impedance of the connection circuit between the semiconductor chip and the package, and suppressing generation of radiation noise, ground bounce and so on. | 08-13-2009 |
20090206479 | SOLDER INTERCONNECT PADS WITH CURRENT SPREADING LAYERS - Structure and methods of making the structures. The structures include a structure, comprising: an organic dielectric passivation layer extending over a substrate; an electrically conductive current spreading pad on a top surface of the organic dielectric passivation layer; an electrically conductive solder bump pad comprising one or more layers on a top surface of the current spreading pad; and an electrically conductive solder bump containing tin, the solder bump on a top surface of the solder bump pad, the current spreading pad comprising one or more layers, at least one of the one or more layers consisting of a material that will not form an intermetallic with tin or at least one of the one or more layers is a material that is a diffusion barrier to tin and adjacent to the solder bump pad. | 08-20-2009 |
20090206480 | FABRICATING LOW COST SOLDER BUMPS ON INTEGRATED CIRCUIT WAFERS - A low cost method of forming solder bumps on an integrated circuit (IC) wafer includes depositing solder directly onto stud bumps formed on bond pads of the IC wafer. In some implementations, stud bumps are formed on the IC wafer by performing wire ball-bonding onto metal bond pads of the wafer. Photodefinable solder mask material is applied to the wafer and cured. The photodefinable solder mask material is exposed to form open solder mask areas at the metal bond pad areas. Solder paste is applied into the open solder mask areas. Reflowing the solder paste on the wafer forms solder bumps that wet to the stud bumps. The solder mask is then stripped from the wafer. Other processes (e.g., a wave-soldering machine, stencil or screen printing process) can also be used to wet solder onto stud bumps to form solder bumps. | 08-20-2009 |
20090206481 | STACKING OF TRANSFER CARRIERS WITH APERTURE ARRAYS AS INTERCONNECTION JOINTS - An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads. | 08-20-2009 |
20090212428 | RE-DISTRIBUTION CONDUCTIVE LINE STRUCTURE AND THE METHOD OF FORMING THE SAME - A conductive line structure of a semiconductor device, the structure comprising a substrate having bonding pad; a first dielectric layer formed over the substrate; a solder pad formed over the first dielectric layer; a buffer scheme formed over the first dielectric layer and between the bonding pad and the solder pad; a conductive line formed over the buffer scheme for coupling between the bonding pad and the solder pad; a second dielectric layer formed over the conductive line to expose the solder pad; and a solder ball formed over the solder pad. | 08-27-2009 |
20090212429 | Semiconductor Device and Method of Supporting a Wafer During Backgrinding and Reflow of Solder Bumps - A semiconductor device is made by providing a semiconductor wafer having an active surface, forming an under bump metallization layer on the active surface of the semiconductor wafer, forming a first photosensitive layer on the active surface of the semiconductor wafer, exposing a selected portion of the first photosensitive layer over the under bump metallization layer to light, removing a portion of a backside of the semiconductor wafer, opposite to the active surface, prior to developing the exposed portion of the first photosensitive layer, developing the exposed portion of the first photosensitive layer after removing the portion of the backside of the semiconductor wafer, and depositing solder material over the under bump metallization layer to form solder bumps. The remaining portion of the first photosensitive layer is then removed. A second photosensitive layer or metal stencil can be formed over the first photosensitive layer. | 08-27-2009 |
20090218688 | OPTIMIZED PASSIVATION SLOPE FOR SOLDER CONNECTIONS - A semiconductor structure includes at least one bond pad. An insulator layer is on the surface of the semiconductor chip and on a portion of the bond pad. The polyimide layer comprises a bottom surface contacting and coplanar with the surface of the semiconductor chip, a top surface opposite and parallel to the bottom surface of the polyimide layer, and a sloped side between corresponding ends of the top surface of the polyimide layer and the bottom surface of the polyimide layer. The sloped side joins the bottom surface of the polyimide layer at the top surface of the bond pad. The sloped side of the polyimide layer forms an angle less than 50° with the bottom surface of the polyimide layer. | 09-03-2009 |
20090218689 | FLIP CHIP SEMICONDUCTOR ASSEMBLY WITH VARIABLE VOLUME SOLDER BUMPS - A method of manufacturing a semiconductor chip is disclosed. A die having a plurality of die-pads is attached to a substrate in a semiconductor package which includes a plurality of substrate-pads. The method involves forming conductive column bumps of differing volumes extending from the die-pads; attaching each of the column bumps to a corresponding substrate-pad to form a subassembly; and reflowing the subassembly so that the column bumps form robust electrical and mechanical connections between the die pads and the substrate pads. | 09-03-2009 |
20090224402 | Semiconductor Package Having Semiconductor Die with Internal Vertical Interconnect Structure and Method Therefor - A semiconductor wafer is made by forming a first conductive layer over a sacrificial substrate, mounting a semiconductor die to the sacrificial substrate, depositing an insulating layer over the semiconductor die and first conductive layer, exposing the first conductive layer and contact pad on the semiconductor die, forming a second conductive layer over the insulating layer between the first conductive layer and contact pad, forming solder bumps on the second conductive layer, depositing an encapsulant over the semiconductor die, first conductive layer, and interconnect structure, and removing the sacrificial substrate after forming the encapsulant to expose the conductive layer and semiconductor die. A portion of the encapsulant is removed to expose a portion of the solder bumps. The solder bumps are sized so that each extends the same outside the encapsulant. The semiconductor die are stacked by electrically connecting the solder bumps. | 09-10-2009 |
20090230553 | SEMICONDUCTOR DEVICE INCLUDING ADHESIVE COVERED ELEMENT - A semiconductor device includes a chip, at least one element electrically coupled to the chip, an adhesive at least partially covering the at least one element, and a mold material at least partially covering the chip and the adhesive. | 09-17-2009 |
20090230554 | WAFER-LEVEL REDISTRIBUTION PACKAGING WITH DIE-CONTAINING OPENINGS - Methods, systems, and apparatuses for integrated circuit packages, and processes for forming the same, are provided. In one example, an integrated circuit (IC) package includes a thick film material that forms a opening, a die, an insulating material, a redistribution interconnect on the insulating material, and a ball interconnect. The die is positioned in the opening. The insulating material covers the die and a surface of the thick film material, and fills a space adjacent to the die in the opening. The redistribution interconnect is formed on the insulating material. The redistribution interconnect has a first portion coupled to a terminal of the die through the layer of the insulating material, and a second portion that extends away from the first portion over the insulating material filling the space adjacent to the die in the opening. The ball interconnect is coupled to the second portion of the redistribution interconnect. | 09-17-2009 |
20090243098 | UNDERBUMP METALLURGY FOR ENHANCED ELECTROMIGRATION RESISTANCE - A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball. | 10-01-2009 |
20090243099 | WINDOW TYPE BGA SEMICONDUCTOR PACKAGE AND ITS SUBSTRATE - A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections. | 10-01-2009 |
20090243100 | Methods to Form a Three-Dimensionally Curved Pad in a Substrate and Integrated Circuits Incorporating such a Substrate - Methods to form a three-dimensionally curved pad in a substrate and integrated circuits incorporating such a substrate are disclosed. An example method to form a three-dimensionally curved pad comprises isotropically etching a portion of a surface of a substrate to form a recess having a radial shape, forming a conductive layer in the recess to form the bonding pad, and placing a conductive element in the pad. | 10-01-2009 |
20090250814 | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof - A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump. | 10-08-2009 |
20090256255 | COMPOSITE INTERCONNECT - A composite interconnect system includes a plurality of carbon nanotubes, a plurality of solder balls and standoff balls disposed on a first device to provide a connection to a second device. A die-attached substrate includes a substrate and one or more die disposed on the substrate by a die-attach composite interconnect. The die-attach composite interconnect includes a plurality of carbon nanotubes, solder bumps, and standoff balls disposed on the die to provide one or more connections to the substrate. A PCB-attached substrate package includes a substrate package and one or more die disposed on the substrate package. The substrate package is disposed on a PCB by a PCB-attach composite interconnect. The PCB-attach composite interconnect includes a plurality of carbon nanotubes, solder balls, and standoff balls disposed on the substrate package to provide one or more connections to the PCB. | 10-15-2009 |
20090256256 | Electronic Device and Method of Manufacturing Same - This application relates to a semiconductor device comprising an array of contact elements soldered to only one surface, wherein the array defines a predetermined pitch length, wherein the contact elements comprise a spherically shaped element and wherein the contact elements protrude from the only one surface by more than 60 percent of the predetermined pitch. | 10-15-2009 |
20090256257 | FINAL VIA STRUCTURES FOR BOND PAD-SOLDER BALL INTERCONNECTIONS - A structure and a method for forming the same. The structure includes a first dielectric layer, an electrically conductive bond pad on the first dielectric layer, and a second dielectric layer on top of the first dielectric layer and the electrically conductive bond pad. The electrically conductive bond pad is sandwiched between the first and second dielectric layers. The second dielectric layer includes N separate final via openings such that a top surface of the electrically conductive bond pad is exposed to a surrounding ambient through each final via opening of the N separate final via openings. N is a positive integer greater than 1. | 10-15-2009 |
20090261473 | Low fabrication cost, fine pitch and high reliability solder bump - A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention. | 10-22-2009 |
20090261474 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF - In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability. | 10-22-2009 |
20090273081 | PAD CUSHION STRUCTURE AND METHOD OF FABRICATION FOR Pb-FREE C4 INTEGRATED CIRCUIT CHIP JOINING - A controlled collapse chip connection (C4) method and integrated circuit structure for lead (Pb)-free solder balls with stress relief to the underlying insulating layers of the integrated circuit chip by deposing soft thick insulating cushions beneath the solder balls and connecting the metallization of the integrated circuit out-of-contact of the cushions but within the pitch of the solder balls. | 11-05-2009 |
20090278256 | SEMICONDUCTOR PACKAGE ENHANCING VARIATION OF MOVABILITY AT BALL TERMINALS - A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop. The stepwise depression can accommodate the die-attaching material to control bleeding contaminations. | 11-12-2009 |
20090289362 | Low Inductance Ball Grid Array Device Having Chip Bumps on Substrate Vias - A high-frequency BGA device ( | 11-26-2009 |
20090289363 | Fine-Pitch Ball Grid Array Package Design - In one aspect, a method for configuring a ball grid array is disclosed. The method may include identifying a number of balls for use in a ball grid array, determining a number of rows and a number of columns for the ball grid array, and populating the ball grid array at least in part with a plurality of ball-space groupings. The method may also include allocating an unpopulated portion of an area bounded by the at least one first outside row, the at least one second outside row, the at least one first outside column, and the at least one second outside column, to be free of balls. The method may also include routing a signal line from a ball of at least one ball-space grouping to a space of the at least one ball-space grouping and routing the signal line to a substrate layer through a via. | 11-26-2009 |
20090289364 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface. | 11-26-2009 |
20090294961 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip and a metal layer electrically coupled to the semiconductor chip. The semiconductor device includes an array of solder balls coupled to the metal layer and a front side protect material directly contacting the metal layer and laterally surrounding a portion of at least a plurality of solder balls. The front side protect material is configured to become fluid during solder reflow. | 12-03-2009 |
20090294962 | PACKAGING SUBSTRATE AND METHOD FOR FABRICATING THE SAME - A packaging substrate and a method for fabricating the same are proposed, including: providing a substrate body having a first surface and an opposing second surface, wherein the first surface has a plurality of flip-chip solder pads and wire bonding pads and the second surface has a plurality of solder ball pads; forming a first and a second solder mask layers on the first and second surfaces respectively and forming openings in the first and second solder mask layers to expose the flip-chip solder pads, the wire bonding pads and the solder ball pads; forming first bumps on the flip-chip solder pads; and forming an electroless Ni/Pd/Au layer on the first bumps and the wire bonding pads by electroless plating, wherein the electroless Ni/Pd/Au layer has a thickness tolerance capable of meeting evenness requirements for fine pitch applications. | 12-03-2009 |
20090302468 | Printed circuit board comprising semiconductor chip and method of manufacturing the same - Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip. | 12-10-2009 |
20090302469 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - A semiconductor device which includes a first semiconductor chip | 12-10-2009 |
20090309219 | INJECTION MOLDED SOLDER BALL METHOD - Methods for making solder balls, which can be used to bump semiconductor wafers are disclosed. Methods for bumping semiconductor wafers with the solder balls are also disclosed. The solder balls can be made using an injection molded soldering (IMS) process. | 12-17-2009 |
20090321928 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 12-31-2009 |
20090321929 | Standing chip scale package - A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed. | 12-31-2009 |
20100013094 | SEMICONDUCTOR PACKAGE AND METHODS OF MANUFACTURING THE SAME - A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy. | 01-21-2010 |
20100019384 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 01-28-2010 |
20100025848 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device and semiconductor device is provided. The method provides a first layer. The first layer includes through-holes. At least one semiconductor chip is provided. The semiconductor chip includes contact elements. The semiconductor chip is placed onto the first layer with the contact elements being aligned with the through-holes. An encapsulant material is applied over the semiconductor chip. | 02-04-2010 |
20100025849 | COPPER ON ORGANIC SOLDERABILITY PRESERVATIVE (OSP) INTERCONNECT AND ENHANCED WIRE BONDING PROCESS - A semiconductor package and a method for constructing the package are disclosed. The package includes a substrate and a die attached thereto. A first contact region is disposed on the substrate and a second contact region is disposed on the die. The first contact region, for example, comprises copper coated with an OSP material. A copper wire bond electrically couples the first and second contact regions. Wire bonding includes forming a ball bump on the first contact region having a flat top surface. Providing the flat top surface is achieved with a smoothing process. A ball bond is formed on the second contact region, followed by stitching the wire onto the flat top surface of the ball bump on the first contact region. | 02-04-2010 |
20100032835 | COMBINATION VIA AND PAD STRUCTURE FOR IMPROVED SOLDER BUMP ELECTROMIGRATION CHARACTERISTICS - The invention generally relates to semiconductor devices, and more particularly to structures and methods for enhancing electromigration (EM) performance in solder bumps and related structures. A semiconductor structure includes a wire comprising first and second wire segments, a pad formed over the wire, and a ball limiting metallization (BLM) layer formed over the pad. The semiconductor structure also includes a solder bump formed over the BLM layer, a terminal via formed over the BLM layer, and at least one peripheral via formed between the second wire segment and the pad. The first and second wire segments are discrete wire segments. | 02-11-2010 |
20100032836 | ENHANCED RELIABILITY FOR SEMICONDUCTOR DEVICES USING DIELECTRIC ENCASEMENT - A method and device for enhanced reliability for semiconductor devices using dielectric encasement is disclosed. The method and device are directed to improving the reliability of the solder joint that connects the integrated circuit (IC) chip to the substrate. The method comprises applying a layer of a photoimageable permanent dielectric material to a top surface of the semiconductor device, and patterning the layer of the photoimageable permanent dielectric material to have an opening over each feature. The method further comprises dispensing or stencil printing fluxing material into the permanent dielectric material openings, and applying solder, which contains no flux, to a top surface of the fluxing material. In one or more embodiments, the method further comprises heating the semiconductor device to a reflow temperature appropriate for the reflow of the solder, thereby causing the solder to conform to sidewalls of the permanent dielectric material openings to form a protective seal. | 02-11-2010 |
20100038780 | UNDERFILL FLOW GUIDE STRUCTURES AND METHOD OF USING SAME - Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes. | 02-18-2010 |
20100038781 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity. | 02-18-2010 |
20100044861 | SEMICONDUCTOR DIE SUPPORT IN AN OFFSET DIE STACK - A semiconductor device is disclosed including a support structure for supporting an edge of a semiconductor die that is not supported on the substrate or semiconductor die below. In embodiments, the semiconductor device may in general include a substrate having a plurality of contact pads, a first semiconductor die mounted on the substrate, and a second semiconductor die mounted on the first semiconductor die in an offset configuration so that an edge of the second semiconductor die overhangs the first semiconductor die. A support structure may be affixed to one or more of the contact pads beneath the overhanging edge to support the overhanging edge during a wire bonding process which exerts a downward force on the overhanging edge. | 02-25-2010 |
20100044862 | METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR SUBSTRATE - A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate. | 02-25-2010 |
20100044863 | Semiconductor device - An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad. | 02-25-2010 |
20100052164 | Wafer level package and method of manufacturing the same - The present invention relates to a wafer level package and a method of manufacturing the same and provides a wafer level package structure including a wafer having a die pad; a redistribution line formed to be connected on a top surface of the die pad; a metal post connected to a top surface of the redistribution line and formed in a flexure hinge structure; and a molding resin formed between the metal posts. | 03-04-2010 |
20100052165 | SEMICONDUCTOR DEVICE INCLUDING COLUMNAR ELECTRODES HAVING PLANAR SIZE GREATER THAN THAT OF CONNECTION PAD PORTION OF WIRING LINE, AND MANUFACTURING METHOD THEREOF - A plurality of wiring lines are provided on a first protective film, a second protective film having an opening in a part corresponding to a connection pad portion of a wring line is provided on the first protective film including the wiring line, a columnar electrode is provided on the upper surface of the connection pad portion of the wring line exposed via the opening in the second protective film and on the second protective film around the connection pad portion. | 03-04-2010 |
20100059883 | METHOD OF FORMING BALL BOND - A method of forming a ball bond ( | 03-11-2010 |
20100059884 | LEADLESS SEMICONDUCTOR CHIP CARRIER SYSTEM - A semiconductor package system includes: providing a semiconductor die with bonding pad on the semiconductor die; attaching the semiconductor die to an intermediate layer; attaching one end of a bonding wire to the bonding pad; forming a bonding ball at the other end of the bonding wire, the bonding ball being fully or partially embedded in the intermediate layer; encapsulating the semiconductor die, the bonding pad, the bonding wire, and a portion of the bonding ball with a mold compound; removing the intermediate layer, resulting in the bonding ball protruding from the exposed mold compound bottom surface; and conditioning the bonding ball | 03-11-2010 |
20100059885 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER - An integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate. | 03-11-2010 |
20100059886 | Carrier structure of SoC with custom interface - The present invention discloses a carrier structure of a System-on-Chip (SoC) with a custom interface. The carrier structure includes a substrate, at least one common die, at least one custom interface and a molding compound. The common die and the custom interface are disposed on the substrate. The molding compound is used to package the common die which electrically connects to the substrate and the custom interface respectively. The carrier structure which includes the common die can form a complete SoC by connecting to an expansive die through the custom interface. The carrier structure with the common die which can be tested and certified in advance allows reducing and simplifying the developing procedures of the SoC. | 03-11-2010 |
20100072618 | Semiconductor Device and Method of Forming a Wafer Level Package with Bump Interconnection - A semiconductor device is made by providing a metal substrate for supporting the semiconductor device. Solder bumps are connected to the substrate. In one embodiment, a conductive material is deposited over the substrate and is reflowed to form the solder bumps. A semiconductor die is mounted to the substrate using a die attach adhesive. The semiconductor die has a plurality of contact pads formed over a surface of the semiconductor die. An encapsulant material is deposited over the solder bumps and the semiconductor die. The encapsulant is etched to expose the contact pads of the semiconductor die. A first redistribution layer (RDL) is formed over the encapsulant to connect each contact pad of the semiconductor die to one of the solder bumps. The substrate is removed to expose the die attach adhesive and a bottom surface of the solder bumps. | 03-25-2010 |
20100072619 | WIRE BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention relates to a wire bonding structure, and more particularly to a manufacturing method for said wire bonding structure. The wire bonding structure comprises a die that connects with a lead via a bonding wire. At least one bond pad is positioned on an active surface of the die, and a gold bump is provided on the bond pad; furthermore, a ball bond can be positioned upon the gold bump. The bond pad and the gold bump can separate the ball bond and the die, which can avoid damaging the die during the bonding process. | 03-25-2010 |
20100078811 | METHOD OF PRODUCING SEMICONDUCTOR DEVICES - A method of producing semiconductor devices. One embodiment provides producing at least two semiconductor chips. An encapsulation material is applied to the at least two semiconductor chips to form an encapsulation layer. The at least two semiconductor chips are separated from each other to obtain at least two separated semiconductor devices. The outline of each one of the semiconductor devices includes three corners in total or more than four corners. | 04-01-2010 |
20100078812 | WINDOW BGA SEMICONDUCTOR PACKAGE - A WBGA semiconductor package primarily comprises a substrate, a chip, a chip-bonding adhesive, a plurality of bonding wires electrically connecting the chip and the substrate, an encapsulant to encapsulate the chip and the bonding wires, and a plurality of external terminals disposed under the substrate. The substrate has a depression for accommodating the chip-bonding adhesive and a slot for passing through bonding wires. The chip is partially embedded in the depression to dispose on the substrate. During the chip bonding step, the chip-bonding adhesive is confined in the depression in a manner to fill the gaps between the sides of the first chip and the inwalls around the depression to generate a non-planar adhering interface by partially covering the sides of the first chip. Therefore, the total package thickness is reduced, the delamination of the passivation layer and the fractures at the sides of the chip are avoided. | 04-01-2010 |
20100078813 | SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR MODULE - A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating layer, and a bump electrode which is electrically connected to the wiring layer and protruded from the wiring layer in an insulating layer side. The semiconductor device has device electrodes disposed counter to the semiconductor substrate and the bump electrodes, respectively. The surface of a metallic layer provided on the device electrode has a rugged shape, resulting in the improved adhesion between the metallic layer and the insulating resin layer. | 04-01-2010 |
20100084765 | Semiconductor package having bump ball - Disclosed is a semiconductor package having a bump ball as an external connection terminal, the bump ball including a core layer containing copper, a copper alloy, aluminum, an aluminum alloy or a combination thereof and a shell layer surrounding the core layer and containing tin, a tin alloy or a combination thereof. | 04-08-2010 |
20100090339 | Structures and Methods for Wafer Packages, and Probes - This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer. | 04-15-2010 |
20100096750 | Packaging substrate - A packaging substrate is disclosed, which comprises: a substrate body, wherein a surface thereof has a plurality of conductive pads and a solder mask disposed on the surface and having a plurality of openings to expose the conductive pads; dielectric rings disposed on the inner walls of the openings and extending to parts of the surface of the solder mask surrounding the openings; and metal bumps disposed in the openings and on the conductive pads exposed thereby, and combined with the dielectric rings. | 04-22-2010 |
20100096751 | SEMICONDUCTOR DEVICE - A semiconductor device, includes: an organic multilayer wiring substrate having an inner conductive layer; a semiconductor element mounted and connected on one surface of the wiring substrate; and a plurality of solder balls disposed on the other surface in a grid array. A defect portion is formed at an area corresponding to a corner solder ball disposed at an outer peripheral corner, or at an area corresponding to the corner solder ball and peripheral solder balls at the inner conductive layer. Temperature rises of the solder balls disposed in a vicinity of the corner are suppressed, and therefore, the semiconductor device of which fatigue life is prolonged and superior in reliability can be obtained. | 04-22-2010 |
20100096752 | SEMICONDUCTOR DEVICE - A semiconductor device according to an aspect of the present invention comprises a package board having first and second surfaces, first external terminals on the first surface which are arranged in matrix, and second external terminals on the first surface which are arranged apart from the first external terminals. Each of the second external terminals includes first and second through holes which extend from the first surface to the second surface, and a metal layer on the first surface which is provided between the first and second through holes. The metal layer passes through the first and second through holes to the second surface. | 04-22-2010 |
20100096753 | THROUGH-SILICON VIA STRUCTURES PROVIDING REDUCED SOLDER SPREADING AND METHODS OF FABRICATING THE SAME - A microelectronic device structure as provided herein includes a conductive via having a body portion extending into a substrate from an upper surface thereof and a connecting portion laterally extending along the upper surface of the substrate. The connecting portion includes a recess therein opposite the upper surface of the substrate. The recess is confined within the connecting portion of the conductive via and does not extend beneath the upper surface of the substrate. A microelectronic device structure is also provided that includes a conductive via having a body portion extending into a substrate from an upper surface thereof and an end portion below the upper surface of the substrate. The end portion has a greater width than that of the body portion. A solder wettable layer is provided on the end portion. The solder wettable layer is formed of a material having a greater wettability with a conductive metal than that of the end portion of conductive via. Related methods of fabrication are also discussed. | 04-22-2010 |
20100096754 | Semiconductor package, semiconductor module, and method for fabricating the semiconductor package - Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line. | 04-22-2010 |
20100102446 | SEMICONDUCTOR ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE USING THE SAME - The problem of the present invention is to provide a chip-on-chip type semiconductor electronic component and a semiconductor device which can meet the requirements for further density increase of semiconductor integrated circuits. | 04-29-2010 |
20100102447 | Substrate of window ball grid array package and method for making the same - The present invention relates to a substrate of a window ball grid array package and a method for making the same. The substrate includes a core layer, a first conductive layer, a second conductive layer, at least one window and at least one via. The window includes a first through hole and a third conductive layer. The first through hole penetrates the substrate and has a first sidewall. The third conductive layer is disposed on the first sidewall and connects the first conductive layer and the second conductive layer. The via includes a second through hole and a fourth conductive layer. The second through hole penetrates the substrate and has a second sidewall. The fourth conductive layer is disposed on the second sidewall and connects the first conductive layer and the second conductive layer. As a result, the substrate has the effect of controlling the characteristic impedance and increasing the signal integrity. | 04-29-2010 |
20100117228 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device has an element interconnection | 05-13-2010 |
20100117229 | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same - The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device. | 05-13-2010 |
20100117230 | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof - A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump. | 05-13-2010 |
20100117231 | RELIABLE WAFER-LEVEL CHIP-SCALE SOLDER BUMP STRUCTURE - A wafer level chip scale package (WLCSP) includes a semiconductor device with a plurality of solder bump pads, patterned passivation regions above each of the solder bump pads, a patterned under bump metallization (UBM) region on each of the solder bump pads and the passivation regions, a polyimide region over a portion of the UBM regions and the passivation regions, solder bumps formed on each of the UBM regions. | 05-13-2010 |
20100123246 | Double Solid Metal Pad with Reduced Area - An integrated circuit structure includes a bond pad; an Mtop pad located directly underlying the bond pad; an Mtop-1 pad having at least a portion directly underlying the Mtop pad, wherein at least one of the Mtop pad and the Mtop-1 pad has a horizontal dimension smaller than a horizontal dimension of the bond pad; a plurality of vias interconnecting the Mtop pad and the Mtop-1 pad; and a bond ball on the bond pad. Each of the Mtop pad and the Mtop-1 pad has positive enclosures to the bond ball in all horizontal directions. | 05-20-2010 |
20100123247 | BASE PACKAGE SYSTEM FOR INTEGRATED CIRCUIT PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a base package system includes: forming a substrate strip assembly including: providing a substrate strip having ball lands, mounting an integrated circuit on the substrate strip, and molding a finger structure, having a knuckle region, on the integrated circuit; and singulating a substrate from the substrate strip assembly. | 05-20-2010 |
20100133688 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). The invention of the present application provides a semiconductor integrated circuit device (semiconductor device or electron circuit device) which includes a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board or the like (wiring substrate). | 06-03-2010 |
20100140801 | Device - In a device acting as a semiconductor device, a first chip has a first protective layer pattern while a second chip has a second protective layer pattern which is two-dimensionally symmetrical with the first protective layer pattern to provide a reflection symmetrical relationship between the first and the second protective layer patterns. When the first and the second chips form a back-to-back structure, both the first and the second protective layer patterns are completely superposed with each other. | 06-10-2010 |
20100148363 | STEP CAVITY FOR ENHANCED DROP TEST PERFORMANCE IN BALL GRID ARRAY PACKAGE - A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls. | 06-17-2010 |
20100148364 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate having an external electrode formed thereon, the external electrode being capable of being electrically connected to an outside; and a semiconductor element having a surface electrode formed thereon, the surface electrode being made from an electrically conducting paste, the semiconductor element being mounted on the substrate, the external electrode being electrically connected by wire bonding to the surface electrode via a connecting member. This provides (i) a semiconductor device including: a substrate having an external electrode capable of being electrically connected to an outside; and a semiconductor element having a surface electrode made from an electrically conducting paste, the semiconductor device allowing for assured bonding reliability and a simplified means or step of connecting the surface electrode to the external electrode, and (ii) a method for producing the semiconductor device. | 06-17-2010 |
20100148365 | GRID ARRAY CONNECTION DEVICE AND METHOD - A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as hardness and abrasion resistance. Land grid array structures are provided that are less expensive to manufacture due to reductions in material cost such as gold. Ball grid array structures are provided with improved resistance to corrosion during fabrication. Ball grid array structures are also provided with improved mechanical properties resulting in improved shock testing results. | 06-17-2010 |
20100155946 | Solder limiting layer for integrated circuit die copper bumps - An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material. | 06-24-2010 |
20100164101 | Ball land structure having barrier pattern - Disclosed is a ball land structure suitable for use with a semiconductor package. The ball land structure includes a ball land and a barrier on a core. The barrier may be configured to connect to the ball land so as to form a barrier hole between an edge of the ball land and an edge of the barrier thus exposing a portion of the core. A solder mask may be deposited on the ball land and a portion of the core exposed by the barrier hole so as to partially expose the core. | 07-01-2010 |
20100171217 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 07-08-2010 |
20100181668 | Semiconductor Device and Electronic Apparatus Equipped with the Semiconductor Device - A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise. | 07-22-2010 |
20100187687 | Underbump Metallization Structure - A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts. | 07-29-2010 |
20100187688 | REDUCED BOTTOM ROUGHNESS OF STRESS BUFFERING ELEMENT OF A SEMICONDUCTOR COMPONENT - The present invention relates to a stress buffering package ( | 07-29-2010 |
20100187689 | SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE - An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer. | 07-29-2010 |
20100187690 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring substrate having connection pads. A first semiconductor chip is mounted on the wiring substrate. A second semiconductor chip is stacked on the first semiconductor chip in a step-like shape. Electrode pads of the first semiconductor chip are electrically connected to the connection pads of the wiring substrate via first metal wires. Electrode pads of the second semiconductor chip are electrically connected to the electrode pads of the first semiconductor chip via second metal wires. One end of the second metal wire is connected from above metal bump formed on the first electrode pad. | 07-29-2010 |
20100187691 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 07-29-2010 |
20100187692 | CHIP PACKAGE WITHOUT CORE AND STACKED CHIP PACKAGE STRUCTURE - A chip package including a base, a chip, a molding compound and a plurality of outer terminals is provided. The base is essentially consisted of a patterned circuit layer having a first surface and a second surface opposite to each other and a solder mask disposed on the second surface, wherein the solder mask has a plurality of first openings by which part of the patterned circuit layer is exposed. The chip is disposed on the first surface and is electrically connected to the patterned circuit layer. The molding compound covers the pattern circuit layer and fixes the chip onto the patterned circuit layer. The outer terminals are disposed in the first openings and electrically connected to the patterned circuit layer. | 07-29-2010 |
20100193948 | SEMICONDUCTOR DEVICE, PRINTED WIRING BOARD FOR MOUNTING THE SEMICONDUCTOR DEVICE AND CONNECTING STRUCTURE FOR THESE - The present invention relates to a connecting structure between semiconductor device | 08-05-2010 |
20100193949 | NOVEL STRUCTURE OF UBM AND SOLDER BUMPS AND METHODS OF FABRICATION - Methods and UBM structures having bilayer or trilayer UBM layers that include a thin TiW adhesion layer and a thick Ni-based barrier layer thereover both deposited under sputtering operating conditions that provide the resultant bilayer or trilayer UBM layers with minimal composite stresses. The Ni-based barrier layer may be pure Ni or a Ni alloy. These UBM layers may be patterned to fabricate bilayer or trilayer UBM capture pads, followed by joining a lead-free solder thereto for providing lead-free solder joints that maintain reliability after multiple reflows. Optionally, the top layer of the trilayer UBM structures may include soluble or insoluble metals for doping the lead-free solder connections. | 08-05-2010 |
20100193950 | WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITIONS, AND METHODS RELATING THERETO - The invention relates generally to wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography. The wafer level package comprises a stress buffer layer containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized. | 08-05-2010 |
20100200988 | GRAIN REFINEMENT BY PRECIPITATE FORMATION IN Pb-FREE ALLOYS OF TIN - Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature. | 08-12-2010 |
20100207272 | SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE ELEMENT - A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion. | 08-19-2010 |
20100207273 | Micro Ball Feeding Method - Provided is a feeding method for feeding conductive balls to the insides of through holes of a mask reliably and efficiently so as to match a fine pitch. In the feeding method, a head ( | 08-19-2010 |
20100213611 | SEMICONDUCTOR DEVICE - A semiconductor device of the invention includes a first wiring layer including a signal wiring line formed therein, and a second wiring layer stacked on the first wiring layer and including a power-supply plane and/or ground plane formed therein, the power-supply plane or the ground plane is not formed at least within a part of the region of the second wiring layer facing the signal wiring line of the first wiring layer. | 08-26-2010 |
20100237498 | PACKAGE FOR SEMICONDUCTOR DEVICE AND PACKAGING METHOD THEREOF - A semiconductor device package and a method thereof are able to reliably package a semiconductor device on a substrate without using flux. The semiconductor device package includes a semiconductor device and a substrate reciprocally disposed with respect to the semiconductor device, wherein the substrate includes a side reciprocal to the semiconductor device on which there are formed a plurality of prominences surrounding an accommodation region where the semiconductor device is to be disposed. The method of packaging a semiconductor device includes preparing the semiconductor device, preparing a substrate, forming a plurality of prominences to surround an accommodation region on the substrate where the semiconductor device is to be disposed, dropping the semiconductor device within the accommodation region, and packaging the semiconductor device on the substrate. | 09-23-2010 |
20100244246 | ELECTRONIC COMPONENT WITH MECHANICALLY DECOUPLED BALL CONNECTIONS - An electronic component including at least one chip and/or one support, the chip configured to be transferred onto the support and linked, at a level of at least one connection site of the chip, formed by at least one portion of a layer of the chip, to at least one connection site of the support formed by at least one portion of a layer of the support, by at least one ball, the chip and/or the support including a mechanism for mechanical decoupling of the connection site of the chip and/or of the support with respect to the chip and/or to the support, which mechanism includes at least one cavity made in the layer of the chip and/or of the support, under the connection site of the chip and/or of the support, and at least one trench, made in the layer of the chip and/or of the support, communicating with the cavity. | 09-30-2010 |
20100252926 | Semiconductor Element, Method for Manufacturing the Same, and Mounting Structure Having the Semiconductor Element Mounted Thereon - A semiconductor element that is excellent in both mechanical reliability and electrical reliability and a mounting structure for the semiconductor element are provided. | 10-07-2010 |
20100258940 | BALL-LIMITING-METALLURGY LAYERS IN SOLDER BALL STRUCTURES - A solder ball structure and a method for forming the same. The structure includes (i) a first dielectric layer which includes a top dielectric surface, (ii) an electrically conductive line, (iii) a second dielectric layer, (iv) a ball-limiting-metallurgy (BLM) region, and (v) a solder ball. The BLM region is electrically connected to the electrically conductive line and the solder ball. The BLM region has a characteristic that a length of the longest straight line segment which is parallel to the top dielectric surface of the first dielectric layer and is entirely in the BLM region does not exceed a pre-specified maximum value. The pre-specified maximum value is at most one-half of a maximum horizontal dimension of the BLM region measured in a horizontal direction parallel to the top dielectric surface of the first dielectric layer. | 10-14-2010 |
20100264539 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a wiring substrate having connection pads and a semiconductor chip having electrode pads. The semiconductor chip is mounted on the wiring substrate, and the electrode pads are connected to the connection pads via solder bumps. An underfill resin formed of a cured thermosetting resin is filled in a gap between the wiring substrate and the semiconductor chip. The underfill resin has a glass transition temperature which increases accompanying growth of crystal grains of the solder bumps. | 10-21-2010 |
20100264540 | IC Package Reducing Wiring Layers on Substrate and Its Carrier - An IC package primarily comprises a substrate, a die-attaching layer, a chip, at least a bonding wire, and a plurality of electrical connecting components. The substrate has a top surface and a bottom surface where the top surface includes a die-attaching area for disposing the die-attaching layer. The chip is attached to the die-attaching area by the die-attaching layer and is electrically connected to the substrate by the electrical connecting components. Both ends of the bonding wire are bonded to two interconnecting fingers on the top surface of the substrate where at least a portion of the bonding wire is encapsulated in the die-attaching layer to replace some wirings or vias inside a conventional substrate. Therefore, the substrate has simple and reduced wiring layers, i.e., to reduce the substrate cost. A chip carrier of the corresponding IC package is also revealed. | 10-21-2010 |
20100264541 | METHODS OF FLUXLESS MICRO-PIERCING OF SOLDER BALLS, AND RESULTING DEVICES - A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate. | 10-21-2010 |
20100264542 | DYNAMIC PAD SIZE TO REDUCE SOLDER FATIGUE - A semiconductor device is provided which comprises a substrate ( | 10-21-2010 |
20100276802 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Provided is a semiconductor device and a method of manufacturing the semiconductor device, in which the semiconductor device has a semiconductor element having a plurality of wires bonded to the semiconductor element with sufficient bonding reliability and has a good heat dissipation property. A semiconductor device in which a first wire is ball bonded on an electrode, and a second wire is further bonded on the ball-bonded first wire, and the first wire or an end of the second wire defines a space between itself and the ball portion of the first wire. | 11-04-2010 |
20100276803 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor element ( | 11-04-2010 |
20100283151 | TECHNIQUES FOR PACKAGING MULTIPLE DEVICE COMPONENTS - Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dices coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package. | 11-11-2010 |
20100289141 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device with a semiconductor chip mounted on a small-sized package substrate that has a large number of external connection terminals. The package substrate includes a slot, the external connection terminals, and bonding fingers. The bonding fingers are connected to the external connection terminals. The bonding fingers constitute a bonding finger arrangement in a central section and end sections of a bonding finger area along each longer side of the slot. The bonding finger arrangement includes a first bonding finger array, which is located at a close distance from the each longer side of the slot, and a second bonding finger array, which is located at a distance farther than the distance of the first bonding finger array from the each longer side of the slot. The central section of the bonding finger area includes at least the second bonding finger array, and the end sections of the bonding finger area includes the first bonding finger array. | 11-18-2010 |
20100289142 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH COIN BONDED INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an interconnect to the substrate; encapsulating the interconnect with an encapsulation leaving a portion of the interconnect not encapsulated; attaching a joint to the interconnect and simultaneously creating a coined-surface of the interconnect contacting the joint; and attaching an integrated circuit to the substrate. | 11-18-2010 |
20100295179 | BGA SEMICONDUCTOR DEVICE HAVING A DUMMY BUMP - A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps. | 11-25-2010 |
20100295180 | WIRE BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention relates to a wire bonding structure, and more particularly to a manufacturing method for said wire bonding structure. The wire bonding structure comprises a die that connects with a lead via a bonding wire. At least one bond pad is positioned on an active surface of the die, and a gold bump is provided on the bond pad; furthermore, a ball bond can be positioned upon the gold bump. The bond pad and the gold bump can separate the ball bond and the die, which can avoid damaging the die during the bonding process. | 11-25-2010 |
20100301475 | Forming Semiconductor Chip Connections - Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape. | 12-02-2010 |
20100301476 | STACKED PACKAGE AND METHOD FOR FORMING STACKED PACKAGE - A semiconductor chip module including a plurality of semiconductor chips, each provided on the side face thereof with a part of connection terminals coupled with a circuit pattern formed on the front face, the chips being stacked and bonded. The stacked element in the lowermost layer is a semiconductor chip or an interposer dedicated for attachment to an external attachment board, and having a plurality of electrode elements (e.g., solder balls) arranged on a face on the attachment side, with each electrode element connected to any one of the connection terminals by a circuit pattern. Connection terminal portions on the side faces of the respective semiconductor chips and the stacked element in the lowermost layer are interconnected by a wiring pattern extending over the side faces. | 12-02-2010 |
20100301477 | Silicon-Based Thin Substrate and Packaging Schemes - A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces are formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips. | 12-02-2010 |
20100308460 | Method of Ball Grid Array Package Construction with Raised Solder Ball Pads - The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls. | 12-09-2010 |
20100308461 | MULTI-CHIP SEMICONDUCTOR PACKAGE - Semiconductor packages that contain multiple stacked chips and methods for making such semiconductor packages are described. The semiconductor packages contain a full land pad array and multiple chips that are stacked vertically. Some of the chips are separated by routing leads which are connected to the land pad array. The chips can be directly connected to an inner part of the land pad array and a second and third chip are respectively connected to the middle and outer part of the land pad array through the routing leads that are connected to solder balls. The semiconductor packages therefore have a high input/output capability with a small package footprint, and a flexible routing capability. Other embodiments are also described. | 12-09-2010 |
20100314760 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a base substrate, a semiconductor chip mounted on the base substrate and including bonding pads, first and second connection terminals disposed adjacent to the semiconductor chip on the base substrate and electrically connected to the bonding pads, a first ball land disposed on the base substrate and electrically connected to the first connection terminal, a second ball land spaced apart from the connection terminals, the first ball land disposed between the second ball land and at least one of the first and second connection terminals, a first insulating layer covering the first ball land but exposing at least a part of the second ball land, and a first conductive wire extending onto the first insulating layer and connecting the second connection terminal to the second ball land. | 12-16-2010 |
20100314761 | SEMICONDUCTOR DEVICE WITH REDUCED CROSS TALK - Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other. A major signal wiring of an external output system connected to the external output terminal, which may be a noise source, is made to be in a wiring layer distant from the semiconductor integrated circuit. | 12-16-2010 |
20100320601 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH THROUGH VIA DIE HAVING PEDESTAL AND RECESS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a structure having a via filled with conductive material completely through the structure, a recess, and a pedestal portion bordering the recess; mounting a semiconductor device inside the recess in the structure; and encapsulating the structure and the semiconductor device in an encapsulation. | 12-23-2010 |
20100320602 | High-Speed Memory Package - The semiconductor package includes a dielectric layer, a trace layer, a conductive layer, a die and an underfill layer. The dielectric layer has first side and an opposing dielectric layer second side. Multiple vias extend through the dielectric layer from the dielectric layer first side to the dielectric layer second side. Multiple solder balls are disposed at the dielectric layer second side. Each of the solder balls is electrically coupled to a different one of the vias. The die is electrically coupled to the solder balls. The conductive layer is disposed between the dielectric layer second side and the die. The conductive layer defines a window there through for allowing the solder balls to electrically couple to the vias without contacting the conductive layer, i.e., no physical or electrical contact. The underfill layer is formed between the die and the conductive layer, while the trace layer is formed at the dielectric layer first side. Traces of the trace layer electrically couple the vias to other solder balls. | 12-23-2010 |
20100320603 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate. | 12-23-2010 |
20100327441 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND WIRING STRUCTURE - A semiconductor device includes a semiconductor package, a circuit board, an interconnection electrically connecting the semiconductor package and the circuit board, and a wiring structure. The wiring structure includes a through hole, a contact disposed at the through hole and a lead pattern extending from the contact. The wiring structure is disposed between the semiconductor package and the circuit board. The interconnection passes through the through hole and connects with the contact. | 12-30-2010 |
20100327442 | Package and the Method for Making the Same, and a Stacked Package - The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement. | 12-30-2010 |
20110001238 | SEMICONDUCTOR CONSTRUCT AND MANUFACTURING METHOD THEREOF AS WELL AS SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring. | 01-06-2011 |
20110001239 | Semiconductor Chip Package and Method for Designing the Same - A semiconductor chip package is disclosed. The semiconductor chip package comprises a package substrate having a bottom surface. At least four adjacent ball pads are on the bottom surface, arranged in a first two-row array along a first direction and a second direction. At least four vias are drilled through the package substrate, arranged in a second two-row array, wherein each of the vias in a row of the second two-row array is offset by a first distance along the first direction and a second distance along the second direction from the connecting ball pads in a row of the first two-row array, and each of the vias in the other adjacent row of the second two-row array is offset by the first distance along an opposite direction to the first direction and the second distance along the second direction from the connecting ball pads in the other adjacent row of the first two-row array. | 01-06-2011 |
20110001240 | Chip Scale Module Package in BGA Semiconductor Package - A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD. | 01-06-2011 |
20110006422 | Structures and methods to improve lead-free C4 interconnect reliability - Controlled collapse chip connection (C4) structures and methods of manufacture, and more specifically to structures and methods to improve lead-free C4 interconnect reliability. A structure includes a ball limited metallization (BLM) layer and a controlled collapse chip connection (C4) solder ball formed on the BLM layer. Additionally, the structure includes a final metal pad layer beneath the BLM layer and a cap layer beneath the final metal pad layer. Furthermore, the structure includes an air gap formed beneath the C4 solder ball between the final metal pad layer and one of the BLM layer and the cap layer. | 01-13-2011 |
20110006423 | SURFACE-MOUNTED SILICON CHIP - A silicon chip surface mounted via balls attached to its front surface, wherein the front and rear surfaces of the chip are covered with a thermosetting epoxy resin having the following characteristics: the resin contains a proportion ranging from 45 to 60% by weight of a load formed of carbon fiber particles with a maximum size of 20 μm and with its largest portion having a diameter ranging between 2 and 8 μm, on the front surface side, the loaded resin covers from 45 to 60% of the ball height, on the rear surface side, the loaded resin has a thickness ranging between 80 and 150 μm. | 01-13-2011 |
20110012259 | PACKAGED SEMICONDUCTOR CHIPS - A chip-sized wafer level packaged device including a portion of a semiconductor wafer including a device, a packaging layer formed over the portion of the semiconductor wafer, the packaging layer including a material having thermal expansion characteristics similar to those of the semiconductor wafer and a ball grid array formed over a surface of the packaging layer and being electrically connected to the device. | 01-20-2011 |
20110012260 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, DESIGNING APPARATUS, SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM, SEMICONDUCTOR INTEGRATED CIRCUIT MOUNTING SUBSTRATE, PACKAGE AND SEMICONDUCTOR INTEGRATED CIRCUIT - To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out. | 01-20-2011 |
20110012261 | Post bump and method of forming the same - A post bump formed over an electrode pad of a substrate for electrically connecting to an external device, the post bump including a metal post formed over the electrode pad; and a solder formed over the metal post and shaped as a dome, the dome occupying a space defined by imaginary lines extending from a perimeter of the metal post along an axial direction of the metal post. | 01-20-2011 |
20110018131 | BONDING PAD FOR PREVENTING PAD PEELING - A bonding pad includes multiple metal layers, insulation layers disposed between the multiple metal layers, and a fixing pin coupled between the uppermost metal layer and an underlying metal layer of the multiple metal layers, where a bonding is performed on the uppermost metal layers. | 01-27-2011 |
20110024904 | SEMICONDUCTOR PACKAGE, PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a wiring board; a first electrode for external connection; a ball pad; a semiconductor chip; a mold resin; an electrode unit connected with the ball pad and penetrating the mold resin; and a second electrode for external connection connected with a portion of the electrode unit on a side of an outer surface of the mold resin. The electrode unit includes a first ball disposed on the ball pad; a second ball disposed between the first ball and the second electrode; and a solder material connecting between the ball pad and the first ball, between the first ball and the second ball, and between the second ball and the second electrode for external connection; each of the first ball and the second ball including a core part having a glass transition temperature which is higher than a melting point of the solder material. | 02-03-2011 |
20110024905 | STRUCTURE AND MANUFACTURING METHOD OF A CHIP SCALE PACKAGE WITH LOW FABRICATION COST, FINE PITCH AND HIGH RELIABILITY SOLDER BUMP - A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required. | 02-03-2011 |
20110024906 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE - A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element. | 02-03-2011 |
20110031618 | Bond Pad Design for Reducing the Effect of Package Stress - An integrated circuit structure includes a semiconductor substrate, and an active device formed at a front surface of the semiconductor substrate. A bond pad is over the front surface of the semiconductor substrate. The bond pad has a first dimension in a first direction parallel to the front surface of the semiconductor substrate. A bump ball is over the bond pad, wherein the bump ball has a diameter in the first direction, and wherein an enclosure of the first dimension and the diameter is greater than about −1 μm. | 02-10-2011 |
20110031619 | SYSTEM-IN-PACKAGE WITH FAN-OUT WLCSP - A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier; a second semiconductor die mounted alongside of the first semiconductor die; a rewiring laminate structure comprising a re-routed metal layer between the first semiconductor die and the package carrier. At least a portion of the re-routed metal layer projects beyond the die edge. A plurality of bumps are arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier. | 02-10-2011 |
20110031620 | METHOD OF THINNING A SEMICONDUCTOR SUBSTRATE - A C4 grind tape and a laser-ablative adhesive layer are formed on a front side of a semiconductor substrate. A carrier substrate is thereafter attached to the laser-ablative adhesive layer. The back side of the semiconductor substrate is thinned by polishing or grinding, during which the carrier substrate provides mechanical support to enable thinning of the semiconductor substrate to a thickness of about 25 μm. A film frame tape is attached to the back side of the thinned semiconductor substrate and the laser-ablative adhesive layer is ablated by laser, thereby dissociating the carrier substrate from the back side of the C4 grind tape. The assembly of the film frame tape, the thinned semiconductor substrate, and the C4 grind tape is diced. The C4 grind tape is irradiated by ultraviolet light to become less adhesive, and is subsequently removed. | 02-10-2011 |
20110031621 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF - In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability. | 02-10-2011 |
20110042809 | SEMICONDUCTOR PACKAGE WITH PAD PARTS ELECTRICALLY CONNECTED TO BONDING PADS THROUGH RE-DISTRIBUTION LAYERS - The semiconductor package includes: a semiconductor chip module having multiple adjacently arranged or integrally formed semiconductor chips each with a bonding pad group and a connection member electrically connecting each of the bonding pads included in the first bonding pad group to the corresponding bonding pad in the second bonding pad group. In the present invention pad parts can be formed on the outside of the semiconductor chip module to conform with the standards of JEDEC. These pad parts are then connected to the semiconductor chips bonding pads through re-distribution layers. The pad parts of the semiconductor package can then conform to the JEDEC standards even while having a semiconductor chip with bonding pads smaller than the standards. | 02-24-2011 |
20110042810 | STACKED PACKAGING IMPROVEMENTS - A plurality of microelectronic assemblies are made by severing an in-process unit including an upper substrate and lower substrate with microelectronic elements disposed between the substrates. In a further embodiment, a lead frame is joined to a substrate so that the leads project from this substrate. Lead frame is joined to a further substrate with one or more microelectronic elements disposed between the substrates. | 02-24-2011 |
20110049710 | INTERCONNECT LAYOUTS FOR ELECTRONIC ASSEMBLIES - Embodiments of the present disclosure provide an apparatus including an electronic device and a substrate to receive the electronic device, the electronic device being electrically coupled to the substrate using a plurality of interconnect structures, the interconnect structures being arranged on the electronic device based at least in part on a layout of the substrate. Other embodiments may be described and/or claimed. | 03-03-2011 |
20110049711 | ELLIPTIC C4 WITH OPTIMAL ORIENTATION FOR ENHANCED RELIABILITY IN ELECTRONIC PACKAGES - An arrangement for the equipping of electronic packages with elliptical C4 connects possessing optimal orientation for enhanced reliability. Furthermore, disclosed is a method providing elliptical C4 connects which possesses optimal orientation for enhanced reliability, as implemented in connection with their installation in electronic packages. Employed are essentially elliptical solder pads or elliptical C4 pad configurations at various preferably corner locations on a semiconductor chip. | 03-03-2011 |
20110049712 | Wafer Level Stacked Die Packaging - A stacked die package in which an adhesive pad separates a bottom die from a top die. The pad may be in the form of a wall of adhesive about a central hollow area. The bottom die is attached to a base with a low temperature curing adhesive or a snap cure adhesive. | 03-03-2011 |
20110057313 | Enhanced Copper Posts for Wafer Level Chip Scale Packaging - An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint. | 03-10-2011 |
20110062585 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, an electrode pad provided in the semiconductor chip, in which the electrode pad includes Al as a major constituent and further includes Cu, a coupling member coupled to the electrode pad, in which the coupling member primarily includes Cu, a plurality of layers of Cu and Al alloys formed between the electrode pad and the coupling member, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, in which the encapsulating resin encapsulates the semiconductor chip, the electrode pad, and the coupling member. The plurality of layers of Cu and Al alloys includes a CuAl | 03-17-2011 |
20110062586 | Chip for Reliable Stacking on another Chip - A chip includes a device, a passivation layer, two dielectric layers, at least one upper redistribution layer, at least one lower redistribution layer, at least one tunnel, at least one conductor, a redistribution passivation layer and at least one solder ball. The device includes at least one pad. The tunnel is defined in the upper redistribution layer, the first dielectric layer, the passivation layer, the pad, the device, the chip, the second dielectric layer and the lower redistribution layer. The conductor is located in the tunnel and connected to the upper and lower redistribution layers. The redistribution passivation layer is located on the second dielectric layer, the lower redistribution layer and the conductor. The solder ball is located on a portion of the lower redistribution layer through an aperture defined in the redistribution passivation layer. The chip can be connected to a printed circuit board by the solder ball. | 03-17-2011 |
20110068469 | SEMICONDUCTOR PACKAGE WITH PRE-FORMED BALL BONDS - A semiconductor package includes an integrated circuit die having first and second sets of connection pads, bond wires, and a substrate with connection pads. The bond wires electrically connect the second set of connection pads of the die with the substrate connection pads. Prior to connecting the wires to the second connection pads, a free air ball (FAB) is formed and pressed against a respective one of the connection pads of the first set to form a pre-formed ball bond. | 03-24-2011 |
20110074029 | FLIP-CHIP PACKAGE COVERED WITH TAPE - A manufacturing method of a semiconductor device includes arranging a melted resin on a substrate, arranging a semiconductor chip on the melted resin, pressing the semiconductor chip and flip-chip mounting the semiconductor chip on the substrate, and hardening the melted resin with the melted resin being subjected to a fluid pressure and forming a resin portion. | 03-31-2011 |
20110079902 | SEMICONDUCTOR DEVICE - A semiconductor device has a wiring substrate provided with an external connecting terminal on a lower surface, a semiconductor chip mounted onto an upper surface of the wiring substrate, a cap-shaped heat dissipation member arranged on the upper surface of the wiring substrate so as to cover the semiconductor chip, a fixing pin for fixing the heat dissipation member onto the upper surface of the wiring substrate, and a heat transfer material sandwiched between a lower surface of the heat dissipation member just above the semiconductor chip and the upper surface of the semiconductor chip. | 04-07-2011 |
20110079903 | CHIP PACKAGE AND FABRICATION METHOD THEREOF - A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate containing a semiconductor component and a conductive pad thereon. A through hole penetrates the semiconductor substrate from a backside thereof to expose the conductive pad. A redistribution layer is below the backside of the semiconductor substrate and electrically connected to the conductive pad in the through hole. A conductive trace layer is below the redistribution layer and extended along a sidewall of the semiconductor substrate to electrically contact with an edge of the redistribution layer. | 04-07-2011 |
20110079904 | Semiconductor device - Wire bonding method for reducing height of a wire loop in a semiconductor device, including a first bonding step of bonding an initial ball formed at a tip end of a wire onto a first bonding point using a capillary, thereby forming a pressure-bonded ball; a wire pushing step of pushing the wire obliquely downward toward the second bonding point at a plurality of positions by repeating a sequential movement for a plurality of times, the sequential movement including moving of the capillary substantially vertically upward and then obliquely downward toward the second bonding point by a distance shorter than a rising distance that the capillary has moved upward; and a second bonding step of moving the capillary upward and then toward the second bonding point, and bonding the wire onto the second bonding point by pressure-bonding. | 04-07-2011 |
20110079905 | Die Stacking System and Method - Die stacking systems and methods are disclosed. In an embodiment, a semiconductor device includes a passivation surface and a conductive die receiving surface located in an opening of the passivation surface. The conductive die receiving surface has a surface area that is larger than a footprint of a second die that is electrically coupled to the conductive die receiving surface. | 04-07-2011 |
20110084389 | Semiconductor Device - The present invention relates to a semiconductor device. The semiconductor device includes a substrate and a chip. The chip is electrically connected to the substrate. The chip includes a chip body, at least one chip pad, a first passivation, an under ball metal layer and at least one metal pillar structure. The chip pad is disposed adjacent to an active surface of the chip body. The first passivation is disposed adjacent to the active surface, and exposes part of the chip pad. The under ball metal layer is disposed adjacent to the chip pad. The metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter. The metal pillar structure is electrically connected to a substrate pad of the substrate to form a second contact surface having a second diameter. The ratio of the first diameter to the second diameter is between 0.7 and 1.0. As a result, the first contact surface and the second contact surface have an equivalent bonding force, which prevents the metal pillar structure from cracking due to a shear stress. Thus, the structure strength of the semiconductor device is enhanced and the semiconductor device can pass the reliability test. | 04-14-2011 |
20110084390 | Chip Design with Robust Corner Bumps - An integrated circuit structure includes a semiconductor chip, which includes a corner, a side, and a center. The semiconductor chip further includes a plurality of bump pad structures distributed on a major surface of a substrate; a first region of the substrate having formed thereon a first bump pad structure having a first number of supporting metal pads associated with it; and a second region of the substrate having formed thereon a second bump structure having a second number of supported metal pads associated with it, the second number being greater than the first number. | 04-14-2011 |
20110089563 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step. | 04-21-2011 |
20110089564 | ADHESIVE ON WIRE STACKED SEMICONDUCTOR PACKAGE - A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof. | 04-21-2011 |
20110089565 | Semiconductor Device and Electronic Apparatus Equipped with the Semiconductor Device - A semiconductor device comprises an IC chip body and a package substrate that has thereon many external electrodes arranged in a two-dimensional grid configuration. Groups of signal lines that are likely to emit noise (noisy signal lines) are separated and spaced apart from groups of signal lines that are susceptible to noise (noise susceptible signal lines). Each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated IC pad group separated and spaced apart from other IC pad groups. Further, each of the noisy signal lines and noise susceptible signal lines is connected to an associated member of an associated external electrode group selected from the multiplicity of external electrodes arranged in a two-dimensional grid configuration on the package substrate. Thus, groups of potentially interfering signal lines are mutually separated and spaced apart from one another, thereby suppressing the noise. | 04-21-2011 |
20110095424 | SEMICONDUCTOR PACKAGE STRUCTURE - The semiconductor package structure includes first and second packages. The first package has at least one first semiconductor chip disposed on a first printed circuit board, and at least one first pad disposed on the at least one first semiconductor chip. The second package has at least one second pad disposed on the first package, and at least one second semiconductor chip disposed on the at least one second pad. The at least one first semiconductor chip is electrically connected to the first printed circuit board. The at least one second pad is electrically connected to the at least one second semiconductor chip. The at least one second pad faces the at least one first pad. | 04-28-2011 |
20110095425 | Ball grid array substrate, semiconductor chip package and method of manufacturing the same - Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed. | 04-28-2011 |
20110095426 | Hybrid Package - The embodiments described herein provide for a packaging configuration that provides leads or connections for a packaging substrate from opposing surfaces of a package. Through silicon vias (TSV) are provided in order to accommodate additional input/output (I/O) pins that smaller dies are supporting. Various combinations of packages are enabled through the embodiments provided. | 04-28-2011 |
20110101525 | SEMICONDUCTOR DEVICE WITH TRENCH-LIKE FEED-THROUGHS - A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated. | 05-05-2011 |
20110101526 | Copper Bump Joint Structures with Improved Crack Resistance - An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium. | 05-05-2011 |
20110101527 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS - The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper. | 05-05-2011 |
20110108983 | Integrated Circuit - An integrated circuit includes a die including contacts formed thereon. A first dielectric layer is formed on the die. The first dielectric layer includes apertures defined therein corresponding to the contacts. A second dielectric layer is formed on the second dielectric layer. The second dielectric layer includes apertures defined therein corresponding to the apertures of the first dielectric layer. Redistribution layers are located in the apertures of the first and second dielectric layers and connected to the contacts. A passivation layer is located on the second dielectric layer and the redistribution layers. The passivation layer includes apertures corresponding to the redistribution layers. A solder ball is located in each of the apertures of the passivation layer and connected to a related one of the redistribution layers. | 05-12-2011 |
20110108984 | CIRCUIT BOARD AND CHIP PACKAGE STRUCTURE - A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided. | 05-12-2011 |
20110115082 | CONFIGURABLE INTERPOSER - A modularized interposer includes a plurality of interposer units that are assembled to provide a complete set of electrical connections between two semiconductor chips. At least some of the plurality of interposer units can be replaced with other interposer units having an alternate configuration to enable selection of different functional parts of semiconductor chips to be connected through the modularized interposer. Bonding structures, connected to conductive metal pads located at peripheries of neighboring interposer units and an overlying or underlying portion of a semiconductor chip, can provide electrical connections between the neighboring interposer units. The interposer units can be provided by forming through-substrate vias (TSV's) in a substrate, forming patterned conductive structures on the substrate, and cutting the substrate into interposers. | 05-19-2011 |
20110115083 | Semiconductor Package Assembly Systems and Methods using DAM and Trench Structures - A packaging system for preventing underfill overflow includes a package substrate having a solder mask a die attach site, a solder mask dam on the solder mask proximal to the die attach site, and a trench in the solder mask proximal to the die attach site. The trench and the solder mask dam are adapted to constrain flow of an underfill material. | 05-19-2011 |
20110115084 | LEAD-FREE SOLDER CONNECTION STRUCTURE AND SOLDER BALL - Solder used for flip chip bonding inside a semiconductor package was a Sn—Pb solder such as a Pb-5Sn composition. Lead-free solders which have been studied are hard and easily form intermetallic compounds with Sn, so they were not suitable for a flip chip connection structure inside a semiconductor package, which requires stress relaxation properties. This problem is eliminated by a flip chip connection structure inside a semiconductor package using a lead-free solder which is characterized by consisting essentially of 0.01-0.5 mass percent of Ni and a remainder of Sn. 0.3-0.9 mass percent of Cu and 0.001-0.01 mass percent of P may be added to this solder composition. | 05-19-2011 |
20110115085 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - In a semiconductor device of the present invention, semiconductor chips are stacked in multi-layers. Each of the semiconductor chip includes: through vias extending through a top main surface thereof to a bottom surface opposite to the top main surface; a circuit element surface formed on the top main surface; pads arranged on the circuit element surface; bumps formed on the pads; and via pads, formed on the bottom surface thereof, to which the bumps of its upper semiconductor chip are joined, and positions at which the bumps of each of the semiconductor chips are respectively arranged are different from those at which the bumps of its upper semiconductor chip are arranged. | 05-19-2011 |
20110121454 | STACK SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stack semiconductor package includes a first insulation member having engagement projections and a second insulation member formed having engagement grooves into which the engagement projections are to be engaged. First conductive members are disposed in the first insulation member and have portions which are exposed on the engagement projections. Second conductive members are disposed in the second insulation member in such a way as to face the first conductive members and have portions which are exposed in the engagement grooves. A first semiconductor chip is disposed within the first insulation member and is electrically connected to the first conductive members. A second semiconductor chip is disposed in the second insulation member and is electrically connected to the second conductive members. | 05-26-2011 |
20110127670 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip. | 06-02-2011 |
20110127671 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence. | 06-02-2011 |
20110127672 | SEMICONDUCTOR PACKAGE HAVING A STACKED WAFER LEVEL PACKAGE AND METHOD FOR FABRICATING THE SAME - A semiconductor package having a stacked wafer level structure includes a base substrate; a semiconductor chip; a redistribution pattern; and a second insulation layer pattern. The base substrate having a chip region and a peripheral region disposed at the periphery of the chip region. The semiconductor chip is disposed over the chip region and has a bonding pad. The first insulation layer pattern covers the chip region and the peripheral region and exposes the bonding pad. The redistribution pattern is disposed over the first insulation layer pattern and extends from the bonding pad to the peripheral region. The second insulation layer pattern is disposed over the first insulation layer pattern and opening some portion of the redistribution pattern disposed in the peripheral region. | 06-02-2011 |
20110133337 | AREA REDUCTION FOR SURFACE MOUNT PACKAGE CHIPS - Using side-wall conductor leads deposited on the side-walls of a base substrate to form package level conductor leads for active circuits manufactured on silicon substrate(s) stacked on the base substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance. | 06-09-2011 |
20110140271 | INTEGRATED CIRCUIT CHIP WITH PYRAMID OR CONE-SHAPED CONDUCTIVE PADS FOR FLEXIBLE C4 CONNECTIONS AND A METHOD OF FORMING THE INTEGRATED CIRCUIT CHIP - Disclosed is a chip and method of forming the chip with improved conductive pads that allow for flexible C4 connections with a chip carrier or with another integrated circuit chip. The pads have a three-dimensional geometric shape (e.g., a pyramid or cone shape) with a base adjacent to the surface of the chip, a vertex opposite the base and, optionally, mushroom-shaped cap atop the vertex. Each pad can include a single layer of conductive material or multiple layers of conductive material (e.g., a wetting layer stacked above a non-wetting layer). The pads can be left exposed to allow for subsequent connection to corresponding solder bumps on a chip carrier or a second chip. Alternatively, solder balls can be positioned on the conductive pads to allow for subsequent connection to corresponding solder-paste filled openings on a chip carrier or a second chip. | 06-16-2011 |
20110140272 | Ball Grid Array Package Enhanced With a Thermal and Electrical Connector - A package is provided. The package includes a substrate having first and second surfaces, a stiffener coupled to the first surface of the substrate, and a thermal connector coupled to the second surface of the substrate that is configured to be coupled to a printed circuit board. | 06-16-2011 |
20110140273 | Semiconductor Devices Including Voltage Switchable Materials for Over-Voltage Protection - Semiconductor devices are provided that employ voltage switchable materials for over-voltage protection. In various implementations, the voltage switchable materials are substituted for conventional die attach adhesives, underfill layers, and encapsulants. While the voltage switchable material normally functions as a dielectric material, during an over-voltage event the voltage switchable material becomes electrically conductive and can conduct electricity to ground. Accordingly, the voltage switchable material is in contact with a path to ground such as a grounded trace on a substrate, or a grounded solder ball in a flip-chip package. | 06-16-2011 |
20110147928 | MICROELECTRONIC ASSEMBLY WITH BOND ELEMENTS HAVING LOWERED INDUCTANCE - Microelectronic assemblies can have multiple conductive bond elements, e.g., bond wires, or a lead bond and a bond wire, extending between a pair of a substrate contact and a chip contact. E.g., a first bond wire can have ends joined to the contacts of the chip and substrate. A second bond wire can be joined to the ends of the first bond wire so that the second bond wire does not touch either the chip contact or the substrate contact to which the first bond wire is joined. In one example, a bond wire has a looped connection with first and second ends joined at a first contact and a middle portion joined to a second contact. In one example, first and second bond elements, e.g., bond wires or lead bonds can connect first and second pairs of a substrate contact with a chip contact. A third bond element, e.g., a bond wire or bond ribbon, can be joined to ends of the first and second bond elements. | 06-23-2011 |
20110147929 | THROUGH MOLD VIA POLYMER BLOCK PACKAGE - Methods for forming an integrated circuit chip package having through mold vias in a polymer block, and such packages are described. For example, a first interconnect layer may be formed on a molded polymer block, wherein the first interconnect layer comprises first interconnects through a first polymer layer and to the block. Then, at least one second interconnect layer may be formed on the first interconnect layer, wherein the second interconnect layer comprises second interconnects through a second polymer layer and to the first interconnects of the first interconnect layer. Through mold vias may then be formed through the block, into the first interconnect layer, and to the first interconnects. The through mold vias may be filled with solder to form bumps contacting the first interconnects and extending above the block. Other embodiments are also described and claimed. | 06-23-2011 |
20110147930 | Semiconductor Component of Semiconductor Chip Size with Flip-Chip-Like External Contacts - A semiconductor component and a method for its production in semiconductor chip size, can have a semiconductor chip, which has external contacts of the semiconductor component that are arranged in the manner of a flip-chip on its active upper side. The semiconductor chip can be encapsulated by a plastic compound at least on its rear side and its side edges. The outer contacts, which can be arranged on external contact connecting areas, can project from the active upper side. | 06-23-2011 |
20110147931 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 06-23-2011 |
20110156250 | FLIP-CHIP FAN-OUT WAFER LEVEL PACKAGE FOR PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE - A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto. | 06-30-2011 |
20110156251 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads. | 06-30-2011 |
20110156252 | SEMICONDUCTOR PACKAGE HAVING ELECTRICAL CONNECTING STRUCTURES AND FABRICATION METHOD THEREOF - A semiconductor package having electrical connecting structures includes: a conductive layer having a die pad and traces surrounding the die pad; a chip; bonding wires; an encapsulant with a plurality of cavities having a depth greater than the thickness of the die pad and traces for embedding the die pad and the traces therein, and the cavities exposing the die pad and the traces; a solder mask layer formed in the cavities and having a plurality of openings for exposing the trace ends and a portion of the die pad; and solder balls formed in the openings and electrically connected to the trace ends. Engaging the solder mask layer with the encapsulant enhances adhesion strength of the solder mask layer so as to prolong the moisture permeation path and enhance package reliability. | 06-30-2011 |
20110156253 | MICRO-BUMP STRUCTURE - A dished micro-bump structure with self-aligning functions is provided. The micro-bump structure takes advantage of the central concavity for achieving the accurate alignment with the corresponding micro-bumps. | 06-30-2011 |
20110156254 | MODIFIED CHIP ATTACH PROCESS - A process for assembling a package for a semiconductor device comprising reducing the stress in an inner dielectric layer during packaging by heating the die and the substrate to a temperature where a solder reflows, dropping to a temperature where a selected epoxy will cure, liquefying the epoxy, adding the liquefied epoxy to the die and substrate, and maintaining the die and substrate at a temperature where the epoxy cures for a selected amount of time. | 06-30-2011 |
20110163443 | METHODS FOR WAFER-LEVEL PACKAGING OF MICROELECTRONIC DEVICES AND MICROELECTRONIC DEVICES FORMED BY SUCH METHODS - Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices re disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The microelectronic workpiece of this embodiment further includes a protective layer over the backside of the substrate. The protective layer is formed on the backside of the substrate from a material that is in a flowable state and is then cured to a non-flowable state. | 07-07-2011 |
20110163444 | SEMICONDUCTOR DEVICE HAVING ELASTIC SOLDER BUMP TO PREVENT DISCONNECTION - Regarding a semiconductor device, especially the present invention suppresses disconnection of the connection structure concerned in the semiconductor device which has the electric and mechanical connection structure using solder, and aims at improving connection reliability. And to achieve the above objects, the semiconductor device has the solder bump which electrically connects a semiconductor chip and a package substrate, the under-filling resin with which it filled up between the semiconductor chip and the package substrate, and a solder ball which electrically connects a package substrate with the outside, and the solder bump's elastic modulus is made lower than the elastic modulus of a solder ball. | 07-07-2011 |
20110163445 | Electronic Packages With Fine Particle Wetting and Non-Wetting Zones - Spreading or keep out zones may be formed in integrated circuit packages by altering the roughness of package surfaces. The surface roughness can be altered by applying or growing particles having a dimension less than 500 nanometers. Hydrophilic surfaces may be made hemi-wicking and hydrophobic surfaces may be made hemi-wicking by particles of the same general characteristics. | 07-07-2011 |
20110169162 | Integrated Circuit Module and Multichip Circuit Module Comprising an Integrated Circuit Module of This Type - The invention relates to an integrated circuit module ( | 07-14-2011 |
20110169163 | ATTACHING PASSIVE COMPONENTS TO A SEMICONDUCTOR PACKAGE - Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed. | 07-14-2011 |
20110175222 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package. The semiconductor package may include a base substrate having a substrate part and at least one support part. The substrate part may include a first surface on which at least one first connection terminal is disposed and a second surface opposite to the first surface. The at least one support part may be on the first surface and may have an area smaller than that of the first surface. The semiconductor package may further include at least one first semiconductor chip on the at least one support part and at least one second semiconductor chip on the first surface under the at least one first semiconductor chip. The at least one second semiconductor chip may have a top surface and two side surfaces, the top surface being at an elevation lower than a top surface of the at least one support part and the two side surfaces may be arranged to face the at least one support part. | 07-21-2011 |
20110175223 | Stacked Semiconductor Components Having Conductive Interconnects - A stacked semiconductor component includes a semiconductor substrate having a substrate contact, a substrate opening extending to an inner surface of the substrate contact, and a conductive interconnect comprising a wire in the substrate opening having a wire bonded connection with the inner surface of the substrate contact. The stacked semiconductor component also includes a second substrate stacked on the semiconductor substrate having a contact bonded to the conductive interconnect on the semiconductor substrate. The second substrate can also include conductive interconnects in the form of wire bonded wires, and the stacked semiconductor substrate can include a third semiconductor substrate stacked on the second substrate. | 07-21-2011 |
20110180928 | ETCHED RECESS PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom. | 07-28-2011 |
20110186997 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a method of manufacturing the same are disclosed. The single-layer board on chip package substrate in accordance with an embodiment of the present invention includes an insulator, which has a window perforated therethrough, a wiring pattern, a wire bonding pad and a solder ball pad, which are embedded in one surface of the insulator, and a solder resist layer, which is formed on the one surface of the insulator such that the solder resist layer covers the wiring pattern but at least portions of the wire bonding pad and the solder ball pad are exposed. | 08-04-2011 |
20110186998 | RECESSED SEMICONDUCTOR SUBSTRATES - Embodiments of the present disclosure provide an apparatus comprising a semiconductor substrate having a first surface, a second surface that is disposed opposite to the first surface, wherein at least a portion of the first surface is recessed to form a recessed region of the semiconductor substrate, and one or more vias formed in the recessed region of the semiconductor substrate to provide an electrical or thermal pathway between the first surface and the second surface of the semiconductor substrate, and a die coupled to the semiconductor substrate, the die being electrically coupled to the one or more vias formed in the recessed region of the semiconductor substrate. Other embodiments may be described and/or claimed. | 08-04-2011 |
20110193226 | MICROELECTRONIC DEVICES WITH THROUGH-SUBSTRATE INTERCONNECTS AND ASSOCIATED METHODS OF MANUFACTURING - Microelectronic devices with through-substrate interconnects and associated methods of manufacturing are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate carrying first and second metallization layers. The second metallization layer is spaced apart from the semiconductor substrate with the first metallization layer therebetween. The semiconductor device also includes a conductive interconnect extending at least partially through the semiconductor substrate. The first metallization layer is in electrical contact with the conductive interconnect via the second metallization layer. | 08-11-2011 |
20110193227 | Methods and Apparatus for Robust Flip Chip Interconnections - Apparatus and methods for providing a robust solder connection in a flip chip arrangement using lead free solder are disclosed. A copper column extends from an input/output terminal of an integrated circuit. A cap layer of a material comprising one of nickel, nickel alloys, palladium, platinum, cobalt, silver, gold, and alloys of these is formed on the exterior surface of the copper column. A lead free solder connector is disposed on the cap layer. A substrate having a metal finish solder pad is aligned with the solder connector. A thermal reflow is performed. The metal finish may be of nickel, nickel alloy and nickel based materials. Following a thermal reflow, the solder connection formed between the copper terminal column and the metal finish solder pad is less than 0.5 wt. %. | 08-11-2011 |
20110193228 | MOLDED UNDERFILL FLIP CHIP PACKAGE PREVENTING WARPAGE AND VOID - A molded underfill flip chip package may include a printed circuit board, a semiconductor chip mounted on the printed circuit board, and a sealant. The printed circuit board has at least one resin passage hole passing through the printed circuit board and at least one resin channel on a bottom surface of the printed circuit board, the at least one resin channel extending from the at least one resin passage hole passing through the printed circuit board. The sealant seals a top surface of the printed circuit board, the semiconductor chip, the at least one resin passage hole, and the at least one resin channel. | 08-11-2011 |
20110193229 | Multi-Chip Package Having Semiconductor Chips Of Different Thicknesses From Each Other And Related Device - A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip. | 08-11-2011 |
20110198751 | BOND PAD WITH MULTIPLE LAYER OVER PAD METALLIZATION AND METHOD OF FORMATION - A semiconductor device structure has a semiconductor die that has a bond pad with a passivation layer surrounding a portion of the bond pad. A nickel layer, which is deposited, is on the inner portion. A space is between a sidewall of the nickel layer and the passivation layer and extends to the bond pad. A palladium layer is over the nickel layer and fills the space. The space is initially quite small but is widened by an isotropic etch so that when the palladium layer is deposited, the space is sufficiently large so that the deposition of palladium is able to fill the space. Filling the space results in a structure in which the palladium contacts the nickel layer, the passivation layer and the bond pad. | 08-18-2011 |
20110198752 | LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 08-18-2011 |
20110198753 | IMPROVED WAFER LEVEL CHIP SCALE PACKAGING - An improved wafer level chip scale packaging technique is described which does not use an encapsulated via to connect between a redirection layer and a pad within the pad ring on the semiconductor die. In an embodiment, a first dielectric layer is formed such that it terminates on each die within the die's pad ring. Tracks are then formed in a conductive layer which contact one of the pads and run over the edge of an opening onto the surface of the first dielectric layer. These tracks may be used to form an electrical connection between the pad and a solder ball. | 08-18-2011 |
20110204513 | Device Including an Encapsulated Semiconductor Chip and Manufacturing Method Thereof - A device includes a semiconductor chip having contact pads arranged on a first main face of the semiconductor chip. A first material has an elongation to break of greater than 35% covering the first main face of the semiconductor chip. An encapsulation body covers the semiconductor chip. A metal layer is electrically coupled to the contact pads of the semiconductor chip and extends over the encapsulation body. | 08-25-2011 |
20110204514 | PACKAGE DEVICE AND FABRICATION METHOD THEREOF - A package device and a fabrication method thereof comprises providing a plurality of package units each having a plurality of penetrated holes; stacking the plurality of package units in a manner such that the penetrated holes of the plurality of package units are aligned; filling a conductive material into the plurality of penetrated holes substantially, so as to electrically connect the plurality of package units through the conductive material; and disposing a plurality of solder balls on the bottom of the conductive material filling the plurality of penetrated holes, and connecting the plurality of solder balls with the conductive material electrically. | 08-25-2011 |
20110204515 | IC DIE INCLUDING RDL CAPTURE PADS WITH NOTCH HAVING BONDING CONNECTORS OR ITS UBM PAD OVER THE NOTCH - An IC die includes active circuitry and I/O nodes tied together in first net and at least a second net. A first die pad and a second die pad adjacent thereto are coupled to the first and second net, respectively. A redirect layer (RDL) coupled to the die pads over a first dielectric vias includes a first RDL trace lateral coupling the first die pad and first RDL pad and a second RDL trace coupling the second die pad and second RDL pad. The first RDL pad includes an RDL notch facing the second RDL trace. Under bump metallization (UBM) pads on a second dielectric include a first UBM pad coupled to the first RDL pad over a second dielectric via. A first metal bonding connector is on the first UBM pad. The first UBM pad or first metal bonding connector overhangs the first RDL pad over the notch. | 08-25-2011 |
20110210443 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME - An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at least a portion of a first metal layer; forming an under-bump metallization (UBM) layer over the tapered via and the first metal layer to form a UBM bucket; and forming a dielectric cap layer over the dielectric layer and a portion of the UBM layer. The UBM bucket is configured to support a solder ball and can advantageously block all alpha particles emitted by the solder ball having a relevant angle of incidence from reaching the active semiconductor regions of the IC. Thus, soft errors, such as single event upsets in memory cells, are reduced or eliminated. | 09-01-2011 |
20110210444 | 3D Semiconductor Package Using An Interposer - A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die. | 09-01-2011 |
20110215470 | Dummy Wafers in 3DIC Package Assemblies - A package structure includes a first die, and a second die over and bonded to the first die. The second die has a size smaller than a size of the first die. A dummy chip is over and bonded onto the first die. The dummy chip includes a portion encircling the second die. The dummy chip includes a material selected from the group consisting essentially of silicon and a metal. | 09-08-2011 |
20110215471 | Package On Package - A package on package structure is provided. The package on package structure may include a first substrate having a first center region and a first C-shaped edge region at a first end of the first center region. In example embodiments, the first C-shaped edge region may faun a first space. The package structure may further include at least two first connection pads on an inner surface of the first C-shaped edge region and the at least two first connection pads may be arranged to face one another. In example embodiments, at least one first solder ball may be arranged in the first space and the at least one first solder ball may be connected to the at least two first connection pads. | 09-08-2011 |
20110215472 | Through Silicon via Bridge Interconnect - An integrated circuit bridge interconnect device includes a first die and a second die provided in a side-by-side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die. | 09-08-2011 |
20110221059 | QUAD FLAT NON-LEADED SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A QFN package includes a chip-mounting base; electrically connecting pads disposed around the periphery of the chip-mounting base, the bottom surfaces of the chip-mounting base and the electrically connecting pads being covered by a copper layer; a chip mounted on the top surface of the chip-mounting base; bonding wires electrically connecting to the chip and the electrically connecting pads; an encapsulant encapsulating the chip-mounting base, the electrically connecting pads, the chip and the bonding wires while exposing the copper layer; and a dielectric layer formed on the bottom surfaces of the encapsulant and the copper layer and having a plurality of openings exposing a portion of the copper layer. The copper layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the interface between the chip-mounting base, the electrically connecting pads and the dielectric layer, thereby avoiding solder extrusion and enhancing product yield. | 09-15-2011 |
20110221060 | Process for Fabricating Electronic Components Using Liquid Injection Molding - A process for fabricating an electronic component includes a liquid injection molding method for overmolding a semiconductor device. The liquid injection molding method includes: i) placing the semiconductor device in an open mold, ii) closing the mold to form a mold cavity, iii) heating the mold cavity, iv) injection molding a curable liquid into the mold cavity to overmold the semiconductor device, v) opening the mold and removing the product of step iv), and optionally vi) post-curing the product of step v). The semiconductor device may have an integrated circuit attached to a substrate through a die attach adhesive. | 09-15-2011 |
20110227219 | ENHANCED WLP FOR SUPERIOR TEMP CYCLING, DROP TEST AND HIGH CURRENT APPLICATIONS - A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection. | 09-22-2011 |
20110227220 | STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a set of stud bumps, which can be formed by wire bonding technology and can be bonded or joined to a semiconductor element to form a stacked package assembly. Since the process of bonding the semiconductor element to the stud bumps can be carried out without reflow, an undesirable deformation resulting from high temperatures can be controlled or reduced. | 09-22-2011 |
20110227221 | ELECTRONIC DEVICE HAVING INTERCONNECTIONS AND PADS - An electronic device includes first and second interconnections formed on a first surface of a substrate and spaced apart from each other. The electronic device includes a first insulating material layer disposed on the substrate including the first and second interconnections and including a first opening exposing a predetermined region of the first interconnection. The electronic device further includes a first pad filling the first opening and having a greater width than the first opening. The first pad covers at least a part of the second interconnection adjacent to one end of the first interconnection, and the first pad is electrically insulated from the second interconnection by the first insulating material layer. | 09-22-2011 |
20110227222 | SURFACE-MOUNTED ELECTRONIC COMPONENT - A surface-mounted electronic component including balls bonded to its front surface and, on the front surface, a protective resin layer having a thickness smaller than the ball height, wherein grooves extend in the resin layer between balls of the chip. | 09-22-2011 |
20110227223 | EMBEDDED DIE WITH PROTECTIVE INTERPOSER - Embodiments of the present disclosure provide a substrate having (i) a first laminate layer, (ii) a second laminate layer, and (iii) a core material that is disposed between the first laminate layer and the second laminate layer; and a die attached to the first laminate layer, the die having an interposer bonded to a surface of an active side of the die, the surface comprising (i) a dielectric material and (ii) a bond pad to route electrical signals of the die, the interposer having a via formed therein, the via being electrically coupled to the bond pad to further route the electrical signals of the die, wherein the die and the interposer are embedded in the core material of the substrate. Other embodiments may be described and/or claimed. | 09-22-2011 |
20110233777 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 09-29-2011 |
20110241204 | Semiconductor device - A semiconductor device includes an electrode pad provided on a semiconductor chip, in which the electrode pad includes aluminum (Al) as a major constituent and further including copper (Cu), a coupling ball primarily including Cu, the coupling ball is coupled to the electrode pad such that a plurality of layers of Cu and Al alloys are formed at a junction between the electrode pad and the coupling ball, and an encapsulating resin including a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and the junction between the electrode pad and the coupling ball. A dimensional area of the plurality of layers of Cu and Al alloys is equal to or larger than 50% of a dimensional area of the junction between the electrode pad and the coupling ball. The plurality of layers of Cu and Al alloys includes a CuAl | 10-06-2011 |
20110241205 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 10-06-2011 |
20110241206 | SEMICONDUCTOR DEVICE - A semiconductor device is provided by the present invention. The semiconductor device includes a first semiconductor die comprising at least a first bond pad; and a second semiconductor die comprising at least a second bond pad with voltage level equivalent to the first bond pad of the first semiconductor die; wherein the first bond pad of the first semiconductor die is electrically connected to the second bond pad of the second semiconductor die via at least a bond wire. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost. | 10-06-2011 |
20110254159 | CONDUCTIVE FEATURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive feature on a semiconductor die. A substrate is provided. A bond pad is formed over the substrate. The bond pad has a first width. A polyimide layer is formed over the substrate and the bond pad. The polyimide layer has a first opening over the bond pad with a second width. A silicon-based protection layer overlies the polyimide layer. The silicon-based protection layer has a second opening over the bond pad with a third width. The first opening and the second opening form a combined opening having sidewalls to expose a portion of the bond pad. A UBM layer is formed over the sidewalls of combined opening to contact the exposed portion of the bond pad. A conductive feature overlies the UBM layer. | 10-20-2011 |
20110254160 | TSVs with Different Sizes in Interposers for Bonding Dies - A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs. | 10-20-2011 |
20110254161 | Integrated Circuit Package Having Under-Bump Metallization - An integrated circuit (IC) device uses a simple structure having X/Cu/Sn metal layers (X can be Ti or Ti/W etc.) without extra barrier layer. Thus, number of layers is reduced for a simple fabrication with good production and low cost. | 10-20-2011 |
20110254162 | High Speed, High Density, Low Power Die Interconnect System - A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias. | 10-20-2011 |
20110260322 | "Semiconductor on semiconductor substrate multi-chip-scale package" - Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT. | 10-27-2011 |
20110266670 | WAFER LEVEL CHIP SCALE PACKAGE WITH ANNULAR REINFORCEMENT STRUCTURE - Annular reinforcement structures that can be used in wafer level chip scale packages (WLCSP) are described. The WLCSP comprises a substrate with an IC device and a bond pad connected to the IC device, a passivation layer protecting an outer portion of the bond pad, an annular ring structure formed on an inner portion of the bond pad, an under bump metal (UBM) layer covering the annular ring structure, and a solder ball attached to the UBM layer. The annular ring structure contains a substantially planar top with vertical or non-vertical sidewalls that slope down to the inner portion of the bond pad. The annular ring structure can slow the solder crack propagation in the solder ball and therefore increase the solder joint reliability in the WLCSP. As well, the annular ring structure can increase the surface area for solder attachment to the UBM layer, improving overall ball shear strength are described. Other embodiments are described. | 11-03-2011 |
20110266671 | SUBSTRATE FOR A SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Disclosed herein are a substrate for a semiconductor package and a manufacturing method thereof. The substrate for the semiconductor package, which has a single-sided substrate structure including circuit patterns having a connection pad formed on only an electronic component mounting surface, can directly connect a connection pad on the top of the substrate to external connection terminals on the bottom of the substrate through a connection via formed of a metal plating layer formed in an inner wall of the via hole and a conductive metal paste filled in the via hole. | 11-03-2011 |
20110266672 | INTEGRATED-CIRCUIT ATTACHMENT STRUCTURE WITH SOLDER BALLS AND PINS - An integrated-circuit attachment structure comprises an integrated circuit and a package assembly. The package assembly includes a package containing the integrated circuit. The package has pins at its corners and a grid at least primarily of solder halls on its bottom face. | 11-03-2011 |
20110272803 | SILICON CONTACTOR INCLUDING PLATE TYPE POWDERS FOR TESTING SEMICONDUCTOR DEVICE - A silicon contactor of which a side contacts test terminals of a semiconductor testing device and of which an other side contacts ball leads of a semiconductor device so as to be used in the semiconductor testing device, including: conductive silicon parts which are formed opposite to the ball leads and/or the test terminals and include silicon rubber and conductive powders; and an insulating silicon part which is formed by filling silicon rubber among areas of the conductive silicon parts, which do not contact the ball leads, and supports the conductive silicon parts, wherein the conductive powders of the conductive silicon parts include plate type powders. Therefore, the plate type powders are used as the conductive powders of the conductive silicon parts to improve contact characteristics between the conductive silicon parts and the semiconductor device. | 11-10-2011 |
20110272804 | SELECTING CHIPS WITHIN A STACKED SEMICONDUCTOR PACKAGE USING THROUGH-ELECTRODES - A stacked semiconductor package includes first and second semiconductor chips including semiconductor chip bodies which have circuit units, first through-electrodes which pass through the semiconductor chip bodies at first positions, and second through-electrodes which pass through the semiconductor chip bodies at second positions and provide a chip enable signal to the circuit units. A spacer including a spacer body may be interposed between the first semiconductor chip and the second semiconductor chip, with an inverter chip embedded in the spacer body. Wiring patterns formed on the spacer body may connect the first through-electrodes of the first semiconductor chip with the second through-electrodes of the second semiconductor chip, the first through-electrodes of the first semiconductor chip with input terminals of the inverter chip, and output terminals of the inverter chip with the second through-electrodes of the first semiconductor chip. | 11-10-2011 |
20110272805 | SEMICONDUCTOR PACKAGE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR MODULE - A semiconductor package, a semiconductor device, and a semiconductor module, the semiconductor package including a substrate, the substrate having a plurality of inner pads; a semiconductor chip attached to the substrate, the semiconductor chip being electrically connected to the inner pads; a plurality of lands on the substrate, the plurality of lands being electrically connected to the inner pads; and at least one bypass interconnection on the substrate, wherein the plurality of lands includes a first land and a second land, the bypass interconnection is connected to the first land and the second land, and the first land is spaced apart from the second land by a distance of about three times or greater an average distance between adjacent lands of the plurality of lands. | 11-10-2011 |
20110272806 | SEMICONDUCTOR DICE INCLUDING AT LEAST ONE BLIND HOLE, WAFERS INCLUDING SUCH SEMICONDUCTOR DICE, AND INTERMEDIATE PRODUCTS MADE WHILE FORMING AT LEAST ONE BLIND HOLE IN A SUBSTRATE - Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material. | 11-10-2011 |
20110272807 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING A CAVITY - An integrated circuit packaging system includes: a carrier, having a carrier top side and a carrier bottom side, without an active device attached to the carrier bottom side; an interconnect over the carrier; and a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation, and with the carrier top side partially exposed with the cavity. | 11-10-2011 |
20110278724 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate. | 11-17-2011 |
20110278725 | STACKING OF TRANSFER CARRIERS WITH APERTURE ARRAYS AS INTERCONNECTION JOINTS - An interconnection mechanism between plated through holes is disclosed, a first embodiment includes a first substrate having a first plated through hole; a second substrate having a second plated through hole; a metal core is configured in between the two plated through holes; the metal ball has a diameter larger than a diameter of the plated through holes; and melted solder binds the first plated through hole, metal core, and the second plated through hole. A second embodiment includes stacked substrate having a gold plated only on ring pads of the plated through holes; melted solder binds the two gold ring pads. | 11-17-2011 |
20110291273 | CHIP BUMP STRUCTURE AND METHOD FOR FORMING THE SAME - A chip bump structure is formed on a substrate. The substrate includes at least one contact pad and a dielectric layer. The dielectric layer has at least one opening. The at least one opening exposes the at least one contact pad. The chip bump structure includes at least one elastic bump, at least one first metal layer, at least one second metal layer, and at least one solder ball. The at least one elastic bump covers a central portion of the at least one contact pad. The at least one first metal layer covers the at least one elastic bump. The at least one first metal layer has a portion of the at least one contact pad. The portion of the at least one contact pad is not overlaid by the at least one elastic bump. The at least one second metal layer is formed on a portion of the at least one first metal layer. The portion of the at least one first metal layer is located on the top of the at least one elastic bump. The at least one solder ball is formed on the at least one second metal layer. The at least one solder ball is also on the top of the at least one elastic bump. | 12-01-2011 |
20110291274 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. One embodiment provides a carrier. Semiconductor chips are placed over the carrier. The semiconductor chips include contact elements. A polymer material is applied over the semiconductor chips and the carrier. The polymer material is removed until the contact elements are exposed. The carrier is removed from the semiconductor chips. | 12-01-2011 |
20110291275 | METHOD OF ASSEMBLING CHIPS - A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material. | 12-01-2011 |
20110298125 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a pillar ball; mounting an interposer having a first functional side and a second functional side over the pillar ball and a semiconductor chip; encapsulating the interposer, the pillar ball, and the semiconductor chip with an encapsulation; forming a via through the first functional side and the second functional side of the interposer, and through the encapsulation to expose a portion of the pillar ball; and filling the via with a pillar post. | 12-08-2011 |
20110298126 | CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD - A method for fabricating a carrier-free semiconductor package includes: half-etching a metal carrier to form a plurality of recess grooves and a plurality of metal studs each serving in position as a solder pad or a die pad; filing each of the recess grooves with a first encapsulant; forming on the metal studs an antioxidant layer such as a silver plating layer or an organic solderable protection layer; and performing die-bonding, wire-bonding and molding processes respectively to form a second encapsulant encapsulating the chip. The recess grooves are filled with the first encapsulant to enhance the adhesion between the first encapsulant and the metal carrier, thereby solving the conventional problem of having a weak and pliable copper plate and avoiding transportation difficulty. The invention eliminates the use of costly metals as an etching resist layer to reduce fabrication cost, and further allows conductive traces to be flexibly disposed on the metal carrier to enhance electrical connection quality. | 12-08-2011 |
20110298127 | Semiconductor Device - A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer. A plurality of first pad electrodes among the plurality of pad electrodes are arranged on an outer circumference of the semiconductor substrate to be along a first side of the semiconductor substrate, a plurality of first ball electrodes among the plurality of ball electrodes are arranged on an outer circumference of the rewiring layer to be along the first side, and any one of the plurality of first ball electrodes is connected to the first pad electrode positioned below the corresponding ball electrode through the contact wiring lines, and the first pad electrodes are not disposed on the lower side of the first ball electrodes positioned at an end of the first side. | 12-08-2011 |
20110298128 | MULTI-CHIP PACKAGE WITH PILLAR CONNECTION - A semiconductor device has a substrate having a first plurality of substrate bonding pads disposed on a bonding surface thereof. A plurality of semiconductor dice is disposed on the substrate. Each die of the plurality of dice has a first plurality of die bonding pads arranged along at least one first edge thereof. A plurality of bonding pillars extends substantially vertically from the substrate bonding pads. Each bonding pillar electrically connects one of the first plurality of substrate bonding pads to a corresponding one of the first plurality of die bonding pads. A method of assembling a semiconductor device is also described. | 12-08-2011 |
20110298129 | STACKED PACKAGE - A stacked package for an electronic device and a method of manufacturing the stacked package include a first semiconductor package being formed with a first conductive pad and a second conductive pad. A second semiconductor package is formed with a third conductive pad and a fourth conductive pad and is disposed over the first semiconductor package. A first conductive connecting member electrically connects the first conductive pad and the third conductive pad. A second conductive connection member electrically connects the second conductive pad and the fourth conductive pad. | 12-08-2011 |
20110298130 | SEMICONDUCTOR DEVICES WITH THROUGH-SILICON VIAS - Through silicon vias (TSVs) include a first metal plug having a cylindrical shape, passing through a semiconductor substrate, and with an outer peripheral surface surrounded by a first insulating film; an isolated semiconductor substrate in the semiconductor substrate and surrounding a first metal plug surrounded by a first insulating film; and a second metal plug surrounding the isolated semiconductor substrate and being surrounded by a second insulating film. A first bias voltage is applied to the isolated semiconductor substrate so that a depletion layer is formed in the isolated semiconductor substrate from an interface between the isolated semiconductor substrate and the first insulating film. The first bias voltage is different from a second bias voltage applied to the semiconductor substrate, which is a main semiconductor substrate, with a device forming area where transistors constituting circuits are formed. | 12-08-2011 |
20110304044 | STACKED CHIP PACKAGE STRUCTURE AND ITS FABRICATION METHOD - A stacked chip package structure includes: a first chip and a second chip stacked on a substrate; a first electrical connection structure electrically connecting the substrate and the first chip; and a second electrical connection structure electrically connecting the second chip and the first chip, wherein the second electrical connection structure, disposed on a third chip, includes an adhesive layer encapsulating a second solder ball structure on the second chip and a first solder ball structure on the first chip; and a plurality of conductive wires disposed in the adhesive layer for conducting the second solder ball structure and the first solder ball structure. A fabrication method for the stacked chip package structure is also disclosed. Forming conductive wires in the adhesive layer electrically connecting the upper and lower chips may improve potential problems caused when using wire bonding technology for the upper chip during stacking of the multilayer chips. | 12-15-2011 |
20110304045 | THERMALLY ENHANCED ELECTRONIC PACKAGE AND METHOD OF MANUFACTURING THE SAME - A thermally enhanced electronic package comprises a chip, a substrate, an adhesive, and an encapsulation. The adhesive or the encapsulation is mixed with carbon nanocapsules. The substrate includes an insulation layer and a wiring layer formed on the substrate. The adhesive covers the chip and the substrate. The chip is electrically connected to the wiring layer. The encapsulation covers the chip and the substrate. | 12-15-2011 |
20110304046 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - A semiconductor element ( | 12-15-2011 |
20110309501 | SEMICONDUCTOR PACKAGE MODULE AND ELECTRIC CIRCUIT ASSEMBLY WITH THE SAME - Disclosed herein is a semiconductor package module. The semiconductor package module includes a circuit substrate having an external connection pattern; electronic components mounted on the circuit substrate; a molding structure having a structure surrounding the circuit substrate so as to seal the electronic components from the external environment; and an external connection structure of which one portion is connected to the external connection pattern and the other portion is exposed to the outside of the molding structure. | 12-22-2011 |
20110309502 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire. | 12-22-2011 |
20110309503 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprises a semiconductor chip having a plurality of electrode pads; an insulation layer having one or more apertures which expose at least a part of the plurality of electrode pads respectively on the semiconductor chip; and a plurality of wires which are electrically connected to the exposed plurality of electrode pads. | 12-22-2011 |
20110309504 | STACK PACKAGE - A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines. | 12-22-2011 |
20110309505 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor integrated circuit device ( | 12-22-2011 |
20110316155 | SEMICONDUCTOR PACKAGING SYSTEM WITH MULTIPART CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a semiconductor packaging system includes: providing a substrate; mounting a semiconductor chip to the substrate; mounting a pillar ball having a ball height electrically connected to the substrate; mounting an interposer above the semiconductor chip and electrically connected to the pillar ball; and wherein: mounting the interposer or mounting the substrate includes connecting the pillar ball to a pillar base having a base height substantially less than the ball height of the pillar ball and the pillar base having vertical sides not covered by the pillar ball. | 12-29-2011 |
20110316156 | Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect - A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL. | 12-29-2011 |
20110316157 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a semiconductor chip; a sealing resin layer formed on the semiconductor chip; and a post electrode formed in a through-hole penetrating through the sealing resin layer in a thickness direction, and having a hemispheric top surface. | 12-29-2011 |
20120001327 | Ball Grid Array with Improved Single-Ended and Differential Signal Performance - An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns. | 01-05-2012 |
20120001328 | CHIP-SIZED PACKAGE AND FABRICATION METHOD THEREOF - A chip-sized package and a fabrication method thereof are provided. The method includes forming a protection layer on an active surface of a chip and attaching a non-active surface of the chip to a carrier made of a hard material; performing a molding process and removing a protection layer from the chip; performing an RDL process to prevent problems as encountered in the prior art, such as softening of adhesive films, an encapsulant overflow, a pliable chip and chip deviation or contamination caused by directly adhering the active surface of the chip to the adhesive film that may even lead to inferior electrical contacts between a circuit layer and a plurality of chip bond pads during subsequent RDL process, and cause the package to be scraped. Further, the carrier employed in this invention can be repetitively used in the process to help reduce manufacturing costs. | 01-05-2012 |
20120001329 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump electrically connecting the first pad to the second pad, and a second bump mechanically connecting the first substrate to the second substrate is disposed between the first substrate where the first pad is not formed and the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump. | 01-05-2012 |
20120013006 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A fabrication method of a chip scale package is provided, which includes forming a protection layer on the active surface of a chip and fixing the inactive surface of the chip to a transparent carrier; performing a molding process; removing the protection layer from the chip and performing a redistribution layer (RDL) process, thereby solving the conventional problems caused by directly attaching the chip on an adhesive film, such as film-softening caused by heat, encapsulant overflow, warpage, chip deviation and contamination that lead to poor electrical connection between the wiring layer formed in the RDL process and the chip electrode pads and even waste product as a result. Further, the transparent carrier employed in the invention can be separated by laser and repetitively used in the process to help reduce the fabrication cost. | 01-19-2012 |
20120013007 | PACKAGE-ON-PACKAGE SEMICONDUCTOR PACKAGE HAVING SPACERS DISPOSED BETWEEN TWO PACKAGE SUBSTRATES - A Package-on-Package (POP) semiconductor package has a structure in which a second semiconductor package is stacked on a first semiconductor package. A plurality of spacers are disposed between a first substrate of the first semiconductor package and a second substrate of the second semiconductor package so as to maintain a gap between the first substrate and the second substrate. The plurality of spacers may project from a bottom surface of the second substrate toward the first substrate, or may project from a top surface of the first substrate toward the second substrate. When an upper molding layer is formed on the second substrate so as to cover a second semiconductor chip, the plurality of spacers may be connected to the upper molding layer via through holes that vertically pass through the second substrate. When a first semiconductor chip is adhered to the top surface of the first substrate with an adhering layer, the plurality of spacers may be connected to the adhering layer on the top surface of the first substrate. | 01-19-2012 |
20120018884 | Semiconductor package structure and forming method thereof - The present invention provides a semiconductor package structure, which includes a substrate having a top surface and a back surface, a plurality of first connecting points on the top surface and a plurality of second connecting points on the back surface; a chip having an active surface and back surface, a plurality of pads on the active surface, and the chip is attached on the top surface of the substrate; a plurality of wires is electrically connected the plurality of pads on the active surface of the chip with the plurality of first connecting points on the top surface of substrate; a first encapsulant is filled to cover portion of the plurality of wires, the chip, and the portion of top surface of the substrate; a second encapsulate is filled to cover the first encapsulant, the plurality of wires and is formed on portion of the top surface of the substrate, in which the Yang's module of the second encapsulant is different with that of the first encapsulant; and a plurality of connecting components is disposed on the back surface of the substrate and is electrically connected the plurality of second connecting points. | 01-26-2012 |
20120018885 | SEMICONDUCTOR APPARATUS HAVING THROUGH VIAS - A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate. | 01-26-2012 |
20120018886 | INTEGRATED CIRCUIT PACKAGE WITH OPEN SUBSTRATE AND METHOD OF MANUFACTURING THEREOF - A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer. | 01-26-2012 |
20120018887 | MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height. | 01-26-2012 |
20120025375 | ROUTABLE ARRAY METAL INTEGRATED CIRCUIT PACKAGE FABRICATED USING PARTIAL ETCHING PROCESS - An integrated circuit assembly is fabricated on a metal substrate strip in an array format that has raised circuitry pattern formed by photolithographic and metal etching processes. The circuitry pattern is formed on one side of the metal substrate only. The raised circuitry's etch depth extends partially through the metal substrate. Die attachment can be performed using a non-conductive material applied directly onto and around the raised circuitry features directly under the die. After wirebond and molding processes, the molded metal substrate strip assembly is processed through a metal etching process to remove the metal substrate portion that is exposed beyond the mold cap. A solder mask coating can be applied to protect the metal circuitry and to define the package pad opening to form Land-Grid-Array (LGA) packages. Solder balls can also be attached to form Ball-Grid-Array (BGA) packages. | 02-02-2012 |
20120025376 | BALL GRID ARRAY PACKAGE - A BGA package includes an IC die, a substrate, a plurality of solder balls, and a square contact pad. The portions of the contact pad capable of interfering with the IC die are removed to ensure the space between two of the contact pads is sufficient to avoid noise interference. | 02-02-2012 |
20120025377 | SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING A WIRING OF A SEMICONDUCTOR DEVICE - A semiconductor device has an LSI chip including a semiconductor substrate, an LSI core section provided at a center portion of the semiconductor substrate and serving as a multilayered wiring layer of the semiconductor substrate, a first rewiring layer provided adjacent to an outer periphery of the LSI core section on the semiconductor substrate and including a plurality of wiring layers, a first pad electrode disposed at an outer periphery of the first rewiring layer, and an insulation layer covering the first pad electrode. The semiconductor device includes a second rewiring layer provided on the LSI chip and including a rewiring connected to the first pad electrode. The semiconductor device includes a plurality of ball electrodes provided on the second rewiring layer. The first rewiring layer is electrically connected to the LSI core section and the first pad electrode. | 02-02-2012 |
20120032326 | AIR THROUGH-SILICON VIA STRUCTURE - A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate. | 02-09-2012 |
20120032327 | SYSTEMS AND METHODS FOR REINFORCING CHIP PACKAGES - In accordance with some embodiments of the present disclosure, a chip package is provided. The chip package may include a chip, a substrate, and an interconnect layer disposed between the chip and the substrate. In some embodiments, the interconnect layer may include an array of bonding interconnects configured to provide electrical communication between the chip and a printed circuit board and reinforcement interconnects arranged around an outermost row of the array of bonding interconnects. | 02-09-2012 |
20120032328 | Package structure with underfilling material and packaging method thereof - A method for packaging semiconductor device is provided, which comprises: providing a carrier substrate having a top surface and a back surface, a circuit arrangement on the top surface of the carrier substrate, and a through hole is disposed near the center of the carrier substrate and is formed passed through the carrier substrate; providing a chip having an active surface and a back surface, a plurality of pads is disposed on the periphery of the active surface and a plurality of connecting elements is disposed thereon; the active surface of chip is flipped and bonded on the circuit arrangement on the top surface of the carrier substrate, and the plurality of connecting elements is not covering the through hole; filling the underfilling material to encapsulate between the plurality of connecting elements and the top surface of the carrier substrate and to fill with the through hole; and performing a suction process to remove the air within the underfilling material between the plurality of connecting elements on the chip and the top surface of the carrier substrate, such that the underfilling material can completely encapsulate between the plurality of connecting elements on the chip and the top surface of the carrier surface. | 02-09-2012 |
20120032329 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate). | 02-09-2012 |
20120032330 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS - Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations. | 02-09-2012 |
20120038044 | CHIP SCALE PACKAGE AND FABRICATION METHOD THEREOF - A CSP includes: a hard board having a first wiring layer with conductive pads; a plurality of conductive elements disposed on at least a portion of the conductive pads; an electronic component having opposite active and inactive surfaces and being mounted on the hard board via the inactive surface; an encapsulating layer disposed on the hard board for encapsulating the conductive elements and electronic component, the active surface of the electronic component and the surfaces of the conductive elements being exposed through the encapsulating layer; a first dielectric layer and a third wiring layer disposed on the encapsulating layer, the third wiring layer being electrically connected to the conductive elements and the electronic component and further electrically connected to the first wiring layer through the conductive elements, thereby obtaining a stacked connection structure without the need of PTHs and using the hard board as a main structure to avoid warpage. | 02-16-2012 |
20120038045 | Stacked Semiconductor Device And Method Of Fabricating The Same - A stacked semiconductor device may have a plurality of chips stacked in three-dimension. The stacked semiconductor device may include a first semiconductor chip and at least one second semiconductor chip. The first semiconductor chip may include a plurality of first through silicon vias (TSVs). The at least one second semiconductor chip may include a plurality of second TSVs. The at least one second semiconductor chip may be stacked above the first semiconductor chip and may be thinner than the first semiconductor chip. Therefore, the stacked semiconductor device may have an improved reliability. | 02-16-2012 |
20120043655 | WAFER-LEVEL PACKAGE USING STUD BUMP COATED WITH SOLDER - A method of fabricated a wafer level package is described. In one embodiment, the method includes fabricating at least one active device on a semiconductor wafer that has not been singulated, with the active device having a plurality of bonding pads exposed at an upper surface of the wafer. Prior to singulating the semiconductor wafer, a plurality of corresponding stud bumps on the plurality of bonding pads with a wire bonding tool are formed. Thereafter, a molding encapsulation layer is applied over the semiconductor wafer leaving an upper portion of each of the plurality of stud bumps exposed. | 02-23-2012 |
20120043656 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE - An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch. | 02-23-2012 |
20120061832 | COLLAR STRUCTURE AROUND SOLDER BALLS THAT CONNECT SEMICONDUCTOR DIE TO SEMICONDUCTOR CHIP PACKAGE SUBSTRATE - In one embodiment, a collar structure includes a non-conductive layer that relieves stress around the perimeter of each of the solder balls that connect the semiconductor die to the semiconductor chip package substrate, and another non-conductive layer placed underneath to passivate the entire surface of the die. | 03-15-2012 |
20120061833 | EMBEDDED BALL GRID ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad. | 03-15-2012 |
20120061834 | SEMICONDUCTOR CHIP, STACKED CHIP SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND FABRICATING METHOD THEREOF - A semiconductor chip includes a silicon wafer formed with a via hole, a metal wire disposed in the via hole, and a filler that exposes a part of an upper portion of the metal wire while filing the via hole. | 03-15-2012 |
20120068338 | IMPEDANCE CONTROLLED PACKAGES WITH METAL SHEET OR 2-LAYER RDL - A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential. | 03-22-2012 |
20120068339 | VLSI Package for High Performance Integrated Circuit - A packaged integrated circuit is presented for placement on a printed circuit board (PCB) layer providing power lines and data access channels. The packaged integrated circuit includes; a package substrate having data channels and power lines; a circuit substrate having functional components, wherein (a) the power lines and the data channels in the package substrate are coupled to the functional components of the substrate by conducting bumps, (b) the conducting balls coupling the data access channels in the PCB to the data channels in the package substrate are located along the edges of the package substrate; and (c) the conducting balls coupling the power lines in the PCB and the power lines in the package substrate are located in an interior portion of the package substrate. Also, an integrated circuit may further include a circuit substrate having active components, including a SerDes circuit at a center portion of the substrate. | 03-22-2012 |
20120068340 | Ball grid array semiconductor package and method of manufacturing the same - Provided is a BGA semiconductor package including: a substrate on which a semiconductor device is mounted; an adhesive for adhering the semiconductor device and the substrate to each other; a micro ball having conductivity, the micro ball being fitted into a through-hole provided in the substrate; a bonding wire for electrically connecting the semiconductor device and the micro ball to each other; and an encapsulation member for encapsulating, with an encapsulation resin, the semiconductor device, the adhesive, a part of the micro ball, and the bonding wire, only on a surface side of the substrate on which the semiconductor device is mounted, in which at least a part of a bottom surface of the micro ball has an exposed portion as an external connection terminal, which is exposed through the through-hole provided in the substrate as a bottom surface of the encapsulation member. | 03-22-2012 |
20120068341 | Method for Depackaging Prepackaged Integrated Circuit Die and a Product from the Method - A method for providing a known good integrated circuit die having enhanced planarity from a prepackaged integrated circuit die having a surface warpage such as in a ball grid array (BGA) package is provided. A partially-depackaged integrated circuit package is affixed to a substrate with a spacer element there between such that the active surface of the die within the partially depackaged integrated circuit die is “bowed” slightly upwardly to define a convex surface. The exposed encapsulant on the now-convex surface of the mounted, partially-depackaged integrated circuit package is then lapped or ground away to a predetermined depth so that an integrated circuit die is provided having an enhanced planarity and surface uniformity. | 03-22-2012 |
20120074566 | Package For Semiconductor Device Including Guide Rings And Manufacturing Method Of The Same - An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate. | 03-29-2012 |
20120074567 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Between Non-Linear Portions of Conductive Layers - A semiconductor device is made by forming a first conductive layer over a first temporary carrier having rounded indentations. The first conductive layer has a non-linear portion due to the rounded indentations. A bump is formed over the non-linear portion of the first conductive layer. A semiconductor die is mounted over the carrier. A second conductive layer is formed over a second temporary carrier having rounded indentations. The second conductive layer has a non-linear portion due to the rounded indentations. The second carrier is mounted over the bump. An encapsulant is deposited between the first and second temporary carriers around the first semiconductor die. The first and second carriers are removed to leave the first and second conductive layers. A conductive via is formed through the first conductive layer and encapsulant to electrically connect to a contact pad on the first semiconductor die. | 03-29-2012 |
20120086122 | Semiconductor Device And Semiconductor Package Having The Same - The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process. | 04-12-2012 |
20120086123 | SEMICONDUCTOR ASSEMBLY AND SEMICONDUCTOR PACKAGE INCLUDING A SOLDER CHANNEL - Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction. | 04-12-2012 |
20120086124 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to this embodiment has an electrode (electrode pad) and an insulative film (protective resin film) formed on the electrode and having an opening for exposing the electrode. The semiconductor device further has an under bump metal (UBM layer) formed over the insulative film and connected with the electrode through the opening, and a solder ball formed over the under bump metal, and the contour line at the lower end of the solder ball is situated inside the contour line of the under bump metal, whereby generation of fracture in the insulative film caused by the stress upon mounting the semiconductor device is suppressed even when the solder ball is formed of a lead-free solder. | 04-12-2012 |
20120086125 | Semiconductor Having Chip Stack, Semiconductor System, and Method of Fabricating the Semiconductor Apparatus - In one embodiment, a semiconductor device includes a plurality of semiconductor chip stacks mounted on a substrate. Bonding terminals disposed on the substrate correspond to the chip stacks, such that at least one chip in each chip stack may be directly connected to a bonding terminal on the substrate and at least one chip in the chip stack is not directly connected to the bonding terminal. The semiconductor chip stacks may each act as one semiconductor device to the outside. | 04-12-2012 |
20120091584 | BUMP FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE HAVING BUMP, AND STACKED SEMICONDUCTOR PACKAGE - A bump for a semiconductor package includes: a first bump formed on a semiconductor chip and having at least two land parts and a connection part which connects the land parts and has a line width smaller than the land parts; and a second bump formed on the first bump and projecting on the land parts of the first bump in shapes of a hemisphere. | 04-19-2012 |
20120091585 | LASER RELEASE PROCESS FOR VERY THIN SI-CARRIER BUILD - A laser release and glass chip removal process for a integrated circuit module avoiding carrier edge cracking is provided. | 04-19-2012 |
20120098129 | METHOD OF MAKING A MULTI-CHIP MODULE HAVING A REDUCED THICKNESS AND RELATED DEVICES - A method of making a multi-chip module may include forming an interconnect layer stack on a sacrificial substrate. The interconnect layer stack may include patterned electrical conductor layers and a dielectric layer between adjacent patterned electrical conductor layers. The method may further include electrically coupling a first integrated circuit (IC) die in a flip chip arrangement to an uppermost patterned electrical conductor layer, and forming a first underfill dielectric layer between the first IC die and adjacent portions of the interconnect layer stack. The method further may include removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at a second integrated circuit die in a flip chip arrangement to the lowermost patterned electrical conductor layer. Still further, the method may include forming a second underfill dielectric layer between the second IC die and adjacent portions of the interconnect layer stack. | 04-26-2012 |
20120098130 | LEAD-FREE STRUCTURES IN A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor die and lead-free solder bumps disposed on a surface of the semiconductor die. A substrate includes metal layers and dielectric layers. One of the metal layers includes contact pads corresponding to lead-free solder bumps, and one of the dielectric layers is an exterior dielectric layer having respective openings for the contact pad. Respective copper posts are disposed on the contact pads. The respective copper post for each contact pad extends from the contact pad through the respective opening for the contact pad. The semiconductor die is mounted on the substrate with connections between the lead-free solder bumps and the copper posts. | 04-26-2012 |
20120104604 | CRACK ARREST VIAS FOR IC DEVICES - An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads. | 05-03-2012 |
20120104605 | Chip Design having Integrated Fuse and Method for the Production Thereof - A chip design ( | 05-03-2012 |
20120104606 | BALL GRID ARRAY SEMICONDUCTOR DEVICE AND ITS MANUFACTURE - A semiconductor device includes: stacked semiconductor chips having respective input/output pads on surfaces thereof; a lower resin body molding the lower semiconductor chip and having a surface coplanar with the lower chip; an upper resin body molding the upper chip and coupled with the first resin body; wirings connected to input/output pads of the lower or upper chip and extending horizontally; external connection metal posts formed on the wirings and having tops exposed from the second resin body; and ball-shaped external connection terminals connected to the tops of the external connection metal posts. | 05-03-2012 |
20120104607 | STACKED SEMICONDUCTOR PACKAGES AND RELATED METHODS - The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer. | 05-03-2012 |
20120104608 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF - In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability. | 05-03-2012 |
20120112345 | HIGH BANDWIDTH SEMICONDUCTOR BALL GRID ARRAY PACKAGE - A high bandwidth semiconductor printed circuit board assembly (PCBA) providing a layer of dielectric substrate containing plated vias with an upper and lower surface plated with etched copper, mated with a second layer of etched copper plated dielectric containing plated vias that is placed on the top surface of the first layer. A third layer of etched copper plated dielectric containing plated vias may be placed on the bottom layer of etched copper foil. A base layer of etched copper plated thick dielectric containing plated vias is laminated simultaneously with the preceding layers to provide the high bandwidth digital and RF section of the assembly. | 05-10-2012 |
20120119362 | NI PLATING OF A BLM EDGE FOR PB-FREE C4 UNDERCUT CONTROL - A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer. | 05-17-2012 |
20120119363 | GRAIN REFINEMENT BY PRECIPITATE FORMATION IN Pb-FREE ALLOYS OF TIN - Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature. | 05-17-2012 |
20120126406 | USING BUMP BONDING TO DISTRIBUTE CURRENT FLOW ON A SEMICONDUCTOR POWER DEVICE - A semiconductor power chip may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; a plurality of ball bumps or a loaf bump disposed on each of the plurality of second elements and the plurality of third elements; and at least one ball bump or loaf on the at least one first contact element. | 05-24-2012 |
20120126407 | WAFER LEVEL CHIP PACKAGE AND A METHOD OF FABRICATING THEREOF - Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies. | 05-24-2012 |
20120139108 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate including a first wiring embedded in the package substrate, a second wiring embedded in the package substrate, the second wiring electrically insulated from the first wiring, and a capacitor embedded in the package substrate, the capacitor including a first electrode electrically connected to the first wiring and a second electrode electrically connected to the second wiring. At least a first semiconductor chip is disposed on the package substrate. A plurality of connection terminals are disposed between the package substrate and the first semiconductor chip and contact the package substrate, and form at least a first group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the first wiring, and at least a second group of at least two connection terminals formed continuously adjacent to each other and electrically connected to the second wiring. | 06-07-2012 |
20120139109 | PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR PACKAGE CONFIGURED TO IMPROVE SOLDER JOINT RELIABILITY AND SEMICONDUCTOR PACKAGE HAVING THE SAME - A a printed circuit board (PCB) for a semiconductor package and a semiconductor package having the same, which may improve adhesion of a PCB with an encapsulant. The semiconductor package includes a PCB for a semiconductor package including a resin through hole disposed in a central portion thereof and at least one resin fixing hole disposed in an outermost edge thereof, a semiconductor chip connected to first connection pads disposed on a first surface of the PCB by bumps, an upper encapsulant configured to hermetically seal the first surface of the PCB and the semiconductor chip, and a lower encapsulant protrusion configured to extend to a second surface of the PCB through the resin through hole and the resin fixing hole disposed in the first surface of the PCB. | 06-07-2012 |
20120139110 | TAPE - A tape for carrying at least a semiconductor package structure comprising a body, a carrying plate and a side wall is provided. The body has at least an opening. The carrying plate is capable of carrying the semiconductor package structure and has a plurality of containing portions. The side wall surrounds the carrying plate and connects between the body and the carrying plate. A side surface of the semiconductor package structure leans against the side wall and a plurality of solder balls disposed on a bottom surface of the semiconductor package structure are contained in the containing portion. Accordingly, the solder balls may be protected from being damaged by the carrying plate. | 06-07-2012 |
20120146218 | Semiconductor package device with cavity structure and the packaging method thereof - A semiconductor device with a cavity structure comprises: a carrier substrate; a first die having an active surface and the pads thereon; a back surface of the first die is disposed on the carrier substrate; a second die having a top surface and a back surface and a cavity structure therein; the top surface of a second die is flipped to dispose on the first die, and the cavity structure is an inverse U-type to dispose between the active surface of the first die and the top surface of the second die; the wires is electrically connected the pads with the first connecting points; a package body encapsulated the first die, the second die, the wires, and the portion of the top surface of the carrier substrate; and the connecting components is disposed on the back surface of the carrier substrate and is electrically connected the second connecting points. | 06-14-2012 |
20120146219 | WAFER-LEVEL INTERCONNECT FOR HIGH MECHANICAL RELIABILITY APPLICATIONS - An interconnect structure comprises a solder including nickel (Ni) in a range of 0.01 to 0.20 percent by weight. The interconnect structure further includes an intermetallic compound (IMC) layer in contact with the solder. The IMC layer comprises a compound of copper and nickel. | 06-14-2012 |
20120153470 | BGA PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A BGA package structure and a method for fabricating the same, wherein the BGA package structure comprises: a substrate having a first surface used to carry a chip and a second surface opposite to the first surface, wherein the substrate is divided into several regions according to different distances from a central point of the substrate; a plurality of contact bonding pads on the second surface electrically connected with the chip; and a plurality of bumps respectively attached to each of the contact bonding pads, wherein the contact bonding pads and bumps in a region which is closest to the central point are the smallest, while the contact bonding pads and bumps in a region which is farthest to the central point are the biggest. Therefore the situation that the bumps at the edge are liable to peel off may improved. | 06-21-2012 |
20120153471 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device according to the present embodiment includes a substrate including wirings. At least one first semiconductor chip is mounted on a first surface of the substrate and is electrically connected to any of the wirings. A first metal ball is provided on the first surface of the substrate and is electrically connected to the first semiconductor chip through any of the wirings. A first resin seals the wirings, the first semiconductor chip, and the first metal ball on the first surface of the substrate. A top of the first metal ball protrudes from a surface of the first resin and is exposed. | 06-21-2012 |
20120153472 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 06-21-2012 |
20120161315 | THREE-DIMENSIONAL SYSTEM-IN-PACKAGE PACKAGE-ON-PACKAGE STRUCTURE - The present invention provides a three-dimensional System-In-Package (SIP) Package-On-Package (POP) structure comprising a support element formed around a first electronic device. A filling material is filled between the first electronic device and the support element. Signal channels are coupled to first die pads of the first electronic device. Conductive elements form signal connection between the first end of the signal channels and the second die pads of a second electronic device. | 06-28-2012 |
20120161316 | SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE - A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate. | 06-28-2012 |
20120161317 | AREA ARRAY SEMICONDUCTOR DEVICE PACKAGE INTERCONNECT STRUCTURE WITH OPTIONAL PACKAGE-TO-PACKAGE OR FLEXIBLE CIRCUIT TO PACKAGE CONNECTION - An area array integrated circuit (IC) package for an IC device. The IC package includes a first substrate with conductive traces electrically coupled to the IC device. An interconnect assembly having a first surface is mechanically coupled to the first substrate. The interconnect assembly includes a plurality of contact members electrically coupled to the conductive traces on the first substrate. A second substrate is mechanically coupled to a second surface of the interconnect assembly so that the first substrate, the interconnect assembly, and the second substrate substantially surround the IC device. The second substrate includes conductive traces that are electrically coupled to the contact members in the interconnect assembly. | 06-28-2012 |
20120168942 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120168943 | PLASMA TREATMENT ON SEMICONDUCTOR WAFERS - A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package. | 07-05-2012 |
20120168944 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120168945 | CHIP PACKAGE STRUCTURE AND CHIP PACKAGING PROCESS - A chip package structure includes a silicon substrate, a sensing component, a metal circuit layer, a first insulating layer and a conductive metal layer. The silicon substrate has opposite first and second surfaces. The sensing component is disposed on the first surface. The metal circuit layer is disposed on the first surface and electrically connected to the sensing component. The first insulating layer covers the second surface and has a first through hole to expose a portion of the second surface. The conductive metal layer is disposed on the first insulating layer and includes first leads and a second lead. The first leads are electrically connected to the metal circuit layer. The second lead is filled in the first through hole to electrically connect to the silicon substrate and one of the first leads. A chip packaging process for fabricating the chip package structure is also provided. | 07-05-2012 |
20120168946 | SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR - A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm. | 07-05-2012 |
20120168947 | Methods and Designs for Localized Wafer Thinning - Methods for localized thinning of wafers used in semiconductor devices and the structures formed from such methods are described. The methods thin localized areas of the backside of the semiconductor wafer to form recesses with a bi-directional channel design that is repeated within the wafer (or die) so that no straight channel line crosses the wafer (or die). The bi-directional pattern design keeps the channels from being aligned with the crystal orientation of the wafer. The recesses are then filled by a solder ball drop process by dropping proper size solder balls into the recesses and then annealing the wafer to reflow the solder balls and flatten them out. The reflow process begins to fill in the recesses from the bottom up, thereby avoiding void formation and the resulting air traps in the reflowed solder material. Other embodiments are also described. | 07-05-2012 |
20120168948 | COPPER PILLAR FULL METAL VIA ELECTRICAL CIRCUIT STRUCTURE - An electrical interconnect including a first circuitry layer with a first surface and a second surface. At least a first dielectric layer is printed on the first surface of the first circuitry layer to include a plurality of first recesses. A conductive material is deposited in a plurality of the first recesses to form a plurality of first conductive pillars electrically coupled to, and extending generally perpendicular to, the first circuitry layer. At least a second dielectric layer is printed on the first dielectric layer to include a plurality of second recesses generally aligned with a plurality of the first conductive pillars. A conductive material is deposited in a plurality of the second recesses to form a plurality of second conductive pillars electrically coupled to, and extending parallel the first conductive pillars. | 07-05-2012 |
20120175772 | ALTERNATIVE SURFACE FINISHES FOR FLIP-CHIP BALL GRID ARRAYS - A ball grid array package device includes a substrate with a copper ball grid array pad formed on the substrate. A nickel layer may be formed on the copper pad and a tin layer formed on the nickel layer. The nickel layer may be formed using an electroless nickel plating process. The tin layer may be formed using an immersion tin process. In some cases, silver may be used instead of tin and formed using an immersion silver process. | 07-12-2012 |
20120175773 | Thermal Enhanced Package Using Embedded Substrate - An integrated circuit (IC) device is provided. The IC device includes an IC die having opposing first and second surfaces, a carrier coupled to the first surface of the IC die, a laminate coupled to the carrier and the second surface of the IC die, and a trace located on a surface of the laminate and electrically coupled to a bond pad located on the second surface of the IC die. The trace is configured to couple the bond pad to a circuit board. | 07-12-2012 |
20120181691 | PACKAGE STRUCTURE, PACKAGING SUBSTRATE AND CHIP - The present invention relates to a package structure, a packaging substrate and a chip. The package structure includes: a chip including a plurality of electrode pads on a surface thereof; a packaging substrate including a plurality of first conductive pads on a surface thereof; and a plurality of connecting units through which the electrode pads electrically communicate with the first conductive pads, in which the chip or the packaging substrate further includes a first surface finish layer over the electrode pads or the first conductive pads, and the first surface finish layer includes a Ni—Pd alloy layer. Accordingly, the surface finish method applied in a package structure, a packaging substrate and a chip has advantages of simple manufacture, low cost and high reliability. | 07-19-2012 |
20120187560 | SEMICONDUCTOR CHIP MODULE, SEMICONDUCTOR PACKAGE HAVING THE SAME AND PACKAGE MODULE - A semiconductor module comprising a plurality of semiconductor chips where at least one semiconductor chip is laterally offset with respect to a second semiconductor chip, and substantially aligned with a third semiconductor chip such that an electrical connection can be made between an electrical contact in the first semiconductor chip and an electrical contact in the third semiconductor chip. | 07-26-2012 |
20120187561 | FORMING SEMICONDUCTOR CHIP CONNECTIONS - Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape. | 07-26-2012 |
20120187562 | Semiconductor Package and Method for Fabricating the Same - A semiconductor package includes a wiring substrate, a semiconductor chip, and a conductor plate in order to reduce a voltage drop at the central portion of a chip caused by wiring resistance from a peripheral connection pad disposed on the periphery of the chip. Central electrode pads for use in ground/power-supply are disposed on the central portion of the chip. The conductor plate for use in ground/power-supply is disposed on the chip such that an insulating layer is disposed therebetween. The central electrode pads on the chip and the conductor plate are connected together by wire bonding through an opening formed in the insulating layer and the conductor plate. An extraction portion of the conductor plate is connected to a power-supply wiring pad on the wiring substrate. Preferably, the conductor plate is composed of a multilayer structure, and each conductor plate is used in power-supply wiring or ground wiring. | 07-26-2012 |
20120193788 | STACKED SEMICONDUCTOR CHIPS PACKAGING - Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate. | 08-02-2012 |
20120193789 | PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF - A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element disposed on a surface thereof, a second package structure having a plurality of second metal posts and a second electronic element disposed on opposite surfaces thereof, and an encapsulant formed between the first and second package structures for encapsulating the first electronic element. By connecting the first and second metal posts, the second package structure is stacked on the first package structure with the support of the metal posts and the encapsulant filling the gap therebetween so as to prevent warpage of the substrate. | 08-02-2012 |
20120193790 | ELECTROSTATIC CHUCKING OF AN INSULATOR HANDLE SUBSTRATE - A back of a dielectric transparent handle substrate is coated with a blanket conductive film or a mesh of conductive wires. A semiconductor substrate is attached to the transparent handle substrate employing an adhesive layer. The semiconductor substrate is thinned in the bonded structure to form a stack of the transparent handle substrate and the semiconductor interposer. The thinned bonded structure may be loaded into a processing chamber and electrostatically chucked employing the blanket conductive film or the mesh of conductive wires. The semiconductor interposer may be bonded to a semiconductor chip or a packaging substrate employing C4 bonding or intermetallic alloy bonding. Illumination of ultraviolet radiation to the adhesive layer is enabled, for example, by removal of the blanket conductive film or through the mesh so that the transparent handle substrate may be detached. The semiconductor interposer may then be bonded to a packaging substrate or a semiconductor chip. | 08-02-2012 |
20120193791 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - Disclosed are: a semiconductor device that comprises a semiconductor element to which a plurality of wires are bonded, wherein bonding strength of the wires is high and sufficient bonding reliability is achieved; and a method for manufacturing the semiconductor device. Specifically disclosed is a semiconductor device which is characterized by comprising a first wire that has one end bonded onto an electrode and the other end bonded to a second bonding point that is out of the electrode, and a second wire that has one end bonded onto the first wire on the electrode and the other end bonded to a third bonding point that is out of the electrode. The semiconductor device is also characterized in that the bonded portion of the first-mentioned end of the second wire covers at least apart of the upper surface and the lateral surface of the first wire. | 08-02-2012 |
20120199973 | INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT - A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed. | 08-09-2012 |
20120199974 | Silicon-Based Thin Substrate and Packaging Schemes - A silicon-based thin package substrate is used for packaging semiconductor chips. The silicon-based thin package substrate preferably has a thickness of less than about 200 μm. A plurality of traces is formed in the silicon-based thin package substrate, connecting BGA balls and solder bumps. A semiconductor chip may be mounted on the solder bumps. The silicon-based thin package substrate may be used as a carrier of semiconductor chips. | 08-09-2012 |
20120205801 | Anti-Tamper Wrapper Interconnect Method and a Device - A method for electrically coupling an anti-tamper mesh to an electronic module or device using wire bonding equipment and a device made from the method. Stud bumps or free air ball bonds are electrically coupled to conductive mesh pads of an anti-tamper mesh. Respective module pads have a conductive epoxy disposed thereon for the receiving of the stud bumps or free air ball bonds, each of which are aligned and bonded together to electrically couple the anti-tamper mesh to predetermined module pads. | 08-16-2012 |
20120205802 | PRINTED CIRCUIT BOARD AND FLIP CHIP PACKAGE USING THE SAME WITH IMPROVED BUMP JOINT RELIABILITY - A printed circuit board and a flip chip package using the same are designed to minimize thermal stress due to different thermal coefficients present in areas having metal lines and solder resist versus other areas on the printed circuit board. The printed circuit board includes an insulation layer; a first metal line formed on one surface of the insulation layer and having at one end thereof a bump land and a projection which integrally extends from the bump land; a second metal line formed on the other surface of the insulation layer and having at one end thereof a ball land; a via metal line formed through the insulation layer to connect the first and second metal lines to each other; and solder resists formed on the upper and lower surfaces of the insulation layer to expose the bump land and the ball land. | 08-16-2012 |
20120205803 | PACKAGING CONFIGURATIONS FOR VERTICAL ELECTRONIC DEVICES USING CONDUCTIVE TRACES DISPOSED ON LAMINATED BOARD LAYERS - This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals. | 08-16-2012 |
20120217636 | Ni PLATING OF A BLM EDGE FOR Pb-FREE C4 UNDERCUT CONTROL - A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer. | 08-30-2012 |
20120217637 | SUBSTRATE FOR HIGH SPEED SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE HAVING THE SAME - The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed. | 08-30-2012 |
20120223429 | Package 3D Interconnection and Method of Making Same - An integrated circuit (IC) package has a package member having a first surface and a second surface opposite the first surface. A first plurality of contact members is physically and electrically fixed to the second surface. An interposer substrate having a second plurality of contact members on one surface thereof which make physical and electrical contact with respective ones of the first plurality of contact members. The interposer substrate is configured to have at least one circuit member mounted to a second surface thereof opposite the one surface thereof. | 09-06-2012 |
20120223430 | SOLDER BALL FOR SEMICONDUCTOR PACKAGING AND ELECTRONIC MEMBER USING THE SAME - The present invention relates to a solder ball for semiconductor packaging and an electronic member having such solder ball. Specifically there are provided: a solder ball capable of ensuring a sufficient thermal fatigue property even when a diameter thereof is not larger than 250 μm as observed in recent years; and an electronic member having such solder ball. More specifically, there are provided: a solder ball for semiconductor packaging that is made of a solder alloy containing Sn as a main element, 0.1-2.5% Ag by mass, 0.1-1.5% Cu by mass and at least one of Mg, Al and Zn in a total amount of 0.0001-0.005% by mass, such solder ball having a surface including a noncrystalline phase that has a thickness of 1-50 nm and contains at least one of Mg, Al and Zn, O and Sn, and an electronic member having such solder ball. | 09-06-2012 |
20120228768 | INTEGRATED CIRCUIT PACKAGING SYSTEM USING B-STAGE POLYMER AND METHOD OF MANUFACTURE THEREOF - An integrated circuit packaging system and method of manufacture thereof includes: a substrate having a bond pad; a B-stage polymer, having a dispersion of conductive particles therein, on the bond pad; and a bond ball inserted into the B-stage polymer for forming intermetallic structures between the bond ball and the bond pad. | 09-13-2012 |
20120228769 | CARRIER-FREE SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design. | 09-13-2012 |
20120235297 | WAFER LEVEL PACKAGING OF MEMS DEVICES - A MEMS device is disclosed. The MEMS device comprises a MEMS substrate and a CMOS substrate having a front surface, a back surface and one or more metallization layers. The front surface being bonded to the MEMS substrate. The MEMS device includes one or more conductive features on the back surface of the CMOS substrate and electrical connections between the one or more metallization layers and the one or more conductive features. | 09-20-2012 |
20120235298 | ELECTRONIC DEVICE AND METHOD FOR PRODUCING A DEVICE - An electronic device or devices and method for producing a device is disclosed. One embodiment provides an integrated component, a first package body and a contact device. The contact device penetrates the package body. | 09-20-2012 |
20120241954 | Unpackaged and packaged IC stacked in a system-in-package module - There is provided a system and method for unpackaged and packaged IC stacked in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad and a second contact pad disposed thereon, a packaged device disposed on the substrate, and an unpackaged device stacked atop the packaged device, wherein a first electrode of the packaged device is electrically and mechanically coupled to the first contact pad, and wherein a second electrode of the unpackaged device is electrically coupled to the second contact pad. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, facilitated die substitution, enhanced thermal and grounding performance through direct connect vias, stacking of wider devices without a spacer, and a simplified single package structure for reduced fabrication time and cost. | 09-27-2012 |
20120241955 | CHIP SCALE PACKAGE ASSEMBLY IN RECONSTITUTION PANEL PROCESS FORMAT - Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate. | 09-27-2012 |
20120241956 | TECHNIQUES FOR PACKAGING MULTIPLE DEVICE COMPONENTS - Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dice coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package. | 09-27-2012 |
20120241957 | MICROELECTRONIC DIE PACKAGES WITH METAL LEADS, INCLUDING METAL LEADS FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS - Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing. | 09-27-2012 |
20120248604 | SELECTIVE ELECTROMIGRATION IMPROVEMENT FOR HIGH CURRENT C4S - The invention includes embodiments of a method for designing a flip chip and the resulting structure. The starting point is a flip chip with a semiconductor substrate, one or more wiring levels, and a plurality of I/O contact pads (last metal pads/bond pads) for receiving and sending electrical current. There is also a plurality of C4 bumps for connecting the I/O contact pads to another substrate. Then it is determined which of the C4s of the plurality of C4 bumps have a level of susceptibility to electromigration damage that meets or exceeds a threshold level of susceptibility, and in response, plating a conductive structure with a high electrical current carrying capacity (such as a copper pillar, copper pedestal, or partial copper pedestal) onto the corresponding I/O contact pads and adding a solder ball to a top portion of the conductive structure. The resulting structure is a flip chip wherein only a select few C4 bumps use enhanced C4s (such as copper pedestals) reducing the chance of defects. | 10-04-2012 |
20120248605 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an electrode (electrode pad), an insulation film (for example, protective resin film) formed over the electrode and having an opening for exposing the electrode. The semiconductor device further includes an under bump metal (UBM layer) formed over the insulation film and connected by way of the opening 5 | 10-04-2012 |
20120256313 | SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS - A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball. | 10-11-2012 |
20120256314 | SHORT AND LOW LOOP WIRE BONDING - A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink. | 10-11-2012 |
20120256315 | SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR CHIP ASSEMBLY, AND METHOD FOR FABRICATING A DEVICE - A method for fabricating a device, a semiconductor chip package, and a semiconductor chip assembly is disclosed. One embodiment includes applying at least one semiconductor chip on a first form element. At least one element is applied on a second form element. A material is applied on the at least one semiconductor chip and on the at least one element. | 10-11-2012 |
20120261819 | BRIDGING ARRANGEMENT AND METHOD FOR MANUFACTURING A BRIDGING ARRANGEMENT - A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type. | 10-18-2012 |
20120261820 | ASSEMBLY OF STACKED DEVICES WITH SEMICONDUCTOR COMPONENTS - A method for forming an assembly including, stacked on each other, first and second devices with semiconductor components including opposite conductive balls, this method including the steps of: a) forming, on the first device, at least one resin pattern, close to at least some of the conductive balls by a distance smaller than or equal to half the ball diameter, and of a height greater than the ball height; and b) bonding the second device to the first device, by using said at least one pattern to guide the balls of the second device towards the corresponding balls of the first device. | 10-18-2012 |
20120261821 | WAFER LEVEL PACKAGE HAVING A STRESS RELIEF SPACER AND MANUFACTURING METHOD THEREOF - In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability. | 10-18-2012 |
20120267782 | PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE - Disclosed is a package-on-package semiconductor device comprising a bottom package, a top package thereon and a ACA (Anisotropic Conductive Adhesive) layer. A plurality of ball pads are disposed on the peripheries of an upper surface of the substrate of the bottom package. A plurality of solder balls are disposed at the peripheries of the lower surface of the substrate of the top package. The ACA layer having a central opening is interposed between the bottom package and the top package where the ACA layer contains a plurality of conductive particles. Therein, the size of the central opening and the thickness of the ACA layer are selected such that the anisotropic conductive adhesive layer adheres the peripheries of the upper surface of the bottom package to the peripheries of the lower surface of the top package and the solder balls are encapsulated inside the anisotropic conductive adhesive layer. The solder balls encapsulate some of the conductive particles to mechanically joint and electrically connect to the ball pads. Thereby, the bonding strength of the solder balls can be improved and the warpage of the substrate of the bottom package is effectively reduced to avoid failure of electrical connections between both packages caused by the breaking of soldering joints. | 10-25-2012 |
20120267783 | STACKED-SUBSTRATE STRUCTURE - The stacked-substrate structure includes a first substrate having a first die embedded therein, a second substrate having a second die embedded therein, a plurality of soldering elements, and a third die. The soldering elements are disposed between the first and the second substrates and connected to the first and the second substrates. The first and the second substrates are electrically connected via the soldering elements. The first substrate, the second substrate, and the soldering elements define an accommodating space. The third die is arranged in the accommodating space and is connected to one surface of the first substrate. The third die is electrically connected to the first and the second dies via the first substrate. Thus, the thickness of the stacked-substrate structure can be reduced, and the first and the second dies of the stacked-substrate structure can be test separately in different platforms. | 10-25-2012 |
20120273946 | SEMICONDUCTOR DEVICE - A semiconductor device entirely having a small height, which performs a fan-out operation for input/output signals and forms a short electrical path is provided. The semiconductor device includes a first semiconductor die having a first surface, a second surface opposed to the first surface, a third surface connecting the first and second surfaces to each other, a first bond pad disposed on the first surface, and a first through electrode passing between the first surface and second surface and electrically connected to the first bond pad. A first redistribution part is disposed under the second surface and includes a first redistribution layer electrically connected to the first through electrode. A second redistribution part is disposed over the first surface and includes a second redistribution layer electrically connected to the first bond pad. | 11-01-2012 |
20120273947 | CHIP PACKAGE WITH A CHIP EMBEDDED IN A WIRING BODY - An electronic device is disclosed. The electronic device comprises at least one electronic chip and a package for the electronic chip. The package comprises a laminate substrate, wherein the electronic chip is attached on the laminate substrate. The laminate substrate comprises one or more conduction layers, one or more insulation layers and a plurality of pads formed in a conduction layer on the side of the laminate substrate opposite to the side connected to the electronic chip. Furthermore, the package comprises an insulation body formed around the electronic chip. Moreover, the package comprises a plurality of electrodes that extend through the insulation body. For each pad of the laminate substrate, wiring is formed in the one or more of conduction layers and in one or more vias passing through the one or more insulation layers for electrically connecting the pad with at least one of the electrodes. The package further comprises an interconnection body formed on the insulation body and the electronic chip. The interconnection body comprises a plurality of pads on the side of the interconnection body opposite to the side connected to the insulation body and the electronic chip and it also comprises wiring inside the interconnection body for electrical connections between the pads of the electronic chip, the electrodes and the pads of the interconnection body. A method for manufacturing the electronic device is also disclosed. | 11-01-2012 |
20120280390 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTED CIRCUIT LEAD ARRAY AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace. | 11-08-2012 |
20120286425 | PACKAGE HAVING MEMS ELEMENT AND FABRICATION METHOD THEREOF - A package structure having an MEMS element is provided, which includes: a protection layer having openings formed therein; conductors formed in the openings, respectively; conductive pads formed on the protection layer and the conductors; a MEMS chip disposed on the conductive pads; and an encapsulant formed on the protection layer for encapsulating the MEMS chip. By disposing the MEMS chip directly on the protection layer to dispense with the need for a carrier, such as a wafer or a circuit board that would undesirably add to the thickness, the present invention reduces the overall thickness of the package to thereby achieve miniaturization. | 11-15-2012 |
20120286426 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first structural body having first electrode pads; a second structural body disposed in a face-up type over the first structural body in such a way as to expose the first electrode pads, and having first connection members with at least two protrusions; and a third structural body disposed in a face-down type over the second structural body, and having second connection members with at least two protrusions, on a surface thereof facing the second structural body, wherein some of the protrusions of the second connection members are electrically connected with the exposed first electrode pads, and at least one of remaining protrusions of the second connection members is electrically connected with the first connection members. | 11-15-2012 |
20120286427 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling. | 11-15-2012 |
20120292762 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a package structure is provided. A metal substrate is provided. The metal substrate has a first surface where a first seed layer is formed. A patterned insulating layer is formed on the first seed layer and exposes a portion of the first seed layer. A patterned circuit layer is formed on the exposed portion of the first seed layer and covers a portion of the patterned insulating layer. A chip-bonding process is performed to electrically connect a chip to the patterned circuit layer. An encapsulant encapsulating the chip and the patterned circuit layer and covering a portion of the pattered insulating layer is formed. The metal substrate and the first seed layer are removed to expose a bottom surface of the patterned insulating layer and a lower surface of the patterned circuit layer. Solder balls are formed on the lower surface of the patterned circuit layer. | 11-22-2012 |
20120292763 | ELECTROMIGRATION IMMUNE THROUGH-SUBSTRATE VIAS - A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions. | 11-22-2012 |
20120299181 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film. | 11-29-2012 |
20120299182 | COPPER BONDING WIRE FOR SEMICONDUCTOR AND BONDING STRUCTURE THEREOF - It is an object of the present invention to provide a bonding structure and a copper bonding wire for semiconductor that are realizable at an inexpensive material cost, superior in a long-term reliability of a bonded portion bonded to an Al electrode, and suitable for use in a vehicle-mounted LSI. A ball-bonded portion is formed by bonding to the aluminum electrode a ball formed on a front end of the copper bonding wire. After being heated at any temperature between 130° C. and 200° C., the aforementioned ball-bonded portion exhibits a relative compound ratio R1 of 40-100%, the relative compound ratio R1 being a ratio of a thickness of a Cu—Al intermetallic compound to thicknesses of intermetallic compounds that are composed of Cu and Al and formed on a cross-sectional surface of the ball-bonded portion. | 11-29-2012 |
20120299183 | SEMICONDUCTOR DEVICE AND STACKED-TYPE SEMICONDUCTOR DEVICE - In a semiconductor device according to the present invention, a solder resist has a plurality of openings that expose electrodes. Solder bumps are formed in the openings and each have a solder ball portion protruding from the corresponding opening. The height of the openings is set to increase with increasing gap distance between the electrodes of an interposer substrate and board electrodes of a printed wiring board on which the semiconductor device is mounted. Thus, the solder bumps that correspond to sections where the gap distance is large can be increased in height, whereas the solder bumps that correspond to sections where the gap distance is small can be decreased in height, thereby avoiding the occurrence of defective joints caused by a reduction in size and thickness of the interposer substrate, as well as extending the lifespan of solder joints. | 11-29-2012 |
20120306075 | SEMICONDUCTOR PACKAGE APPARATUS - A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball. | 12-06-2012 |
20120306076 | Semiconductor Micro-Connector With Through-Hole Via and a Method for Making the Same - A micro-connector fabricated from a semiconductor material is disclosed. The micro-connector has one or more low resistance regions having a predetermined low resistance through its thickness. Opposing surfaces of the semiconductor layer have one or more complementary and opposing receiving volumes and one or more complementary mating elements defined on each of the respective surfaces within the low resistance regions for the receiving of a solder ball bond from, for instance a stackable microelectronic layer or component. The solder ball bonds of a separately provided electronic element can be inserted through the mating elements and into the volume and mechanically affixed and electrically coupled to the micro-connector on each of the surfaces for the electronic coupling of a first electronic element to a second electronic element. | 12-06-2012 |
20120306077 | SEMICONDUCTOR DEVICE - A semiconductor device includes an electrode pad provided on a semiconductor chip, the electrode pad includes aluminum (Al) of between 50% wt. and 99.9% wt. and further includes copper (Cu), a coupling ball that primarily includes Cu, the coupling ball being coupled to the electrode pad so that a CuAl | 12-06-2012 |
20120306078 | EXPOSED INTERCONNECT FOR A PACKAGE ON PACKAGE SYSTEM - An integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate; connecting an interposer to the integrated circuit with a wire-in-film adhesive; connecting an exposed interconnect having an upper surface to the substrate; and encapsulating the integrated circuit with an encapsulation. | 12-06-2012 |
20120313242 | SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASED POST HEIGHT - An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces. | 12-13-2012 |
20120313243 | CHIP-SCALE PACKAGE - A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer. | 12-13-2012 |
20120313244 | SEMICONDUCTOR PACKAGE, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring. | 12-13-2012 |
20120319274 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A circuit substrate having a mounting surface on which a semiconductor chip is mounted and at least one connection pad formed on the mounting surface is connected to a support plate having at least one mounting portion with a diameter larger than a diameter of the connection pad, through a truncated-cone-shaped solder layer which is formed from at least one solder ball on the basis of a difference between the diameter of the mounting portion and the diameter of the connection pad. The resin layer is formed between the mounting surface of the circuit substrate and the support plate and the support plate is subsequently removed, whereby a truncated-cone-shaped via is formed in the resin layer along the truncated-cone-shaped solder layer. A reflow process is thereafter performed, whereby the truncated-cone-shaped solder layer is formed into a spherical solder layer within the truncated-cone-shaped via. | 12-20-2012 |
20120319275 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 12-20-2012 |
20120319276 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 12-20-2012 |
20120326304 | Externally Wire Bondable Chip Scale Package in a System-in-Package Module - There is provided a system and method for an externally wire bondable chip scale package in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad disposed thereon, a packaged device attached to the substrate, wherein an electrode of the packaged device is wirebonded to the first contact pad, and an unpackaged device, wherein an electrode of the unpackaged device is coupled to the substrate. By flipping the packaged device within the module and utilizing wire bondable finishes on the packaged device, an externally wire bondable chip scale package may be provided. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, a single assembly line, facilitated die substitution, reduced heat stress, higher package density, and a simplified single package structure for reduced fabrication time and cost. | 12-27-2012 |
20120326305 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a dielectric layer having opposing first and second surfaces and side surfaces; a copper wiring layer disposed on the first surface of the dielectric layer and having extension pads; a surface processing layer disposed on the wiring layer; a semiconductor chip disposed on the wiring layer and electrically connected to the surface processing layer; and an encapsulant disposed on the first surface of the dielectric layer for encapsulating the semiconductor chip, the wiring layer and the surface processing layer while exposing the second surface of the dielectric layer. Further, vias are disposed between the side surfaces of the dielectric layer and the encapsulant such that the extension pads are exposed from the vias so as for solder balls to be disposed thereon. Due to improved electrical connection between the copper and solder materials, the electrical connection quality of the package is improved. | 12-27-2012 |
20120326306 | POP PACKAGE AND MANUFACTURING METHOD THEREOF - The present invention relates to a package on package (POP) package and a manufacturing method thereof, and provides a POP package and a manufacturing method thereof in which the POP package can be implemented by using a transfer mold method without employing a top gate mold method. To this end, the present invention comprises: a lower semiconductor package which includes a first solder ball and a semiconductor chip formed on the upper surface of a substrate, and a mold for molding the semiconductor chip and the solder ball so that a part of the first solder ball may be exposed; and an upper semiconductor package which is stacked so that a connection is made to an exposed part of a second solder ball through the second solder ball formed on the lower surface. | 12-27-2012 |
20120326307 | STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device including a plurality of semiconductor chips stacked vertically, a plurality of scribe lane elements each forming a step with a semiconductor chip of the plurality of semiconductor chips and respectively formed on a side surface of each of the plurality of semiconductor chips, a redistribution element respectively formed on each of the plurality of semiconductor chips and the scribe lane elements, and a signal connection member formed on the side surface of each of the plurality of semiconductor chips and electrically connecting the redistribution elements. | 12-27-2012 |
20120326308 | ENHANCED WLP FOR SUPERIOR TEMP CYCLING, DROP TEST AND HIGH CURRENT APPLICATIONS - A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection. | 12-27-2012 |
20130001776 | Interconnect Structure for Wafer Level Package - A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI. | 01-03-2013 |
20130001777 | COPPER WIRE RECEIVING PAD - On embodiment is directed to a welding pad capable of receiving a ball-shaped copper wire at its end, including a first copper pad coated with a protection layer and topped with a second pad containing aluminum having dimensions smaller than those of the first pad and smaller than the ball diameter once said ball has been welded to the welding pad. | 01-03-2013 |
20130001778 | BUMP-ON-TRACE (BOT) STRUCTURES - A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described. | 01-03-2013 |
20130001779 | STACK PACKAGE HAVING FLEXIBLE CONDUCTORS - A stack package includes a first package having a first semiconductor chip and a first encapsulation member which seals the first semiconductor chip. A second package is stacked on the first package, and includes a second semiconductor chip and a second encapsulation member which seals the second semiconductor chip. Flexible conductors are disposed within the first encapsulation member of the first package in such a way as to electrically connect the first package and the second package. | 01-03-2013 |
20130001780 | MULTI-COMPONENT INTEGRATED CIRCUIT CONTACTS - An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member. | 01-03-2013 |
20130009307 | Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers - A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed. | 01-10-2013 |
20130009308 | SEMICONDUCTOR STACK PACKAGE APPARATUS - A semiconductor stack package apparatus includes an upper semiconductor package and a lower semiconductor package. The upper semiconductor chip includes a chip pad, an upper substrate including a substrate pad formed on a top surface of the upper substrate and an upper ball land formed on a bottom surface of the upper substrate and attached to an intermediate solder ball, and a wire connecting the chip pad and the substrate pad. The lower semiconductor package includes a lower semiconductor chip including a bump, and a lower substrate including a bump land formed on a top surface of the lower substrate in an area corresponding to the bump, an intermediate ball land formed on the top surface of the lower substrate in an area corresponding to the intermediate solder ball, and a lower ball land formed on a bottom surface of the lower substrate and attached to a lower solder ball. | 01-10-2013 |
20130015578 | INTERCONNECTION AND ASSEMBLY OF THREE-DIMENSIONAL CHIP PACKAGESAANM Thacker; Hiren D.AACI San DiegoAAST CAAACO USAAGP Thacker; Hiren D. San Diego CA USAANM Cunningham; John E.AACI San DiegoAAST CAAACO USAAGP Cunningham; John E. San Diego CA USAANM Shubin; IvanAACI San DiegoAAST CAAACO USAAGP Shubin; Ivan San Diego CA USAANM Krishnamoorthy; Ashok V.AACI San DiegoAAST CAAACO USAAGP Krishnamoorthy; Ashok V. San Diego CA US - In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate. | 01-17-2013 |
20130015579 | SOLDER BALL CONTACT SUSCEPTIBLE TO LOWER STRESS - A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball. | 01-17-2013 |
20130020702 | DOUBLE-SIDED FLIP CHIP PACKAGE - Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module. | 01-24-2013 |
20130020703 | Method for Making a Stackable Package - The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized. | 01-24-2013 |
20130026630 | FLIP CHIPS HAVING MULTIPLE SOLDER BUMP GEOMETRIES - In certain embodiments, a flip chip includes a first and second solder bump. The first solder bump has a solder bump height that is greater than the second solder bump. | 01-31-2013 |
20130032942 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a circuit substrate, a first semiconductor chip disposed on the circuit substrate, a plurality of first spacers disposed on the first semiconductor chip, a second semiconductor chip which includes a first adhesive agent layer on a lower face thereof and is disposed on upper portions of the plurality of spacers, a wire which connects the circuit substrate to the first semiconductor chip, and a first sealing material which seals a gap between the first semiconductor chip and the first adhesive agent layer, wherein each height of the plurality of the first spacers is greater than height of the wire relative to an upper face of the first semiconductor chip. | 02-07-2013 |
20130037948 | SEMICONDUCTOR DEVICE HAVING A THROUGH-SUBSTRATE VIA - Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a top wafer and a bottom wafer bonded together with a patterned adhesive material. The top wafer and the bottom wafer include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the top and bottom wafers. A via is formed through the top wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the top wafer and the integrated circuits formed in the bottom wafer. The via includes a conductive material that furnishes the electrical interconnection between the top and bottom wafers. | 02-14-2013 |
20130037949 | SEMICONDUCTOR ASSEMBLIES WITH MULTI-LEVEL SUBSTRATES AND ASSOCIATED METHODS OF MANUFACTURING - Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate. | 02-14-2013 |
20130037950 | Multi-Chip Wafer Level Package - A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer. | 02-14-2013 |
20130037951 | SEMICONDUCTOR PACKAGE STRUCTURE WITH LOW INDUCTANCE - A semiconductor package structure includes: a substrate comprising a plurality of power supply balls on a first surface of the substrate, a first metal conductor on a second surface of the substrate and at least one via coupling a power supply ball to the first metal conductor of the substrate; a die, comprising a plurality of bond pads on a first surface of the die, a first metal conductor on a second surface of the die and at least one via coupling a bond pad to the first metal conductor of the die; and a plurality of first wire bonds for coupling the first metal conductor of the substrate to the first metal conductor of the die. | 02-14-2013 |
20130037952 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a substrate, a driving chip module including a plurality of driving chips stacked on the substrate, and a molding part formed on the substrate by compressing a sheet type molding member in a semi-cured (B-stage) state to cover the driving chip module. | 02-14-2013 |
20130043587 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls. | 02-21-2013 |
20130043588 | SEMICONDUCTOR DICE INCLUDING AT LEAST ONE BLIND HOLE, WAFERS INCLUDING SUCH SEMICONDUCTOR DICE, AND INTERMEDIATE PRODUCTS MADE WHILE FORMING AT LEAST ONE BLIND HOLE IN A SUBSTRATE - Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material. | 02-21-2013 |
20130049195 | Three-Dimensional Integrated Circuit (3DIC) Formation Process - A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench. | 02-28-2013 |
20130049196 | THROUGH INTERPOSER WIRE BOND USING LOW CTE INTERPOSER WITH COARSE SLOT APERTURES - A microelectronic package includes a subassembly, a second substrate, and a monolithic encapsulant. The subassembly includes a first substrate that has at least one aperture, a coefficient of thermal expansion (CTE) of eight parts per million per degree Celsius or less, and first and second contacts arranged so as to have a pitch of 200 microns or less. First and second microelectronic elements are respectively electrically connected to the first and second contacts. Wire bonds may be used to connect the second element contacts with the second contacts. A second substrate may underlie either the first or the second microelectronic elements and be electrically interconnected with the first substrate. The second substrate may have terminals configured for electrical connection to a component external to the microelectronic package. A monolithic encapsulant may contact the first and second microelectronic elements and the first and second substrates. | 02-28-2013 |
20130049197 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer. | 02-28-2013 |
20130049198 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor package structure is provided. A chip is provided. An active surface of the chip is disposed on a carrier. A molding compound is formed on the carrier with a metal layer disposed thereon. The metal layer has an upper and lower surface, multiple cavities formed on the upper surface and multiple protrusions formed on the lower surface and corresponding to the cavities. The protrusions are embedded in the molding compound. The metal layer is patterned to form multiple pads on a portion of the molding compound. The carrier and the molding compound are separated. Multiple through holes are formed on the molding compound exposing the protrusions. A redistribution layer is formed on the molding compound and the active surface of the chip. Multiple solder balls are formed on the redistribution layer. A portion of the solder balls are correspondingly disposed to the pads. | 02-28-2013 |
20130056871 | Thermally Enhanced Structure for Multi-Chip Device - A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved. | 03-07-2013 |
20130056872 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 03-07-2013 |
20130062760 | Packaging Methods and Structures Using a Die Attach Film - Packaging methods and structures for semiconductor devices that utilize a novel die attach film are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer and forming a die attach film (DAF) that includes a polymer over the carrier wafer. A plurality of dies is attached to the DAF, and the plurality of dies is packaged. At least the carrier wafer is removed from the packaged dies, and the packaged dies are singulated. | 03-14-2013 |
20130062761 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 03-14-2013 |
20130062762 | IN-GRID ON-DEVICE DECOUPLING FOR BGA - Embodiments of the invention place surface-mount such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, between BGA pads. | 03-14-2013 |
20130062763 | DE-POP ON-DEVICE DECOUPLING FOR BGA - Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads. | 03-14-2013 |
20130062764 | SEMICONDUCTOR PACKAGE WITH IMPROVED PILLAR BUMP PROCESS AND STRUCTURE - A flip chip structure formed on a semiconductor substrate includes a first plurality of copper pillars positioned directly over, and in electrical contact with respective ones of a plurality of contact pads on the front face of the semiconductor substrate. A layer of molding compound is positioned on the front face of the substrate, surrounding and enclosing each of the first plurality of pillars and having a front face that is coplanar with front faces of each of the copper pillars. Each of a second plurality of copper pillars is positioned on the front face of one of the first plurality of copper pillars, and a solder bump is positioned on a front face of each of the second plurality of pillars. | 03-14-2013 |
20130062765 | LOW LOOP WIRE BONDING - A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die. | 03-14-2013 |
20130062766 | System and Method for 3D Integrated Circuit Stacking - A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit. | 03-14-2013 |
20130069231 | SOLDER CAP BUMP IN SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap. | 03-21-2013 |
20130075904 | COPLANER WAVEGUIDE TRANSITION - A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second side of the substrate. The coplanar waveguide transition includes a first, a second, and a third via through the substrate electrically coupling the first coplanar waveguide to the second coplanar waveguide. The coplanar waveguide transition includes voids through the substrate between the first, second, and third vias and edges of the first coplanar waveguide and edges of the second coplanar waveguide. | 03-28-2013 |
20130075905 | Semiconductor Chips and Semiconductor Packages and Methods of Fabricating the Same - A semiconductor device includes a substrate and a through via penetrating the substrate. The through via has a protruding portion at a first end thereof extending out from a first surface of the substrate and a second end of the via contacting an interconnection line proximate a second, opposite, end of the substrate. A wetting layer is positioned between the via and the substrate and extends over the protruding portion of the via. The wetting layer includes a material selected to improve an adhesive strength between the wetting layer and a solder ball contacting the wetting layer extending over the protruding portion of the via when a solder ball is coupled to the wetting layer. | 03-28-2013 |
20130075906 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region. | 03-28-2013 |
20130082383 | ELECTRONIC ASSEMBLY HAVING MIXED INTERFACE INCLUDING TSV DIE - An electronic assembly includes an interposer having an inner aperture including a first side and a second side. A through-substrate-via (TSV) die is within the aperture including a plurality of TSVs, a bottomside, and a topside including topside bonding features thereon including of a first portion of the plurality of TSVs or pads coupled to the first TSVs. A ball grid array (BGA) is coupled to the topside bonding features of the TSV die and to pads on the second side of the interposer. Mold material is over at least a portion of the first side of the interposer, and within the inner aperture to fill a gap between the TSV die and the interposer. Respective ones of a second portion of the plurality of TSVs from the bottomside of the TSV die are connected by a lateral connector to pads on the first side of the interposer. | 04-04-2013 |
20130082384 | MICROELECTRONIC DEVICES HAVING INTERMEDIATE CONTACTS FOR CONNECTION TO INTERPOSER SUBSTRATES, AND ASSOCIATED METHODS OF PACKAGING MICROELECTRONIC DEVICES WITH INTERMEDIATE CONTACTS - Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball. | 04-04-2013 |
20130087914 | WAFER LEVEL CHIP SCALE PACKAGE AND METHOD OF MANUFACTURING THE SAME - A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices. | 04-11-2013 |
20130087915 | Copper Stud Bump Wafer Level Package - There is provided a system and method for a copper stud bump wafer level package. There is provided a semiconductor package comprising a semiconductor die having a plurality of bond pads on an top surface thereof, a plurality of metallic stud bumps mechanically and electrically coupled to said plurality of bond pads, and a plurality of solder balls mechanically and electrically coupled to said plurality of metallic stud bumps. Advantageously, the metallic stud bumps may be provided using standard wirebonding equipment, avoiding the conventional wafer level package requirement for photolithography and deposition steps to provide a multi-layer metallic routing structure. As a result, reduced cycle times, lower cost, and reduced complexity may be provided. Alternative fabrication processes utilizing metallic stud bumps may also support multi-die packages with dies from different wafers and packages with die perimeter pads wirebonded to substrates. | 04-11-2013 |
20130087916 | Methods of Packaging Semiconductor Devices and Structures Thereof - Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies. | 04-11-2013 |
20130087917 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a connection member to electrically connect the first semiconductor chip and the second semiconductor chip. The connection member may include a connection pad disposed on the first semiconductor chip, a connection pillar disposed on the second semiconductor chip, and a bonding member to connect the connection pad and the connection pillar. An anti-contact layer may be formed on at least one surface of the connection pad. | 04-11-2013 |
20130087918 | Ball Grid Array with Improved Single-Ended and Differential Signal Performance - An improved system and method for assigning power and ground pins and single ended or differential signal pairs for a ball grid array semiconductor package. In certain embodiments, the system uses a hexagonal pattern where the grid may be represented by a multiplicity of nested hexagonal patterns. | 04-11-2013 |
20130093084 | Wafer-Level Chip Scale Package with Re-Workable Underfill - A package includes a printed circuit board (PCB), and a die bonded to the PCB through solder balls. A re-workable underfill is dispensed in a region between the PCB and the die. | 04-18-2013 |
20130093085 | DUAL INTERLOCK HEATSINK ASSEMBLY FOR ENHANCED CAVITY PBGA PACKAGES, AND METHOD OF MANUFACTURE - A semiconductor package is provided, including a laminate substrate with an aperture sized to receive a semiconductor die. Through-holes in the substrate are filled with a thermally conductive adhesive. A first heat spreader is attached to the by the adhesive, and a semiconductor die is positioned in the aperture with a back face in thermal contact with the heat spreader. Wire bonds couple the die to electrical traces on the substrate. A second heat spreader is attached by the adhesive to the substrate over the die, directly opposite the first heat spreader. A portion of the second heat spreader is encapsulated in molding compound. Openings in the second heat spreader admits molding compound to fill the space around the die between the heat spreaders. Heat is transmitted from the die to the first spreader, and thence, via the through-holes and conductive paste, to the second heat spreader. | 04-18-2013 |
20130093086 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - This disclosure provides a semiconductor package and a method of fabricating the same. The semiconductor package includes an insulating layer; a plurality of traces and connection pads disposed in the insulating layer and protruded from the insulating layer; a plurality of bumps formed on the plurality of traces; a semiconductor chip disposed on the bumps; and an encapsulant formed on the insulating layer to encapsulate the semiconductor chip, the plurality of bumps, traces and connection pads. When the encapsulant is formed, voids can be prevented from being generated in the traces and the connection pads and thus the yield of process is significantly increased. | 04-18-2013 |
20130093087 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds. | 04-18-2013 |
20130093088 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS - A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds. | 04-18-2013 |
20130099380 | WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF - The present invention discloses a wafer level chip scale package device. The device includes: a chip including at least one bonding pad; a UBM layer disposed on the bonding pad; a pre-solder layer disposed on the UBM layer; and a bump melted and combined with the pre-solder layer. | 04-25-2013 |
20130099381 | SEMICONDUCTOR DEVICE AND CONNECTION CHECKING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a first land formed in a first surface of the substrate, a second land formed in a second surface of the substrate, a first terminal coupled to the second land, a line coupled to the first land and the second land, a second terminal formed in the second surface of the substrate and a branch line coupled to the line and the second terminal. The second terminal is coupled to the first land and the second land and is not coupled to other lands in the first surface. The second surface is different surface from the first surface. | 04-25-2013 |
20130105972 | STACKED PACKAGES USING LASER DIRECT STRUCTURING | 05-02-2013 |
20130105973 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130113097 | METHODS OF AND SEMICONDUCTOR DEVICES WITH BALL STRENGTH IMPROVEMENT - In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received. The pattern includes a number of columns and rows crossing each other. The balls are arranged at intersections of the columns and rows. An arrangement of balls in a region of the ball pattern is modified so that the region includes no isolated balls. | 05-09-2013 |
20130113098 | THROUGH VIA PACKAGE - An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side. | 05-09-2013 |
20130113099 | PACKAGE CARRIER, PACKAGE CARRIER MANUFACTURING METHOD, PACKAGE STRUCTURE FOR SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A package substrate including a dielectric layer, a first conductive layer, a second conductive layer and a bonding pad is provided. The dielectric layer has a top surface and a bottom surface. The first conductive layer is embedded into the dielectric layer, and a first surface of the first conductive layer is exposed from the top surface and has the same plane with the top surface. The second conductive layer is embedded into the dielectric layer and contacts the first conductive layer, and a second surface of the second conductive layer is exposed from the bottom surface and has the same plane with the bottom surface. The bonding pad is partially or completely embedded into the first conductive layer and the dielectric layer, so that the periphery of the bonding pad is confined within a cavity by the sidewalls of both the first conductive layer and the dielectric layer. | 05-09-2013 |
20130119538 | WAFER LEVEL CHIP SIZE PACKAGE - A method of making a wafer level chip size package (WCSP) comprising providing a die having a first face with a plurality of bond pads thereon, a second face opposite the first face and a plurality of side faces extending between the first face and the second face, at least one of the plurality of side faces having saw induced microcracks therein; and coating at least one of the plurality of side faces with a thin veneer of adhesive that penetrates the microcracks. A WCSP produced by the method is also disclosed. | 05-16-2013 |
20130119539 | Package Structures and Methods for Forming the Same - A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface. | 05-16-2013 |
20130119540 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a semiconductor package and a method for manufacturing the same. The method includes preparing a substrate having one surface and the other surface; mounting a semiconductor device mounted on one surface of the substrate; forming external connection terminals on the other surface of the substrate; forming a warpage preventing layer formed on one surface of the substrate or the other surface of the substrate; and performing a reflow process on the substrate. | 05-16-2013 |
20130119541 | PRINTED CIRCUIT BOARD - In a printed wiring board of a printed circuit board, a region for mounting a first semiconductor package is divided into a first region on which first solder ball electrodes are disposed and a second region on which first solder ball electrodes are not disposed, and a region for mounting a second semiconductor package on the back side of the first semiconductor package is located within a region on the back side of the second region. | 05-16-2013 |
20130119542 | PACKAGE HAVING STACKED MEMORY DIES WITH SERIALLY CONNECTED BUFFER DIES - A multi-chip package has a substrate, and a plurality of memory dies stacked on the substrate. A plurality of buffer dies each has an input and an output. The input of a first buffer die is connectable to an external input. The output of a last buffer die of the plurality of buffer dies is connectable to an external output. Each of the remaining inputs and outputs is connected respectively to an output or an input of another of the plurality of buffer dies to form a serial connection between the plurality of buffer dies. Each of the memory dies is connected to one of the buffer dies, such that each buffer die is connected to its respective memory dies in parallel arrangement. A memory device having multiple serially interconnected MCPs and a controller is also described. | 05-16-2013 |
20130127052 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. | 05-23-2013 |
20130127053 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MODULE HAVING THE SAME - Disclosed herein is a semiconductor package including: a semiconductor chip having a bonding pad; and a first substrate including a rerouting layer having short type rerouting patterns electrically connected with the bonding pad and formed to be seamlessly connected with each other and a plurality of open type rerouting patterns separately formed on the same layer as the short type rerouting patterns and connection terminals for signal connection each formed on the open type rerouting patterns. | 05-23-2013 |
20130127054 | STACKED-CHIP PACKAGES IN PACKAGE-ON-PACKAGE APPARATUS, METHODS OF ASSEMBLING SAME, AND SYSTEMS CONTAINING SAME - A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer. | 05-23-2013 |
20130134588 | Package-On-Package (PoP) Structure and Method - Package-On-Package (PoP) structures and methods of forming PoP structures are disclosed. According to an embodiment, a structure comprises a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. | 05-30-2013 |
20130147040 | MEMS CHIP SCALE PACKAGE - A flip-chip manufactured MEMS device. The device includes a substrate and a MEMS die. The substrate has a plurality of bumps, a plurality of connection points configured to electrically connect the MEMS device to another device, and a plurality of vias electrically connecting the bumps to the connections points. The MEMS die is attached to the substrate using flip-chip manufacturing techniques, but the MEMS die is not subjected to processing normally associated with creating bumps for flip-chip manufacturing. | 06-13-2013 |
20130147041 | STACK PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A stack package structure is provided, including: a substrate; an insulating layer formed on the substrate and having openings for exposing die attach pads and conductive pads of the substrate, respectively; a plurality of first and second conductive terminals formed on the insulating layer and electrically connected to the die attach pads and the conductive pads, respectively; a dielectric layer formed on the insulating layer and having a cavity for exposing the first conductive terminals and a plurality of openings exposing the second conductive terminals; copper pillars formed respectively in the openings of the dielectric layer; a semiconductor chip disposed in the cavity and electrically connected to the first conductive terminals; solder balls formed respectively on the copper pillars that are located proximate to the die attach area; and a package structure disposed on and electrically connected to the solder balls. | 06-13-2013 |
20130147042 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias. | 06-13-2013 |
20130147043 | SUBSTRATE WITH EMBEDDED STACKED THROUGH-SILICON VIA DIE - A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate. | 06-13-2013 |
20130147044 | MULTI-CHIP PACKAGE HAVING A STACKED PLURALITY OF DIFFERENT SIZED SEMICONDUCTOR CHIPS, AND METHOD OF MANUFACTURING THE SAME - Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate, and a plurality of semiconductor chips stacked on the substrate, each of the plurality of semiconductor chips having a different size. Each of the plurality of semiconductor chips including a pad group and a reference region associated with the pad group, each pad group having a plurality of pads, and the plurality of pads in each pad group located at same coordinates with respect to the associated reference region, and each of the plurality of semiconductor chips having their reference regions vertically aligned. | 06-13-2013 |
20130154091 | SEMICONDUCTOR DEVICE PACKAGING USING ENCAPSULATED CONDUCTIVE BALLS FOR PACKAGE-ON-PACKAGE BACK SIDE COUPLING - A semiconductor device package having an embedded three-dimensional interconnect structure and a process for making such a package is provided. One or more ball conductors are attached to a major surface of a substrate that provides at least an electrical conduit from the ball conductor to an opposite major surface of the substrate. The substrate can also provide an interconnect between solder balls. The combination of solder balls and substrate is encapsulated in the semiconductor device package. The ends of the signal conduits are exposed on one major surface of the device package, while a portion of the ball conductors is exposed on the opposite major surface of the device package. The ball conductors and signal conduits provide signal-bearing pathways between the major surfaces of the package. Contacts created by the back grinded ball conductors are used to form a package-on-package structure by coupling with contacts from another package. | 06-20-2013 |
20130154092 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system including: providing a package carrier; mounting an integrated circuit to the package carrier; mounting a circuit interposer above the integrated circuit; mounting a mounting integrated circuit above the circuit interposer; forming a conductive pillar to the circuit interposer adjacent to the mounting integrated circuit; connecting the circuit interposer to the package carrier; and forming an encapsulation on the package carrier. | 06-20-2013 |
20130161816 | SEMICONDUCTOR PACKAGE - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors. Whereby, the solder mask contacts the first pads directly, and thus results in higher bonding strength, so as to avoid the bridge between the first conductors caused by the first conductors permeating into the interface between the solder mask and the first pads. | 06-27-2013 |
20130168854 | Semiconductor Package with a Bridge Interposer - There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs). | 07-04-2013 |
20130168855 | Methods and Apparatus for Package On Package Devices with Reduced Strain - Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed. | 07-04-2013 |
20130168856 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a bottom packaged die having solder balls disposed on the top surface thereof and a top packaged die having metal stud bumps disposed on a bottom surface thereof. The metal stud bumps include a bump region and a tail region coupled to the bump region. Each metal stud bump on the top packaged die is coupled to one of the solder balls on the bottom packaged die. | 07-04-2013 |
20130168857 | MOLDED INTERPOSER PACKAGE AND METHOD FOR FABRICATING THE SAME - The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs. | 07-04-2013 |
20130168858 | EMBEDDED WAFER LEVEL BALL GRID ARRAY BAR SYSTEMS AND METHODS - A bar formed from a reconstituted wafer and containing one or more conductive material filled voids is used to electrically and physically connect the top and bottom packages in a package-on-package (PoP) package. The bar is disposed in the fan out area of the lower package forming the PoP package. | 07-04-2013 |
20130168859 | POSITIVE PHOTOSENSITIVE RESIN COMPOSITION, METHOD OF CREATING RESIST PATTERN, AND ELECTRONIC COMPONENT - The positive-type photosensitive resin composition according to the present invention comprises an alkali-soluble resin having a phenolic hydroxyl group, a compound that produces an acid by light, a thermal crosslinking agent, and a silane compound having at least one functional group selected from an epoxy group and a sulfide group. | 07-04-2013 |
20130175684 | Integrated Circuit Packaging With Ball Grid Array Having Differential Pitch To Enhance Thermal Performance - A ball grid array (BGA) includes a plurality of metal balls adapted for connection between an electrical circuit and a substrate. A first portion of the BGA contains a first group of the metal balls arranged according to a first pitch. A second portion of the BGA contains a second group of metal the balls arranged according to a second pitch that is less than the first pitch, to provide increased metal contact area and correspondingly enhanced thermal transfer capability. | 07-11-2013 |
20130175685 | UBM Formation for Integrated Circuits - A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad. | 07-11-2013 |
20130175686 | Enhanced Flip Chip Package - A flip chip package structure is proposed in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer. | 07-11-2013 |
20130175687 | PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF - A package stack device includes a first package structure having a plurality of first metal posts and a first electronic element, a second package structure having a plurality of second metal posts and a second electronic element, and an encapsulant formed between the first and second package structures to encapsulate the first electronic element. By connecting the second metal posts to the first metal posts, respectively, the second package structure is stacked on the first package structure with the support of the metal posts. Further, the gap between the two package structures is filled with the encapsulant to avoid warpage of the substrates. | 07-11-2013 |
20130175688 | TIN-BASED SOLDER BALL AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A tin(Sn)-based solder ball and a semiconductor package including the same are provided. The tin-based solder ball includes about 0.2 to 4 wt. % silver(Ag), about 0.1 to 1 wt. % copper(Cu), about 0.001 to 0.3 wt. % aluminum(Al), about 0.001% to 0.1 wt. % germanium(Ge), and balance of tin and unavoidable impurities. The tin-based solder ball has a high oxidation resistance. | 07-11-2013 |
20130187272 | SEMICONDUCTOR MODULE - According to one embodiment, a semiconductor module includes a semiconductor chip that is mounted on a printed substrate, a terminal electrode that is formed on the printed substrate so as to be electrically connected to the semiconductor chip, a metal coating layer that is formed on the terminal electrode, a plating lead wire that is electrically connected to the terminal electrode, and a gap that is formed in the plating lead wire. | 07-25-2013 |
20130193572 | BALL GRID ARRAY PACKAGE SUBSTRATE WITH THROUGH HOLES AND METHOD OF FORMING SAME - In accordance with an embodiment, there is provided a substrate of a ball grid array package that includes a first layer including reinforcement fibers. The reinforcement fibers reinforce the first layer such that the first layer has a higher tensile strength relative to a layer in the ball grid array package that is free of reinforcement fibers. In an embodiment, the substrate comprises a second layer disposed adjacent to the first layer with the second layer being free of reinforcement fibers. In an embodiment, the substrate also includes a through hole penetrating each of the first layer and the second layer. The through hole penetrates each of the first layer and the second layer based on each of the first layer and the second layer having been drilled in accordance with a mechanical drilling process. | 08-01-2013 |
20130207260 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via. | 08-15-2013 |
20130207261 | MAINTAINING ALIGNMENT IN A MULTI-CHIP MODULE USING A COMPRESSIBLE STRUCTURE - An MCM includes a two-dimensional array of facing chips, including island chips and bridge chips that communicate with each other using overlapping connectors. In order to maintain the relative vertical spacing of these connectors, compressible structures are in cavities in a substrate, which house the bridge chips, provide a compressive force on back surfaces of the bridge chips. These compressible structures include a compliant material with shape and volume compression. In this way, the MCM may ensure that facing surfaces of the island chips and the bridge chips, as well as connectors on these surfaces, are approximately coplanar without bending the bridge chips. | 08-15-2013 |
20130207262 | INTEGRATED ANTENNAS IN WAFER LEVEL PACKAGE - A semiconductor module, comprises a package molding compound layer comprising an integrated circuit (IC) device embedded within a package molding compound, the integrated circuit device and the package molding compound having a common surface. Structures are formed to connect the semiconductor module to an external board, the structures electrically connected to the integrated circuit device. A layer is formed on the common surface, the layer comprising at least one integrated antenna structure, the integrated antenna structure being coupled to the IC device. | 08-15-2013 |
20130207263 | SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE - An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer. | 08-15-2013 |
20130214410 | ORGANIC INTERFACE SUBSTRATE HAVING INTERPOSER WITH THROUGH-SEMICONDUCTOR VIAS - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 08-22-2013 |
20130221522 | MECHANISMS OF FORMING CONNECTORS FOR PACKAGE ON PACKAGE - The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements. | 08-29-2013 |
20130221523 | ELECTRONIC DEVICE AND ELECTRONIC COMPONENT - The disclosure discloses an electronic device including an electronic component including a chip main body, a plurality of electrodes, a passivation which includes openings, and UBMs which are respectively formed to be smaller than an opening area of the opening, a substrate including a plurality of substrate electrodes, and a plurality of spherical solder bumps configured to electrically connect the plurality of electrodes with the plurality of substrate electrodes. The solder bump is bonded to the electrode at a bonding portion located on a bottom surface of the spherical shape. Each of the plurality of electrodes includes an exposed portion generated because a bonding area between the solder bump and the electrode via the UBM is smaller than the opening area. The solder bump is separated apart from the passivation via an upper space located above the exposed portion of the electrode. | 08-29-2013 |
20130228921 | SUBSTRATE STRUCTURE AND FABRICATION METHOD THEREOF - A substrate structure includes a substrate body and a plurality of conductive pads formed on the substrate body and each having a first copper layer, a nickel layer, a second copper layer and a gold layer sequentially stacked. The thickness of the second copper layer is less than the thickness of the first copper layer. As such, the invention effectively enhances the bonding strength between the conductive pads and solder balls to be mounted later on the conductive pads, and prolongs the duration period of the substrate structure. | 09-05-2013 |
20130234326 | SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor apparatus comprises of a first semiconductor chip having a through silicon via (TSV) and a second semiconductor chip also having a TSV, wherein the respective semiconductor chips are stacked vertically and are connected through a conductive connection member without the assistance of an additional bump between the conductive connection member and the second semiconductor chip. | 09-12-2013 |
20130234327 | SEMICONDUCTOR DEVICE BONDING WITH STRESS RELIEF CONNECTION PADS - An inventive semiconductor device includes: a semiconductor chip; an internal pad provided on a surface of the semiconductor chip for electrical connection; a surface protective film covering the surface of the semiconductor chip and having a pad opening from which the internal pad is exposed; a stress relief layer provided on the surface protective film and having an opening portion through which the internal pad exposed from the pad opening is exposed; a connection pad including an anchor buried in the pad opening and the opening portion and connected to the internal pad, and a projection provided integrally with the anchor as projecting on the stress relief layer, the projection having a width greater than an opening width of the opening portion; and a metal ball provided for external electrical connection as covering the projection of the connection pad. | 09-12-2013 |
20130234328 | METHODS OF FLUXLESS MICRO-PIERCING OF SOLDER BALLS, AND RESULTING DEVICES - A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure. | 09-12-2013 |
20130234329 | STRUCTURES AND METHODS TO REDUCE MAXIMUM CURRENT DENSITY IN A SOLDER BALL - Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance. | 09-12-2013 |
20130241056 | WELL-THROUGH TYPE DIODE ELEMENT/COMPONENT AND MANUFACTURING METHOD FOR THEM - A well-through type diode element/component manufacturing method which has a pair (pairs) of first and said second electrodes of a diode element/component built on same plane by a process of metallization after a mode of well-through type to penetrate a PN junction depletion region/barrier region, and leads electrons of one of the electrodes to flow through the Depletion/Barrier region without hindrance; the present invention directly conduct the operations of insulation protecting, metallization and the process of elongate welding ball etc., it can independently complete a novel technique of Chip-Scale Package (CSP); it has the features of: grains being exactly the article produced, no need of connecting lines, low energy consumption, low cost and light, thin and small etc. | 09-19-2013 |
20130241057 | Methods and Apparatus for Direct Connections to Through Vias - Methods and apparatus for direct connection to a through via. An apparatus includes a substrate having a front side surface and a back side surface; conductive through vias formed in the substrate and having through via protrusions extending from the back side surface; solder connectors on another device and coupling the another device to the substrate, wherein the solder connectors correspond to the through via protrusions and enclose the through via protrusions to form solder joints; and connectors on the front side surface of the substrate for forming additional electrical connections. Methods include providing a substrate with through vias; thinning the substrate; etching the substrate to create through via protrusions; aligning another device with solder connectors on a surface corresponding to the through via protrusions; placing the solder connectors in contact with the protrusions; and performing a thermal reflow to form solder joints around the through via protrusions. | 09-19-2013 |
20130241058 | Wire Bonding Structures for Integrated Circuits - A device includes a substrate, and a bond pad over the substrate. A protection layer is disposed over the bond pad. The protection layer and the bond pad include different materials. A bond ball is disposed onto the protection layer. A bond wire is joined to the bond ball. | 09-19-2013 |
20130241059 | Integrated Antennas in Wafer Level Package - A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package. | 09-19-2013 |
20130249092 | PACKAGED MICROELECTRONIC DEVICES RECESSED IN SUPPORT MEMBER CAVITIES, AND ASSOCIATED METHODS - Packaged microelectronic devices recessed in support member cavities, and associated methods, are disclosed. Method in accordance with one embodiment includes positioning a microelectronic device in a cavity of a support member, with the cavity having a closed end with a conductive layer, and an opening through which the cavity is assessable. The microelectronic device can have bond sites, a first surface, and a second surface facing opposite from the first surface. The microelectronic device can be positioned in the cavity so that the second surface faces toward and is carried by the conductive layer. The method can further include electrically coupling the bond sites of the microelectronic device to the conductive layer. In particular embodiments, the microelectronic device can be encapsulated in the cavity without the need for a releasable tape layer to temporarily support the microelectronic device. | 09-26-2013 |
20130256883 | ROTATED SEMICONDUCTOR DEVICE FAN-OUT WAFER LEVEL PACKAGES AND METHODS OF MANUFACTURING ROTATED SEMICONDUCTOR DEVICE FAN-OUT WAFER LEVEL PACKAGES - In various aspects of the disclosure, a package may be provided. The package may include at least one semiconductor device rotated about an axis with respect to an edge of the package, at least one bond pad on each semiconductor device, and at least one conductive trace electrically connected to the semiconductor device through the at least one bond pad. | 10-03-2013 |
20130256884 | GRID FAN-OUT WAFER LEVEL PACKAGE AND METHODS OF MANUFACTURING A GRID FAN-OUT WAFER LEVEL PACKAGE - In various aspects of the disclosure, a chip packaging arrangement may be provided. The chip packaging arrangement may include a dielectric layer with at least one semiconductor device adjoining the dielectric layer, at least one bonding area on the semiconductor device, the bonding area being exposed through the dielectric layer, a first material comprising a first coefficient of thermal expansion substantially surrounding the semiconductor device and adjoining the dielectric layer, a second material comprising a second coefficient of thermal expansion substantially surrounding the semiconductor device and the first material; and at least one conductive trace electrically connected to the semiconductor device. | 10-03-2013 |
20130256885 | Copper Sphere Array Package - Presented is a method for fabricating a semiconductor package, and the associated semiconductor package. The method includes providing a compliant coverlay having a resin film disposed thereon. A plurality of metallic spheres may be placed at predetermined positions in the resin film. A top surface and a bottom surface of the metallic spheres may be flattened. Tamp blocks on opposing sides of the metallic spheres may be used. The resin film may then be cured to permanently set the metallic spheres in the resin film, and the compliant overlay may then be removed. A semiconductor die may then be placed on the plurality of metallic spheres. An encapsulating layer may then be deposited over the semiconductor die, the plurality of metallic spheres, and the resin film. The semiconductor package may then be diced. The method does not include fabricating a metal leadframe for the semiconductor die. | 10-03-2013 |
20130256886 | SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate which has a plurality of pad electrodes provided on a top surface thereof and has an approximately rectangular shape; a rewiring layer which is provided with a plurality of contact wiring lines connected to the plurality of pad electrodes, is disposed on the semiconductor substrate through an insulating film, and has an approximately rectangular shape; and a plurality of ball electrodes which are provided on the rewiring layer. | 10-03-2013 |
20130256887 | STACKED SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package includes a semiconductor package module including a plurality of semiconductor packages each of which has a first surface, a second surface facing away from the first surface, side surfaces connecting the first surface and the second surface and through-holes formed on the side surfaces to pass through the first surface and the second surface and which are stacked such that their through-holes vertically connect with one another, and adhesive members which are formed between the semiconductor packages and attach the semiconductor packages to one another, a main substrate supporting the semiconductor package module and formed, on a third surface thereof facing the semiconductor package module, with main connection pads which are aligned with the through-holes, and conductive connection members formed in the through-holes and electrically connecting the semiconductor packages with the main connection pads. | 10-03-2013 |
20130264708 | SUBSTRATE DEVICE - A substrate device includes: a plurality of substrates stacked one on another including a substrate on which electronic components are mounted; and a coupling member connecting mechanically and electrically the two opposed substrates, and the coupling member includes: a plurality of core-less solder balls connecting mechanically and electrically the two opposed substrates; and a plurality of spacers configured to keep a clearance between the two opposed substrates wider than a mounting height of the electronic component between the substrates. | 10-10-2013 |
20130264709 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 10-10-2013 |
20130270698 | STRAIN REDUCED STRUCTURE FOR IC PACKAGING - A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region. | 10-17-2013 |
20130270699 | Conical-Shaped or Tier-Shaped Pillar Connections - A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled. | 10-17-2013 |
20130270700 | PACKAGE ON PACKAGE STRUCTURES AND METHODS FOR FORMING THE SAME - The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. | 10-17-2013 |
20130270701 | SYSTEM AND METHODS FOR WIRE BONDING - A semiconductor package comprises a bond pad formed on a first semiconductor die, a surface of the bond pad exposed through an opening in a passivation layer on the first semiconductor die; a raised conductive area formed on top of a passivation layer on a second semiconductor die; and a bond wire having a first end coupled to the bond pad via a ball bond and a second end coupled directly to a surface of the raised conductive area via a stitch bond. The raised conductive area is comprised of a plurality of metal layers, each of the metal layers comprised of a respective material and having a respective thickness. The thickness and material of at least one of the plurality of metal layers is selected such that a hardness of the raised conductive area is at least as hard as a hardness of the bond wire. | 10-17-2013 |
20130277838 | Methods and Apparatus for Solder Connections - Methods and apparatus for solder connections. An apparatus includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive terminal in the opening and extending in a direction normal to the surface of the substrate; and a solder connection formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder connections are disclosed. | 10-24-2013 |
20130277839 | CHIP PACKAGE AND METHOD FOR ASSEMBLING SAME - A chip package includes a PCB, a chip positioned on the PCB and bonding wires electrically connecting the chip to the PCB. The PCB includes a number of first bonding pads formed thereon. Each first bonding pad includes a first soldering ball. The chip includes a number of second bonding pads. Each second bonding pad includes a second bonding ball. Each bonding wire electrically connects a first bonding pad to a corresponding second bonding ball. Each bonding wire forms a vaulted portion upon the first bonding ball. | 10-24-2013 |
20130277840 | Thermally Enhanced Structure for Multi-Chip Device - A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved. | 10-24-2013 |
20130285237 | Low Profile Interposer with Stud Structure - An interposer includes a substrate having a contact pad structure and a stud operably coupled to the contact pad structure. A solder ball is seated on the contact pad structure and formed around the stud. The stud is configured to regulate a collapse of the solder ball when a top package is mounted to the substrate. | 10-31-2013 |
20130285238 | STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES - A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. | 10-31-2013 |
20130285239 | CHIP ASSEMBLY AND CHIP ASSEMBLING METHOD - A chip assembly includes a PCB and a chip positioned on the PCB. The PCB includes a number of first bonding pads. Each bonding pad includes two soldering balls formed thereon. The chip includes a number of second bonding pads, and each second bonding pad corresponds to a respective first bonding pad. The two soldering balls of each first bonding pad are electrically connected to a corresponding second bonding pad via two bonding wires, and the bonding wires are bonded to the second corresponding bonding pad by a wedge bonding manner. | 10-31-2013 |
20130285240 | SENSOR ARRAY PACKAGE - A sensor array package can include a sensor disposed on a first side of a substrate. Signal trenches can be formed along the edges of the substrate and a conductive layer can be deposited in the signal trench and can couple to sensor signal pads. Bond wires can be attached to the conductive layers and can be arranged to be below a surface plane of the sensor. The sensor array package can be embedded in a printed circuit board enabling the bond wires to terminate at other conductors within the printed circuit board. | 10-31-2013 |
20130285241 | Apparatus For Dicing Interposer Assembly - Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed. | 10-31-2013 |
20130285242 | PIN GRID INTERPOSER - An interposer to form a frame around a bottom chip bonded to a package substrate and to standoff a top chip or package for clearance of the bottom chip. The interposer has pins arrayed on a first side which are soldered to the package substrate for reduced interposer z-height and pads arrayed on a second side to which the top package (chip) is bonded. During assembly, the interposer pins may be pressed against pre-soldered pads and the solder reflowed to join the interposer to the package substrate. A top package (chip) is then joined to an opposite side of the interposer to integrate the first and second chips. | 10-31-2013 |
20130292830 | Interposer Having a Defined Through Via Pattern - A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone. | 11-07-2013 |
20130292831 | Methods and Apparatus for Package on Package Devices - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. | 11-07-2013 |
20130292832 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package includes: a first insulating layer; a plurality of first conductive elements disposed in the first insulating layer; a first circuit layer formed on the first insulating layer; a semiconductor chip disposed on the first insulating layer; and an encapsulant formed on the first insulating layer and encapsulating the semiconductor chip. The first conductive elements that are bonding wires have a small diameter and thus occupy desired limited space on the first insulating layer. Therefore, more space is available for the first circuit layer. | 11-07-2013 |
20130292833 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device may include a lower semiconductor package including at least one lower semiconductor chip, at least one upper semiconductor package mounted on the lower semiconductor package to include at least one upper semiconductor chip, a molding layer provided between the lower and upper semiconductor packages, and connection solder balls provided in the molding layer to electrically connect the lower and upper semiconductor packages to each other. Each of the connection solder balls may include a portion protruding upward from the molding layer, and there may be no gap between the connection solder balls and the molding layer. | 11-07-2013 |
20130292834 | MICROELECTRONIC ASSEMBLY WITH JOINED BOND ELEMENTS HAVING LOWERED INDUCTANCE - First and second bond elements, e.g., wire bonds, electrically connect a chip contact with one or more substrate contacts of a substrate, and can be arranged so that the second bond element is joined to the first bond element at each end and so that the second bond element does not touch the chip contact or one or more substrate contacts. A third bond element can be joined to ends of the first and second bond elements. In one embodiment, a bond element can have a looped connection, having first and second ends joined at a first contact and a middle portion joined to a second contact. | 11-07-2013 |
20130299977 | RAMP-STACK CHIP PACKAGE WITH VARIABLE CHIP SPACING - A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique. | 11-14-2013 |
20130299978 | WIRING BOARDS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME - A wiring board and a semiconductor package are provided. The wiring board includes: a metal core including a first surface and a second surface opposite the first surface; a first buildup portion and a second buildup portion including an insulating layer and a pad pattern sequentially stacked, the first and second buildup portions being provided on the first surface and the second surface, respectively; a mask pattern including an opening exposing the pad pattern, the mask pattern being provided on the second buildup portion; and a bather pattern in an area in which a region of the metal core which overlaps with the pad pattern of the second buildup portion is removed, wherein a minimum width of an outer circumference of the barrier pattern is greater than a maximum width of the pad pattern of the second buildup portion. | 11-14-2013 |
20130299979 | PLATED TERMINALS WITH ROUTING INTERCONNECTIONS SEMICONDUCTOR DEVICE - A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals. | 11-14-2013 |
20130299980 | PROTRUDING TERMINALS WITH INTERNAL ROUTING INTERCONNECTIONS SEMICONDUCTOR DEVICE - A semiconductor package includes terminals extending from a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. Each terminal includes a first plated section, a second plated section, and a portion of a sheet carrier from which the semiconductor package is built upon, wherein the portion is coupled between the first and second plated sections. Each interconnection routing is electrically coupled with a terminal and can extend planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes at least one intermediary layer, each including a via layer and an associated routing layer. The semiconductor package includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals. | 11-14-2013 |
20130299981 | MOLDING MATERIAL, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR DEVICE - A molding material used to fabricate a semiconductor package, a method of fabricating the molding composition, and a semiconductor package obtained by using the molding composition are disclosed. A molding composition includes a molding resin material, a filler, and a water absorption material coated on a surface of the filler, such that an amount of external moisture penetrating into the semiconductor package may be diminished. A semiconductor package includes a substrate, at least one chip mounted on the substrate, a connecting portion electrically connecting the at least one chip and the substrate, and a molding portion encapsulating the at least one chip on the substrate, wherein the molding portion includes a molding composition including a molding resin material, a filler, and a water absorption material coated on a surface of the filler, such that an amount of external moisture penetrating into the semiconductor package may be diminished. | 11-14-2013 |
20130299982 | Semiconductor Device and Method of Forming Interposer with Opening to Contain Semiconductor Die - A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die. | 11-14-2013 |
20130299983 | Through Wire Interconnect (TWI) For Semiconductor Components Having Wire In Via And Bonded Connection With Substrate Contact - A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from the first side to the second side thereof; a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate; a dielectric material in the via configured to electrically insulate the wire from the semiconductor substrate; a bonding member bonded to the first end of the wire and to the substrate contact configured to secure the wire to the substrate contact; and a contact on the second end of the wire. | 11-14-2013 |
20130299984 | Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging - Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress. | 11-14-2013 |
20130307148 | LOW LOOP WIRE BONDING - A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die. | 11-21-2013 |
20130307149 | Three-Dimensional Integrated Circuit (3DIC) - An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer. | 11-21-2013 |
20130313705 | IMPLEMENTING DECOUPLING DEVICES INSIDE A TSV DRAM STACK - A method and structures are provided for implementing decoupling capacitors within a DRAM TSV stack. A DRAM is formed with a plurality of TSVs extending completely through the substrate and filled with a conducting material. A layer of glass is grown on both the top and bottom of the DRAM providing an insulator. A layer of metal is grown on each glass layer providing a conductor. The metal and glass layers are etched through to TSVs with a gap provided around the perimeter of via pads. A respective solder ball is formed on the TSVs to connect to another DRAM chip in the DRAM TSV stack. The metal layers are connected to at least one TSV by one respective solder ball and are connected to a voltage source and a dielectric is inserted between the metal layers in the DRAM TSV stack to complete the decoupling capacitor. | 11-28-2013 |
20130313706 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, which comprises a first semiconductor package, a second semiconductor package, and a connection structure. The first semiconductor package includes a first substrate. The first substrate includes a first region and a second region. The second semiconductor package is mounted on the first semiconductor package. The connection structure electrically connects the second semiconductor package and the first semiconductor package. The connection structure comprises first connection patterns at the first region. The first connection patterns provide a data signal at the first region. The connection structure further comprises second connection patterns at the second region. The second connection patterns provide a control/address signal at the second region. A number of the second connection patterns is less than a number of the first connection patterns. | 11-28-2013 |
20130313707 | Electrical Interconnections of Semiconductor Devices and Methods for Fabricating the Same - Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad. | 11-28-2013 |
20130313708 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate). | 11-28-2013 |
20130313709 | INTERCONNECTION OF A PACKAGED CHIP TO A DIE IN A PACKAGE UTILIZING ON-PACKAGE INPUT/OUTPUT INTERFACES - Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme. A second set of single-ended receiver circuits is included on a third die. The receiver circuits have termination. Conductive lines are coupled between the second set of transmitter circuits and the second set of receiver circuits. The lengths of the conductive lines are matched and the second set of receiver circuits is disposed within a second package. | 11-28-2013 |
20130320529 | REACTIVE BONDING OF A FLIP CHIP PACKAGE - An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process. | 12-05-2013 |
20130320530 | SEMICONDUCTOR DEVICE WITH REDISTRIBUTED CONTACTS - A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices. | 12-05-2013 |
20130320531 | Stacked Integrated Chips and Methods of Fabrication Thereof - Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion. | 12-05-2013 |
20130320532 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate. | 12-05-2013 |
20130320533 | 3D SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least one flip package layer on the first functional surface of the packaging substrate and forming at least one wiring and package layer on the flip package layer. The flip package layer is formed by subsequently forming a flip mounting layer, an underfill, a sealant layer, and a wiring layer; and the wiring and package layer is formed by subsequently forming a straight mounting layer, a sealant layer, and a wiring layer. Further, the method includes planting connection balls on the second functional surface of the packaging substrate. | 12-05-2013 |
20130320534 | SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate. | 12-05-2013 |
20130320535 | THREE-DIMENSIONAL SYSTEM-LEVEL PACKAGING METHODS AND STRUCTURES - A 3D system-level packaging method includes providing a packaging substrate, forming a glue layer on the substrate, and attaching a first chip layer at an opposite side of a functional surface of the first chip layer on the packaging substrate through the glue layer. The method also includes forming a first sealant layer on the packaging substrate at a same side attached with the first chip layer and exposing bonding pads of the first chip layer. The method also includes forming first vias in the first sealant layer, forming first vertical metal wiring in the first vias, and forming a first horizontal wiring layer on the sealant layer interconnecting the first chip layer and the first vertical metal wiring. Further, the method includes forming a plurality of package layers on the first sealant layer, and each of the plurality of package layers includes a chip layer, a sealant layer covering the chip layer, and vertical metal wiring and a horizontal wiring layer interconnecting adjacent package layers. | 12-05-2013 |
20130328190 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need. | 12-12-2013 |
20130328191 | CTE ADAPTION IN A SEMICONDUCTOR PACKAGE - A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value | 12-12-2013 |
20130328192 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers. | 12-12-2013 |
20130328193 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of increasing the number of signals. A semiconductor device according to an embodiment of the invention includes memories; a controller that designates addresses of the memories; a mounting board having lines formed thereon, the lines connecting the controller with the memories; and a first ball group that connects the controller with the lines of the mounting board. A plurality of address lines formed on the mounting board includes an address line formed of a front surface wiring layer, and an address line formed of a back surface wiring layer. In each of the front surface wiring layer and the back surface wiring layer, each of the address lines from first balls of the first ball group is routed in order from a first memory to a fourth memory. | 12-12-2013 |
20130328194 | SHORT AND LOW LOOP WIRE BONDING - A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads disposed thereon. The upper surface of the second semiconductor die may be substantially coextensive with the upper surface of the first semiconductor die and extend substantially along a plane. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires has a kink disposed at a height above the plane, a first hump disposed between the first semiconductor die and the kink, and a second hump disposed between the second semiconductor die and the kink. | 12-12-2013 |
20130334685 | EMBEDDED PACKAGES AND METHODS OF MANUFACTURING THE SAME - An embedded package that may be realized by surrounding a semiconductor chip (or a semiconductor die) in a package substrate. A semiconductor chip of an embedded package may be electrically connected to external connection terminals through interconnection wires instead of bumps, and the interconnection wires may be formed using a wire bonding process. A high reliability embedded package results. | 12-19-2013 |
20130341790 | INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT - A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed. | 12-26-2013 |
20130341791 | Process For Enhanced 3D Integration and Structures Generated Using the Same - An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks. | 12-26-2013 |
20140001632 | SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN AIR GAP AND METHOD FOR FORMING | 01-02-2014 |
20140008798 | SEMICONDUCTOR DEVICE - A technique capable of improving reliability of a semiconductor device is provided. In the present invention, as a wiring board on which a semiconductor chip is mounted, a build-up wiring board is not used but a through wiring board THWB is used. In this manner, in the present invention, the through wiring board formed of only a core layer is used, so that it is not required to consider a difference in thermal expansion coefficient between a build-up layer and the core layer, and besides, it is not required either to consider the electrical disconnection of a fine via formed in the build-up layer because the build-up layer does not exist. As a result, according to the present invention, the reliability of the semiconductor device can be improved while a cost is reduced. | 01-09-2014 |
20140015131 | STACKED FAN-OUT SEMICONDUCTOR CHIP - A stacked semiconductor device and method of manufacturing a stacked semiconductor device are described. The semiconductor device may include a reconstituted base layer having a plurality of embedded semiconductor chips. A first redistribution layer may contact the electrically conductive contacts of the embedded chips and extend beyond the boundary of one or more of the embedded chips, forming a fan-out area. Another chip may be stacked above the chips embedded in the base layer and be electrically connected to the embedded chips by a second redistribution layer. Additional layers of chips may be included in the semiconductor device. | 01-16-2014 |
20140015132 | Systems and Methods for Mechanical and Electrical Package Substrate Issue Mitigation - Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers. Further, the package substrate includes a plurality of metallic elements disposed within the plurality of voids and electrically isolated from the generally uniform metallic layer, the metallic elements configured to reduce a physical size of respective voids without electrically contacting the generally uniform metallic layer. | 01-16-2014 |
20140015133 | SUPPLY VOLTAGE OR GROUND CONNECTIONS FOR INTEGRATED CIRCUIT DEVICE - Embodiments disclosed herein may relate to supply voltage or ground connections for integrated circuit devices. As one example, two or more supply voltage bond fingers may be connected together via one or more electrically conductive interconnects. | 01-16-2014 |
20140015134 | Method of Packaging a Die - A method of attaching a die to a substrate is disclosed. A major surface of the die has an array of electrical contacts, and is covered with a tape segment having an array of apertures in register with the contacts. Solder balls are inserted into the apertures. The die is positioned against a substrate with the solder balls in register with the die pads on the surface of the substrate, and a heat treatment process is performed to bond the conductive elements to the corresponding bond pads. | 01-16-2014 |
20140021605 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint. | 01-23-2014 |
20140021606 | CONTROL OF SILVER IN C4 METALLURGY WITH PLATING PROCESS - A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition. | 01-23-2014 |
20140021607 | SOLDER VOLUME COMPENSATION WITH C4 PROCESS - An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side. | 01-23-2014 |
20140021608 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a first semiconductor chip including a first chip pad located on an upper surface thereof, a second semiconductor chip offset-stacked on the upper surface of the first semiconductor chip and including a second chip pad located on an upper surface thereof, a chip coupling ball located on a first board pad of the first semiconductor chip, a chip coupling bump located on a second board pad of the second semiconductor chip, and a chip connection wire connecting the chip coupling ball and the chip coupling bump. The chip connection wire has a chip connection curve part with a reverse curve shape. | 01-23-2014 |
20140027906 | SEMICONDUCTOR DEVICE, A MOBILE COMMUNICATION DEVICE, AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - There is reduced the difference in inductance between bonding wires to be coupled to two semiconductor chips stacked one over another. A semiconductor device includes external terminals, lower and upper semiconductor chips, and first and second bonding wires. The lower semiconductor chip has first bonding pads, and the upper semiconductor chip has second bonding pads. The first bonding wire couples the first bonding pad of the lower semiconductor chip and the external terminal, and the second bonding wire couples the second bonding pad of the upper semiconductor chip and the external terminal. The diameter of the second bonding wire is larger than the diameter of the first bonding wire. | 01-30-2014 |
20140027907 | SEMICONDUCTOR DEVICE WITH EMBEDDED INTERCONNECT PAD - A semiconductor device comprising: a lower semiconductor package that comprises a first set of one or more semiconductor dies, an upper semiconductor package that is stacked on the lower semiconductor package, the upper semiconductor package comprises a second set of one or more semiconductor dies, and a first interconnect pad that is embedded in a top side of the lower semiconductor package to couple the upper semiconductor package to the lower semiconductor package. | 01-30-2014 |
20140035135 | SOLDER BUMP FOR BALL GRID ARRAY - A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1. | 02-06-2014 |
20140035136 | Embedded Package Security Tamper Mesh - Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die. | 02-06-2014 |
20140035137 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - Semiconductor packages are disclosed. In a semiconductor package, a package board may include a hole. A mold layer may cover an upper portion of the package board and extend through the hole to cover at least a portion of a bottom surface of the package board. Each of the sidewalls of a lower mold portion may have a symmetrical structure with respect to the hole penetrating the package board, such that a warpage phenomenon of the semiconductor package may be reduced. | 02-06-2014 |
20140035138 | PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT AND FABRICATION METHOD THEREOF - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapuslant, the warpage of the built-up structure is prevented. | 02-06-2014 |
20140042621 | Package on Package Devices and Methods of Forming Same - An embodiment is a package-on-package (PoP) device comprising a first package on a first substrate and a second package over the first package. A plurality of wire sticks disposed between the first package and the second package and the plurality of wire sticks couple the first package to the second package. Each of the plurality of wire sticks comprise a conductive wire of a first height affixed to a bond pad on the first substrate and each of the plurality of wire sticks is embedded in a solder joint. | 02-13-2014 |
20140042622 | Fine Pitch Package-on-Package Structure - A package-on-package (PoP) device including a substrate having an array of contact pads arranged around a periphery of the substrate, a logic chip mounted to the substrate inward of the array of contact pads, and non-solder bump structures mounted on less than an entirety of the contact pads available. | 02-13-2014 |
20140042623 | SYSTEM IN PACKAGE AND METHOD OF FABRICATING SAME - An assembly has at least one integrated circuit (IC) die fixed in a medium. The assembly has a redistribution layer over the IC die. The redistribution layer has conductors connecting first pads on active faces of the IC die to second pads at an exposed surface of the assembly. A die unit is provided over the IC die. The die unit has a bottom die interconnected to a package substrate. Respective portions of the redistribution layer corresponding to each of the at least one IC die partially underlie the bottom die, and extend beyond the bottom die. The package substrate has contacts connected to the ones of the second pads corresponding to the at least one IC die. | 02-13-2014 |
20140048934 | METHOD TO CONTROL UNDERFILL FILLET WIDTH - A semiconductor device assembly includes a substrate having an area of the surface treated to form a surface roughness. A die is mounted on the substrate by a plurality of coupling members. An underfill substantially fills a gap disposed between the substrate and the die, wherein a fillet width of the underfill is substantially limited to the area of surface roughness. | 02-20-2014 |
20140054772 | SEMICONDUCTOR PACKAGES INCLUDING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME - A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided. | 02-27-2014 |
20140054773 | ELECTRONIC COMPONENT BUILT-IN SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually. | 02-27-2014 |
20140061902 | TECHNIQUES AND CONFIGURATIONS FOR SURFACE TREATMENT OF AN INTEGRATED CIRCUIT SUBSTRATE - Embodiments of the present disclosure are directed towards techniques and configurations for surface treatment of an integrated circuit (IC) substrate. In one embodiment, an apparatus includes an integrated circuit substrate, an interconnect structure disposed on the integrated circuit substrate, the interconnect structure being configured to route electrical signals to or from the integrated circuit substrate and comprising a metal surface, and a protective layer disposed on the metal surface of the interconnect structure, the protective layer comprising a first functional group bonded with the metal surface and a second functional group bonded with the first functional group, wherein the second functional group is hydrophobic to inhibit contamination of the metal surface by hydrophilic materials and further inhibits oxidation of the metal surface. Other embodiments may be described and/or claimed. | 03-06-2014 |
20140061903 | PACKAGE ON PACKAGE STRUCTRUE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing a package on package structure includes the steps of: providing a connection substrate comprising a main body and electrically conductive posts, the main body comprising a first surface and an opposite second surface, each electrically conductive post passing through the first and second surfaces, and each end of the two ends of the electrically conductive post protruding from the main body; arranging a first package device on a side of the first surface of the connection substrate, arranging a package adhesive on a side of the second surface of the connection substrate, thereby obtaining a semi-finished package on package structure; and arranging a second package device on a side of the package adhesive furthest from the first package device, thereby obtaining a package on package structure. | 03-06-2014 |
20140061904 | SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a chip fan-out structure, said method includes forming a dry film with a predetermined pattern. Providing a chip wherein the distribution of the pad is corresponding to the dry film's predetermined pattern. Contacting the surface of the pad with the dry film. Forming a molding compound to encapsulate the chip, and removing the dry film to expose the pads. | 03-06-2014 |
20140061905 | Polyol Photosensitizers, Carrier Gas UV Laser Ablation Sensitizers, and Other Additives and Methods For Making and Using Same - Disclosed are photo sensitizers that include a polyol moiety covalently bonded to a fused aromatic moiety. Also disclosed is a method for improving UV laser ablation performance of a coating, such as a cationic UV curable coating, by incorporating an oxalyl-containing additive into the cationic UV curable or other coating. Oxalyl-containing sensitizers having the formula Q-O—C(O)—C(O)—O—R | 03-06-2014 |
20140061906 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes a semiconductor substrate, a metal layer formed on the semiconductor substrate, a conductive pillar, and a solder ball. The conductive pillar is formed on and electrically connected with the metal layer, wherein the conductive pillar has a bearing surface and a horizontal sectional surface under the bearing surface, and the contact surface area of the bearing surface is larger than the area of the horizontal sectional surface. The solder ball is located on the conductive pillar and covers the bearing surface. | 03-06-2014 |
20140061907 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes a metal line and a metal pad formed at different integration levels of a semiconductor substrate, and an isolation layer by which the metal line and the metal pad are spaced apart from each other. The semiconductor device prevents short-circuiting between the metal pad and the metal line although the isolation layer is dislocated. | 03-06-2014 |
20140061908 | PLASTIC BALL GRID ARRAY PACKAGE HAVING REINFORCEMENT RESIN - A plastic ball grid array package having a reinforcement resin that may address the problem of delamination and cracks in a boundary region between a sealing resin and a substrate. The reinforcement resin is formed at an outer region of a sealing resin and has a height that is lower than that of the sealing resin. The reinforcement resin may be formed of the same material used to form the sealing resin and has a structure completely covering a first surface of the substrate. Accordingly, cracks and delamination defects of the semiconductor package may be reduced by absorbing stress that occurs by physical impact in a boundary region between the substrate and the sealing resin. | 03-06-2014 |
20140070412 | Semiconductor Device and Method for Manufacturing the Same - A method for manufacturing a semiconductor device includes forming a lower electrode pattern on a substrate, forming a first insulating layer on the lower electrode pattern, forming an upper electrode pattern on the first insulating layer, forming an etch blocking spacer at a side of the upper electrode pattern, forming a second insulating layer on the upper electrode pattern, etching the second insulating layer to form a cavity which exposes the etch blocking spacer, and forming a contact ball in the cavity. | 03-13-2014 |
20140070413 | SEMICONDUCTOR DEVICE WITH FRONT AND BACK SIDE RESIN LAYERS HAVING DIFFERENT THERMAL EXPANSION COEFFICIENT AND ELASTICITY MODULUS - Disclosed are a semiconductor device wherein warping of a semiconductor chip due to a sudden temperature change can be prevented without increasing the thickness, and a semiconductor device assembly. The semiconductor device comprises a semiconductor chip, a front side resin layer formed on the front surface of the semiconductor chip by using a first resin material, and a back side resin layer formed on the back surface of the semiconductor chip by using a second resin material having a higher thermal expansion coefficient than the first resin material. The back side resin layer is formed thinner than the front side resin layer. | 03-13-2014 |
20140077369 | Packaging Devices and Methods - Packaging devices and packaging methods are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming a plurality of through-substrate vias (TSVs) in an interposer substrate. The interposer substrate is recessed or a thickness of the plurality of TSVs is increased to expose portions of the plurality of TSVs. A conductive ball is coupled to the exposed portion of each of the plurality of TSVs. | 03-20-2014 |
20140077370 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity. | 03-20-2014 |
20140077371 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a semiconductor device including at least one of the following steps: ( | 03-20-2014 |
20140077372 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on/over the lower electrode pattern. (3) Forming a second interlayer insulating layer over the first interlayer insulating layer to include an intermediate electrode pattern. (4) Forming an upper electrode pattern over the second interlayer insulating layer. (5) Forming a third interlayer insulating layer over the upper electrode pattern. (6) Etching the first to third interlayer insulating layers to form a cavity which exposes a portion of the intermediate electrode pattern. (7) Forming a contact ball in the cavity. | 03-20-2014 |
20140077373 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. | 03-20-2014 |
20140084461 | FLUX MATERIALS FOR HEATED SOLDER PLACEMENT AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure are directed towards flux materials for heated solder placement and associated techniques and configurations. In one embodiment, a method includes depositing a flux material on one or more pads of a package substrate, the flux material including a rosin material and a thixotropic agent and depositing one or more solder balls on the flux material disposed on the one or more pads, wherein depositing the one or more solder balls on the flux material is performed at a temperature greater than 80° C., and wherein the rosin material and the thixotropic agent are configured to resist softening at the temperature greater than 80° C. Other embodiments may be described and/or claimed. | 03-27-2014 |
20140084462 | Wafer Level Semiconductor Package - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 03-27-2014 |
20140084463 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE STRUCTURE - A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect. | 03-27-2014 |
20140091461 | DIE CAP FOR USE WITH FLIP CHIP PACKAGE - A die cap for use with flip chip packages, flip chip packages using a die cap, and a method for manufacturing flip chip packages with a die cap are provided in the invention. A die cap encases the die of flip chip packages about its top and sides for constraining the thermal deformation of the die during temperature change. The CTE (coefficient of thermal expansion) mismatch between the die and substrate of flip chip packages is the root cause for warpage and reliability issues. The current inventive concept is to reduce the CTE mismatch by using a die cap to constrain the thermal deformation of the die. When a die cap with high CTE and high modulus is used, the die with the die cap has a relatively high overall CTE, reducing the CTE mismatch. As a result, the warpage and reliability of flip chip packages are improved. | 04-03-2014 |
20140091462 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a dielectric layer made of a material used for fabricating built-up layer structures; a conductive trace layer formed on the dielectric layer; a semiconductor chip is mounted on and electrically connected to the conductive trace layer; and an encapsulant formed over the dielectric layer to encapsulate the semiconductor chip and the conductive trace layer. Since a strong bonding is formed between the dielectric layer and the conductive trace layer, the present invention can prevent delamination between the dielectric layer and the conductive trace layer from occurrence, thereby improving reliability and facilitating the package miniaturization by current fabrication methods. | 04-03-2014 |
20140091463 | SEMICONDUCTOR PACKAGE APPARATUS - According to example embodiments of inventive concepts, a semiconductor package apparatus includes a first semiconductor package including a first substrate, a first solder resist layer on the first substrate, and a first sealing member that covers and protects the first solder resist layer, and a plurality of solder balls on the first substrate. The plurality of solder balls includes a first solder ball having a first height and a second solder ball having a second height that is different from the first height. The first sealing member includes holes that expose the solder balls. | 04-03-2014 |
20140091464 | SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a semiconductor substrate provided with semiconductor elements, a lower layer wiring pattern which includes first wiring and second wiring, the first wiring and the second wiring disposed separately so as to be flush with each other, and the first wiring and the second wiring being fixed at a mutually different potential, an uppermost interlayer film disposed on the lower layer wiring pattern, a titanium nitride layer disposed on the uppermost interlayer film so as to cover the first wiring and the second wiring, and the titanium nitride having the thickness of 800 Å or more, and a pad metal disposed on the titanium nitride layer. | 04-03-2014 |
20140097535 | STACKED MULTI-CHIP INTEGRATED CIRCUIT PACKAGE - A multi-chip integrated circuit (IC) package is provided which is configured to protect against failure due to warpage. The IC package may comprise a substrate, a level-one IC die and a plurality of level-two IC dies. The level-one IC die having a surface that is electrically coupled to the substrate. The plurality of level-two IC dies is stacked above the level-one IC die. The plurality of level-two IC dies may each have an active surface that is electrically coupled to the substrate. The plurality of level-two IC dies may be arranged side by side such that the active surfaces of the plurality of level-two IC dies are positioned substantially in a same plane. Relative to a single die configuration, the level-two IC dies are separated thereby inhibiting cracking, peeling and/or other potential failures due to warpage of the IC package. | 04-10-2014 |
20140097536 | TWO-SIDED-ACCESS EXTENDED WAFER-LEVEL BALL GRID ARRAY (eWLB) PACKAGE, ASSEMBLY AND METHOD - A two-sided-access (TSA) eWLB is provided that makes it possible to easily access electrical contact pads disposed on both the front and rear faces of the die(s) of the eWLB package. When fabricating the IC die wafer, metal stamps are formed in the IC die wafer in contact with the rear faces of the IC dies. When the IC dies are subsequently reconstituted in an artificial wafer, portions of the metal stamps are exposed through the mold of the artificial wafer. When the artificial wafer is sawed to singulate the TSA eWLB packages and the packages are mounted on PCBs, any electrical contact pad that is disposed on the rear face of the IC die can be accessed via the respective metal stamp of the IC die. | 04-10-2014 |
20140110838 | SEMICONDUCTOR DEVICES AND PROCESSING METHODS - Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness. | 04-24-2014 |
20140110839 | Metal Bump Joint Structure - A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension. | 04-24-2014 |
20140110840 | Semiconductor Packages with Integrated Antenna and Method of Forming Thereof - In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface. | 04-24-2014 |
20140110841 | Semiconductor Packages with Integrated Antenna and Methods of Forming Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar. | 04-24-2014 |
20140110842 | USING A DOUBLE-CUT FOR MECHANICAL PROTECTION OF A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP) - Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (θ) of tooling impact upon a vertical face the semiconductor device. | 04-24-2014 |
20140117543 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes a substrate having a vent hole extending through the substrate, a semiconductor chip mounted on an upper surface of the substrate, a plurality of solder ball pads formed on a lower surface of the substrate, and an encapsulant covering the upper surface of the substrate, the semiconductor chip, and an entirety of the lower surface of the substrate except for regions in which the solder ball pads are formed. | 05-01-2014 |
20140117544 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A resin sealed semiconductor device includes a semiconductor element having a plurality of metal plated plastic particle core or metal particle core micro-balls including an internal terminal surface and an external connection electrode. Metal wires electrically connect the semiconductor element to the internal terminal and are bonded to the internal terminal surface by a wire bond connection coupling the metal wire to the metal plating, where the metal wire and the metal plating are different materials. A sealing body seals the semiconductor element, a part of each the plurality of the terminals, and the metal wires, where a back surface of the semiconductor element is exposed by the sealing body, and a part of each the plurality of micro-balls project from a bottom surface of the sealing body to provide the external connection electrodes. | 05-01-2014 |
20140124925 | MULTI-SOLDER TECHNIQUES AND CONFIGURATIONS FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY - Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed. | 05-08-2014 |
20140124926 | Method And System For A Chaser Pellet In A Semiconductor Package Mold Process - Methods and systems for a chaser pellet in a semiconductor mold process are disclosed and may include a semiconductor package comprising semiconductor die coupled to a packaging substrate where the packaging substrate and the coupled semiconductor die may be placed in a mold chase. A chaser pellet may be placed on a target pellet comprising low alpha epoxy mold compound (EMC) in a pellet chamber coupled to the mold chase via a runner. Heat may be applied to the pellet chamber to melt the target pellet. Pressure may be applied to the chaser pellet to force EPM from the molten target pellet through the runner to the mold chase. The die may be encapsulated with the epoxy mold compound from the molten target pellet. Passive devices may be coupled to the semiconductor package and may be encapsulated by the EPM from the molten target pellet. | 05-08-2014 |
20140124927 | SEMICONDUCTOR IC PACKAGING METHODS AND STRUCTURES - An IC packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a metal pad and an insulating layer and the insulating layer has an opening to expose the meal pad. The method also includes forming an under-the-ball meal electrode on the exposed metal pad. The under-the-ball metal electrode has an electrode body and an electrode tail, the electrode body is located at a bottom portion of the under-the-ball metal electrode and is in contact with the metal pad, and the electrode tail is located at a top portion of the under-the-ball meal electrode. Further, the method includes forming a solder ball on the under-the-ball metal electrode. | 05-08-2014 |
20140124928 | SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor packaging structures and methods for forming the same. In an exemplary method, a chip having a metal interconnect structure thereon can be provided. An insulating layer can be formed on the chip to expose the metal interconnect structure. A columnar electrode can be formed on the metal interconnect structure. A portion of the metal interconnect structure surrounding a bottom of the columnar electrode can be exposed. A diffusion barrier layer can be formed on sidewalls and a top surface of the columnar electrode, and on the exposed portion of the metal interconnect structure surrounding the bottom of the columnar electrode. A solder ball can then be formed on the diffusion barrier layer. The solder ball can wrap at least the sidewalls and the top surface of the columnar electrode. | 05-08-2014 |
20140124929 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the semiconductor substrate, a first insulating layer disposed over the semiconductor substrate, a columnar electrode disposed over the solder pad, and a solder ball disposed on the columnar electrode. The first insulating layer can include a first opening to expose a solder pad of the plurality of solder pads. The columnar electrode can include a bulk material and a through hole in the bulk material. The through hole can expose at least a surface portion of the solder pad. The solder ball can include a convex metal head on a top surface of the bulk material of the columnar electrode, and a filling part filled in the through hole. | 05-08-2014 |
20140124930 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 05-08-2014 |
20140131866 | TRACE ROUTING WITHIN A SEMICONDUCTOR PACKAGE SUBSTRATE - A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces. | 05-15-2014 |
20140131867 | SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE USING COMPUTING SYSTEM, APPARATUS FOR FABRICATING SEMICONDUCTOR PACKAGE INCLUDING THE SYSTEM, AND SEMICONDUCTOR PACKAGE DESIGNED BY THE METHOD - A system for designing a semiconductor package using a computing system, comprising: a virtual stacking module configured to receive a layout parameter for a first chip, a layout parameter for a second chip, and a layout parameter for a package substrate, and in response to the layout parameters of the first chip, the second chip, and the package substrate, generate a plurality of virtual layouts in which the first and second chips are stacked, on the package substrate; a modeling module configured to model operating parameters for the first and second chips and the package substrate in response to the virtual layouts; and a characteristic analyzing module configured to analyze operating characteristics of the virtual layouts in response to the modeled operating parameters. | 05-15-2014 |
20140138822 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE - An integrated circuit (IC) package, device, including a substrate having a top surface with an IC die mounting area and a peripheral area surrounding the mounting area, a plurality of parallel conductor layers, a plurality of insulating layers and a plurality of plated through holes (PTHs) extending through the conductor layers and insulating layers. Various substrate structures in which certain of the PTHs and/or conductor layers and/or insulating layers have different CTE's than the others is disclosed. The various structures may reduce circuit failures due to substrate warpage and/or solder joint damage associated with a CTE mismatch between the substrate and the IC die. | 05-22-2014 |
20140138823 | VARIABLE-SIZE SOLDER BUMP STRUCTURES FOR INTEGRATED CIRCUIT PACKAGING - One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package. | 05-22-2014 |
20140138824 | OFFSET INTEGRATED CIRCUIT PACKAGING INTERCONNECTS - One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0° C. to about −100° C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature. | 05-22-2014 |
20140138825 | MOLDED INSULATOR IN PACKAGE ASSEMBLY - Embodiments of the present disclosure describe techniques and configurations for package assembly including an embedded element and a molded insulator material. In some embodiments, an apparatus includes an electrical element (such as a die or a bridge interconnect structure) positioned on a surface of an insulator layer, a conductive pad positioned on the surface of the insulator layer and spaced apart from the electrical element, and a molded insulator material disposed on the surface of the insulator layer adjacent to the electrical element and on the conductive pad. Other embodiments may be described and/or claimed. | 05-22-2014 |
20140138826 | High-Density Package-on-Package Structure - A bare-die first package includes a patterned insulating layer that exposes first package balls in vias. The vias enable a second package to be positioned on the first package in a proper ball-to-ball alignment without the need for flattening or coining. | 05-22-2014 |
20140138827 | ENHANCED FLIP CHIP PACKAGE - According to various embodiments, a flip chip package structure is provided in which a redistribution layer (RDL) is disposed on a surface of both a semiconductor chip and one or more lateral extensions of the semiconductor chip surface. The lateral extensions may be made using, e.g., a reconstituted wafer to implement a fanout region lateral to one or more sides of the semiconductor chip. One or more electrical connectors such as solder bumps or copper cylinders may be applied to the RDL, and an interposer such as a PCB interposer may be connected to the electrical connectors. In this way, a relatively tight semiconductor pad pitch may be accommodated and translated to an appropriate circuit board pitch without necessarily requiring a silicon or glass interposer. | 05-22-2014 |
20140145331 | MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A multi-chip package may include a system on a chip (SOC) and a plurality of memory devices arranged in the same layer on the SOC. Accordingly, as the multi-chip package may not need to use a TSV, so that manufacturing cost of the multi-chip package is reduced. Moreover, a memory bandwidth between the SOC and the first and second memory devices may increase. | 05-29-2014 |
20140151879 | STRESS-RESILIENT CHIP STRUCTURE AND DICING PROCESS - A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes. | 06-05-2014 |
20140151880 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a package on package arrangement comprising a first package including a substrate layer including a top side, and a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface, and a first die coupled to the bottom side of the substrate layer. The arrangement also comprises a second package including a plurality of rows of solder balls and at least one of one or both of an active component or a passive component. The second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package. The active component and/or a passive component is attached to the substantially flat surface of the top side of the substrate layer of the first package. | 06-05-2014 |
20140151881 | PACKAGED SEMICONDUCTOR CHIPS WITH ARRAY - A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device. | 06-05-2014 |
20140159237 | SEMICONDUCTOR PACKAGE AND METHOD FOR ROUTING THE PACKAGE - A semiconductor package having improved performance and reliability and a method of fabricating the same are provided. The semiconductor package includes a processing chip including a first pin at a first side to output a first signal, and a second pin at a second side to output a second signal different from the first signal, and a substrate having the processing chip thereon, the substrate including a first bump ball electrically connected to the first pin and a second bump ball electrically connected to the second pin, wherein the first bump ball and the second bump ball are adjacent at one of the first and second sides of the substrate. | 06-12-2014 |
20140167262 | SEMICONDUCTOR PACKAGE SIGNAL ROUTING USING CONDUCTIVE VIAS - A mechanism is provided by which signal travel distance within and between semiconductor device packages is reduced and substrate size and complexity can be reduced. This capacity is provided by virtue of a conductive via that intersects a wire bond molded within a package substrate. The via provides a direct electrical connection between an external signal transmitter or receiver and the points connected by the wire bond, and thereby avoiding the need for the signal to transit built up interconnects in the semiconductor device package. Conductive vias can provide connectivity through or to a package substrate, and can be through vias or blind vias. The conductive via is formed by either mechanical or laser drilling, and is filled using standard fill techniques, and is therefore readily incorporated into a package production flow. | 06-19-2014 |
20140175644 | METHODS OF FORMING ULTRA THIN PACKAGE STRUCTURES INCLUDING LOW TEMPERATURE SOLDER AND STRUCTURES FORMED THERBY - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure. | 06-26-2014 |
20140175645 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Embodiments relate to a method for manufacturing a semiconductor device including at least one of: (1) Forming a lower electrode pattern on a substrate. (2) Forming an etch stop film on/over the lower electrode pattern. (3) Forming a first interlayer insulating layer on/over the etch stop film. (4) Forming an upper electrode pattern on/over the first interlayer insulating layer. (5) Forming a second interlayer insulating layer on/over the upper electrode pattern. (6) Forming an etch blocking layer positioned between the lower electrode pattern and the upper electrode pattern which passes through the second interlayer insulating layer and the first interlayer insulating layer. (7) Forming a cavity which exposes a side of the etch blocking layer by etching the second interlayer insulating layer and the first interlayer insulating layer. (8) Forming a contact ball in the cavity. | 06-26-2014 |
20140175646 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME - An exemplary package substrate includes a package substrate, a first connection substrate, a first chip, a dielectric adhesive sheet, a second chip, and a second connection substrate. The package substrate includes many first and second electrical contact pads. The first connection substrate includes many third and fourth electrical contact pads. Each fourth electrical contact pad is electrically connected to one first electrical contact pad. The first chip includes many first electrode pads. Each first electrode pad is electrically connected to the corresponding third electrical contact pad. The second chip is connected to the first chip by the dielectric adhesive sheet, and includes many second electrode pads. The second connection substrate includes many fifth and sixth electrical contact pads. Each fifth electrical contact pad is electrically connected to one second electrode pad, and each sixth electrical contact pad is electrically connected to one second electrical contact pad. | 06-26-2014 |
20140175647 | PACKAGED MICROELECTRONIC ELEMENTS HAVING BLIND VIAS FOR HEAT DISSIPATION - System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having atop surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind vias to other connecting components. | 06-26-2014 |
20140175648 | Semiconductor Device and Power Supply Unit Utilizing the Same - A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact, with the IC socket of the semiconductor device. Each pair of nearest neighbors, of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals. | 06-26-2014 |
20140183731 | Package on Package (PoP) Bonding Structures - Various embodiments of mechanisms for forming through package vias (TPVs) with multiple conductive layers and/or recesses in a die package and a package on package (PoP) device with bonding structures utilizing the TPVs are provided. One of the multiple conductive layers acts as a protective layer of the main conductive layer of the TPVs. The protective layer is less likely to oxidize and also has a slower formation rate of intermetallic compound (IMC) when exposed to solder. The recesses in TPVs of a die package are filled by solder from the other die package and the IMC layer formed is below the surface of TPVs, which strengthen the bonding structures. | 07-03-2014 |
20140183732 | PACKAGE ON PACKAGE BONDING STRUCTURE AND METHOD FOR FORMING THE SAME - The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages. | 07-03-2014 |
20140183733 | METAL CORE SOLDER BALL AND HEAT DISSIPATION STRUCTURE FOR SEMICONDUCTOR DEVICE USING THE SAME - Disclosed is a metal core solder ball having improved heat conductivity, including a metal core having a diameter of 40˜600 μm, a first plating layer formed on the outer surface of the metal core, and a second plating layer formed on the outer surface of the first plating layer. | 07-03-2014 |
20140183734 | SEMICONDUCTOR DEVICE - Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads. | 07-03-2014 |
20140197536 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THEREOF - The invention provides an electronic device package and method for manufacturing thereof. The electronic device package includes a substrate, an electronic chip, a bonding pad, a first passivation layer, a conductive layer, a second passivation layer, and a solder ball. The conductive layer has a first side end and a second side end, and the solder ball is positioned on the first side end of the conductive layer. The second passivation layer contacts with both the upper surface and the sidewall of the second side end of the conductive layer, and the first passivation layer contacts with the lower surface of the second side end of the conductive layer, so as to completely encapsulate the second end of the conductive layer. The electronic device package accordingly prevents the moisture penetration and to enhance the reliability of the electronic device. | 07-17-2014 |
20140203433 | IN-SITU THERMOELECTRIC COOLING - Methods and structures for thermoelectric cooling of 3D semiconductor structures are disclosed. Thermoelectric vias (TEVs) to form a thermoelectric cooling structure. The TEVs are formed with an etch process similar to that used in forming electrically active through-silicon vias (TSVs). However, the etched cavities are filled with materials that exhibit the thermoelectric effect, instead of a conductive metal as with a traditional electrically active TSV. The thermoelectric materials are arranged such that when a voltage is applied to them, the thermoelectric cooling structure carries heat away from the interior of the structure from the junction where the thermoelectric materials are electrically connected. | 07-24-2014 |
20140210080 | PoP Device - A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate. | 07-31-2014 |
20140210081 | Packaging Methods and Packaged Semiconductor Devices - Packaging methods and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging semiconductor devices includes forming first contact pads on a carrier, forming a wiring structure over the first contact pads, and forming second contact pads over the wiring structure. A first packaged semiconductor device is coupled to a first set of the second contact pads, and a second packaged semiconductor device is coupled to a second set of the second contact pads. The carrier is removed. The second packaged semiconductor device comprises a different package type than the first packaged semiconductor device. | 07-31-2014 |
20140210082 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device. The semiconductor device includes: a first board; a second board joined to the first board; a connection terminal provided between the first board and the second board and electrically connecting the first board and the second board; and an electronic component on at least one of the first board and the second board. The connection terminal serves as an antenna. | 07-31-2014 |
20140210083 | THERMALLY AND ELECTRICALLY ENHANCED BALL GRID ARRAY PACKAGE - In one embodiment, a device package is provided. The device package can include a substrate having first and second opposing surfaces, an opening being formed through the first and second surfaces of the substrate; a stiffener coupled to the first surface of the substrate, the stiffener having an extending portion that extends into the opening of the substrate; and an integrated circuit (IC) die coupled to the extending portion of the stiffener, the IC die being electrically coupled to the substrate. | 07-31-2014 |
20140217585 | 3D INTEGRATED CIRCUIT PACKAGE WITH THROUGH-MOLD FIRST LEVEL INTERCONNECTS - 3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die. | 08-07-2014 |
20140217586 | PACKAGE-ON-PACKAGE DEVICE - A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package. Further, data and command pads of a logic chip may be located to be adjacent to data and command pads of the memory chips. Accordingly, a routing distance between pads can be contracted and thus signal delivery speed can be improved. This makes it possible to improve an operation speed of the device. | 08-07-2014 |
20140217587 | Wafer Leveled Chip Packaging Structure and Method Thereof - A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias. | 08-07-2014 |
20140231992 | MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE AND RELATED METHOD - Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad. | 08-21-2014 |
20140231993 | PACKAGE-ON-PACKAGE STRUCTURES - Embodiments of the present disclosure provide a first package configured to be coupled to a second package, wherein the first package comprises: a ball grid array substrate; a die coupled to the ball grid array substrate; two rows of ball pads arranged around a periphery of the ball grid array substrate, wherein the ball pads of the two rows of ball pads are configured to receive solder balls to couple the first package to the second package, wherein an outer row of the two rows of ball pads comprises at least some ball pads configured as a first type of ball pad, wherein an inner row of the two rows of ball pads comprises at least some ball pads configured as a second type of ball pad, wherein the first type of ball pad is different than the second type of ball pad. | 08-21-2014 |
20140231994 | APPARATUS FOR LEAD FREE SOLDER INTERCONNECTIONS FOR INTEGRATED CIRCUITS - An apparatus includes an integrated circuit having at least one input/output terminal comprising copper formed thereon. A metal cap layer overlies an upper surface of the at least one input/output terminal. A substrate includes at least one conductive trace formed on a first surface, and a metal finish layer overlies a portion of the at least one conductive trace. A lead free solder connection is disposed between the metal cap layer and the metal finish layer, and a first intermetallic compound is disposed at an interface between the metal cap layer and the lead free solder connection. The lead free solder connection has a copper content of less than 0.5 wt. %, and the first intermetallic compound is substantially free of copper. | 08-21-2014 |
20140239497 | PACKAGED SEMICONDUCTOR DEVICE - A packaged semiconductor device includes a substrate including a first major surface, a second major surface, first vias running between the first major surface and the second major surface, first contact pads contacting the first vias at the first major surface, second contact pads contacting the first vias at the second major surface, and an opening between the first major surface and the second major surface. A first integrated circuit (IC) die is positioned in the opening in the substrate. Electrical connections are formed between the second IC die and the second contact pads. A first conductive layer is over the first contact pads and contact pads on the first IC die. Encapsulating material is on the second major surface of the substrate around the first IC die, the second IC die, the electrical connections, and between edges of the opening and edges of the first IC die. | 08-28-2014 |
20140246773 | Chip on Chip Attach (Passive IPD and PMIC) Flip Chip BGA Using New Cavity BGA Substrate - An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack. The die stack is flip-chip attached to a laminate substrate having a cavity drilled therein wherein the smaller die fits into the cavity. The die to die attach is not limited to IPD and PMIC and can be used for other die types as required. | 09-04-2014 |
20140246774 | SEMICONDUCTOR DEVICE HAVING A BUFFER LAYER AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and method for manufacturing the same are provided. A metal pad can be electrically connected to metal interconnections in a lower portion of the device. A passivation layer can be provided and can exposes a portion of the metal pad, and a buffer layer can be formed on lateral sides of the passivation layer. | 09-04-2014 |
20140252608 | Method and Apparatus for Packaging Pad Structure - Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing. | 09-11-2014 |
20140252609 | Package-on-Package Structure and Methods for Forming the Same - A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material. | 09-11-2014 |
20140252610 | Packaging Devices and Methods of Manufacture Thereof - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region. | 09-11-2014 |
20140252611 | Ball Amount Process in the Manufacturing of Integrated Circuit - An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness. | 09-11-2014 |
20140252612 | WIRING SUBSTRATE FOR A SEMICONDUCTOR DEVICE HAVING DIFFERENTIAL SIGNAL PATHS - A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land. | 09-11-2014 |
20140252613 | SEMICONDUCTOR DEVICE - The present invention reduces the occurrence of fracture in external terminal connecting sections and improves the reliability of secondary packaging of a semiconductor device. Specifically, the present invention provides a semiconductor device including a wiring board, a semiconductor chip mounted on one surface of the wiring board via a bonding member, and external electrodes formed on the other surface of the wiring board and electrically connected to the semiconductor chip. In the semiconductor device, a peripheral end of the bonding member is arranged in a position where the peripheral end does not overlap the external electrodes. | 09-11-2014 |
20140264853 | Adhesion between Post-Passivation Interconnect Structure and Polymer - An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a thin oxide film layer directly over a top surface of the PPI structure, and a polymer layer over the thin oxide film layer and PPI structure. | 09-18-2014 |
20140264854 | MULTI-CHIP MODULE WITH SELF-POPULATING POSITIVE FEATURES - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are mechanically coupled and aligned by positive and negative features on facing surfaces of the substrates. These positive and negative features may mate and self-lock with each other. The positive features may be self-populated into the negative features on at least one of the substrates using a hydrophilic layer in the negative feature. This hydrophilic layer may be used in conjunction with a hydrophobic layer surrounding the negative features on a top surface of at least one of the substrates. | 09-18-2014 |
20140264855 | SEMICONDUCTOR COMPOSITE LAYER STRUCTURE AND SEMICONDUCTOR PACKAGING STRUCTURE HAVING THE SAME THEREOF - A semiconductor composite layer structure disposed on a substrate having an electronic circuit structure and a first conductive layer is disclosed. The semiconductor composite layer structure comprises a plurality of dielectric layers, a first wetting layer, a stiff layer and a second wetting layer. The dielectric layers are disposed on the substrate separately. The first wetting layer is disposed on the dielectric layer and the substrate between the dielectric layers. The stiff layer is disposed on the first wetting layer. The second wetting layer is disposed on stiff layer, for contacting with a second conductive layer. | 09-18-2014 |
20140264856 | Package-on-Package Structures and Methods for Forming the Same - A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. | 09-18-2014 |
20140264857 | Package-on-Package with Via on Pad Connections - An interposer includes a core dielectric material, a conductive pipe penetrating through the core dielectric material, and a metal pad underlying the conductive pipe. The metal pad includes a center portion overlapped by a region encircled by the conductive pipe, and an outer portion in contact with the conductive pipe. A dielectric layer is underlying the core dielectric material and the metal pad. A via is in the dielectric layer, wherein the via is in physical contact with the center portion of the metal pad. | 09-18-2014 |
20140264858 | Package-on-Package Joint Structure with Molding Open Bumps - A device comprises a bottom package comprising a plurality of metal bumps formed on a first side of the bottom package and a plurality of first bumps formed on a second side of the bottom package, a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps, and wherein second bumps and respective metal bumps form a joint structure and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer. | 09-18-2014 |
20140264859 | Packaging Devices and Methods of Manufacture Thereof - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate. | 09-18-2014 |
20140284794 | TIN-BASED SOLDER BALL AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A tin (Sn)-based solder ball having appropriate characteristics for electronic products and a semiconductor package including the same are provided. The tin-based solder ball includes about 0.3 to 3.0 wt. % silver (Ag), about 0.4 to 0.8 wt. % copper (Cu), about 0.01 to 0.09 wt. % nickel (Ni), about 0.1% to 0.5 wt. % bismuth (Bi), and balance of tin (Sn) and unavoidable impurities. | 09-25-2014 |
20140284795 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Various embodiments are directed to a semiconductor package and a method for manufacturing the same. A semiconductor package includes the following: a substrate having a plurality of connection pads; a semiconductor chip provided with a plurality of bonding pads on a first surface thereof and attached onto the substrate in a face-down position so that the bonding pads are positioned right above the corresponding connection pads; and thermoplastic conductive members introduced between the substrate and the semiconductor chip such that the bonding pad and the corresponding connection pad may be electrically connected. | 09-25-2014 |
20140284796 | MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES - Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece having a plurality of dies and at least one passage extending through the microfeature workpiece from a first side of the microfeature workpiece to an opposite second side of the microfeature workpiece. The method can further include forming a conductive plug in the passage adjacent to the first side of the microelectronic workpiece, and depositing conductive material in the passage to at least generally fill the passage from the conductive plug to the second side of the microelectronic workpiece. | 09-25-2014 |
20140291842 | ENHANCED FLIP-CHIP DIE ARCHITECTURE - A method of assembling a multi-chip electronic device into a thin electronic package entails inverting a flip-chip die arrangement over a hollow substrate, stacking additional dies on the hollow substrate to form a multi-chip electronic device, and encapsulating the multi-chip electronic device. Containment of the encapsulant can be achieved by joining split substrate portions, or by reinforcing a hollow unitary substrate, using a removable adhesive film. Use of the removable adhesive film facilitates surrounding the multi-chip electronic device with the encapsulant. The adhesive film can also prevent encapsulant from creeping around the substrate to an underside of the substrate that supports solder ball pads for subsequent attachment to a ball grid array (BGA) or a land grid array (LGA). | 10-02-2014 |
20140291843 | HYBRID SOLDER AND FILLED PASTE IN MICROELECTRONIC PACKAGING - Hybrid solder for solder balls and filled paste are described. A solder ball may be formed of a droplet of higher temperature solder and a coating of lower temperature solder. This may be used with a solder paste that has an adhesive and a filler of low temperature solder particles, the filler comprising less than 80 weight percent of the paste. The solder balls and paste may be used in soldering packages for microelectronic devices. A package may be formed by applying a solder paste to a bond pad of a substrate, attaching a hybrid solder ball to each pad using the paste, and attaching the package substrate to a microelectronic substrate by reflowing the hybrid solder balls to form a hybrid solder interconnect. | 10-02-2014 |
20140291844 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device having a stably formed structure capable of being electrically connected to a second electronic device without causing damage to the semiconductor device, and a manufacturing method thereof. In one embodiment, the semiconductor device may comprise a semiconductor die, an encapsulation part formed on lateral surfaces of the semiconductor die, a dielectric layer formed on the semiconductor die and the encapsulation part, a redistribution layer passing through a part of the dielectric layer and electrically connected to the semiconductor die, a plurality of conductive balls extending through other parts of the dielectric layer and electrically connected to the redistribution layer where the conductive balls are exposed to an environment outside of the semiconductor device, and conductive vias extending through the encapsulation part and electrically connected to the redistribution layer. | 10-02-2014 |
20140291845 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. | 10-02-2014 |
20140306343 | CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME - A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size. | 10-16-2014 |
20140312495 | FAN OUT INTEGRATED CIRCUIT DEVICE PACKAGES ON LARGE PANELS - A method of manufacturing an integrated circuit package. The method comprises providing a carrier substrate having a planar surface. The method comprises placing a plurality of semiconductor device dies active-side down at laterally spaced-apart locations on the planar surface. The method comprises covering the semiconductor device dies with a mold compound to define laterally spaced-apart mold sub-arrays on the planar surface. The method comprises curing the laterally spaced-apart mold sub-arrays, wherein the semiconductor device dies are retained at substantially the same laterally spaced-apart locations on the planar surface after the curing. | 10-23-2014 |
20140312496 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICE - The present invention relates to a semiconductor package and a semiconductor device and a method of making the same. The method of making the semiconductor package comprises: providing a substrate; attaching a chip to a surface of the substrate; forming a plurality of connecting elements for electrically connecting the chip and the substrate; forming a plurality of first conductive bodies on the surface of the substrate; forming a molding compound for encapsulating the surface of the substrate, the chip, the connecting elements and the first conductive bodies; and removing a part of a border portion of the molding compound, so that the molding compound has two heights and one end of each first conductive bodies is exposed. Thereby, the molding compound covers the entire surface of the substrate, so that the bonding pads on the surface of the substrate will not be polluted. | 10-23-2014 |
20140319681 | SEMICONDUCTOR PACKAGE INCLUDING SOLDER BALL - There is provided a semiconductor package comprising: a chip mounted on a substrate; and at least one solder ball formed under the substrate, wherein the solder ball comprises: a solder layer; a shell surrounded by the solder layer; and a phase change material contained in the shell. | 10-30-2014 |
20140319682 | MULTI-SOLDER TECHNIQUES AND CONFIGURATIONS FOR INTEGRATED CIRCUIT PACKAGE ASSEMBLY - Embodiments of the present disclosure are directed towards multi-solder techniques and configurations for integrated circuit (IC) package assembly. In one embodiment, a method includes depositing a plurality of solder balls on a plurality of pads of a package substrate, the plurality of solder balls corresponding with the plurality of pads and performing a solder reflow process to form a solder joint between the plurality of solder balls and the plurality of pads. Individual solder balls of the plurality of solder balls include a first solder material and a second solder material, the first solder material having a liquidus temperature that is greater than a peak temperature of the solder reflow process and the second solder material having a liquidus temperature that is less than the peak temperature of the solder reflow process. Other embodiments may be described and/or claimed. | 10-30-2014 |
20140319683 | Packaged Semiconductor Devices and Packaging Devices and Methods - Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound. | 10-30-2014 |
20140327138 | SEMICONDUCTOR DEVICE - The long sides of a rectangular control chip and the long sides of a rectangular memory chip are arranged parallel with first sides of the upper surface of a wiring substrate in a BGA. A lid includes a pair of first brims and a pair of second brims, the widths of the second brims are formed wider than those of the first brims, and a mounting area for mounting chip parts and a junction base area for joining the lid are secured outside the short sides of the control chip mounted on the upper surface of the wiring substrate and outside the short sides of the memory chip mounted on the upper surface of the wiring substrate, which enables the wide-width second brims of the lid to be disposed on the junction base area. Hence, the mounting area of the BGA can be reduced. | 11-06-2014 |
20140332956 | INTEGRATED CIRCUIT PACKAGE WITH SPATIALLY VARIED SOLDER RESIST OPENING DIMENSION - An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB). | 11-13-2014 |
20140332957 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage. | 11-13-2014 |
20140339698 | SEMICONDUCTOR DEVICE WITH THROUGH-SUBSTRATE VIA COVERED BY A SOLDER BALL AND RELATED METHOD OF PRODUCTION - The semiconductor device comprises a semiconductor substrate ( | 11-20-2014 |
20140339699 | UNDER BALL METALLURGY (UBM) FOR IMPROVED ELECTROMIGRATION - An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer. | 11-20-2014 |
20140353824 | PACKAGE-ON-PACKAGE STRUCTURE - The present invention discloses a package-on-package structure including a top package and a bottom package from top to bottom, where the bottom package includes a first substrate and a second substrate from top to bottom; a pad is placed on one surface of the first substrate, where the pad is electrically connected to the top package; a chip is placed on the other surface of the first substrate; the second substrate is placed opposite to and below the chip; a first metal terminal is placed at a position that is between the first substrate and the second substrate and bypasses the chip; the first substrate is electrically connected to one surface of the second substrate by using the first metal terminal; and a second metal terminal is placed on the other surface of the second substrate. The present invention is applicable to electronic component packaging. | 12-04-2014 |
20140361434 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 12-11-2014 |
20140367854 | INTERCONNECT STRUCTURE FOR MOLDED IC PACKAGES - Various examples are provided for interconnection structures for molded IC packages. In one example, among others, an IC package includes a substrate and an interposer. A plurality of conductive elements provide physical and electrical contact between a surface of the substrate and a surface of the interposer. A standoff element disposed between the surfaces of the substrate and interposer provides a minimum spacing between the surfaces of the substrate and interposer. In some implementations, a standoff element is disposed between an IC die disposed on the surface of the substrate and the surface of the interposer. In another example, a method includes coupling conductive elements to a surface of an interposer, attaching a standoff element, coupling the conductive elements to a surface of a substrate, and forming an embedded layer between the interposer and substrate. The standoff element defines a minimum gap between the interposer and the substrate. | 12-18-2014 |
20140374902 | STACK TYPE SEMICONDUCTOR PACKAGE - A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate. | 12-25-2014 |
20150008580 | STACKED PACKAGE AND METHOD FOR MANUFACTURING THE SAME - The disclosure relates to a stacked package and a method for manufacturing the same. The stacked package includes: a lower package including a substrate formed with ball lands in a periphery of an upper surface thereof, a semiconductor chip mounted over the upper surface, first solder balls formed over the ball lands and each having a side surface cut along an edge of the substrate and a polished upper surface, and a mold part for molding the upper surface including the semiconductor chip and the first solder balls, the cutted side surfaces and polished upper surfaces being exposed by the mold part; and an upper package stacked over the lower package and provided with second solder balls bonded to the first solder balls. | 01-08-2015 |
20150008581 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder regions remain in physical contact with the release film. | 01-08-2015 |
20150014851 | INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME - A structure comprises a passivation layer formed over a semiconductor substrate, a connection pad enclosed by the passivation layer, a redistribution layer formed over the passivation layer, wherein the redistribution layer is connected to the connection pad, a bump formed over the redistribution layer, wherein the bump is connected to the redistribution layer and a molding compound layer formed over the redistribution layer. The molding compound layer comprises a flat portion, wherein a bottom portion of the bump is embedded in the flat portion of the molding compound layer and a protruding portion, wherein a middle portion of the bump is surrounded by the protruding portion of the molding compound layer. | 01-15-2015 |
20150014852 | PACKAGE ASSEMBLY CONFIGURATIONS FOR MULTIPLE DIES AND ASSOCIATED TECHNIQUES - Embodiments of the present disclosure are directed towards package assembly configurations for multiple dies and associated techniques. In one embodiment, a package assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die mounted on the first side and electrically coupled with the package substrate by one or more first die-level interconnects, a second die mounted on the second side and electrically coupled with the package substrate by one or more second die-level interconnects and package-level interconnect structures disposed on the first side of the package substrate and configured to route electrical signals between the first die and an electrical device external to the package substrate and between the second die and the external device. Other embodiments may be described and/or claimed. | 01-15-2015 |
20150021767 | SEMICONDUCTOR DEVICE WITH PLATED CONDUCTIVE PILLAR COUPLING - A semiconductor device with plated conductive pillar coupling is disclosed and may include a semiconductor die comprising a conductive pillar formed on a bond pad on the die, a substrate comprising an insulating layer with conductive patterns formed on a first surface of the substrate and a second surface opposite to the first surface, and a plating layer electrically coupling the conductive pillar and the bond pad on the first surface of the die to the conductive pattern on the first surface of the substrate. The conductive pillar, the conductive patterns, and the plating layer may comprise copper. The plating layer may fill a void between the copper pillar and the conductive pattern on the first surface of the substrate. The substrate may comprise a rigid circuit board, a flexible circuit board, a ceramic substrate, a semiconductor die, or semiconductor wafer. | 01-22-2015 |
20150021768 | SEMICONDUCTOR DEVICE AND POWER SUPPLY UNIT UTILIZING THE SAME - A semiconductor device has pluralities of grid array terminals forming a grid array structure, e.g. a BGA structure, in which the output end of a built-in switch circuit is connected to multiple terminals of the grid array structure, thereby reducing the current that flows through each of the multiple terminals below a permissible level and minimizing the heat due to contact resistances of the multiple terminals in contact with the IC socket of the semiconductor device. Each pair of nearest neighbors of the multiple terminals is interposed by at least one further array terminal. The multiple terminals are all located at the outermost peripheral terminal positions of the grid array structure. Thus, the heat generated in the respective multiple terminals connected to the switch circuit is reduced, thereby minimizing the possibility of hazardous melting of the terminals. | 01-22-2015 |
20150021769 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die. | 01-22-2015 |
20150028477 | SEMICONDUCTOR PACKAGES HAVING SEMICONDUCTOR CHIPS DISPOSED IN OPENING IN SHIELDING CORE PLATE - A semiconductor package includes a first plate having a through hole therein, at least one interconnection layer disposed on a first surface of the first plate, and at least one semiconductor chip disposed on the at least one interconnection layer in a space defined by the through hole and electrically connected to the least one interconnection layer. The package further includes a second plate disposed on the at least one semiconductor chip and a second surface of the first plate on a side of the first plate opposite the first surface, and at least one conductive pad disposed on the second surface of the first plate and electrically connected to the at least one interconnection layer. | 01-29-2015 |
20150028478 | SEMICONDUCTOR DEVICES - A semiconductor device includes: a chip having at least one electrically conductive contact at a first side of the chip; an extension layer extending laterally from one or more sides of the chip; a redistribution layer on a surface of the extension layer and the first side, and coupled to the contact; an interposer having at least one electrically conductive contact at a first surface of the interposer and coupled to the redistribution layer, and at least one electrically conductive contact at a second surface of the interposer opposite to the first surface; a molding material at least partially enclosing the chip and the redistribution layer, and in contact with the interposer. Another semiconductor device includes: an interposer; a redistribution layer over the interposer; a circuit having first and second circuit portions, wherein the redistribution layer includes the first circuit portion, and the interposer includes the second circuit portion. | 01-29-2015 |
20150028479 | SEMICONDUCTOR DEVICES WITH CLOSE-PACKED VIA STRUCTURES HAVING IN-PLANE ROUTING AND METHOD OF MAKING SAME - The invention relates to a semiconductor structure, comprising a substrate of a semiconductor material having a first side (FS) and an opposite second side (BS). There is at least one conductive wafer-through via (V) comprising metal, and at least one recess (RDL) provided in the first side of the substrate and in the semiconductor material of the substrate. The recess is filled with metal and seamlessly connected with the wafer-through via. The exposed surfaces of the metal filled via and the metal filled recess are essentially flush with the substrate surface on the first side of the substrate. There is also provide an interposer comprising the above structure, further comprising contacts for attaching circuit boards and integrated circuits on opposite sides of the interposer. A method of making the structure is also provided. | 01-29-2015 |
20150028480 | SUBSTRATE AND ASSEMBLY THEREOF WITH DIELECTRIC REMOVAL FOR INCREASED POST HEIGHT - An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces. | 01-29-2015 |
20150028481 | SEMICONDUCTOR DEVICES WITH BALL STRENGTH IMPROVEMENT - A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern. | 01-29-2015 |
20150035146 | Through Package Via (TPV) - A through package vias (TPV), a package including a plurality of the TPVs, and a method of forming the through package via are provided. Embodiments of a through package via (TPV) for a package include a build-up film layer, a metal pad disposed over the build-up film layer, a polymer ring disposed over the metal pad, and a solder feature electrically coupled with the metal pad. | 02-05-2015 |
20150035147 | Fine Pitch stud POP Structure and Method - A fine pitch stud POP structure and method is disclosed. The studs are made in bonding pads on the top surface of a lower substrate, which greatly increase the height of the interconnection such as solder balls. In addition, the lower substrate and the upper substrate are connected by reflowing two solder balls on them separately. The two features make the diameter of the bonding balls greatly reduce and further make the pitch between two bonding balls on the lower substrate or the upper substrate greatly reduce, and then the fine pitch POP is achieved. | 02-05-2015 |
20150035148 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package including a lower package including a lower package substrate and a lower semiconductor chip, the lower package substrate including an interconnection part and a core part, the core part including connection vias exposed by openings, the lower semiconductor chip buried in the core part, an upper package including an upper package substrate, an upper semiconductor chip provided on the upper package substrate, and solder balls provided on a bottom surface of the upper package substrate, and an intermetallic compound layer at an interface between the connection vias and the solder balls in the openings may be provided. | 02-05-2015 |
20150041979 | METHOD TO ENHANCE RELIABILITY OF THROUGH MOLD VIA TMVA PART ON PART POP DEVICES - A Through Mold Via (TMV) Integrated Circuit (IC) package is provided as a bottom IC package for a TMV Package on Package (POP) configuration. The TMV IC package has an overmold top portion having a substantially flat surface and spacer or standoff features extending upward from the flat surface. The spacer or standoff features are configured to abut the bottom surface of the top POP package during softer reflow in order to maintain a gap of predetermined height between the top and bottom IC packages. | 02-12-2015 |
20150041980 | Semiconductor Package with Reduced Thickness - A method for forming a reduced thickness semiconductor package is disclosed and may include providing a first die with an active layer, a through-silicon via (TSV), and a pattern and an under bump metal (UBM) in a dielectric layer on the active layer. A carrier may be bonded to the dielectric layer and the UBM. The first die may be thinned to expose the TSV. A bump pad may be formed on the exposed TSV and a second die may be bonded to the bump pad. The first die, the second die, and an outer surface of the dielectric layer may be encapsulated utilizing a first encapsulant. The carrier may be removed from the dielectric layer and the UBM, and a solder ball may be formed on the UBM. A groove may be formed through the dielectric layer and into the first die. | 02-12-2015 |
20150048502 | PREVENTING MISSHAPED SOLDER BALLS - “Thick line dies” that, during manufacture, avoid locating an upstanding edge of a photoresist layer (for example, the edge of a dry film photoresist layer) on top of a “discontinuity.” In this way solder does not flow into the mechanical interface between the photoresist layer and the layer under the photoresist layer in the vicinity of an upstanding edge of the photoresist layer. | 02-19-2015 |
20150048503 | Packages with Interposers and Methods for Forming the Same - A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias. | 02-19-2015 |
20150048504 | PACKAGE ASSEMBLY FOR CHIP AND METHOD OF MANUFACTURING SAME - A package assembly includes a substrate, a chip located on the substrate, solder balls, pads, an encapsulation and separating posts corresponding to the pads one by one. The chip is electrically connected to the pads via the solder balls, and is encapsulated by the encapsulation. The separating posts extend from the edge of the corresponding pads in a direction away from the pads. The solder balls are accommodated in the separating posts to avoid a short connection between any two adjacent solder balls. A method of manufacturing the package assembly is also provided. | 02-19-2015 |
20150054154 | METHOD AND ENCAPSULANT FOR FLIP-CHIP ASSEMBLY - A method of forming an assembly of a substrate and a flip-chip having solder balls thereon, the method having steps of: placing the flip chip with the solder balls in contact with the substrate to form a first interim assembly at a first predetermined temperature; providing an encapsulant to the first interim assembly to form a second interim assembly at a second predetermined temperature that is lower than a melting temperature of the solder balls and higher than the first predetermined temperature; and subjecting the second interim assembly to an environment of a third predetermined temperature that is sufficient to melt the solder balls. An encapsulant for use in forming an assembly of a substrate and a flip-chip having solder balls thereon, the encapsulant consisting essentially of: an epoxy resin; an anhydride curing agent; a fluxing agent having a hydroxyl (—OH) group; and an inorganic filler. | 02-26-2015 |
20150054155 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a substrate comprising a top surface and a back surface, a semiconductor chip having a plurality of functions and mounted on the top surface of the substrate, and a plurality of balls formed on the back surface of the substrate to connect the substrate to an external substrate of the semiconductor package. The substrate further comprises a plurality of electrodes that correspond to the plurality of functions and are formed on the back surface of the substrate, and a subset of the plurality of electrodes corresponds to a subset of the plurality of functions, and each of the plurality of balls is respectively disposed on each of the electrodes in the subset. | 02-26-2015 |
20150061126 | MANUFACTURE INCLUDING SUBSTRATE AND PACKAGE STRUCTURE OF OPTICAL CHIP - A manufacture includes a package structure, a first substrate, and a conductive member of a same material. The package structure includes a chip comprising a conductive pad, a conductive structure over the chip, and a passivation layer over the conductive structure. The passivation layer has an opening defined therein, and the opening exposes a portion of a planar portion of the conductive structure. The first substrate includes a first surface defining a first reference plane and a second surface defining a second reference plane. The conductive member extends across the first reference plane and the second reference plane and into the opening. The conductive member is electrically coupled to the exposed portion of the planar portion. | 03-05-2015 |
20150061127 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads are arranged in a ball grid array (BGA), and the BGA includes a plurality of corners. A metal dam is disposed around each of the plurality of corners of the BGA. | 03-05-2015 |
20150061128 | BALL ARRANGEMENT FOR INTEGRATED CIRCUIT PACKAGE DEVICES - An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs. | 03-05-2015 |
20150061129 | Bump Electrode, Board Which Has Bump Electrodes, and Method for Manufacturing the Board - A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01° C./sec and less than 0.3. | 03-05-2015 |
20150061130 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement may include: a first semiconductor chip having a first side and a second side opposite the first side; a second semiconductor chip having a first side and a second side opposite the first side, the second semiconductor chip disposed at the first side of the first semiconductor chip and electrically coupled to the first semiconductor chip, the first side of the second semiconductor chip facing the first side of the first semiconductor chip; an encapsulation layer at least partially encapsulating the first semiconductor chip and the second semiconductor chip, the encapsulation layer having a first side and a second side opposite the first side, the second side facing in a same direction as the second side of the second semiconductor chip; an interconnect structure disposed at least partially within the encapsulation layer and electrically coupled to at least one of the first and second semiconductor chips, wherein the interconnect structure may extend to the second side of the encapsulation layer; and a third semiconductor chip disposed at at least one of the second side of the second semiconductor chip and the second side of the encapsulation layer, the third semiconductor chip having a first side and a second side opposite the first side, the second side of the third semiconductor chip facing in the same direction as the second side of the second semiconductor chip and the second side of the encapsulation layer. | 03-05-2015 |
20150069603 | COPPER PILLAR BUMP AND FLIP CHIP PACKAGE USING SAME - Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads. | 03-12-2015 |
20150069604 | SEMICONDUCTOR DEVICE HAVING A BOUNDARY STRUCTURE, A PACKAGE ON PACKAGE STRUCTURE, AND A METHOD OF MAKING - A semiconductor device includes a substrate and a first conductive pad on a top surface of the substrate. The semiconductor device further includes a boundary structure on the top surface of the substrate around the conductive pad. | 03-12-2015 |
20150069605 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF AND SEMICONDUCTOR STRUCTURE - A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer. | 03-12-2015 |
20150069606 | Methods and Apparatus for Package on Package Devices - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors contained in the bottom package and not connected to any corresponding connector in the top package. | 03-12-2015 |
20150069607 | THROUGH VIA PACKAGE - An integrated circuit package includes an integrated circuit die in a reconstituted substrate. The active side is processed then covered in molding compound while the inactive side is processed. The molding compound on the active side is then partially removed and solder balls are placed on the active side. | 03-12-2015 |
20150076691 | SEMICONDUCTOR PACKAGE - Provided is a semiconductor package, including: a lower package to which elements are mounted; a metal post connected to the lower package and including at least one metal material portion; and an upper package to which elements is mounted, and which is connected to the metal post via a solder ball. | 03-19-2015 |
20150076692 | FLIP CHIP ASSEMBLY PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY - In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, attaching solder balls to a backside of the coreless substrate strip, and forming a backside stiffening mold amongst the solder balls. Other embodiments are also disclosed and claimed. | 03-19-2015 |
20150084192 | TALL SOLDERS FOR THROUGH-MOLD INTERCONNECT - Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate. | 03-26-2015 |
20150091167 | STRESS BUFFER LAYER FOR INTEGRATED MICROELECTROMECHANICAL SYSTEMS (MEMS) - Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus. | 04-02-2015 |
20150091168 | MULTI-CHIP PACKAGE - A multi-chip package may include a bonding finger. The bonding finger may have a bonding portion having a wide width so that lower ends of conductive wires may be accurately connected to the wide bonding portion. Thus, an electrical connection between a package substrate and semiconductor chips may be improved. | 04-02-2015 |
20150091169 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. | 04-02-2015 |
20150091170 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate including a first surface and an opposing second surface, and a semiconductor chip. The semiconductor chip is mounted over the first surface, includes signal electrodes, power-supply electrodes and ground electrodes, which connect to pads on the first surface of the insulating substrate. Lands provided on the second surface of the insulating substrate include signal lands, power-supply lands and ground lands through vias penetrate from the first surface to the second surface of the insulating substrate, and include signal vias electrically connected the signal connection pads to the signal lands, power-supply vias electrically connected the power-supply connection pads to the power-supply lands and ground vias electrically connected the ground connection pads to the ground lands. At least one of the signal vias are closer to the connection pads than immediately adjacent one of the power-supply vias or the ground vias. | 04-02-2015 |
20150108641 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor device includes providing a carrier including a first layer, a second layer, a first surface of the first layer and a second surface of the second layer, disposing a plurality of solder bumps on the second surface, disposing a molding between the plurality of solder bumps and over the second surface, cutting the first layer to form a first recess in the first layer, wherein the first recess is above a position between at least two of the plurality of solder bumps, and cutting the molding from a bottom surface of the first recess to form a second recess in the molding between the at least two of the plurality of solder bumps. Further, a semiconductor device includes a carrier including a first layer and a second layer, a plurality of solder bumps disposed on the second layer, a molding disposed over the second layer and surrounding the plurality of solder bumps, the molding includes a protruded portion protruding from a sidewall of the first layer adjacent to an end portion of the first layer. | 04-23-2015 |
20150108642 | STRUCTURE TO PREVENT SOLDER EXTRUSION - A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond pad of a chip. The method further includes forming a spacer structure on sidewalls of the solder preform connection. The method further includes subjecting the solder preform connection to a predetermined temperature to form a solder connection with the spacer structure remaining thereabout. | 04-23-2015 |
20150108643 | SEMICONDUCTOR DEVICE WITH EMBEDDED SEMICONDUCTOR DIE AND SUBSTRATE-TO-SUBSTRATE INTERCONNECTS - A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate. | 04-23-2015 |
20150115441 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a semiconductor substrate and a pad. The pad is on a top surface of the semiconductor substrate. The semiconductor structure further includes a circuit board and a bump. The circuit board has a contact area corresponding to the pad on the top surface of the semiconductor substrate, and the bump is between the pad on the top surface of the semiconductor substrate and the contact area, wherein the contact area is a non-metallic surface. | 04-30-2015 |
20150115442 | Redistribution layer and method of forming a redistribution layer - A redistribution layer for a chip is provided, wherein the redistribution layer comprises at least one electrical conductor path connecting two connection points with each other, wherein the at least one electrical conductor path is arranged on a planar supporting layer and wherein the electrical conductor path comprises copper and at least one other further electrical conductive material in an amount of more than 0.04 mass percent. | 04-30-2015 |
20150115443 | SEMICONDUCTOR PACKAGE - There is provided a semiconductor package including a first semiconductor package including a first semiconductor chip and a first substrate on which the first semiconductor chip is mounted and in which a via hole is formed outwardly of the first semiconductor chip, a second semiconductor package including a second semiconductor chip, a second substrate, on which the second semiconductor chip is mounted and in which a through hole is formed outwardly of the second semiconductor chip, and a connection member extended from the second substrate and connected to the first substrate, and a conductive member disposed in the through hole and extended to the outside of the second substrate to be electrically connected to a first upper wiring pattern formed on the first substrate. The second substrate and the connection member are formed of a conductive material. | 04-30-2015 |
20150123275 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR INTEGRATED DEVICE AND METHOD OF MANUFACTURING THE SAME - A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip. | 05-07-2015 |
20150123276 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need. | 05-07-2015 |
20150123277 | BALL GRID ARRAY SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A BGA semiconductor package includes a semiconductor device adhered by adhesive to a substrate, and a conductive micro ball fitted into a through-hole provided in the substrate. A bonding wire electrically connects the semiconductor device and the micro ball to each other. An encapsulation member made of resin encapsulates the semiconductor device, the adhesive, part of the micro ball, and the bonding wire, only on a surface side of the substrate on which the semiconductor device is mounted. At least a part of a bottom surface of the micro ball has an exposed portion as an external connection terminal, which is exposed through the through-hole provided in the substrate as a bottom surface of the encapsulation member. | 05-07-2015 |
20150130059 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - According to one embodiment, a semiconductor device includes a board, a sealing portion, a controller, a semiconductor chip, and solder balls. The board includes a first surface and a second surface opposite to the first surface. The controller and the semiconductor chip are covered with the sealing portion. The solder balls are on the second surface of the board. The solder balls include a plurality of solder ball sets each corresponding to a pair of differential input and differential output signals, and the plurality of solder ball sets are arranged substantially parallel to a side of the board. | 05-14-2015 |
20150130060 | SEMICONDUCTOR PACKAGE SUBSTRATE, PACKAGE SYSTEM USING THE SAME AND METHOD FOR MANUFACTURING THEREOF - A semiconductor package substrate includes an insulating substrate, a circuit pattern on the insulating substrate, a protective layer formed on the insulating substrate to cover the circuit pattern on the insulating substrate, a pad formed on the protective layer while protruding from a surface of the protective layer, and an adhesive member on the pad. | 05-14-2015 |
20150130061 | Bump-on-Trace Methods and Structures in Packaging - A method and structure for bump-on-trace bonding is provided. In an embodiment traces to be used for bump-on-trace (BOT) bonding are protected during a pre-solder treatment. The pre-solder treatment improves the adhesion between the exposed traces (e.g., the non-BOT traces) and a solder resist layer. | 05-14-2015 |
20150137362 | REWORKABLE EPOXY RESIN AND CURATIVE BLEND FOR LOW THERMAL EXPANSION APPLICATIONS - A curable composition including: an epoxy resin; and an amine curing component including: an aromatic amine curing agent; and a solubilizer including an aliphatic amine, a cycloaliphatic amine, a non-volatile primary alcohol, non-volatile solvent or a mixture thereof. An electronic assembly including: a substrate; an underfill including a cured product of the curable composition on the substrate; and a ball grid array on the underfill is also disclosed. | 05-21-2015 |
20150137363 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device includes a substrate, a sealing portion, a controller, a semiconductor chip, and a plurality of differential signal balls. The substrate has a first surface and a second surface positioned on a side opposite to the first surface. The sealing portion is formed on the first surface of the substrate. The controller is covered with the sealing portion. The semiconductor chip is electrically connected to the controller, and is covered with the sealing portion. The plurality of differential signal balls are formed on the second surface of the substrate. At least some of the plurality of differential signal balls are arranged substantially parallel to one side of the substrate. | 05-21-2015 |
20150137364 | MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die. | 05-21-2015 |
20150137365 | SEMICONDUCTOR DEVICE ASSEMBLY WITH THROUGH-PACKAGE INTERCONNECT AND ASSOCIATED SYSTEMS, DEVICES AND METHODS - Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device. | 05-21-2015 |
20150137366 | REACTIVE BONDING OF A FLIP CHIP PACKAGE - An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process. | 05-21-2015 |
20150145130 | SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF - The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape. | 05-28-2015 |
20150145131 | SUBSTRATES HAVING BALL LANDS, SEMICONDUCTOR PACKAGES INCLUDING THE SAME, AND METHODS OF FABRICATING SEMICONDUCTOR PACKAGES INCLUDING THE SAME - A package substrate includes a core layer having a first surface and a second surface which are opposite to each other, a ball land pad disposed on the first surface of the core layer, an opening that penetrates the core layer to expose the ball land pad, and a dummy ball land disposed on the second surface of the core layer to surround the opening. The dummy ball land includes at least one sub-pattern and at least one vent hole. Related semiconductor packages and related methods are also provided. | 05-28-2015 |
20150145132 | BALL ARRANGEMENT FOR INTEGRATED CIRCUIT PACKAGE DEVICES - An integrated circuit package includes a ball arrangement that includes transmitter contact pairs arranged in a first portion of a ball grid array disposed in the integrated circuit package. Each of the transmitter contact pairs include transmitter differential signal contacts. Pairs of the transmitter contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes receiver contact pairs arranged in a second portion of the ball grid array. Each of the receiver contact pairs include receiver differential signal contacts. Pairs of the receiver contact pairs located adjacent to one another are in a staggered arrangement. The ball arrangement also includes voltage supply contacts arranged at least between every two pairs of the transmitter contact pairs and the receiver contact pairs. | 05-28-2015 |
20150145133 | Apparatus for Dicing Interposer Assembly - Apparatus for performing dicing of die on wafer interposers. Apparatuses are disclosed for use with the methods of dicing an interposer having integrated circuit dies mounted thereon. An apparatus includes a wafer carrier mounted in a frame and having a size corresponding to a silicon interposer, a fixture mounted to the wafer carrier and comprising a layer of material to provide mechanical support to the die side of the silicon interposer, the fixture being patterned to fill spaces between integrated circuit dies mounted on an interposer; and an adhesive tape disposed on a surface of the fixture for adhering to the surface of a silicon interposer. Additional alternative apparatuses are disclosed. | 05-28-2015 |
20150294949 | CHIP PACKAGING STRUCTURE AND PACKAGING METHOD - A chip packaging structure and packaging method. The packaging structure comprises: a semiconductor substrate; a metal pad provided inside the semiconductor substrate; an insulating layer provided on the semiconductor substrate, the insulating layer having an opening for exposing the metal pad; a sub-ball metal electrode provided on the metal pad; a solder ball provided on the surface of the sub-ball metal electrode, the solder ball having a first apron structure and the first apron structure covering partial metal pad on the periphery of the bottom of the under-ball metal electrode. The chip packaging structure of the present invention enhances the adhesion between the solder ball and the metal pad, and improves the reliability in chip packaging. | 10-15-2015 |
20150303120 | SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A method for fabricating semiconductor package structure is disclosed. The method includes: providing a wafer having a front side and a backside; forming a plurality of through-silicon vias (TSVs) in the wafer and a plurality of metal interconnections on the TSVs, in which the metal interconnections are exposed from the front side of the wafer; performing a monitoring step to screen for TSV failures from the backside of the wafer; and bonding the wafer to a substrate. | 10-22-2015 |
20150303137 | MULTI-USE SUBSTRATE FOR INTEGRATED CIRCUIT - A sub-assembly for a packaged integrated circuit (IC) device has a planar substrate. The substrate's top side has multiple sets electrically connected bond posts arranged in corresponding nested contour zones. Each contour zone includes a different bond post of each bond-post set. The bottom side has a different set of pad connectors electrically connected to the each top-side bond-post set. The sub-assembly can be used for different IC packages having IC dies of different sizes, with different contours of bond posts available for electrical connection depending on the size of the IC die. | 10-22-2015 |
20150303148 | DIE PACKAGE COMPRISING DIE-TO-WIRE CONNECTOR AND A WIRE-TO-DIE CONNECTOR CONFIGURED TO COUPLE TO A DIE PACKAGE - Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer. | 10-22-2015 |
20150303159 | SEMICONDUCTOR DEVICE PACKAGE AND PACKAGING METHOD - A semiconductor device package and packaging method, the semiconductor device packaging method comprising: providing a chip with a bonding pad formed on the chip surface; forming a passivation layer and a bump on the chip surface, wherein the passivation layer has an opening exposing part of the pad, the bump is located in the opening and the size of the bump is less than the size of the opening; forming a solder ball covering the top surface and the side wall of the bump, and the bottom surface of the opening. The formed semiconductor device package is not easy to form a short circuit. The bonding strength between the solder ball and the bump is high and the performance of the semiconductor device is stable. | 10-22-2015 |
20150311165 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface. | 10-29-2015 |
20150311177 | CHIP PACKAGING METHOD AND CHIP PACKAGE USING HYDROPHOBIC SURFACE - A chip packaging method using a hydrophobic surface includes forming superhydrophobic surfaces forming hydrophilic surfaces on predetermined positions of the superhydrophobic surfaces formed on the one of a first chip or the first board and the one of a second chip or a second board, respectively, generating liquid metal balls on the hydrophilic surfaces formed on the one of the first chip or the first board and the one of the second chip or the second board, respectively, and packaging the one of the first chip or the first board and the one of the second chip or the second board by combing the liquid metal ball of the one of the first chip or the first board and the liquid metal ball of the one of the second chip or the second board with each other. | 10-29-2015 |
20150318229 | WAFER LEVEL PACKAGE AND FAN OUT RECONSTITUTION PROCESS FOR MAKING THE SAME - A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer. | 11-05-2015 |
20150318262 | INTEGRATED DEVICE COMPRISING HIGH DENSITY INTERCONNECTS IN INORGANIC LAYERS AND REDISTRIBUTION LAYERS IN ORGANIC LAYERS - Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects. | 11-05-2015 |
20150318264 | Stacked Dies With Wire Bonds and Method - Semiconductor dies are bonded to each other and electrically connected to each other. An encapsulant is utilized to protect the semiconductor dies and external connections are formed to connect the semiconductor dies within the encapsulant. In an embodiment the external connections may comprise conductive pillars, conductive reflowable material, or combinations of such. | 11-05-2015 |
20150325542 | CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME - A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. | 11-12-2015 |
20150325543 | CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE - In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball ( | 11-12-2015 |
20150325544 | CHIP PACKAGING STRUCTURES AND TREATMENT METHODS THEREOF - A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer. | 11-12-2015 |
20150325551 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided. | 11-12-2015 |
20150325552 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third device substrate is attached to a second surface of the second device substrate opposite to the first surface. An insulating layer covers the first, second and third device substrates and has at least one opening therein. At least one bump is disposed under a bottom of the opening. A redistribution layer is disposed on the insulating layer and electrically connected to the bump through the opening. A method for forming the chip package is also provided. | 11-12-2015 |
20150332993 | PRINTED CIRCUIT BOARD HAVING TRACES AND BALL GRID ARRAY PACKAGE INCLUDING THE SAME - A printed circuit board (PCB) includes a base substrate including upper and lower surfaces, a plurality of solder ball pads separately formed on the lower surface of the base substrate in a radial direction and forming one or more radial pad groups, a plurality of first traces respectively connected to the plurality of solder ball pads and extending to an inside of the radial pad group, and a plurality of second traces respectively connected to the plurality of first traces and extending to an outside of the radial pad group. | 11-19-2015 |
20150333028 | WAFER LEVEL PACAKGES HAVING NON-WETTABLE SOLDER COLLARS AND METHODS FOR THE FABRICATION THEREOF - Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings. | 11-19-2015 |
20150348937 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes an insulative resin, an interconnect, a plurality of semiconductor elements, and a first metal member. The insulative resin includes a first region and a second region. The interconnect is arranged with the first region in a first direction. The first direction intersects a direction from the first region toward the second region. The plurality of semiconductor elements is provided between the first region and the interconnect. At least one of the plurality of semiconductor elements is electrically connected to the interconnect. The first metal member includes a first through-portion and a first end portion. The first through-portion pierces the second region in the first direction. The first end portion is connected to the first through-portion. A width of the first end portion is wider than a width of the first through-portion in a second direction intersecting the first direction. | 12-03-2015 |
20150357278 | Packaged Semiconductor Devices and Packaging Devices and Methods - Packaged semiconductor devices and packaging devices and methods are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a first integrated circuit die that is coupled to a first surface of a substrate that includes through-substrate vias (TSVs) disposed therein. A conductive ball is coupled to each of the TSVs on a second surface of the substrate that is opposite the first surface of the substrate. A second integrated circuit die is coupled to the second surface of the substrate, and a molding compound is formed over the conductive balls, the second integrated circuit die, and the second surface of the substrate. The molding compound is removed from over a top surface of the conductive balls, and the top surface of the conductive balls is recessed. A redistribution layer (RDL) is formed over the top surface of the conductive balls and the molding compound. | 12-10-2015 |
20150357312 | RECESSED AND EMBEDDED DIE CORELESS PACKAGE - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands. | 12-10-2015 |
20150364395 | Methods of Packaging Semiconductor Devices and Structures Thereof - Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies. | 12-17-2015 |
20150364438 | BALANCED CURRENT DISTRIBUTION STRUCTURE FOR LARGE CURRENT DELIVERY - Methods and apparatuses for balancing current delivery. The method couples a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section. The method couples at least one ball of the BGA to the low resistance portion over a narrow trace. | 12-17-2015 |
20150364447 | SEMICONDUCTOR DEVICE - A semiconductor device includes a package interface including N numbers of first group of data balls which are disposed on a first side thereof, N numbers of second group of data balls which are disposed on a second side thereof, and M numbers of command/address balls which are disposed between the first side and the second side; a first semiconductor chip which is stacked on the first side over the package interface, and includes 2N numbers of first group of data pads and M numbers of first command/address pads; and a second semiconductor chip which is stacked on the second side over the package interface, and includes 2N numbers of second group of data pads and M numbers of second command/address pads. | 12-17-2015 |
20150371971 | SEMICONDUCTOR DEVICE - To provide a CoC type semiconductor device capable of preventing a power supply voltage from dropping (IR drop) in a center portion of a chip, and preventing deterioration in timing reliability. The semiconductor device includes a substrate, a first semiconductor chip placed on the substrate, having a circuit formation surface on an upper surface provided opposite to a surface facing the substrate, and including a TSV electrode and a connection pad electrically connected to the substrate, a second semiconductor chip placed on the upper surface of the first semiconductor chip, and electrically connected to the first semiconductor chip through a bump, a connection member for electrically connecting the connection pad of the first semiconductor chip to the substrate, and a redistribution layer formed on the upper surface of the first semiconductor chip, and electrically connected to the TSV electrode. | 12-24-2015 |
20150380347 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including a plurality of solder balls on a surface the semiconductor device, and a retaining body associated with a first solder ball of the plurality of solder balls, separating the first solder ball from at least a second solder ball of the plurality of solder balls. The retaining body includes a conductive portion and an insulating portion configured to cover the conductive portion. Also, a method of manufacturing a semiconductor device, including acts of forming a plurality of retaining bodies on a surface of a wiring substrate, each retaining body comprising a conductive portion and an insulating portion covering the conductive portion, each retaining body forming an opening section, and forming a solder ball in the opening section formed by each of the retaining bodies. | 12-31-2015 |
20150380366 | SEMICONDUCTOR PACKAGE - A semiconductor package including a first metal layer configured for use as a bonding pad, a second metal layer formed over the first metal layer, and the second metal layer having a separation allowing for the second metal layer to be positioned above distal ends of the first metal layer. The semiconductor package also including a third metal layer formed over the second metal layer, and the third metal layer having a separation allowing for the third metal layer to be positioned above distal ends of the first metal layer, a trench defined by the separation of the third metal layer and second metal layer, and extending through the third metal layer and the second metal layer to expose the first metal layer, and a bonding ball located within the trench. | 12-31-2015 |
20150380373 | SOLDER BALLS AND SEMICONDUCTOR DEVICE EMPLOYING THE SAME - A solder ball and a semiconductor device using the same are provided. In a Sn-based solder ball in which a first plating layer and a second plating layer are sequentially formed on a core ball, the second plating layer includes a Sn—Ag—Cu alloy, and Ag | 12-31-2015 |
20160005653 | FLEXIBLE WAFER-LEVEL CHIP-SCALE PACKAGES WITH IMPROVED BOARD-LEVEL RELIABILITY - Consistent with an example embodiment, there is a method for manufacturing integrated circuit (IC) devices from a wafer substrate, the wafer substrate having a front-side surface with active devices and a back-side surface. A temporary covering to the front-side of the wafer substrate is applied. The back-side of the wafer substrate having a pre-grind thickness is ground to a post-grind thickness. To a predetermined thickness, the back-side of the wafer substrate is coated with a resilient coating. The wafer is mounted onto a second carrier tape on its back-side surface. After removing the temporary carrier tape from the front-side of the wafer substrate, the wafer is sawed along active device boundaries and active devices are singulated. | 01-07-2016 |
20160005704 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. | 01-07-2016 |
20160005716 | Semiconductor Package and Method - A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks. | 01-07-2016 |
20160013134 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES | 01-14-2016 |
20160013146 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF | 01-14-2016 |
20160020195 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls. | 01-21-2016 |
20160027719 | Semiconductor Die Connection System and Method - A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate. | 01-28-2016 |
20160027752 | Elongated Bump Structures in Package Structure - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d | 01-28-2016 |
20160035622 | PACKAGE ON PACKAGE (PoP) INTEGRATED DEVICE COMPRISING A PLURALITY OF SOLDER RESIST LAYERS - Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad. | 02-04-2016 |
20160035701 | SEMICONDUCTOR TSV DEVICE PACKAGE FOR CIRCUIT BOARD CONNECTION - An electronic device includes a circuit board and a semiconductor device package. The semiconductor device package includes a laminate layer. The semiconductor device package includes a semiconductor die having an active side, an inactive side opposite the active side, and through-silicon vias (TSVs) conductively connecting the active side to the inactive side and conductively connecting the semiconductor die to one of the laminate layer and the circuit board. The semiconductor device package includes a laminate layer having a side attached to the active side or the inactive side semiconductor die. The semiconductor device package includes solder balls at the side of the laminate layer attached to the semiconductor die, around the semiconductor die, and attached to the circuit board. | 02-04-2016 |
20160035709 | Package on Package Devices and Methods of Packaging Semiconductor Dies - Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint. | 02-04-2016 |
20160043052 | LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF - A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit. | 02-11-2016 |
20160056087 | PACKAGE-ON-PACKAGE STRUCTURE WITH ORGANIC INTERPOSER - A device comprises a substrate having a die mounted on the first side of the substrate and a moldable underfill (MUF) disposed on the first side of the substrate and around the die. An interposer is mounted on the first side of the substrate, with the interposer having lands disposed on a first side of the interposer. The interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate. A package is mounted on the first side of the interposer and is electrically connected to the lands. At least one of the lands is aligned directly over the die and wherein a pitch of the connectors is different than a pitch of the lands. | 02-25-2016 |
20160056117 | Directly Sawing Wafers Covered with Liquid Molding Compound - A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound. | 02-25-2016 |
20160071816 | Integrated Circuit Packages and Methods of Forming Same - Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages. | 03-10-2016 |
20160071822 | OPTIMIZING POWER DISTRIBUTION FROM A POWER SOURCE THROUGH A C4 SOLDER BALL GRID INTERCONNECTED THROUGH SILICON VIAS IN INTERMEDIATE INTEGRATED CIRCUIT CHIP CONNECTED TO CIRCUITRY IN AN UPPER INTEGRATED CIRCUIT CHIP THROUGH A GRID OF MICRO uC4 SOLDER BALLS - In an integrated chip stack arrangement, wherein power is provided to an upper integrated chip, including a processor core with a grid arrangement of cells connected to a power supply in a substrate by a conventional C4 solder ball array on the substrate connected through TSVs in an intermediate integrated circuit chip, it has been recognized that for maximum current efficiency and minimum electro migration the vias should not be directly coincident with the micro C4 solder balls connecting the upper chip with the intermediate chip. | 03-10-2016 |
20160071824 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip. | 03-10-2016 |
20160079190 | Package with UBM and Methods of Forming - Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer. | 03-17-2016 |
20160079207 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - [Problem] To provide a semiconductor device suitable for use as an upper-side package of a semiconductor device having a PoP structure. [Solution] This invention is provided with a semiconductor chip ( | 03-17-2016 |
20160079216 | SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, there is provided a semiconductor device including a first semiconductor chip and a second semiconductor chip. The second semiconductor chip is mounted on a back surface of the first semiconductor chip. The first semiconductor chip includes a substrate, a back surface wiring, a multi-layer wiring, a through silicon via, and a front surface electrode. The back surface wiring is arranged on a back surface of the substrate. The back surface wiring is electrically connected to a terminal of the second semiconductor chip. The multi-layer wiring is arranged on a front surface of the substrate. The through silicon via is configured to electrically connect the back surface wiring and the multi-layer wiring through the substrate. The front surface electrode is arranged on the multi-layer wiring and electrically connected to the multi-layer wiring. | 03-17-2016 |
20160079222 | SEMICONDUCTOR DEVICE HAVING TERMINALS FORMED ON A CHIP PACKAGE INCLUDING A PLURALITY OF SEMICONDUCTOR CHIPS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a chip package including plurality of stacked semiconductor chips, a sealing layer covering at least an upper surface of the chip package, a plurality of first conductive elements disposed on the chip package and exposed on an upper surface of the sealing layer, and a plurality of second conductive elements, each being disposed on one of the exposed surfaces of the first conductive elements. | 03-17-2016 |
20160086880 | COPPER WIRE THROUGH SILICON VIA CONNECTION - A semiconductor device includes a semiconductor substrate having opposing first and second main surfaces, a via (TSV) extending from the first main surface of the substrate to the second main surface of the substrate, first electrical connectors formed near the first main surface and second electrical connectors formed near the second main surface. There are insulated bond wires, each extending through the via and having a first end bonded to a respective one of the first electrical connectors and a second end bonded to a respective one of the second electrical connectors. The via may be filled with an encapsulating material. | 03-24-2016 |
20160086907 | Chip Mounting - A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less. | 03-24-2016 |
20160093582 | Fan Out Package Structure and Methods of Forming - An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening. | 03-31-2016 |
20160104656 | ELECTRONIC DEVICE WITH REDISTRIBUTION LAYER AND STIFFENERS AND RELATED METHODS - An electronic device may include an integrated circuit (IC), electrically conductive connectors coupled to the IC, and a heat sink layer adjacent the IC and opposite the electrically conductive connectors. The electronic device may include an encapsulation material surrounding the IC and the electrically conductive connectors, a redistribution layer having electrically conductive traces coupled to the electrically conductive connectors, a stiffener between the heat sink layer and the redistribution layer, and a fan-out component between the heat sink layer and the redistribution layer and being in the encapsulation material. | 04-14-2016 |
20160104667 | SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND PROCESS FOR MANUFACTURING - A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved. | 04-14-2016 |
20160111359 | ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF - A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield. | 04-21-2016 |
20160111385 | PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME - The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. | 04-21-2016 |
20160126126 | PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabricating a package structure is provided, including the steps of: disposing on a carrier a semiconductor chip having an active surface facing the carrier; forming a patterned resist layer on the carrier; forming on the carrier an encapsulant exposing an inactive surface of the semiconductor chip and a surface of the patterned resist layer; and removing the carrier to obtain a package structure. Thereafter, redistribution layers can be formed on the opposite sides of the package structure, and a plurality of through holes can be formed in the patterned resist layer by drilling, thus allowing a plurality of conductive through holes to be formed in the through holes for electrically connecting the redistribution layers on the opposite sides of the package structure. Therefore, the invention overcomes the conventional drawback of surface roughness of the through holes caused by direct drilling the encapsulant having filler particles. | 05-05-2016 |
20160126171 | CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS - Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder mask on a circuit board with a first opening that has a sidewall. A solder interconnect pad is formed in the first opening. The sidewall sets the lateral extent of the solder interconnect pad. | 05-05-2016 |
20160126173 | HIGH DENSITY FAN OUT PACKAGE STRUCTURE - A high density fan out package structure may include a contact layer. The contact layer includes a conductive interconnect layer having a first surface facing an active die and a second surface facing a redistribution layer. The high density fan out package structure has a barrier layer on the first surface of the conductive interconnect layer. The high density fan out package structure may also include the redistribution layer, which has conductive routing layers. The conductive routing layers may be configured to couple a first conductive interconnect to the conductive interconnect layer. The high density fan out package structure may further include a first via coupled to the barrier liner and configured to couple with a second conductive interconnect to the active die. | 05-05-2016 |
20160133554 | BALL GRID ARRAY AND LAND GRID ARRAY ASSEMBLIES FABRICATED USING TEMPORARY RESIST - Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder. | 05-12-2016 |
20160133557 | OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES - An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads. | 05-12-2016 |
20160133592 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device according to the present invention includes a semiconductor substrate, a pad formed on the semiconductor substrate, a rewiring that is electrically connected to the pad and led to a region outside the pad, a resin layer formed on the rewiring, and an external terminal electrically connected to the rewiring via the resin layer, and the resin layer is formed so as to enter the inside of a slit formed in a region along the periphery of the external terminal in the rewiring. | 05-12-2016 |
20160133594 | SEMICONDUCTOR PACKAGE - The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via. | 05-12-2016 |
20160133601 | WAFER-LEVEL STACK CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor product in the form of a stack chip package and a method of manufacturing the same, where a plurality of semiconductor chips are stacked one on another so as to enable the exchange of electrical signals between the semiconductor chips, and where a conductive layer is included for inputting and outputting signals to and from individual chips. A stack chip package having a compact size may, for example, be manufactured by stacking, on a first semiconductor chip, a second semiconductor chip having a smaller surface area by means of interconnection structures so as to enable the exchange of electrical signals between the first and second semiconductor chips, and by using a conductive layer for inputting and outputting signals to and from individual semiconductor chips, in lieu of a thick substrate. Furthermore, heat dissipation effects can be enhanced by the addition of a heat dissipation unit. | 05-12-2016 |
20160141262 | REDISTRIBUTION FILM FOR IC PACKAGE - A redistribution film for IC package is disclosed, which comprises a top redistribution layer configured on top of a bottom redistribution layer. The top redistribution layer is fabricated following PCB design rule, and the bottom redistribution layer is fabricated following IC design rule. Further, the interface between the top redistribution layer and the bottom redistribution layer is optionally made roughed to increase bonding forces therebetween. | 05-19-2016 |
20160148890 | Method and Apparatus for Cooling Semiconductor Device Hot Blocks and Large Scale Integrated Circuit (IC) Using Integrated Interposer for IC Packages - A method, system, and apparatus for improved IC device packaging is described. In an aspect, an (IC) device package includes an IC die having at one or more contact pads, each contact pad located at a corresponding hotspot on a surface of th28e IC die. The package also includes a thermally conductive interposer which is thermally coupled to the IC die at the contact pads. In another aspect, an underfill material fills a space between the IC die and the interposer. The interposer may also be electrically coupled to the IC die. In an aspect, the interposer and the IC die are coupled through thermal interconnects or “nodules.” | 05-26-2016 |
20160148915 | LOW-IMPEDANCE POWER DELIVERY FOR A PACKAGED DIE - A system includes a semiconductor die mounted on a packaging substrate, a signal redistribution layer that is formed within the packaging substrate, a power plane that is formed on a surface of the packaging substrate, and a ground plane that is formed within the packaging substrate. The power plane couples the semiconductor die to a capacitor disposed on the packaging substrate and the ground plane is disposed between the power plane and the signal redistribution layer. An advantage of the disclosed system is that loop inductance between power and ground paths to a packaged semiconductor die is reduced, thereby lowering the impedance of the packaged semiconductor die system and signal noise associated with the packaged semiconductor system. | 05-26-2016 |
20160148967 | Bonding Pad on a Back Side Illuminated Image Sensor - A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view. | 05-26-2016 |
20160155680 | Semiconductor Package and Method of Fabrication Thereof | 06-02-2016 |
20160163578 | Semiconductor Packages and Methods of Forming the Same - A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer and protrude from the patterned layer to expose tapered sidewalls. | 06-09-2016 |
20160167951 | LOW STRESS COMPACT DEVICE PACKAGES | 06-16-2016 |
20160172291 | SEMICONDUCTOR PACKAGE | 06-16-2016 |
20160172326 | BONDING METHOD AND BONDING STRUCTURE FORMED USING THE SAME | 06-16-2016 |
20160181222 | PICKHEAD FOR SOLDER BALL PLACEMENT ON AN INTEGRATED CIRCUIT PACKAGE | 06-23-2016 |
20160189983 | METHOD AND STRUCTURE FOR FAN-OUT WAFER LEVEL PACKAGING - A method for fan-out wafer level chip packaging includes: providing a carrier substrate; forming a plurality of conductive base layers on a surface of the carrier substrate; mounting a plurality of chips on the conductive base layers and electrically connecting the chips to the conductive base layers by using a plurality of wire leads; forming a packaging layer to encapsulate the chips, the wire leads, the conductive base layers, and a top surface of the carrier substrate; removing the carrier substrate; and forming a plurality of conductive layers on bottom surfaces of the conductive base layers. | 06-30-2016 |
20160190028 | METHOD AND STRUCTURE FOR FAN-OUT WAFER LEVEL PACKAGING - A method for fan-out wafer level packaging includes: providing a carrier substrate; forming a strippable protective film with a polarity of openings; forming at least one metal layer in the openings; removing the carrier substrate; mounting a plurality of chips onto the metal layer and electrically connecting the chips to the metal layer; packing the chips, the metal layer, and the strippable protective film by using a packaging layer; forming a plurality of redistribution layers; and finally, forming soldering balls on the surfaces of the redistribution layers. | 06-30-2016 |
20160190109 | STACK SEMICONDUCTOR PACKAGE - A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance. | 06-30-2016 |
20160197031 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND METHOD OF MOUNTING SEMICONDUCTOR DEVICE | 07-07-2016 |
20160197053 | Ball Grid Array Rework | 07-07-2016 |
20160197057 | SEMICONDUCTOR PACKAGES | 07-07-2016 |
20160197058 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS | 07-07-2016 |
20160204051 | FLEXIBLE MICROSYSTEM STRUCTURE | 07-14-2016 |
20160204081 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 07-14-2016 |
20160254221 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF | 09-01-2016 |
20160254240 | Interconnect Structures, Packaged Semiconductor Devices, and Methods of Packaging Semiconductor Devices | 09-01-2016 |
20160254242 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF | 09-01-2016 |
20160379935 | WAFER LEVEL PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor device includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is electrically connected to the chip. A molding compound covers and encapsulates the chip. A first stress-relief feature is embedded in the molding compound within a peripheral area adjacent to the chip mounting area. A second stress-relief feature is embedded in the molding compound within the chip mounting area. The first stress-relief feature is composed of a first material. The second stress-relief feature is composed of a second material that is different from the first material. | 12-29-2016 |
20160379953 | SEMICONDUCTOR WIRE BONDING AND METHOD - Circuitry is disclosed that includes a first conductive portion of a first die and a first conductive pillar electrically and physically connected to the first conductive portion. The first conductive pillar includes a first conductive pillar surface. A first bond connects the first conductive pillar surface to a first end of a bond wire. | 12-29-2016 |
20160379961 | SEMICONDUCTOR PACKAGE INCLUDING A STEP TYPE SUBSTRATE - Disclosed herein are semiconductor packages. A semiconductor package may include a substrate configured to include a first face and a second face opposite the first face and to have a recess formed in the first face. The semiconductor package may include a first semiconductor chip disposed on the bottom of the recess. The semiconductor package may include a second semiconductor chip disposed on the second face of the substrate. The semiconductor package may include a third semiconductor chip disposed over the first face of the substrate and the first semiconductor chip. The semiconductor package may include a fourth semiconductor chip disposed over the third semiconductor chip. | 12-29-2016 |
20170236763 | POP Structures with Dams Encircling Air Gaps and Methods for Forming the Same | 08-17-2017 |
20170236793 | Semiconductor Device | 08-17-2017 |
20180026002 | Under Bump Metallurgy (UBM) And Methods Of Forming Same | 01-25-2018 |
20180026018 | Package-on-Package Devices with Multiple Levels and Methods Therefor | 01-25-2018 |
20190148275 | STACKED-CHIP PACKAGES IN PACKAGE-ON-PACKAGE APPARATUS, METHODS OF ASSEMBLING SAME, AND SYSTEMS CONTAINING SAME | 05-16-2019 |
20190148277 | Fan-Out Package Structure and Method | 05-16-2019 |
20190148288 | Semiconductor Device and Method of Manufacture | 05-16-2019 |
20190148349 | SEMICONDUCTOR PACKAGE | 05-16-2019 |