Entries |
Document | Title | Date |
20080197482 | SEMICONDUCTOR MODULE, PORTABLE DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE - A semiconductor module is provided, which is capable of suppressing the deterioration of reliability and improving heat radiation. The semiconductor module includes: a semiconductor substrate in which electrodes of a circuit element are formed on its surface; a re-wiring pattern connected to the electrodes to ensure large pitch of the electrodes; an electrode integrally formed with the re-wiring pattern; an insulating layer formed on a rear surface of the semiconductor substrate; a radiator formed on the insulating layer; and projections integrally formed with the radiator and penetrating the insulating layer to connect to the rear surface of the semiconductor substrate. | 08-21-2008 |
20080237841 | Microelectronic package, method of manufacturing same, and system including same - A microelectronic package includes a substrate ( | 10-02-2008 |
20080237842 | Thermally conductive molding compounds for heat dissipation in semiconductor packages - Methods and apparatus relating to thermally conductive molding compounds are described. In one embodiment, a molding compound may include thermally conductive particles to form a thermally conductive path in the molding compound (e.g., for improved heat dissipation through the molding compound). Other embodiments are also described. | 10-02-2008 |
20080246142 | Heat dissipation unit and a semiconductor package that has the heat dissipation unit - A heat dissipation unit and a semiconductor package having the same are disclosed. The semiconductor package includes a carrier; an electronic component mounted on and electrically connected to the carrier; a heat dissipation unit, which includes a flat section attached to the electronic component, extension sections connected to the flat section, and a heat dissipation section connected to the extension sections; and an encapsulant encapsulating the electronic component and the heat dissipation unit, wherein stress releasing sections are at least disposed at intersectional corners between the extension sections and the flat section so as to prevent projections from being formed by concentrated stresses in a punching process of the heat dissipation unit, thereby maintaining flatness of the flat section and further preventing circuits of the electronic component from being damaged due to a contact point produced between the electronic component and the flat section in a molding process. | 10-09-2008 |
20080246143 | EMBEDDED METAL HEAT SINK FOR SEMICONDUCTOR - An embedded metal heat sink for a semiconductor device is described. The embedded metal heat sink for a semiconductor device comprises a metal thin layer, a metal heat sink and two bonding pads. The metal thin layer including a first surface and a second surface on opposite sides, wherein at least one semiconductor device is embedded in the first surface of the metal thin layer, and the semiconductor device has two electrodes with different conductivity types. The metal heat sink is deposited on the second surface of the metal thin layer. The bonding pads are deposed on the first surface of the metal thin layer around the semiconductor device and are respectively corresponding to the electrodes, wherein the electrodes are electrically and respectively connected to the corresponding bonding pads by at least two wires, and the bonding pads are electrically connected to an outer circuit. | 10-09-2008 |
20080251910 | Fabricating method of semiconductor package and heat-dissipating structure applicable thereto - A method for fabricating semiconductor packages is disclosed, including mounting and electrically connecting a semiconductor chip onto a chip carrier; mounting a heat-dissipating structure on the semiconductor chip; placing the heat-dissipating structure into a mold cavity for filling therein a packaging material to form an encapsulant, wherein the heat-dissipating structure has a heat spreader having a size larger than that of the predetermined size of the semiconductor package, a covering layer formed on the, and a plurality of protrusions formed on edges of the covering layer that are free from being corresponding in position to the semiconductor chip, such that the protrusions can abut against a top surface of the mold cavity to prevent the heat spreader from being warped; and finally performing a singulation process according to the predetermined size and removing the encapsulant formed on the covering layer to form the desired semiconductor package. Also, this invention discloses a heat-dissipating structure applicable to the method described above. | 10-16-2008 |
20080258294 | Heat-dissipating semiconductor package structure and method for manufacturing the same - A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking. | 10-23-2008 |
20080265405 | SUBSTRATE WITH MULTI-LAYER INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The invention provides a substrate with multi-layer interconnection structure, which includes a substrate and a multi-layer interconnection structure formed on the substrate. The multi-layer interconnection structure is adhered to the substrate in partial areas. The invention also provides a method of manufacturing and recycling such substrate and a method of packaging electronic devices by using such substrate. The invention also provides a method of manufacturing multi-layer interconnection devices. | 10-30-2008 |
20080277777 | Heat dissipation semiconductor package - A heat dissipation semiconductor package includes a chip carrier, a semiconductor chip, a heat conductive adhesive, a heat dissipation member, and an encapsulant. The semiconductor chip is flip-chip mounted on the chip carrier and defined with a heat conductive adhesive mounting area. Periphery of the heat adhesive mounting area is spaced apart from edge of the semiconductor chip. The heat dissipation member is mounted on the heat conductive adhesive formed in the heat conductive adhesive mounting area. The encapsulant formed between the chip carrier and the heat dissipation member encapsulates the semiconductor chip and the heat conductive adhesive, and embeds edges of the active surface and non-active surface and side edge of the semiconductor chip, thereby increasing bonding area between the encapsulant and the semiconductor chip. The side edges of the heat conductive adhesive and the semiconductor chip are not flush with each other, thereby preventing propagation of delamination. | 11-13-2008 |
20080284001 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device, in which a semiconductor element is mounted on one side of a circuit board that is made up from an insulating layer and a wiring layer, includes metal posts provided on the side of said circuit board on which said semiconductor element is mounted; and a sealing layer provided on the side of said circuit board on which said semiconductor element is mounted such that said semiconductor element is covered and such that only portions of said metal posts are exposed. | 11-20-2008 |
20080290498 | Semiconductor Device - A semiconductor device is disclosed that includes a circuit board, a semiconductor element, a heat sink, and a stress relaxation member. The circuit board includes an insulated substrate, a metal circuit joined to one side of the insulated substrate, and a metal plate joined to the other side of the insulated substrate. The semiconductor element is joined to the metal circuit. The heat sink radiates heat generated in the semiconductor element. The stress relaxation member thermally joins the heat sink to the metal plate. The stress relaxation member is formed of a material having a high thermal conductivity. The stress relaxation member includes recesses, which curve inward from the peripheral portion of the stress relaxation member, to form stress relaxation spaces at the peripheral portion of the stress relaxation member. | 11-27-2008 |
20080290499 | Semiconductor device - A semiconductor device is disclosed that includes a ceramic substrate having first and second surfaces, a semiconductor element, a radiator, and an interposed portion located between the second surface and the radiator. The interposed portion has coupling regions that couple the second surface to the radiator, and non-coupling regions that do not couple the second surface to the radiator. Each non-coupling region is formed as an elongated groove. In the group of the non-coupling regions, the width of the outermost non-coupling region in the interposed portion is greater than the width of the innermost non-coupling region in the interposed portion. Regarding an adjacent pair of the non-coupling regions in the width direction, the width of the outer non-coupling region is greater than or equal to the width of the inner non-coupling region. | 11-27-2008 |
20080290500 | Semiconductor device - A semiconductor device has a ceramic substrate having a first surface and a second surface, a metal layer that is coupled to the second surface, a heat sink that is coupled to the metal layer and a stress relaxation member. The stress relaxation member is arranged between the metal layer and the heat sink and has a first surface that is coupled to the metal layer and a second surface that is coupled to the heat sink. A plurality of stress relaxation spaces are provided over the entire surface of at least one of the first and second surfaces of the stress relaxation member. The stress relaxation spaces that are arranged at the outermost portions of the stress relaxation member are deeper than the other stress relaxation spaces. | 11-27-2008 |
20080290501 | SEMICONDUCTOR PACKAGE - There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor chip. The stiffener includes: an insulating material layer; and a rigid plate mounted substantially parallel to a surface of the substrate in the insulating material layer, the rigid plate having formed therein a plurality of through holes, at least a part of the through holes being filled with the insulating material. | 11-27-2008 |
20080296754 | APPARATUS TO MINIMIZE THERMAL IMPEDANCE USING COPPER ON DIE BACKSIDE - A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress. | 12-04-2008 |
20080296755 | Semiconductor device - A semiconductor includes a board, a semiconductor element mounted on the board, an electronic component, with the semiconductor element, mounted on the board, a heat radiation member provided so as to face the board, the heat radiation member configured to radiate heat of the semiconductor element, and a thermal connecting member being configured to thermally connect the heat radiation member and the semiconductor element. A metal material is used as the thermal connecting member, and an adhesion preventing member is provided so as to be separated from the electronic component, the adhesion preventing member being configured to prevent the metal material molten and flowing at a heating time being adhered to the electronic component. | 12-04-2008 |
20080308927 | Semiconductor device with heat sink plate - A semiconductor chip is mounted on an upper surface of the heat sink plate that is provided with a plurality of heat releasing terminals on a lower surface of the heat releasing. A plurality of electric signal terminals are regularly disposed in a lattice-like manner around the heat sink plate. Lower end surfaces of the electric signal terminals and the heat releasing terminals are exposed from and sealed with a sealing resin. The heat sink plate is formed as an integrated body including a protruding portion that protrudes from a central portion of an upper surface and supports the semiconductor chip, a plurality of supporting portions that are positioned around a rear surface of the protruding portion so as to support the protruding portion and that are exposed at a rear surface of the sealing resin, the plurality of heat releasing terminals, and a thin-walled portion that is recessed from lower end surfaces of the supporting portions and the heat releasing terminals. Lower surfaces of the protruding portion and the thin-walled portion are covered with the sealing resin. The plurality of supporting portions are disposed so that they are continuous with the protruding portion and symmetrical to each other around the protruding portion. A degree of freedom is improved in board wiring below the heat sink plate in a land grid array type package. | 12-18-2008 |
20080315401 | Power Semiconductor Module And Method of Manufacturing the Power Semiconductor Module - A power semiconductor module has a silicon nitride insulated substrate, a metal circuit plate made of Cu or a Cu alloy, which is disposed on one surface of the silicon nitride insulated substrate, a semiconductor chip mounted on the metal circuit plate, and a heat dissipating plate made of Cu or a Cu alloy, which is disposed on the other surface of the silicon nitride insulated substrate; a carbon fiber-metal composite made of carbon fiber and Cu or a Cu alloy is provided between the silicon nitride insulated substrate and the metal circuit plate; the thermal conductivity of the carbon fiber-metal composite in a direction in which carbon fiber of the carbon fiber-metal composite is oriented is 400 W/m·k or more. Accordingly, a power semiconductor module that has a low thermal resistance between the semiconductor chip and a heat dissipating mechanism and also has improved cooling capacity is provided. | 12-25-2008 |
20080315402 | PRINTED CIRCUIT BOARD, MEMORY MODULE HAVING THE SAME AND FABRICATION METHOD THEREOF - A printed circuit board, a memory module having the same, and a fabrication method thereof. The printed circuit board includes an interconnection substrate on which electronic components are mounted and in which a plurality of signal lines are arranged. The signal lines are electrically coupled to the electronic components. A heat sink is disposed on one surface of the interconnection substrate to dissipate heat of the electronic components, and in which no signal lines are arranged. The printed circuit board includes a bending substrate coupling the interconnection substrate to the heat sink, and formed of a flexible material configured to be bent. | 12-25-2008 |
20090001556 | LOW TEMPERATURE THERMAL INTERFACE MATERIALS - A method may provide thermal interface material. The method comprises providing a first coating layer on a top side of a base metal layer and a second coating layer on a bottom side of the base metal layer, wherein the coating layer has a melting point lower than a melting point of the base metal layer; attaching the base metal layer to a die and a heat spreader; and melting the first coating layer and the second coating layer to bond to the die and the heat spreader. | 01-01-2009 |
20090001557 | Forming a semiconductor package including a thermal interface material - In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM) layer including copper (Cu) and a heat spreader having a contact surface including Cu, where the TIM is formed of an alloy including indium (In) and tin (Sn), and bonding the TIM to the die and the heat spreader to form at least one quaternary intermetallic compound (IMC) layer. Other embodiments are described and claimed. | 01-01-2009 |
20090001558 | Lamp Seat for a Light Emitting Diode and Capable of Heat Dissipation, and Method of Manufacturing the Same - A lamp seat includes a metal substrate having opposite first and second surfaces, first and second conductive patterns formed on the first surface, and third and fourth conductive patterns formed on the second surface and connected respectively and integrally to the first and second conductive patterns. A heat-conductive first insulating layer is disposed between the metal substrate and each of the first, second, third and fourth conductive patterns. A heat-conductive second insulating layer is formed over the first insulating layer such that corresponding parts of the first and second conductive patterns are exposed outwardly of the second insulating layer for electrical connection with positive and negative electrodes of a light emitting diode, respectively. | 01-01-2009 |
20090001559 | Semiconductor device, a method of manufacturing the same and an electronic device - A novel semiconductor device high in both heat dissipating property and connection reliability in mounting is to be provided. The semiconductor device comprises a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member. | 01-01-2009 |
20090008770 | HEAT DISSIPATION PLATE AND SEMICONDUCTOR DEVICE - A heat dissipation plate having a lamination of a copper layer, a molybdenum layer and a graphite layer, and outer copper layers each provided on a surface of the lamination, is disclosed. And also a semiconductor device using the heat dissipation plate is disclosed. | 01-08-2009 |
20090014865 | HEAT-CONDUCTIVE PACKAGE STRUCTURE - A heat-conductive package structure includes a carrier board having a first surface and an opposing second surface and formed with a through opening passing the carrier board; a first heat-conductive structure including a heat-conductive hole in the through opening, a first heat-conductive sheet on the carrier board, and a second heat-conductive sheet on the carrier board, wherein the first and second heat-conductive sheets are conductively connected by the heat-conductive hole; a first dielectric layer formed on the first surface of the carrier board and formed with a first opening for exposing the first heat-conductive sheet; a second dielectric layer formed on the second surface of the carrier board and formed with at least a second opening for exposing a portion of the second heat-conductive sheet; and a second heat-conductive structure formed in the second opening and mounted on the second heat-conductive sheet. | 01-15-2009 |
20090020867 | SEMICONDUCTOR DEVICE - A semiconductor device, includes: a wiring substrate having a wiring pattern on a front surface thereof; a first semiconductor chip mounted on the front surface of the wiring substrate; a first heat radiator having a first recess housing the first semiconductor chip and making contact with the front surface of the wiring substrate and the first semiconductor chip directly or with a first insulation layer; a second heat radiator making contact with a rear surface of the wiring substrate directly or with a second insulation layer; and a first fixing member passing through the first heat radiator, the wiring substrate, and the second heat radiator, and pressing the first heat radiator and the second heat radiator to the wiring substrate. | 01-22-2009 |
20090026605 | Heat Extraction from Packaged Semiconductor Chips, Scalable with Chip Area - A semiconductor device ( | 01-29-2009 |
20090026606 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device and a method for manufacturing the same are described. The semiconductor device comprises: a heat sink having at least one opening passing through the heat sink; at least one semiconductor chip disposed in the opening, wherein the semiconductor chip includes a first side and a second side on opposite sides; an electricity conducting thin film filling in a first depth portion of the opening, wherein the second side of the semiconductor chip is embedded in the electricity conducting thin film; a heat conducting thick film filling in a second depth portion of the opening, wherein the electricity conducting thin film is directly connected with the heat conducting thick film; at least one wire electrically connecting the semiconductor chip and an external circuit; and an encapsulant covering a portion of the heat sink, the semiconductor chip, the wire and an exposed portion of the electricity conducting thin film. | 01-29-2009 |
20090032936 | SEMICONDUCTOR DEVICE, METHOD FOR THE SAME, AND HEAT RADIATOR - A semiconductor device includes a semiconductor chip, and a multicomponent alloy layer formed on a face of the semiconductor chip, the multicomponent alloy layer being in a solid-liquid coexisting state in a specific temperature range, and including a surface having concavity and convexity caused by solidification segregation. | 02-05-2009 |
20090032937 | COOLING SYSTEMS FOR POWER SEMICONDUCTOR DEVICES - A cooling device is provided for liquid cooling a power semiconductor device. The device includes a coolant diverter for guiding liquid coolant to the power semiconductor device. The coolant diverter has a first plate for dividing the coolant diverter into a first cavity and a second cavity. The second cavity positioned adjacent the power semiconductor device. The first plate further includes an opening to fluidly couple the first cavity with the second cavity such that the liquid coolant flows into the first cavity, through the opening in the first plate, and into the second cavity to cool the power semiconductor device. The first cavity has a cross-sectional area that generally decreases in a downstream direction, and the second cavity has a cross-sectional area that generally increases in the downstream direction. | 02-05-2009 |
20090039500 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a base plate having first and second surfaces both facing in opposite directions, and a plurality of anisotropic heat conducting members disposed in the base plate and spaced away from each other. A semiconductor element having a heat generating unit is mounted on the first surface, and the second surface is supported on a supporting member having a thermal conductivity. Each anisotropic heat conducting member has a sheet shape intersecting with the first and second surfaces, and orientates a direction of higher thermal conductivity than the thermal conductivity of the base plate in a direction from the first surface toward the second surface. | 02-12-2009 |
20090045506 | Cu-Mo SUBSTRATE AND METHOD FOR PRODUCING SAME - A Cu—Mo substrate | 02-19-2009 |
20090051026 | PROCESS FOR FORMING METAL FILM AND RELEASE LAYER ON POLYMER - A process for forming a releasable metal film includes depositing a metal onto a polymeric sheet such that the metal layer provides a low adhesive interface and exhibits relatively low stress. A barrier layer is then deposited onto the surface of the low adhesion interface. A thin film of a stress relief layer of silicon dioxide, aluminum oxide, copper or aluminum is then deposited followed by addition of a second barrier layer onto the stress relief layer. The stress relief layer provides compressive relief to balance the tensile stress of the so-stacked metal films. An additional solderable layer maybe added for soldering applications. To fabricate the working device with sputtering tools, an extremely high gas pressure is used to achieve low adhesion force between the wettable metallic layer and the polymeric carrier film. | 02-26-2009 |
20090072382 | MICROELECTRONIC PACKAGE AND METHOD OF FORMING SAME - A microelectronic package includes a carrier ( | 03-19-2009 |
20090072383 | SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT MODULE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor element is provided with a heat dissipating path defined by a non-through hole in a first principal surface and that is filled with a conductive material. The semiconductor element is bonded to a heat sink with the conductive material disposed therebetween. Solder can be used as the conductive material, for example. By introducing molten solder into the non-through hole while having solder disposed between the semiconductor element and the heat sink, the heat dissipating path is provided and the heat sink is bonded to the semiconductor element. | 03-19-2009 |
20090072384 | Packaging substrate having heat-dissipating structure - Provided is a packaging substrate with a heat-dissipating structure, including a core layer with a first surface and an opposite second surface having a first metal layer and a second metal layer respectively. Portions of the first metal layer are exposed from a second cavity penetrating the core layer and second metal layer. Portions of the second metal layer are exposed from a first cavity penetrating the core layer and first metal layer. Semiconductor chips each having an active surface with electrode pads thereon and an opposite inactive surface are received in the first and second cavities and attached to the second metal layer and the first metal layer respectively. Conductive vias disposed in build-up circuit structures electrically connect to the electrode pads of the semiconductor chips. A heat-dissipating through hole penetrating the core layer and build-up circuit structures connects the metal layers and contact pads. | 03-19-2009 |
20090079061 | THERMALLY ENHANCED ELECTRONIC FLIP-CHIP PACKAGING WITH EXTERNAL-CONNECTOR-SIDE DIE AND METHOD - A method and apparatus for making a package having improved heat conduction characteristics and high frequency response. A relatively thick package substrate, such as copper, has a wiring layer bonded to one face, leaving the opposite face exposed, for example, to be a surface for connection to a heat sink. One or more chips are bonded to the wiring layer, and an array of connectors, such as solder balls are provided around the periphery of the chip(s) for connection to a printed circuit board. In some embodiments, the printed circuit board has a hole that the chip(s) extend into to allow smaller external-connection solder balls. In some embodiments, a second heat sink is connected to the back of the chip through the PCB hole. | 03-26-2009 |
20090079062 | SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE - A semiconductor package is provided. The semiconductor package includes: a package substrate on which a semiconductor device is mounted; a heat spreader at least bonded to a surface of the semiconductor device and having a thermal expansion coefficient value equal to or less than a thermal expansion coefficient value of the package substrate; a metal layer provided on a bonding face of the heat spreader bonded to the semiconductor device; and a solder layer formed between the metal layer and semiconductor device, and bonding the heat spreader to the semiconductor device. | 03-26-2009 |
20090096085 | Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate. | 04-16-2009 |
20090102046 | ON-CHIP TEMPERATURE GRADIENT MINIMIZATION USING CARBON NANOTUBE COOLING STRUCTURES WITH VARIABLE COOLING CAPACITY - An electronic device comprises a die with at least one defined hot-spot area; and at least one defined intermediate temperature area at a temperature lower than the temperature of the hot-spot area. The device also comprises a cooling structure comprising at least one bundle of first nanotubes for cooling the hot spot area and at least one bundle of additional nanotubes for cooling the intermediate temperature area, and having heat conductivity lower than the bundle of first nanotubes. The heat conductivity of both sets of the nanotubes is sufficient to decrease any temperature gradient between the defined hot spot area, the defined intermediate temperature area, and at least one lower temperature area on the die. The walls of the first nanotubes and the additional nanotubes are surrounded by a heat conducting matrix material operatively associated with the lower temperature area. | 04-23-2009 |
20090115053 | Semiconductor Package Thermal Performance Enhancement and Method - A semiconductor device package and related method are disclosed for providing a semiconductor device encapsulated in a protective package body. The device has an exposed surface to which a thermal compound is applied for improving a thermal path for the egress of heat from the device. Preferred embodiments are disclosed in which a removable cover is attached to the thermal compound for further improved protection during handling. | 05-07-2009 |
20090121342 | SEMICONDUCTOR DEVICE INCLUDING MAIN SUBSTRATE AND SUB SUBSTRATES AND FABRICATION METHOD OF THE SAME - A semiconductor device according to a preferred embodiment of the present invention is a semiconductor device including a main substrate and one or more sub substrates, and the semiconductor device includes first heat generating devices mounted on the sub substrates, sub-substrate heatsinks mounted to the first heat generating devices, and a main-substrate heatsink mounted to the main substrate, wherein the sub-substrate heatsinks and the main-substrate heatsink are secured to each other, such that there is a predetermined positional relationship between the sub substrates and the main substrate. | 05-14-2009 |
20090127700 | THERMAL CONDUCTOR LIDS FOR AREA ARRAY PACKAGED MULTI-CHIP MODULES AND METHODS TO DISSIPATE HEAT FROM MULTI-CHIP MODULES - Multi-chip modules and methods to form multi-chip modules are disclosed. A disclosed method to form a multi-chip module includes attaching a first integrated circuit to a top surface of a substrate, attaching a second integrated circuit to the top surface of the substrate, the top surface of the second integrated circuit having a top surface taller than a top surface of the first integrated circuit, and attaching a heat conductor to the top surface of the first and second integrated circuits. | 05-21-2009 |
20090146292 | SEMICONDUCTOR DEVICE THERMAL CONNECTION - A semiconductor device thermal connection used to remove heat from a semiconductor device, such as an integrated circuit, includes a metallic barrier layer on the semiconductor device, and a high thermal conductivity material on the metallic barrier layer that joins the semiconductor device to a thermal heat spreader. The metallic barrier layer may be one or more sputtered layers, and the high thermal conductivity material may be a metallic material, for instance including indium, that is soldered onto the sputtered material. The high thermal conductivity material may form a primary thermal connection in conducting heat away from the semiconductor device. A secondary thermal connection may be made between the heat spreader and a heat sink. The secondary thermal connection may include a compressible solid carbon fiber material. A diaphragm may be used to contain the carbon fiber material, to prevent carbon fibers from coming into contact with the semiconductor device. | 06-11-2009 |
20090152712 | Packaging apparatus for optical-electronic semiconductors and a packaging method therefor - A packaging apparatus for optical-semiconductors includes a mold base having a longitudinal receiving space, an encapsulating module attached to the mold base, and a fixing member attached to the encapsulating module. The bottom of the mold base has at least one air-vent and the mold base has a predetermined width. The encapsulating module includes a plate engaged with the mold base, a plurality of molding bodies penetrating the plate and received in the receiving space, and a plurality of supporting members connected to the molding bodies. The fixing member has a plurality of holding slots to hold the supporting members so that the supporting members are more stable. Furthermore, the width of the mold base is optimized with the dimension of a furnace so that the production rate is increased and the stability of the packaging structure is improved. | 06-18-2009 |
20090166853 | MULTI-LAYER STACKED WAFER LEVEL SEMICONDUCTOR PACKAGE MODULE - A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad. | 07-02-2009 |
20090174064 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SLUG - An integrated circuit package system is provided including providing a substrate having a die attached and electrically bonded thereto. The system includes forming heat slug pillars on the substrate, positioning a heat slug on the heat slug pillars, and encapsulating the substrate, the die, the heat slug pillars, and the heat slug in a mold compound. The system includes singulating the substrate, the die, the heat slug, and the mold compound. | 07-09-2009 |
20090174065 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 07-09-2009 |
20090179322 | ELECTRONIC PACKAGE METHOD AND STRUCTURE WITH CURE-MELT HIERARCHY - Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing. | 07-16-2009 |
20090194868 | PANEL LEVEL METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS WITH INTEGRATED HEAT SINKS - Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package. | 08-06-2009 |
20090194869 | HEAT SINK PACKAGE - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 08-06-2009 |
20090200661 | Devices with faraday cages and internal flexibility sipes - A computer or microchip comprising an outer chamber and at least one inner chamber inside the outer chamber. The outer chamber and the inner chamber being separated at least in part by an internal sipe, and at least a portion of a surface of the outer chamber forming at least a portion of a surface of the internal sipe. The internal sipe has opposing surfaces that are separate from each other and therefore can move relative to each other, and at least a portion of the opposing surfaces are in contact with each other in a unloaded condition. The outer chamber including a Faraday Cage. A computer, comprising an undiced semiconductor wafer having a multitude of microchips. The multitude of microchips on the wafer forming a plurality of independently functioning computers, each computer having independent communication capabilities. | 08-13-2009 |
20090212417 | Semiconductor Device - A semiconductor device including: a heat sink, a die on the heat sink, resin encapsulating the die, and a mounting aperture in the resin having at least a segment between the heat sink and a first end of the resin, wherein the thickness of the heat sink is no greater than 35% of the thickness of the device. | 08-27-2009 |
20090218680 | PROCESS OF GROUNDING HEAT SPREADER/STIFFENER TO A FLIP CHIP PACKAGE USING SOLDER AND FILM ADHESIVE - A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the substrate. The grounding pads may be configured to provide electrical grounding. The stiffener may have a number of second holes corresponding with the number of first holes of the adhesive film and number the grounding pads of the substrate. The grounding pads are generally exposed through the first and the second holes. | 09-03-2009 |
20090230543 | Semiconductor package structure with heat sink - A semiconductor package structure with a heat sink is disclosed herein. The semiconductor package structure includes a substrate having a chip mounting area and a plurality of through holes surrounding the chip mounting area; a chip set on the chip mounting area and electrically connected to the substrate; a heat sink covering the chip, wherein the heat sink has a plurality of support portions extending from the upper surface to the lower surface of the substrate via those through holes; and a molding compound covering the chip, a portion of the substrate and the heat sink. Those support portions of the heat sink are utilized to improve the heat dissipation efficiency and the warpage issue of the package. | 09-17-2009 |
20090230544 | HEAT SINK STRUCTURE AND SEMICONDUCTOR PACKAGE AS WELL AS METHOD FOR CONFIGURING HEAT SINKS ON A SEMICONDUCTOR PACKAGE - A heat sink structure according to the present invention is provided. The heat sink has a through opening extending from the upper surface through to the lower surface. A solder is disposed in the through opening and on the upper and lower surfaces of the heat sink, wherein the portion of the solder in the through opening is connected with the portions of the solder on the upper and lower surfaces. | 09-17-2009 |
20090243085 | APPARATUS AND METHOD FOR ATTACHING A HEAT DISSIPATING DEVICE - A microelectronic package is provided. The microelectronic package includes a heat dissipating device having a top side and a bottom side and a thermal interface material disposed adjacent to the bottom side of the heat dissipating device. The microelectronic package also includes a patterned metal layer comprising at least two metals disposed on the bottom side of the heat dissipating device, wherein the patterned metal layer is to adhere the heat dissipating device to the thermal interface material. | 10-01-2009 |
20090243086 | Enhanced Thermal Dissipation Ball Grid Array Package - In a semiconductor chip, a thermal adhesive is used to bond an internal heat spreader to an active functional die. In an alternative embodiment a dummy die is place directly on top of the active functional die and a thermal adhesive is used to bond an internal heat spreader to the dummy die. This provides a direct and relatively low thermal conductivity path from the heat source, i.e., the functional device to the top of the package, that is, the internal metal heat spreader which is also exposed to the air. | 10-01-2009 |
20090250806 | SEMICONDUCTOR PACKAGE USING AN ACTIVE TYPE HEAT-SPREADING ELEMENT - A semiconductor package includes a carrier, a chip, a stiffener, a heat spreader and an active type heat-spreading element. The chip and the stiffener are disposed on the carrier. The heat spreader is disposed on the stiffener and includes a through opening. The active type heat-spreading element is disposed on the chip and located in the through opening. | 10-08-2009 |
20090250807 | Electronic Component and Method for its Production - An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s). | 10-08-2009 |
20090273077 | MULTI-LID SEMICONDUCTOR PACKAGE - A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance. | 11-05-2009 |
20090289351 | Semiconductor apparatus having both-side heat radiation structure and method for manufacturing the same - A semiconductor apparatus having a first surface and a second surface opposite to the first surface includes: a semiconductor chip having a front side and a backside; a first heat radiation member electrically and thermally coupled with the backside of the chip; a second heat radiation member electrically and thermally coupled with the front side of the chip; and a resin mold sealing the first and second heat radiation members together with the chip. At least one of the first and second heat radiation members is exposed on both of the first and second surfaces. | 11-26-2009 |
20090289352 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes: a first substrate, having a grounding layer and holes formed therein for filling with an electroconductive material; a semiconductor chip over such first substrate; and an electroconductive heat releasing member, electrically coupled to the semiconductor chip able to release heat from the semiconductor chip. The heat releasing member includes a ceiling section covering the surface of the semiconductor chip and side surface extending from the ceiling section toward the sides of the first substrate. The ceiling section of the heat releasing member and the side surface sections are formed to compose an integral member. Tips of the side surface sections are inserted in the respective holes of the first substrate. The tips of the side surface section, in turn, are fixed in the inside of the respective holes with the electroconductive material, and the tips are electrically coupled to the grounding layer through the electroconductive material. | 11-26-2009 |
20090289353 | COVERED DEVICES IN A SEMICONDUCTOR PACKAGE - An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base plate. The sidewalls have a height. A plurality of devices is attached to underside of the base plate. The devices have length corresponding to the height such that the devices are sealed within the cover when the cover is attached to a surface. | 11-26-2009 |
20090302460 | SELF-ASSEMBLED MONOLAYER RELEASE FILMS - A release film for soft composite materials is provided. The release film contains a film with a closely packed self-assembled monolayer. A method of applying soft composite materials to a substrate without loss of the soft composite material to the release film is also provided. The method is useful in applications such as applying thermal pastes to semiconductor packaging. | 12-10-2009 |
20090315172 | Semiconductor chip assembly - A semiconductor chip assembly includes a semiconductor chip and a pyrolytic graphite element that is an electrode that is electrically connected to and provides electrical conduction of current from the chip during operation of the chip. | 12-24-2009 |
20090321923 | MAGNETIC PARTICLE-BASED COMPOSITE MATERIALS FOR SEMICONDUCTOR PACKAGES - A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity. | 12-31-2009 |
20100007013 | Semiconductor device - A semiconductor device, comprising: a semiconductor element | 01-14-2010 |
20100013089 | Semiconductor component and manufacturing method of semiconductor component - A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member. | 01-21-2010 |
20100019377 | SEGMENTATION OF A DIE STACK FOR 3D PACKAGING THERMAL MANAGEMENT - An apparatus to reduce a thermal penalty of a three-dimensional (3D) die stack for use in a computing environment is provided and includes a substrate installed within the computing environment, a first component to perform operations of the computing environment, which is coupled to the substrate in a stacking direction, a set of second components to perform operations of the computing environment, each of which is coupled to the first component and segmented with respect to one another to form a vacated region, a thermal interface material (TIM) disposed on exposed surfaces of the first and second components, and a lid, including a protrusion, coupled to the substrate to overlay the first and second components such that the protrusion extends into the vacated region and such that surfaces of the lid and the protrusion thermally communicate with the first and second components via the TIM. | 01-28-2010 |
20100019378 | SEMICONDUCTOR MODULE AND A METHOD FOR PRODUCING AN ELECTRONIC CIRCUIT - A semiconductor module has at least one die, made of silicon carbide, in which semiconductor components are patterned. The die includes at least one exposed surface for contacting an external heat sink. | 01-28-2010 |
20100052156 | CHIP SCALE PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A chip scale package (CSP) structure and the packaging process thereof are described. By using a matrix of interlinked heat sink units compatible with the block substrate, the packaging process can be simplified and a plurality of packages units or chip scale packages with enhanced thermal performance can be obtained after singulation. | 03-04-2010 |
20100052157 | CHANNEL FOR A SEMICONDUCTOR DIE AND METHODS OF FORMATION - In semiconductor die packaging, stereo lithography cures a material around the die such that a channel is defined in the material. The channel exposes a portion of the die surface, and the channel is closed off above the die surface. The same stereo lithography process may also be used to define an opening that exposes a through-silicon via extending from the die surface. An additional or alternative channel may be similarly defined at a side perpendicular to that surface. The die may be stacked with other die, and the stereo lithography process may occur before or after stacking. A heat sink contacting the channel may also be added. | 03-04-2010 |
20100059879 | Power Amplifier Assembly - The power amplifier module comprises a laminate substrate comprising thermal vias and terminals, as well as a platform device with an interconnection substrate of a semiconductor material. This substrate is provided with electrical interconnects at a first side, and having been mounted on the laminate substrate with an opposite second side. Electrically conducting connections extend from the first to the second side through the substrate. A power amplifier device is attached to the second side of the substrate. One of the electrically conducting connection through the interconnection substrate is a grounding path for the power amplifier, while a thermal path is provided by the semiconductor material. There is an optimum thickness for the interconnection substrate, at which both a proper grounding and a acceptable thermal dissipation is effected. | 03-11-2010 |
20100072612 | BARE DIE PACKAGE WITH DISPLACEMENT CONSTRAINT - Embodiments of the present invention describe a bare die package and its methods of fabrication The bare die package comprises a die electrically coupled to a package substrate, and a displacement constraint. In an embodiment of the present invention, the displacement constraint is a plurality of members fixedly attached onto the package substrate and surrounds the die. When the bare die package is secured between a socket and a heat sink, the plurality of members provide structural support to the package substrate and prevent excessive substrate warpage. | 03-25-2010 |
20100078806 | MICROELECTRONIC PACKAGE WITH WEAR RESISTANT COATING - A microelectronic package is provided. The microelectronic package includes a semiconductor substrate and a die having a top surface and a bottom surface, wherein the bottom surface of the die is coupled to the semiconductor substrate. The microelectronic package also includes a nanomaterial layer disposed on the top surface of the die. | 04-01-2010 |
20100090335 | SEMICONDUCTOR PACKAGE FOR DISCHARGING HEAT AND METHOD FOR FABRICATING THE SAME - A semiconductor package for quickly discharging heat and a method for fabricating the same are disclosed. The semiconductor package includes a semiconductor package module having a first insulation member and at least one fluid passage passing through the insulation member. Circuit patterns are formed on a first face of the first insulation member. Semiconductor chips are then disposed on the first face and are electrically connected with the circuit patterns respectively. A second insulation member is formed so as to surround the side faces of the semiconductor chips, the first insulation member, and the circuit patterns. Finally, a through electrode is formed passing through the second insulation member of the semiconductor package module and electrically connecting to the circuit patterns. | 04-15-2010 |
20100127388 | METAL INJECTION MOLDED HEAT DISSIPATION DEVICE - A heat dissipation device is provided. The heat dissipation device includes an integrated heat spreader and a base plate coupled to the integrated heat spreader, wherein tile base plate comprises a plurality of metal pellets to dissipate heat from the integrated heat spreader. | 05-27-2010 |
20100127389 | POWER SEMICONDUCTOR MODULE - The power semiconductor module includes: a circuit substrate; power semiconductor elements joined to element mounting portions of the wiring pattern on the circuit substrate; the cylindrical external terminal communication section joined to the wiring pattern; circuit forming means for connecting between portions that require electrical connection therebetween; and transfer molding resin for sealing these components. The cylindrical external terminal communication section is a metal cylinder, and the cylindrical external terminal communication section has a hole filled with gel. | 05-27-2010 |
20100133683 | SYSTEM AND APPARATUS FOR VENTING ELECTRONIC PACKAGES AND METHOD OF MAKING SAME - An apparatus and method, the apparatus includes a substrate configured to support a plurality of dielectric layers, a device coupling area positioned in the substrate, and a plurality of gas exit apertures formed through the substrate. The plurality of gas exit apertures is configured to provide venting of at least one of moisture and outgassed material and the device coupling area is configured to receive an electronic device coupleable to the plurality of dielectric layers. | 06-03-2010 |
20100133684 | POWER SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF - A power semiconductor module includes: a circuit board having a metal base plate, a high thermal conductive insulating layer, and a wiring pattern; power semiconductor elements electrically connected to the wiring pattern; tubular external terminal connection bodies provided to the wiring pattern for external terminals; and a transfer mold resin body encapsulated to expose through-holes in the metal base plate and used to fixedly attach cooling fins to the face of the metal base plate on the other side with attachment members, the face of the metal base plate on the other side, and top portions of the tubular external terminal connection bodies, to form insertion holes for the attachment members communicating with the through-holes and having a larger diameter than the through-holes, and to cover the one side and side faces of the metal base plate and the power semiconductor elements. | 06-03-2010 |
20100140791 | INTEGRATED CIRCUIT PACKAGING STRUCTURE AND METHOD OF MAKING THE SAME - The invention provides an integrated circuit packaging and method of making the same. The integrated circuit packaging includes a substrate, a semiconductor die, a heat-dissipating module, and a protection layer. The substrate has an inner circuit formed on a first surface, and an outer circuit formed on a second surface and electrically connected to the inner circuit. The semiconductor die is mounted on the first surface of the substrate such that the plurality of bond pads contact the inner circuit. The heat-dissipating module includes a heat-conducting device, and the heat-conducting device, via a flat end surface thereof, contacts and bonds with a back surface of the semiconductor die. The protection layer contacts a portion of the first surface of the substrate and a portion of the heat-conducting device, such that the semiconductor die is encapsulated therebetween. | 06-10-2010 |
20100148356 | STACKED SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a first substrate; a second substrate provided over the first substrate, and divided into a plurality of portions; a cooling member provided in a gap between the divided second substrate portions on the first substrate; and a third substrate provided on the second substrate portions and the cooling member. For example, a heat pipe or the like is used as the cooling member. | 06-17-2010 |
20100187681 | Silicon Substrate Having Through Vias and Package Having the Same - The present invention relates to a silicon substrate having through vias and a package having the same. The silicon substrate includes a substrate body, a plurality of through vias and at least one heat dissipating area. The substrate body has a surface, and the material of the substrate body is silicon. The through vias penetrate the substrate body, and each of the through vias has a conductive material therein. The heat dissipating area is disposed on the surface of the substrate body and covers at least two through vias. The heat dissipating area is made of metal, and the through vias inside the heat dissipating area have same electrical potential. Thus, the heat in the through vias is transmitted to the heat dissipating area, and since the area of the heat dissipating area is large, the silicon substrate has good heat dissipation efficiency. | 07-29-2010 |
20100193941 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate having a ceramic substrate and metal coating layers on opposite surfaces of the ceramic substrate, a semiconductor chip mounted on one surface of the insulating substrate, a heat sink directly or indirectly fixed to the other surface of the insulating substrate and thermally connected to the semiconductor chip through the insulating substrate and at least one anti-warping sheet disposed on at least one surface of the heat sink. The anti-warping sheet is made of a metal sheet having a coating layer and has coefficient of thermal expansion between those of the insulating substrate and the heat sink. | 08-05-2010 |
20100219526 | FLEXIBLE MICROELECTRONICS ADHESIVE - A curable thermal interface material is provided comprising a functionalized elastomer and a filler. Preferred materials comprise an epoxidized polybutadiene cured with an iodonium catalyst and a filler comprising silver and/or aluminum oxide. | 09-02-2010 |
20100224990 | SEMICONDUCTOR PACKAGE HAVING AN INTERNAL COOLING SYSTEM - A semiconductor package having an internal cooling system is presented which includes a semiconductor chip and a through-electrode. The semiconductor chip has a circuit section. The through-electrode passes through an upper surface and a lower surface the semiconductor chip. The through-electrode is electrically connected with the circuit section of the semiconductor chip. The through-electrode also has a through-hole for allowing cooling fluid to flow therethrough. | 09-09-2010 |
20100230804 | THERMAL RESISTOR, SEMICONDUCTOR DEVICE USING THE SAME, AND ELECTRIC DEVICE - A thermal resistor is a metal body having a contact surface to be partially in contact to form a void and is electrically conductive as a whole. The thermal body may be a layered body having a plurality of metal bodies layered so as to be partially in contact with one another to form a void between them, or a metal body having a plurality of convex and concave portions on the surface, or a metal body formed by a plurality of metal plates each having a plurality of creases and layered so that the creases of the adjacent metal plates intersect, or a layered metal body formed by metal plates each having elasticity in the thickness direction and having elasticity in the layered direction as a whole, or metal body having a film formed by a different metal. Also disclosed in a semiconductor device having the thermal resistor inserted between a heating semiconductor element and a case cover and between a heat spreader and the case cover. Also disclosed is an electric device using the device. | 09-16-2010 |
20100230805 | MULTI-DIE SEMICONDUCTOR PACKAGE WITH HEAT SPREADER - A semiconductor device includes first and second stacked semiconductor dies on a substrate. A lid having a plurality of fins extending downwardly into the cavity is mounted on the substrate to encapsulate the semiconductor dies. At least some of the fins are longer than other ones of said fins. The lid is attached to the substrate, with the longer fins extending downwardly above a region of the substrate not occupied by the first die. The shorter fins extend downwardly above a region of said first die not covered by said second die. A thermal interface material fills the remainder of the cavity and is in thermal communication with both dies, the substrate and the fins. The lid may be molded from metal. The lid may be bonded to the topmost die, using a thermal bonding material that may be liquid metal, or the like. | 09-16-2010 |
20100237496 | Thermal Interface Material with Support Structure - Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader. | 09-23-2010 |
20100264536 | SELF-HEALING THERMAL INTERFACE MATERIALS FOR SEMICONDUCTOR PACKAGES - A semiconductor package is described. The semiconductor package includes an internal housing and a semiconductor die coupled with the internal housing by a layer of self-healing thermal interface material. | 10-21-2010 |
20100283142 | MOLD LOCK ON HEAT SPREADER - A mold lock and a method of forming the mold lock are provided. The mold lock is used in an encapsulated semiconductor device and includes a neck and a shaped head integral with the neck. The mold lock can be formed to project above a support component, such as a heat spreader, of the semiconductor device and the neck is formed from the support component. The shaped head is of a greater dimension than the neck and can present a “T” shape in side view or a “Y” shape in side view. A base portion of the neck is seated within the support component. A method is provided for forming the described mold lock. | 11-11-2010 |
20100289136 | SEMICONDUCTOR PACKAGE - A semiconductor package comprises a semiconductor chip, through electrodes and cooling parts. The semiconductor chip has bonding pads on an upper surface thereof. The through-electrodes are formed in the semiconductor chip. The cooling parts are formed in the semiconductor chip and on the upper surface of the semiconductor chip in order to dissipate heat. | 11-18-2010 |
20100289137 | HEAT SINK PACKAGE - Provided are a heat sink package in which a semiconductor package and a heat sink are bound to each other and a method of fabricating the same. | 11-18-2010 |
20100295172 | POWER SEMICONDUCTOR MODULE - Disclosed is a power semiconductor module having improved heat dissipation performance, including an anodized metal substrate including a metal plate, an anodized layer formed on a surface of the metal plate, and a circuit layer formed on the anodized layer on the metal plate, a power device connected to the circuit layer, and a housing mounted on the metal plate and for defining a sealing space which accommodates a resin sealing material for sealing the circuit layer and the power device. | 11-25-2010 |
20100327430 | SEMICONDUCTOR DEVICE ASSEMBLY HAVING A STRESS-RELIEVING BUFFER LAYER - Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE | 12-30-2010 |
20100327431 | Semiconductor Chip Thermal Interface Structures - Various thermal interface structures and methods are disclosed. In one aspect, a method of manufacturing is provided. The method includes providing plural carbon nanotubes in a thermal interface structure. The thermal interface structure is soldered to a side of a semiconductor chip. In another aspect, an apparatus is provided. The apparatus includes a thermal interface structure that has plural carbon nanotubes. A semiconductor chip is soldered to the thermal interface structure. | 12-30-2010 |
20100327432 | PACKAGE WITH HEAT TRANSFER - A semiconductor package includes an encapsulant, a semiconductor device within the encapsulant, and one or more terminals for electrically coupling the semiconductor device to a node exterior to the package. The package further includes bonding means coupling the semiconductor device to the one or more terminals. The semiconductor package is configured to dissipate heat through a top surface of the package. To directly dissipate heat via the top surface of the package, a thermally conductive layer is coupled to the semiconductor device, and the layer is exposed at a surface of the package. | 12-30-2010 |
20110012255 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring substrate, a first semiconductor chip mounted on the wiring substrate, a second semiconductor chip mounted to the wiring substrate in a lateral direction thereof, a first radiation unit connected to the first semiconductor chip, and arranged to extend from an upper side of the first semiconductor chip to an upper side the second semiconductor chip, and a second radiation unit connected to the second semiconductor chip, and arranged to extend from an lower side of the first radiation unit to an outside thereof in a non-contact state to the first radiation unit. | 01-20-2011 |
20110012256 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor chip having a switching function, a resin portion that covers the chip, terminals, and a heat dissipation portion. The resin portion includes first and second surfaces, which are opposed to each other and expand generally parallel to an imaginary plane; and a substrate is located on a first surface-side of the resin portion. The terminals project from the resin portion in a direction of the imaginary plane and are soldered onto the substrate. The heat dissipation portion is disposed on a second surface-side of the resin portion to release heat generated in the chip. One of the terminals is connected to the heat dissipation portion such that heat is transmitted from the one of the terminals to the heat dissipation portion. | 01-20-2011 |
20110037165 | Semiconductor Device and Method of Mounting Semiconductor Die to Heat Spreader on Temporary Carrier and Forming Polymer Layer and Conductive Layer Over the Die - A semiconductor device is made by forming a heat spreader over a temporary carrier. A semiconductor die is mounted to the heat spreader. A first polymer layer is formed over the semiconductor die and heat spreader. A first conductive layer is formed over the first polymer layer. The first conductive layer is connected to the heat spreader and contact pads on the semiconductor die. A second polymer layer is formed over the first conductive layer. A second conductive layer is formed over the second polymer layer. The second conductive layer is electrically connected to the first conductive layer. Bumps are formed through a solder masking layer on the second conductive layer. The temporary carrier is removed. The heat spreader dissipates heat from the semiconductor die and provides shielding from inter-device interference. The heat spreader is grounded through the first and second conductive layers. | 02-17-2011 |
20110037166 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The object of the present invention is to efficiently dissipate heat from the upper and lower main surfaces of a semiconductor device carrying a semiconductor element. A semiconductor device ( | 02-17-2011 |
20110049701 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a substrate; a semiconductor chip mounted over the substrate; resin encapsulating the semiconductor chip; and a heat dissipation material that is arranged over the semiconductor chip and in contact with the resin, wherein the resin includes a first resin region made of a first resin composition, a second resin region made of a second resin composition, and a mixed layer that is formed between the first and second resin regions and obtained by mixing the first resin composition and the second resin composition. | 03-03-2011 |
20110062578 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip having a connection electrode on a surface side, and a resin substrate sealing a periphery of the semiconductor chip and formed to have a thickness from a back surface of the semiconductor chip to a lower side thereof, and the resin substrate whose lower surface is positioned to a lower side than the back surface of the semiconductor chip. A wiring layer is connected directly to the connection electrode of the semiconductor chip without the intervention of solder. | 03-17-2011 |
20110062579 | GROUP III NITRIDE BASED FLIP-CHIP INTEGRATED CIRCUIT AND METHOD FOR FABRICATING - A circuit substrate has one or more active components and a plurality of passive circuit elements on a first surface. An active semiconductor device has a substrate with layers of material and a plurality of terminals. The active semiconductor device is flip-chip mounted on the circuit substrate and at least one of the terminals of the device is electrically connected to an active component on the circuit substrate. The active components on the substrate and the flip-chip mounted active semiconductor device, in combination with passive circuit elements, form preamplifiers and an output amplifier respectively. In a power switching configuration, the circuit substrate has logic control circuits on a first surface. A semiconductor transistor flip-chip mounted on the circuit substrate is electrically connected to the control circuits on the first surface to thereby control the on and off switching of the flip-chip mounted device. | 03-17-2011 |
20110084379 | SEMICONDUCTOR DEVICE HAVING IMPROVED HEAT SINK - The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the second semiconductor element. The first heat sink is fixed to the first semiconductor element. The second heat sink is fixed to the second semiconductor element. The first heat sink is spaced apart from the second heat sink. | 04-14-2011 |
20110089558 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology capable of reducing the mounting burden on the part of a customer which is a recipient of a package. Over a metal board, a single package and another single package are mounted together via an insulation adhesion sheet, thereby to form one composite package. As a result, as compared with the case where six single packages are mounted, the number of packages to be mounted is smaller in the case where three sets of the composite packages are mounted. This can reduce the mounting burden on the part of a customer. | 04-21-2011 |
20110108978 | GRAPHENE NANOPLATELET METAL MATRIX - A metal matrix composite is disclosed that includes graphene nanoplatelets dispersed in a metal matrix. The composite provides for improved thermal conductivity. The composite may be formed into heat spreaders or other thermal management devices to provide improved cooling to electronic and electrical equipment and semiconductor devices. | 05-12-2011 |
20110133329 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The heat-release properties of semiconductor device are to be improved and the reliability thereof is to be improved. | 06-09-2011 |
20110147920 | APPARATUS AND METHOD FOR EMBEDDING COMPONENTS IN SMALL-FORM-FACTOR, SYSTEM-ON-PACKAGES - According to various aspects of the present disclosure, an apparatus is disclosed that includes a small form factor mobile platform including a system-on-package architecture, the system-on-package architecture arranged as a stack of layers including: a first layer having a first conformable material; a second layer having a second conformable material; a third layer having a third material; and one or more electronic components embedded within the stack of layers, wherein the first conformable material, the second conformable material, or both are configured to allow high frequency signal routing. | 06-23-2011 |
20110163439 | DIE BONDING A SEMICONDUCTOR DEVICE - A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon. | 07-07-2011 |
20110175218 | PACKAGE ASSEMBLY HAVING A SEMICONDUCTOR SUBSTRATE - Embodiments of the present disclosure provide a method that includes providing a semiconductor substrate comprising a semiconductor material, forming a dielectric layer on the semiconductor substrate, forming an interconnect layer on the dielectric layer, attaching a semiconductor die to the semiconductor substrate, and electrically coupling an active side of the semiconductor die to the interconnect layer, the interconnect layer to route electrical signals of the semiconductor die. Other embodiments may be described and/or claimed. | 07-21-2011 |
20110233756 | WAFER LEVEL PACKAGING WITH HEAT DISSIPATION - A heat dissipating wafer level package and method for manufacturing a heat dissipating wafer level package is provided. The heat dissipating wafer level package has a thermally conductive coating integrated thereon which facilitates the dissipation of heat from a device into the surrounding air and/or the thermal transfer of heat away from the device toward a heat spreader or heat sink. Additionally, the coating enhances the structural integrity and strength of the wafer during the manufacturing process as well as the resulting WLP. | 09-29-2011 |
20110233757 | Method for Facilitating the Stacking of Integrated Circuits Having Different Areas and an Integrated Circuit Package Constructed by the Method - An integrated circuit package comprises a package substrate, an application specific integrated circuit (ASIC) having a first area and formed on a first wafer made from a select semiconductor material, a second wafer of the select semiconductor material, and a supplemental-integrated circuit. The supplemental-integrated circuit has a second area different from the first area. The first wafer includes a through-wafer via to couple the ASIC to the package substrate. An active surface of the ASIC is coupled to the second wafer. The second wafer is arranged with a window there through that is sized to closely receive and align one or more bonding interfaces of the supplemental-integrated circuit to respective bonding interfaces of the ASIC. A corresponding method for assembling a die-stacked integrated circuit package is disclosed. | 09-29-2011 |
20110254149 | SEMICONDUCTOR COMPONENT AND MANUFACTURING METHOD OF SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor element that has a plurality of signals, a wiring board that is disposed below the semiconductor element and that draws the plurality of signals of the semiconductor element, a heat conduction member that dissipates heat generated by the semiconductor element, a joining member that is disposed between the semiconductor element and the heat conduction member and that joins the heat conduction member to the semiconductor element, a support member formed with an opening so as to surround the semiconductor element that supports the heat conduction member, a first adhesive member that is disposed between the support member and the wiring board to bond the support member with the wiring board and a second adhesive member that is disposed between the support member and the heat conduction member to bond the support member with the heat conduction member. | 10-20-2011 |
20110278715 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point. | 11-17-2011 |
20110291258 | HEAT RADIATION COMPONENT AND SEMICONDUCTOR PACKAGE INCLUDING SAME - A heat radiation component configured to be provided through a thermal interface material on a semiconductor device mounted on a board includes a first layer to be positioned on a first side and a second layer stacked on the first layer to be positioned on a second side farther from the semiconductor device than the first side. The coefficient of thermal expansion of the second layer is lower than the coefficient of thermal expansion of the first layer. | 12-01-2011 |
20110304039 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a first main surface and a second main surface; a stacked structure on which the semiconductor chip is disposed; and a cooling body on which the stacked structure is disposed. The stacked structure includes a first thermal conductor fixed to the cooling body, an insulator disposed on the first thermal conductor, and a second thermal conductor disposed on the insulator and having the semiconductor chip disposed thereon. The first main surface of the semiconductor chip opposite to the second main surface in contact with the stacked structure is sealed with an insulation material. At least a part of the first thermal conductor protrudes outwardly of the insulation material in plan view. | 12-15-2011 |
20120007229 | ENHANCED THERMAL MANAGEMENT OF 3-D STACKED DIE PACKAGING - A die stack package is provided and includes a substrate, a stack of computing components, at least one thermal plate, which is thermally communicative with the stack and a lid supported on the substrate to surround the stack and the at least one thermal plate to thereby define a first heat transfer path extending from one of the computing components to the lid via the at least one thermal plate and a fin coupled to a surface of the lid and the at least one thermal plate, and a second heat transfer path extending from the one of the computing components to the lid surface without passing through the at least one thermal plate. | 01-12-2012 |
20120012995 | Semiconductor device - A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K | 01-19-2012 |
20120012996 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device that can properly relax a stress produced by a difference in coefficient of linear expansion between an insulating substrate and a cooler and can properly remove heat by cooling of a semiconductor element. A semiconductor device comprises an insulating substrate, a semiconductor element provided on the insulating substrate, a cooler, and a porous metal plate provided between the insulating substrate and the cooler. Through holes in the porous metal plate are open at least to that surface of the porous metal plate which faces the cooler. The sectional size of the pores decreases gradually from the cooler side toward the insulating substrate side. | 01-19-2012 |
20120025367 | SEMICONDUCTOR DEVICE - A semiconductor device which includes a substrate, a semiconductor element arranged on the substrate, a heat dissipation component arranged on the semiconductor element, and a mold component covering an upper part of the substrate, the semiconductor element and the heat dissipation component, wherein an area of a surface on the semiconductor element of the heat dissipation component is larger than an area of a surface on which the heat dissipation component of the semiconductor element is arranged. | 02-02-2012 |
20120074561 | BACKMETAL REPLACEMENT FOR USE IN THE PACKAGING OF INTEGRATED CIRCUITS - One aspect of the invention pertains to an arrangement for forming exposed die packages. The arrangement includes a semiconductor wafer having multiple integrated circuit dice whose back surfaces cooperate to form the back surface of the wafer. A thermally conductive adhesive layer is deposited on the back surface of the wafer. The metal foil is attached to the wafer with the adhesive layer. Methods of forming exposed die packages using the above arrangement are also described. | 03-29-2012 |
20120104591 | Systems and methods for improved heat dissipation in semiconductor packages - Today's high speed semiconductor chips offer high performance at the expense of increase heat generation. A heat spreader can be build into a mold compound covering a semiconductor die in a semiconductor package by forming holes in the mold compound and filling the holes with a thermally conductive material such as thermally conductive adhesive. This heat dissipation capability can further be enhanced by a layer of thermally conductive material on the surface of the mold compound and optionally by an external metal layer or heat sink. | 05-03-2012 |
20120104592 | SEMICONDUCTOR MODULE HAVING A SEMICONDUCTOR CHIP STACK AND METHOD - A semiconductor module having a semiconductor chip stack and a method for producing the same is disclosed. In one embodiment, a thermally conductive layer with anisotropically thermally conductive particles is arranged between the semiconductor chips. The anisotropically thermally conductive particles have a lower thermal conductivity in a direction vertically with respect to the layer or the film than in a direction of the layer or the film. | 05-03-2012 |
20120112337 | Optoelectronic Component, and Method for the Production of an Optoelectronic Component - An optoelectronic component ( | 05-10-2012 |
20120112338 | HEAT DISSIPATING SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS - An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages. | 05-10-2012 |
20120119350 | Heat Sink Module - An improved heat sink module includes a main body and at least one diode. Mounting brackets, each having a through hole, extend from the outer periphery of the arcuate main body. A plurality of engaging holes are formed on the backside of the main body and each have at least one vent slot. To increase the heat dissipation area and yield rate of the main body, a plurality of upright, alternately arranged first and second fins are provided on the front side of the main body. The first fins extend between the inner and the outer peripheries of the main body, whereas the second fins extend from the outer periphery toward the inner periphery but are spaced therefrom. Each diode is peripherally provided with engaging ribs and has a wired end. The vent slots allow the at least one diode to be inserted into the engaging holes without difficulty. | 05-17-2012 |
20120139097 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package may include a circuit substrate, a semiconductor chip mounted on the circuit substrate, a chip package interaction disposed between the circuit substrate and the semiconductor chip, a first molding portion covering part of the semiconductor chip and part of the chip package interaction, a second molding portion formed on the first molding portion, and an adhesion portion adhering the first and second molding portions to each other, the adhesion portion being disposed between the first and second molding portions. | 06-07-2012 |
20120153453 | METALLIC THERMAL JOINT FOR HIGH POWER DENSITY CHIPS - A method for the assembly of a semiconductor package that includes cleaning a surface of a chip and a surface of a heat removal device by reverse sputtering is given. The method includes sequentially coating the surface of the chip and the surface of the heat removal device with an adhesive layer, a barrier layer, and a protective layer over a target joining area. The chip and the heat removal device are placed into carrier fixtures and preheated to a target temperature. Then a metallic thermal interface material (TIM) preform is mechanically rolled onto the surface of the chip and the first and the second carrier fixtures are attached together such that the metallic TIM layer on the surface of the chip is joined to the coated surface of the heat removal device through a fluxless process. The method includes heating the joined carrier fixtures in a reflow oven. | 06-21-2012 |
20120153454 | SEMICONDUCTOR DEVICE - A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters. | 06-21-2012 |
20120153455 | SEMICONDUCTOR DEVICE, COOLING DEVICE, AND COOILNG DEVICE FABRICATION METHOD - A semiconductor device includes a semiconductor chip having an electric circuit; and a cooling device including at least one channel serving as a flow path through which coolant flows, an external surface including projections, and a metallic layer formed over the external surface including the projections. In the semiconductor device, the projections of the external surface of the cooling device are brought into contact with a first surface of the semiconductor chip via the metallic layer such that the semiconductor chip is cooled by allowing the coolant to flow through the channel formed in the cooling device. | 06-21-2012 |
20120175766 | SYSTEM AND METHOD OF ACHIEVING MECHANICAL AND THERMAL STABILITY IN A MULTI-CHIP PACKAGE - A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package. | 07-12-2012 |
20120187556 | Thermal Interface Material with Epoxidized Nutshell Oil - A thermal interface material comprises an epoxy resin derived from nutshell oil or an epoxidized dimer fatty acid, or both, and fusible metal particles substantially devoid of added lead. Optionally, the TIM comprises a catalyst for the epoxy functionality. | 07-26-2012 |
20120241941 | Semiconductor Device and Method of Forming a Thermally Reinforced Semiconductor Die - A semiconductor device includes a substrate with conductive traces. A semiconductor die is mounted with an active surface oriented toward the substrate. An underfill material is deposited between the semiconductor die and substrate. A recess is formed in an interior portion of the semiconductor die that extends from a back surface of the semiconductor die opposite the active surface partially through the semiconductor die such that a peripheral portion of the back surface of the semiconductor die is offset with respect to a depth of the recess. A thermal interface material (TIM) is deposited over the semiconductor die and into the recess such that the TIM in the recess is laterally supported by the peripheral portion of the semiconductor die to reduce flow of the TIM away from the semiconductor die. A heat spreader including protrusions is mounted over the semiconductor die and contacts the TIM. | 09-27-2012 |
20120241942 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, and a heat conductive member composed of a solder material. The heat conductive member covers the semiconductor element, and is connected to a connection pad formed on the substrate. A heat radiator is disposed on the heat conductive member. The heat conductive member thermally connecting the semiconductor element to the heat radiator reduces the risk that electromagnetic noise may be emitted from or may be incident on the semiconductor element. | 09-27-2012 |
20120261811 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate, a metal pattern formed on the insulating substrate, a power terminal bonded onto the metal pattern, and a plurality of power chips bonded onto the metal pattern. The plurality of power chips are all separated from the power terminal by a distance sufficient to thermally isolate the plurality of power chips from the power terminal. | 10-18-2012 |
20120280382 | SEMICONDUCTOR PACKAGES - Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding. | 11-08-2012 |
20120280383 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME - A semiconductor device and a method of producing the same, wherein a joining member and a joined member are bonded by means of brazing in a way such that no voids are left inside the joining layer. The semiconductor device comprises a joined member and a joining member which is joined to the joined member by means of brazing. The joined member is provided with a through hole which is open on the joining surface with the joining member, and a path communicating with the through hole is provided on at least one of the joining surface of the joining member with the joined member or the joining surface of the member with the joining member. | 11-08-2012 |
20120299175 | SYSTEMS AND METHODS TO COOL SEMICONDUCTOR - Systems and methods are disclosed for fabricating a semiconductor device by forming heat conducting nanowires on a first side of a wafer; and depositing semiconductor structures on a second side of the wafer. | 11-29-2012 |
20120326295 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor chip having a switching function, a resin portion that covers the chip, terminals, and a heat dissipation portion. The resin portion includes first and second surfaces, which are opposed to each other and expand generally parallel to an imaginary plane; and a substrate is located on a first surface-side of the resin portion. The terminals project from the resin portion in a direction of the imaginary plane and are soldered onto the substrate. The heat dissipation portion is disposed on a second surface-side of the resin portion to release heat generated in the chip. One of the terminals is connected to the heat dissipation portion such that heat is transmitted from the one of the terminals to the heat dissipation portion. | 12-27-2012 |
20130020696 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point. | 01-24-2013 |
20130037931 | SEMICONDUCTOR PACKAGE WITH A HEAT SPREADER AND METHOD OF MAKING - An apparatus and method of forming a semiconductor package includes having and applying, respectively, a thermal interface material on a semiconductor die. The semiconductor die is included on a die assembly. The semiconductor die is installed in a heat spreader. The heat spreader is at least partially filled with mold compound and the semiconductor die is at least partially immersed in the mold compound once the die assembly is mounted on the heat spreader. The mold compound is then cured. | 02-14-2013 |
20130043581 | SEMICONDUCTOR DEVICE - A semiconductor device includes a wiring substrate, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip mounted on the wiring substrate. The second semiconductor chip generates less heat than the first semiconductor chip. A heat dissipation plate is arranged on the wiring substrate and partially at a higher location than the first and second semiconductor chips. The heat dissipation plate is connected to the first semiconductor chip and includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip. The upper surface of the second semiconductor chip is entirely exposed from the heat dissipation plate through the opening. | 02-21-2013 |
20130069218 | HIGH DENSITY PACKAGE INTERCONNECT WITH COPPER HEAT SPREADER AND METHOD OF MAKING THE SAME - The integrated circuit packaging techniques of the disclosed embodiments utilize a thermally conductive heat sink to partially enclose an integrated circuit. The heat sink is separated from the integrated circuit by a substrate that is conformally positioned into a recess in the heat sink, enabling the heat sink to transfer thermal energy from the integrated circuit. | 03-21-2013 |
20130082377 | INTEGRATED THREE-DIMENSIONAL MODULE HEAT EXCHANGER FOR POWER ELECTRONICS COOLING - Embodiments discussed herein are directed to a power semiconductor packaging that removes heat from a semiconductor package through one or more cooling zones that are located in a laterally oriented position with respect to the semiconductor package. Additional embodiments are directed to circuit elements that are constructed from one or more modular power semiconductor packages. | 04-04-2013 |
20130087905 | CURABLE ORGANOPOLYSILOXANE COMPOSITION AND SEMICONDUCTOR DEVICE - A curable organopolysiloxane composition in grease or paste form, which including: | 04-11-2013 |
20130093075 | Semiconductor Device Package and Method - An embodiment is a structure. The structure comprises a substrate, a chip, and a reinforcement component. The substrate has a first surface, and the first surface comprises depressions. The chip is over and attached to the first surface of the substrate. The reinforcement component is over a first area of the first surface of the substrate. The first area is not under the chip. The reinforcement component has a portion disposed in at least some of the depressions in the first area. | 04-18-2013 |
20130105964 | Semiconductor Device | 05-02-2013 |
20130127037 | SEMICONDUCTOR DEVICE BUILT-IN SUBSTRATE - An object of the present invention is to provide a semiconductor device built-in substrate, which can be made thin and can suppress occurrence of warpage. The present invention provides a semiconductor substrate which is featured by including a first semiconductor device serving as a substrate, a second semiconductor device placed on the circuit surface side of the first semiconductor device in the state where the circuit surfaces of the first and second semiconductor devices are placed to face in the same direction, and an insulating layer incorporating therein the second semiconductor device, and which is featured in that a heat dissipation layer is formed at least between the first semiconductor device and the second semiconductor device, and in that the heat dissipation layer is formed on the first semiconductor device so as to extend up to the outside of the second semiconductor device. | 05-23-2013 |
20130134575 | PACKAGED DIE FOR HEAT DISSIPATION AND METHOD THEREFOR - A heat spreader die holder that covers at least 50% of both major sides of a semiconductor die. The heat spreader die holder includes at least one opening. The heat spreader die holder is attached to a substrate. Electrically conductive structures of the die are electrically coupled to electrically conductive structures of the substrate. | 05-30-2013 |
20130147028 | HEAT SPREADER FOR MULTIPLE CHIP SYSTEMS - Various heat spreaders and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a heat spreader that has a surface adapted to establish thermal contact with a first semiconductor chip and a second semiconductor chip on a substrate. The surface includes a first portion adapted to thermally contact a solder-based thermal interface material and a second portion having an opening adapted to hold an organic thermal interface material. | 06-13-2013 |
20130154081 | SEMICONDUCTOR MODULE - A semiconductor module which includes a semiconductor device; a wiring member that is connected to the semiconductor device; a cooling plate that includes a first surface on a side of the semiconductor device and a second surface on a side opposite to the first surface and has a fastening portion at an end thereof in a first direction; and a molded portion that is formed by molding a resin on the semiconductor device, the wiring member and the cooling plate, wherein the fastening portion is exposed out of the molded portion, and a terminal portion of the wiring member is exposed out of the molded portion such that the terminal portion of the wiring member extends in a second direction which is substantially perpendicular to the first direction. | 06-20-2013 |
20130168844 | METAL INJECTION MOLDED HEAT DISSIPATION DEVICE - A heat dissipation device is provided. The heat dissipation device includes an integrated heat spreader and a base plate coupled to the integrated heat spreader, wherein the base plate comprises a plurality of metal pellets to dissipate heat from the integrated heat spreader. | 07-04-2013 |
20130168845 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor device, a first conductive member, a second conductive member, a cylinder, and a cover. The first conductive member is in contact with a first electrode of the semiconductor device. The second conductive member is in contact with a second electrode of the semiconductor device. The cylinder encompasses the semiconductor device and is fixed to the first conductive member, and a first thread groove is formed on the cylinder. A second thread groove is formed on the cover. The cover is fixed to the cylinder by an engagement of the second thread groove with the first thread groove. The semiconductor device and the second conductive member are fixed by being sandwiched between the first conductive member and the cover. The second conductive member includes a portion extending from inside to outside the cylinder by penetrating an outer peripheral wall of the cylinder. | 07-04-2013 |
20130200510 | SEMICONDUCTOR DEVICE, HEAT RADIATION MEMBER, AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device has a substrate having a front surface, and a rear surface including a fin forming region and a peripheral region surrounding the fin forming region. An insulating substrate is disposed on the front surface of the substrate. A semiconductor chip is disposed on the insulating substrate. A plurality of fins is formed in the fin forming region, and a reinforcing member is formed on the substrate through a bonding member, so as to overlap the peripheral region. | 08-08-2013 |
20130207255 | SEMICONDUCTOR DEVICE PACKAGE HAVING BACKSIDE CONTACT AND METHOD FOR MANUFACTURING - A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive. | 08-15-2013 |
20130207256 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. | 08-15-2013 |
20130221514 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME - Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase diffusion bonding. The fabrication method for this system is provided. The semiconductor device | 08-29-2013 |
20130228914 | Heat Sink Apparatus for Microelectronic Devices - One embodiment of the present invention is a heat sink apparatus for cooling a semiconductor device includes: (a) a rigid support ring having a top surface and a bottom surface; (b) a thermally conductive bottom sheet having a top and a bottom surface, wherein the top surface of the sheet is attached to the bottom surface of the rigid support ring; and (c) a channel for cooling fluid formed by a volume contained by the rigid support ring, the sheet, and an enclosure; wherein the sheet is held in tension by the rigid support ring, thereby reducing the macroscopic coefficient of thermal expansion (CTE) of the sheet. In use, thermally induced mechanical stress in a semiconductor device attached to the bottom surface of the sheet may be ameliorated by the reduction in macroscopic CTE, thereby increasing reliability of an assembly as it is cycled in temperature during normal operation. | 09-05-2013 |
20130241047 | POWER SEMICONDUCTOR MODULE AND POWER UNIT DEVICE - A power semiconductor module includes: a plurality of first metal plates arranged in the same planar state; a power semiconductor chip mounted on the first metal plate; and an overbridge-shaped second metal plate which is composed of bridge frame sections and leg sections that support the bridge frame sections, the leg sections being for appropriately performing solder bonding between electrodes of the power semiconductor chips and between the electrode of the power semiconductor chip and the first metal plate, the power semiconductor module being configured by a resin package in which these members are sealed with electrically insulating resin. In the power semiconductor module, the solder bonding section of the leg section is formed in a planar shape by bending process and is provided at a position lower than the bridge frame section. | 09-19-2013 |
20130256867 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed that includes an insulation substrate, a metal wiring layer, a semiconductor element, a heat sink, and a stress relaxation member located between the insulation substrate and the heat sink. The heat sink has a plurality of partitioning walls that extend in one direction and are arranged at intervals. The stress relaxation member includes a stress absorbing portion formed by through holes extending through the entire thickness of the stress relaxation member. Each hole is formed such that its dimension along the longitudinal direction of the partitioning walls is greater than its dimension along the arranging direction of the partitioning walls. | 10-03-2013 |
20130264701 | INTEGRATED COLD PLATE FOR ELECTRONICS - A cold plate has a base plate connected to a cover to form an enclosure, with an inlet and outlet nozzle penetrating the enclosure for coolant flow. The base plate includes a top surface opposite a bottom surface, Where the top surface includes enhancements positioned within the enclosure under the cover. The base plate has an inlet trough and an outlet trough that serve as headers, so the inlet nozzle connects to the inlet trough, and coolant from the inlet trough can flow through the enhanced surface, collect in the outlet trough, and then exit the cold plate through the outlet nozzle. The enhanced surface includes enhancements that begin at a point in between the bottom surface and the top surface, and the enhancements extend to a point above the top surface. | 10-10-2013 |
20130264702 | SEMICONDUCTOR UNIT - A semiconductor unit includes a cooler having a fluid flow space, an insulating substrate bonded to the cooler through a metal, a semiconductor device soldered to the insulating substrate, an intermediate member interposed between the insulating substrate and the fluid flow space and having a first surface where the insulating substrate is mounted, and a mold resin having a lower coefficient of liner expansion than the intermediate member. The insulating substrate, the semiconductor device and the cooler are molded by the mold resin. The intermediate member has a second surface that extends upward or downward relative to the first surface. The first surface is covered by the mold resin. The second surface is covered by a resin cover. | 10-10-2013 |
20130277820 | SEMICONDUCTOR DEVICE - A semiconductor device configured to enable efficient cooling of an element and downsizing of the device. The semiconductor device including an element unit connected to a surface of a cooler. A support member that has a condenser housing chamber that houses the condenser. The condenser has two parallel planar surfaces that are parallel with each other. The condenser housing chamber has a parallel opposing surface that is arranged in parallel with the element unit arrangement surface and faces the element unit arrangement surface, and houses the condenser in a state where the two parallel planar surfaces are arranged in parallel with the parallel opposing surface. The support member is fixed to the cooler in a state where the parallel opposing surface presses the element unit toward the cooler. | 10-24-2013 |
20130285234 | Power Module with Directly Attached Thermally Conductive Structures - A power module includes a substrate having an electrically insulative member with opposing first and second metallized sides and one or more semiconductor die attached to the first metallized side of the substrate. A plurality of thermally conductive structures are laterally spaced apart from one another and individually attached directly to the second metallized side of the substrate so that the plurality of thermally conductive structures extend outward from the second metallized side. | 10-31-2013 |
20130285235 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first heat spreader; a second heat spreader separated from the first heat spreader; a first semiconductor element on the first heat spreader and having a back face jointed to the first heat spreader; a second semiconductor element on the second heat spreader and having a back face jointed to the second heat spreader; a resin coating the first and second heat spreaders and the first and second semiconductor elements; and a reinforcing member provided across a region between the first and second heat spreaders in the resin, and having rigidity higher than rigidity of the resin. | 10-31-2013 |
20130299963 | PRODUCTION METHOD OF COOLER - The production method of a cooler includes a laminated material production step S | 11-14-2013 |
20130307136 | SHEET STRUCTURE, METHOD OF MANUFACTURING SHEET STRUCTURE, AND ELECTRONIC DEVICE - A sheet structure has: a bundle structure including a plurality of linear structures made of carbon which are oriented in a predetermined direction; a covering layer covering the plurality of linear structures made of carbon; and a filling layer provided between the plurality of linear structures made of carbon covered with the covering layer. The thickness of the covering layer is not uniform in a direction crossing the predetermined direction. | 11-21-2013 |
20130320518 | WAFER-LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME - A wafer-level package and a method of manufacturing the same. The wafer-level package includes a first semiconductor chip on an upper side of which an active surface facing downward is disposed, a redistribution formed on the active surface of the first semiconductor chip, a second semiconductor chip disposed on the redistribution using a flip-chip bonding (FCP) technique, a copper (Cu) post and a first solder ball sequentially disposed on the redistribution, a molding member formed on the active surface of the first semiconductor chip to expose a bottom surface of the first solder ball and an inactive surface of the second semiconductor chip, and a second solder ball disposed on the first solder ball and electrically connected to an external apparatus. | 12-05-2013 |
20130328184 | COMPOSITE MEMBER INCLUDING SUBSTRATE MADE OF COMPOSITE MATERIAL - A composite member has a substrate made of a composite material having SiC combined with magnesium or a magnesium alloy, and has a warpage degree of not less than 0.01×10 | 12-12-2013 |
20140001628 | AIR CAVITY PACKAGES HAVING HIGH THERMAL CONDUCTIVITY BASE PLATES AND METHODS OF MAKING | 01-02-2014 |
20140027899 | CONTROLLING THERMAL INTERFACE MATERIAL BLEED OUT - An extended preform of a thermal interface material (TIM) is formed between a heat spreader and a die on a substrate. The preform has an extension beyond a footprint of the die. The preform is cured. A bleed out of the TIM is controlled by the extension upon curing of the preform. | 01-30-2014 |
20140035123 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor element; a substrate; a metal plate; and a plurality of spherical particles. The substrate has the semiconductor element mounted thereon. The metal plate has one surface and the other surface that face each other, and the substrate is provided on the one surface. The plurality of spherical particles each has a spherical outer shape, and a part of the spherical outer shape is buried in the other surface of the metal plate. With such a configuration, there can be obtained a semiconductor device that allows promotion of heat dissipation from the semiconductor element, and a method for manufacturing the semiconductor device. | 02-06-2014 |
20140042610 | PACKAGE STRUCTURE AND THE METHOD TO FABRICATE THEREOF - The invention discloses a package structure with at least one portion of a first conductive element disposed in a through-opening of a first substrate. A conductive structure is disposed on the first substrate and the first conductive element, wherein the conductive structure is electrically connected to the first substrate and said at least one first I/O terminal of the first conductive element. The conductive structure comprises at least one of a second conductive element, a second substrate or a conductive pattern. | 02-13-2014 |
20140061893 | HYBRID THERMAL INTERFACE MATERIAL FOR IC PACKAGES WITH INTEGRATED HEAT SPREADER - Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM. | 03-06-2014 |
20140061894 | HEAT SPREADER FOR USE WITHIN A PACKAGED SEMICONDUCTOR DEVICE - A packaged semiconductor device, comprising a package substrate, an integrated circuit (IC) die mounted on the package substrate, and a heat spreader mounted on the package substrate. The heat spreader surrounds at least a portion of the IC die and includes a lid with a plurality of openings. An inner portion of the heat spreader includes a plurality of thermally conductive protrusions adjacent the die. | 03-06-2014 |
20140070399 | ELECTROCHEMICALLY DEPOSITED INDIUM COMPOSITES - Electrochemically deposited indium composites are disclosed. The indium composites include indium metal or an alloy of indium with one or more ceramic materials. The indium composites have high bulk thermal conductivities. Articles containing the indium composites also are disclosed. | 03-13-2014 |
20140077354 | SEMICONDUCTOR MODULE AND AN INVERTER MOUNTING SAID SEMICONDUCTOR MODULE - A semiconductor module has a first substrate and a second substrate placed opposite to the first substrate. A first semiconductor element is provided such that the high-heat main face of the first semiconductor faces the second substrate and is thermally connected to the second substrate via a wiring layer. A second semiconductor element is provided such that the high-heat main face of the second semiconductor faces the first substrate and is thermally connected to the first substrate via another wiring layer. The emitter electrode of the first semiconductor element and the collector electrode of the second semiconductor element are electrically connected to each other via a heat spreader. | 03-20-2014 |
20140084446 | SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DEVICES WITH THE SAME - A semiconductor package includes a substrate, a ground circuit supported by the substrate, at least one semiconductor chip disposed on the substrate and a carbon-containing heat-dissipating part disposed on the substrate and electrically connected to the ground circuit. The heat-dissipating part may include carbon fibers and/or carbon cloth. | 03-27-2014 |
20140091453 | COOLING DEVICE AND SEMICONDUCTOR DEVICE - A cooling device includes a base and a plurality of radiator fins. The base includes an exterior, an interior, an inlet, and an outlet. A heat generation element is connected to the exterior of the base. The radiator fins are located near the heat generation element in the interior of the base. The radiator fins are arranged from the inlet to the outlet. Each radiator fin has a sidewise cross-section with a dimension in a flow direction of the cooling medium and a dimension in a lateral direction orthogonal to the flow direction of the cooling medium. The dimension in the flow direction is longer than the dimension in the lateral direction. The radiator fins are separated from one another by a predetermined distance in the lateral direction. | 04-03-2014 |
20140097533 | Pop Package Structure - A package on package (PoP) package structure is disclosed, the structure includes at least two layers of carrier boards that are packaged and stacked in sequence, wherein chips are arranged on the bottom side of the carrier boards, a heat sink is arranged on the bottom side of a carrier board other than a layer-1 carrier board, a pad welded to a system board is arranged on the bottom side of the layer-1 carrier board, and a chip on a carrier board other than a top-layer carrier board is surface-mounted onto the heat sink adjacent to the chip. The heat sink increases the heat dissipation area of the chip, enhances the heat dissipation capabilities of the PoP stacked packages massively, breaks the bottleneck of the high-density integration and miniaturization of the PoP stacked packages, and enhances the packaging density of the PoP stacked packages. | 04-10-2014 |
20140124914 | SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD - A semiconductor packaging method is provided. The method includes providing a semiconductor substrate. The semiconductor substrate has a first surface and a second surface, and an electroplating seed layer on the first surface of the semiconductor substrate. The method also includes forming a plurality of columnar electrodes over the electroplating seed layer, where the columnar electrodes include first columnar electrodes and second columnar electrodes. Further, the method includes forming a diffusion barrier layer over the first columnar electrodes and the second columnar electrodes, forming a plurality of first solder balls over the diffusion barrier layer on the first columnar electrodes. The method also includes providing a packaging substrate having solder terminals corresponding to the first solder balls, and mounting the semiconductor substrate onto the packaging substrate in a flipped position, such that the first solder balls are connected with the solder terminals. | 05-08-2014 |
20140151870 | SEMICONDUCTOR PACKAGE INCLUDING A HEAT-SPREADING PART AND METHOD FOR ITS MANUFACTURE - A semiconductor package includes a substrate, a semiconductor chip attached to an upper surface of the substrate, a molding material configured to surround side surfaces of the semiconductor chip, and a heat-spreading part disposed on the semiconductor chip. The heat-spreading part includes a thermal conductive film and a heat slug that are integrated together. Also provided is a method for its manufacture. | 06-05-2014 |
20140151871 | HEAT SPREADER WITH FLEXIBLE TOLERANCE MECHANISM - A semiconductor device packaging system includes a substrate, a heat spreader, a stiffener attached to the substrate, and at least one die electrically coupled to the substrate and thermally coupled to the heat spreader. The semiconductor device packaging system further includes at least one stud coupled to one of the stiffener and the heat spreader and at least one orifice formed through one of the stiffener and the heat spreader. In addition, the at least one orifice is aligned with the at least one stud. | 06-05-2014 |
20140167244 | CHIP THERMAL DISSIPATION STRUCTURE - Disclosed is a chip thermal dissipation structure, employed in an electronic device comprising a first chip having a first chip face and a first chip back, comprising chip molding material, covering a lateral of the first chip; a first case, contacting the first chip back; a packaging substrate, connecting with the first chip face via first bumps; and a print circuit board, having a first surface and a second surface and connecting with the packaging substrate via solders. The chip thermal dissipation structure further comprises a second case, contacting the second surface. The thermal energy generated by the first chip is conducted toward the first case via the first chip back and toward the second case via the first chip face, the first bumps, the packaging substrate, the solders and the print circuit board. | 06-19-2014 |
20140167245 | SEMICONDUCTOR PACKAGE AND DISPLAY APPARATUS USING THE SAME - A semiconductor package includes a flexible base film having a first surface opposing a second surface, a semiconductor chip mounted on the first surface of the base film, and a touch sensing structure including at least one conductive pattern adjacent to the semiconductor chip. The at least one conductive pattern is disposed through the base film and has a surface exposed at the second surface of the base film. A contact condition of the semiconductor package is determined based on detection of a conductive path between the at least one conductive pattern and a conductive frame or support surface of the semiconductor package. The contact condition provides an indication of heat dissipation that may be expected to occur for the chip during operation. | 06-19-2014 |
20140167246 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point. | 06-19-2014 |
20140167247 | SEMICONDUCTOR DEVICE PACKAGE HAVING BACKSIDE CONTACT AND METHOD FOR MANUFACTURING - A method and apparatus for forming a backside contact, electrical and/or thermal, for die encapsulated in a semiconductor device package are provided. Die of varying thicknesses can be accommodated within the semiconductor device package. Embodiments of the present invention provide a conductive pedestal coupled to a backside contact of a die, where the coupling is performed prior to encapsulating the die within the package. In addition, conductive pedestals coupled to varying die within a semiconductor device package are of such a thickness that each conductive pedestal can be exposed on the back side of the package without exposing or damaging the backside of any encapsulated die. Embodiments of the present invention provide for the conductive pedestals being made of electrically or thermally conductive material and coupled to the device die contact using an electrically and/or thermally conductive adhesive. | 06-19-2014 |
20140175633 | THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH EMBEDDED CHIP AND INTERPOSER AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of making a thermally conductive semiconductor assembly. In accordance with a preferred embodiment, the method includes: providing a chip; providing an interposer that includes a through via, a first contact pad on a first surface and a second contact pad on an opposite second surface; electrically coupling the chip to the first contact pad of the interposer by a conductive bump or a wire; providing a heat sink with a cavity; then attaching the chip and the interposer on the heat sink using an adhesive with the chip inserted into the cavity; and then forming a build-up circuitry on the second surface of the interposer. Accordingly, the heat sink can provide essential thermal dissipation for the embedded chip, and the interposer and build-up circuitry can respectively provide first and second level fan-out routing/interconnection for the embedded chip. | 06-26-2014 |
20140191386 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer. | 07-10-2014 |
20140191387 | METHOD OF FABRICATING LAND GRID ARRAY SEMICONDUCTOR PACKAGE - A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board. | 07-10-2014 |
20140197533 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element. | 07-17-2014 |
20140203425 | HEAT DISSIPATING DEVICE - A heat dissipating device includes a semiconductor packaging structure having a stator set and a semiconductor element provided therein, a fan wheel set pivotally connected to the semiconductor packaging structure, and a guiding structure having a guiding channel. The guiding structure receives the semiconductor packaging structure and the fan wheel set. The fan wheel set includes a plurality of blades located above the surface of the semiconductor packaging structure. The stator set and the semiconductor element controls the first blades. The blades extend beyond side surfaces the semiconductor packaging structure and have their sizes increased, such that the airflow volume can be increased without changing the size of the semiconductor packaging structure. | 07-24-2014 |
20140210068 | HORIZONTALLY ALIGNED GRAPHITE NANOFIBERS IN ETCHED SILICON WAFER TROUGHS FOR ENHANCED THERMAL PERFORMANCE - The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip, and a heat removal device thermally connected to the thermal interface material pad. | 07-31-2014 |
20140210069 | CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - The present invention discloses a chip package and a manufacturing method thereof. The chip package includes: a semiconductor chip having an upper surface and a lower surface opposite to each other; a metal heat conductive layer formed on the lower surface, for conducting or absorbing heat generated by the semiconductor chip; and a bond pad formed on the upper surface, for electrically connecting to a circuit in the semiconductor chip. | 07-31-2014 |
20140210070 | Friction Stir Welding Structure and Power Semiconductor Device - A friction stir welding structure is comprised of a first and a second member integrated into one piece by friction stir welding, and in which a thin section is formed along the friction stir weld section on at least one of either of the first and the second member. | 07-31-2014 |
20140217573 | LOW COST AND HIGH PERFORMANCE FLIP CHIP PACKAGE - A low cost and high performance flip chip package is disclosed. By assembling the package using a substrate panel level process, a separate fabrication of a substrate is avoided, thus enabling the use of a coreless substrate. The coreless substrate may include multiple stacked layers of laminate dielectric films having conductive traces and vias. As a result, electrical connection routes may be provided directly from die contact pads to package contact pads without the use of conventional solder bumps, thus accommodating very high density semiconductor dies with small feature sizes. The disclosed flip chip package provides lower cost, higher electrical performance, and improved thermal dissipation compared to conventional fabricated substrates with solder bumped semiconductor dies. | 08-07-2014 |
20140231982 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A circuit assembly is disclosed which includes first and second substrates disposed on a heat dissipation base, and first and second semiconductor elements mounted on the first and second substrates. The first and second substrates are wired together, and three main electrode terminals are provided when the first and second semiconductor elements are connected in series, while two main electrode terminals are provided when the first and second semiconductor element are connected in parallel. In both cases, the circuit assembly is covered with a common exterior case so that one portion of each main electrode terminal or one portion of each main electrode terminal is exposed. Parts used in the circuit assembly are shared, and by changing the wiring between the first and second substrates, semiconductor modules with different functions are realized at low cost. | 08-21-2014 |
20140239482 | INTEGRATED HEAT SPREADER FOR MULTI-CHIP PACKAGES - An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive structures secured within the heat spreader frame openings. The thermally conductive structures can be formed to have various thicknesses which compensate for varying heights between at least two microelectronic devices in a multi-chip package. The thermally conductive structures can be secured in the heat spreader frame by sizing the openings and the thermally conductive structures such that the thermally conductive structures can be secured within the openings without requiring welding or adhesives. | 08-28-2014 |
20140239483 | HEAT SPREADING IN MOLDED SEMICONDUCTOR PACKAGES - A molded semiconductor package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, and one or more heat conductors in the molding compound that are thermally coupled to the substrate. Advantageously, the heat conductors are mounted in the molding compound near one or more of the corners of the die. The package may also include a lid. The heat conductors produce a more uniform distribution of heat in the substrate. The package is assembled by mounting the die on the substrate, mounting the heat conductors on the substrate and applying the molding compound to the substrate, the die, and the heat conductors mounted on the substrate. For packages that use a lid, the lid is then secured to the package and coupled to the heat conductors. | 08-28-2014 |
20140239484 | METHOD FOR FORMING SINTERED SILVER COATING FILM, BAKING APPARATUS, AND SEMICONDUCTOR DEVICE - In a method for forming a sintered silver coating film, for use as a heat spreader, on a semiconductor substrate or a semiconductor package, a coating film of an ink or paste containing silver nanoparticles is formed on one surface of the semiconductor substrate or the substrate package. Further, the coating film is sintered by heating the coating film under an atmosphere of a humidity of 30% to 50% RH (30° C.) by a ventilation oven. | 08-28-2014 |
20140239485 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 08-28-2014 |
20140246770 | COPPER NANOROD-BASED THERMAL INTERFACE MATERIAL (TIM) - A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters. | 09-04-2014 |
20140252586 | SEMICONDUCTOR DEVICES THAT INCLUDE A DIE BONDED TO A SUBSTRATE WITH A GOLD INTERFACE LAYER - Embodiments of a semiconductor device include a primary portion of a substrate, a die, and a die attach layer between the die and the primary portion of the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon. | 09-11-2014 |
20140252587 | SEMICONDUCTOR DEVICE, AND ON-BOARD POWER CONVERSION DEVICE - Provided is a semiconductor device capable of improving heat-radiating performance of a heating element. The semiconductor device of the present invention includes: a heating element ( | 09-11-2014 |
20140264816 | SEMICONDUCTOR PACKAGE STRUCTURE - Various embodiments relating to semiconductor package structures having reduced thickness while maintaining rigidity are provided. In one embodiment, a semiconductor package structure includes a substrate including a surface, a semiconductor die including a first interface surface connected to the surface of the substrate and a second interface surface opposing the first interface surface, a mold compound applied to the substrate surrounding the semiconductor die. The second interface surface of the semiconductor die is exposed from the mold compound. The semiconductor package structure includes a heat dissipation cover attached to the second interface surface of the semiconductor die and the mold compound. | 09-18-2014 |
20140264817 | Semiconductor Device and Method of Using Partial Wafer Singulation for Improved Wafer Level Embedded System in Package - A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die. | 09-18-2014 |
20140264818 | POLYMER THERMAL INTERFACE MATERIAL HAVING ENHANCED THERMAL CONDUCTIVITY - A polymer thermal interface material is described that has enhanced thermal conductivity. In one example, a vinyl-terminated silicone oil is combined with a silicone chain extender, and a thermally conductive filler comprising at least 85% by weight of the material, and comprising surface wetted particles with a range of shapes and sizes. The material may be used for bonding components inside a microelectronic package, for example. | 09-18-2014 |
20140264819 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a link portion that connects a second heat sink to a third heat sink via a solder. The solder is arranged on a connecting surface of a base portion of the link portion, which is orthogonal to a plate thickness direction of the base portion, in a direction perpendicular to first and second surfaces. The link portion has a rib that protrudes from the base portion in a direction orthogonal to the first and second surfaces, and a thickness of a portion where the rib is provided is equal to or less than the thickness of the corresponding heat sink. The rib is provided across an entire length of a first region that is sealed by a sealing resin body and that is between the second and the third heat sinks, in an alignment direction of a first heat sink and the third heat sink. | 09-18-2014 |
20140284786 | SEMICONDUCTOR DEVICE - An aspect of the present embodiment, there is provided a semiconductor device, including an insulating substrate, at least one semiconductor chip provided above the insulating substrate, a wiring terminal including a connection portion electrically connected to the semiconductor chip, a surrounding frame surrounding the semiconductor chip and the connection portion, an embedded material provided in the surrounding frame covering the semiconductor chip and the connection portion, and a pressing unit provided on a surface of the embedded material. | 09-25-2014 |
20140291831 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes a metallic plate, a bonding layer, a semiconductor chip, and a resin molding. The semiconductor chip is fixed to the metallic plate with the bonding layer. The resin molding is in contact with the metallic plate, and covers the semiconductor chip. In the semiconductor device, a dent is provided in the metallic plate so that the dent is located next to an edge of a fillet of the bonding layer, in a plan view of the metallic plate. | 10-02-2014 |
20140299981 | High Power Single-Die Semiconductor Package - A semiconductor package includes a single semiconductor die and an electrically and thermally conductive base. The single semiconductor die includes a semiconductor body having opposing first and second surfaces and insulated sides between the first and second surfaces. The single semiconductor die further includes a first electrode at the first surface and a second electrode at the second surface. The single semiconductor die has a defined thickness measured between the first and second surfaces, a defined width measured along one of the insulated sides, and a defined length measured along another one of the insulated sides. The base is attached to the second electrode at the second surface of the single semiconductor die and has the same length and width as the single semiconductor die. | 10-09-2014 |
20140299982 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a package | 10-09-2014 |
20140312485 | SEMICONDUCTOR MODULE SYSTEM, SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR MOUNTING A SEMICONDUCTOR MODULE ON A HEAT SINK - A semiconductor module system has a semiconductor module and a protective cover. The semiconductor module has a bottom side with a heat dissipation surface and a top side opposite the bottom side, the top side being separated from the bottom side in a vertical direction. The protective cover can be mounted irreleasably on the semiconductor module in such a way that, in a mounted state, the top side is exposed and the protective cover covers the heat dissipation surface. By virtue of the protective cover, a thermal interface material applied onto the heat dissipation surface can be protected. | 10-23-2014 |
20140319671 | SEMICONDUCTOR DEVICE AND GRINDING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, and a grinding-processed layer laminated on one surface of the semiconductor chip. Further, the semiconductor device includes a sealing resin that seals the semiconductor chip and the grinding-processed layer; and a metal remaining-thickness checking portion provided adjacent to the grinding-processed layer, sealed by the sealing resin, and having a inclined plane that is inclined with respect to a laminating direction of the grinding-processed layer. | 10-30-2014 |
20140319672 | FLOW CHANNEL MEMBER, HEAT EXCHANGER USING SAME, SEMICONDUCTOR DEVICE, AND DEVICE FOR MANUFACTURING SEMICONDUCTOR - Channel members | 10-30-2014 |
20140319673 | SEMICONDUCTOR DEVICE - In a semiconductor device in which a semiconductor chip is cooled by a cooler, an insulating member between a semiconductor chip and a cooler is omitted in order to simplify the configuration. A cooler ( | 10-30-2014 |
20140327127 | Power module with cooling structure on bonding substrate for cooling an attached semiconductor chip - According to an exemplary embodiment, a power module is provided which comprises a semiconductor chip, a bonding substrate comprising an electrically conductive sheet and an electric insulator sheet which is directly attached to the electrically conductive sheet and which is thermally coupled to the semiconductor chip, and an array of cooling structures directly attached to the electrically conductive sheet and configured for removing heat from the semiconductor chip when interacting with cooling fluid. | 11-06-2014 |
20140332948 | THERMAL MANAGEMENT IN 2.5 D SEMICONDUCTOR PACKAGING - Lower semiconductor dies in 2.5 D semiconductor packaging configurations can be cooled by thermally coupling the lower semiconductor dies to a heat sink positioned above the interposer, to an upper semiconductor die, to a heat sink affixed beneath a substrate, or to free-flowing air circulating above the interposer or beneath the substrate. The thermal coupling can be achieved using heat pipes, thermal vias, or other conductive passage ways. | 11-13-2014 |
20140332949 | METHOD FOR CREATING A SELECTIVE SOLDER SEAL INTERFACE FOR AN INTEGRATED CIRCUIT COOLING SYSTEM - A method for forming cooling channels in an interface for soldering to a semiconductor structure. The method includes: forming a metal seed layer on a surface of a substrate; patterning the metal seed layer into a patterned, plating seed layer covering portions of the substrate and exposing other portions of the substrate; using the patterned plating seed layer to form channels through the exposed portions of the substrate; and plating the patterned plating seed layer with solder. A heat exchanger haying cooling channels therein is affixed to one surface of the interface and the semiconductor structure is soldered to an opposite surface of the interface. The cooling channels of the heat exchanger are aligned with the channels in the interface. | 11-13-2014 |
20140332950 | SEMICONDUCTOR DEVICE - A semiconductor device includes a cooling portion, which is made of ceramic or resin and includes a mounting surface, a metal circuit board, which is mounted on the mounting surface of the cooling portion and includes an element mounting surface, and a semiconductor element mounted on the element mounting surface of the circuit board. At least a part of the circuit board, which corresponds to the element mounting surface, is covered with resin with respect to the cooling portion. | 11-13-2014 |
20140332951 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate with a conductive pattern including an insulating substrate, a conductive pattern formed on a front surface of the insulating substrate, and a rear heat-sink formed on a back surface of the insulating substrate; a semiconductor chip joined on the conductive pattern through joining material, and leading terminals; and a mold resin exposing a surface of the rear heat-sink and end portions of the leading terminals, and sealing a front surface of the insulating substrate with the conductive pattern, a back surface of the insulating substrate with the conductive pattern, the semiconductor chip, the rear heat-sink excluding the exposed surface thereof, and the leading terminals excluding the end portions thereof. Each of side surfaces of the conductive pattern and the rear heat-sink is formed with a recessed groove, and the recessed grooves are filled with the mold resin. | 11-13-2014 |
20140346660 | POWER ELECTRONICS DEVICES HAVING THERMAL STRESS REDUCTION ELEMENTS - Power electronics devices having thermal stress reduction elements are disclosed. A power electronics device includes a heat source having a heat source perimeter, a first conduction member coupled to the heat source, and a substrate coupled to the first conduction member. The first conduction member includes a support portion that extends to at least the heat source perimeter and a plurality of finger portions extending from the support portion and separated from one another by web regions, where the plurality of finger portions have a finger thickness that is greater than a web thickness of the web regions. | 11-27-2014 |
20140353813 | SEMICONDUCTOR PACKAGE HAVING A SYSTEM-IN-PACKAGE STRUCTURE - A semiconductor package includes a substrate. A lower semiconductor chip is disposed above the substrate. An upper semiconductor chip is disposed on the lower semiconductor chip. A top surface of the lower semiconductor chip at an end of the lower semiconductor chip is exposed. A heat slug disposed above the upper semiconductor chip. A molding layer is disposed between the substrate and the heat slug. The molding layer is configured to seal the lower semiconductor chip and the upper semiconductor chip. An upper spacer is disposed between the lower semiconductor chip and the heat slug. The upper spacer is disposed on the exposed surface of the lower semiconductor chip. | 12-04-2014 |
20140353814 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device incorporating a heat spreader and improved to inhibit dielectric breakdown is provided. The semiconductor device has an electrically conductive heat spreader having a bottom surface, a sheet member having a front surface and a back surface electrically insulated from each other, IGBTs and diodes fixed on the heat spreader and electrically connected thereto, and a molding resin. The front surface contacts with the bottom surface and has a peripheral portion jutting out from edges thereof. The molding resin encapsulates the front surface of the sheet member, the heat spreader and the semiconductor elements. At least part of the back surface of the sheet member is exposed out of the molding resin. The heat spreader has, at a corner of its bottom surface, corner portions having a beveled shape or a curved-surface shape as seen in plan and having a rectangular shape as seen in section. | 12-04-2014 |
20140353815 | SEMICONDUCTOR DIE ASSEMBLIES AND SEMICONDUCTOR DEVICES INCLUDING SAME - Methods of fabricating multi-die assemblies including a wafer segment having no integrated circuitry thereon and having a plurality of vertically stacked dice thereon electrically interconnected by conductive through vias, resulting multi-die assemblies, and semiconductor devices comprising such multi-die assemblies. The wafer segment may function as a heat sink to enhance heat transfer from the stacked dice in the resulting multi-die assembly. The die stacks are fabricated at the wafer level on a base wafer, from which the wafer segment and die stacks are singulated after at least peripheral encapsulation. | 12-04-2014 |
20140367844 | UNDERFILL-ACCOMMODATING HEAT SPREADERS AND RELATED SEMICONDUCTOR DEVICE ASSEMBLIES AND METHODS - Heat spreaders for dissipating heat from semiconductor devices comprise a contact surface located within a recess on an underside of the heat spreader, the contact surface being configured to physically and thermally attach to a semiconductor device, and a trench extending into the heat spreader adjacent to the contact surface sized and configured to receive underfill material extending from the semiconductor device into the trench. Related semiconductor device assemblies may include these heat spreader and methods may include physically and thermally attaching these heat spreaders to semiconductor devices such that underfill material extends from a semiconductor device into the trench. | 12-18-2014 |
20140367845 | SEMICONDUCTOR DEVICE - Stress relief layers are each provided on each circuit on an insulating substrate in a semiconductor module; a metal base coming into contact with the semiconductor module is divided into a thinned and low stiffened first metal base and a thickened and high stiffened second metal base; and the semiconductor module is bonded to the first metal base and then the first and the second metal bases are bonded to be integrated. | 12-18-2014 |
20140374896 | SEMICONDUCTOR DEVICE, METHOD FOR INSTALLING HEAT DISSIPATION MEMBER TO SEMICONDUCTOR DEVICE, AND A METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device is fastened to a heat dissipation member such that a force directed downward acts from a metal substrate onto the heat dissipation member, with a rim portion of a storage region as a fulcrum with respect to the heat dissipation member. As a result, a heat conductive material can be spread into a thinner layer between the metal substrate and the heat dissipation member, improving the heat dissipation between the metal substrate and the heat dissipation member. | 12-25-2014 |
20150021754 | Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management - A semiconductor device has a first semiconductor die and an encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and encapsulant. A thermal interface material is formed over the first semiconductor die and encapsulant. A stiffening layer is formed over the first semiconductor die and an edge portion of the encapsulant. Alternatively, an insulating layer is formed adjacent to the first semiconductor die and a stiffening layer is formed over the insulating layer. The stiffening layer includes metal, ferrite, ceramic, or semiconductor material. A heat spreader is disposed over the first semiconductor die and a central portion of the encapsulant. Openings are formed in the heat spreader. A recess is formed in the heat spreader along an edge of the heat spreader. A coefficient of thermal expansion (CTE) of the stiffening layer is less than a CTE of the heat spreader. | 01-22-2015 |
20150035134 | 3DIC PACKAGES WITH HEAT DISSIPATION STRUCTURES - A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion not overlapped by the first die. A first Thermal Interface Material (TIM) is over and contacting a top surface of the first die. A heat dissipating lid has a first bottom surface contacting the first TIM. A second TIM is over and contacting the second portion of the second die. A heat dissipating ring is over and contacting the second TIM. | 02-05-2015 |
20150035135 | 3DIC Packages with Heat Sinks Attached to Heat Dissipating Rings - A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending beyond edges of the first die. A first Thermal Interface Material (TIM) is overlying and contacting a top surface of the first die. A heat sink has a first bottom surface over and contacting the first TIM. A second TIM is overlying and contacting the second portion of the second die. A heat dissipating ring is overlying and contacting the second TIM. | 02-05-2015 |
20150035136 | SEMICONDUCTOR DEVICE TO BE ATTACHED TO HEAT RADIATION MEMBER - A semiconductor device includes a semiconductor module and a pressing member pressing the semiconductor module to a heat radiation member. The semiconductor module includes heat generation elements generating heat by energization, three or more conductive members each of which mounted with at least one of the heat generation elements, and a molding part integrally molding the heat generation elements and the conductive members. The semiconductor module has a heat radiation possible region in which a forcing pressure by the pressing member is equal to or greater than a predetermined pressure. The conductive member mounted with the heat generation element disposed outside the heat radiation possible region has such a shape that at least a part of the conductive member is included in the heat radiation possible region. | 02-05-2015 |
20150035137 | SOLDER JOINT STRUCTURE, POWER MODULE, POWER MODULE SUBSTRATE WITH HEAT SINK AND METHOD OF MANUFACTURING THE SAME, AND PASTE FOR FORMING SOLDER BASE LAYER - There are provided a solder joint structure, a power module using the joint structure, a power module substrate with a heat sink and a method of manufacturing the same, as well as a solder base layer forming paste which is disposed and fired on a metal member to thereby react with an oxide film generated on the surface of the metal member and form the solder base layer on the metal member, capable of suppressing the occurrence of waviness and wrinkles on the surface of the metal member even at the time of loading the power cycle and heat cycle and improving the joint reliability with a joint member. | 02-05-2015 |
20150035138 | SEMICONDUCTOR DEVICE - A circuit pattern is bonded to a top surface of a ceramic substrate. A cooling body is bonded to an undersurface of the ceramic substrate. An IGBT and a FWD are provided on the circuit pattern. A coating film covers a junction between the ceramic substrate and the circuit pattern, and a junction between the ceramic substrate and the cooling body. A mold resin seals the ceramic substrate, the circuit pattern, the IGBT, the FWD, the cooling body, and the coating film etc. The ceramic substrate has higher thermal conductivity than the coating film. The coating film has lower hardness than the mold resin and alleviates stress applied from the mold resin to the ceramic substrate. The circuit pattern and the cooling body includes a groove contacting the mold resin without being covered with the coating film. | 02-05-2015 |
20150048493 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor package includes a circuit substrate, a plurality of semiconductor chips stacked on the circuit substrate, insulating adhesive patterns interposed between the semiconductor chips, a heat slug provided on an uppermost semiconductor chip and adhered to the uppermost semiconductor chip by a heat dissipative adhesive pattern, and a mold structure provided on the circuit substrate to cover sidewalls of the semiconductor chips, the insulating adhesive patterns, the heat dissipative adhesive pattern and the heat slug. A failure of the semiconductor package during a manufacturing process of the mold structure may be reduced. The semiconductor package may therefore have good operating characteristics and reliability. | 02-19-2015 |
20150061108 | Packaged Semiconductor Device - A packaged semiconductor device includes a semiconductor component, first and second heat dissipation means disposed between the semiconductor component and the first and second main faces, respectively, encapsulated by an encapsulant, the shape of the packaged semiconductor device being non-rectangular cuboid. | 03-05-2015 |
20150061109 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a semiconductor chip and connection terminals, a cooling fin to which the semiconductor element is fixed, and an external cooling body having a passage for cooling medium, the cooling fin being fixed to the external cooling body. The semiconductor element has a protruding cooling block that is inserted and fixed to the cooling fin, which in turn is fixed to the external cooling body such that the cooling fin is in contact with the cooling medium. | 03-05-2015 |
20150069596 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion. | 03-12-2015 |
20150069597 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers. | 03-12-2015 |
20150076685 | FLOW PATH MEMBER, AND HEAT EXCHANGER AND SEMICONDUCTOR DEVICE USING THE SAME - Provided are a flow path member that suppresses flow path breakage, a heat exchanger and a semiconductor device using the same. This flow path member has a flow path in which a fluid flows and which is constituted by a lid portion, a partition wall portion, a side wall portion and a bottom plate portion. At least one of the partition wall portion and the sidewall portion is partly embedded in at least one of the lid portion and the bottom plate portion for direct connection. | 03-19-2015 |
20150091154 | SUBSTRATELESS PACKAGES WITH SCRIBE DISPOSED ON HEAT SPREADER - Disclosed is a substrateless semiconductor package having a plurality of scribe lines formed on a heat spreader, primarily comprising the heat spreader, a chip disposed on the heat spreader and an encapsulant. Formed on a thermally dissipating surface of the heat spreader are a plurality of scribe line grooves with a plurality of openings formed inside to penetrate through the die-attaching surface of the heat spreader. The chip is disposed on the die-attaching surface and the encapsulant is formed on the die-attaching surface to encapsulate a first surface of the chip on which a plurality of external pads are formed Without being covered by the encapsulant. Therein, the encapsulant is filled in the scribe line grooves via the openings so that a scribe line pattern exposed from the thermally dissipating surface is formed. | 04-02-2015 |
20150091155 | Chip Embedded Package Method and Structure - A chip embedded package method is provided by an embodiment of the present invention. The method comprises: etching metallic sinks on the thicker metal layer of each organic substrate; part of metallic sinks is used for packaging at least one chip, and other metallic sinks are used for via-holes; mounting the at least one chip into a metallic sink of each organic substrate via adhesive; flipping one organic substrate on another to form a combination; drilling blind-holes on both sides of the combination of the two organic substrates to pass through the adhesive; drilling via-holes to get through the combination of the two organic substrates, wherein the via-holes locates beyond the metallic sinks with chips; filling the blind-holes and via-holes with conductive medium through an electroplating process. | 04-02-2015 |
20150108628 | Packages with Thermal Interface Material on the Sidewalls of Stacked Dies - A package includes a die stack that includes at least two stacked dies, and a Thermal Interface Material (TIM). The TIM includes a top portion over and contacting a top surface of the die stack, and a sidewall portion extending from the top portion down to lower than at least one of the at least two stacked dies. A first metallic heat-dissipating feature is over and contacting the top portion of TIM. A second metallic heat-dissipating feature has a sidewall contacting a sidewall of the sidewall portion of the TIM. | 04-23-2015 |
20150108629 | SEMICONDUCTOR DEVICE - A cooling fin | 04-23-2015 |
20150115431 | THERMAL ENERGY DISSIPATION USING BACKSIDE THERMOELECTRIC DEVICES - Embodiments of the present invention provide a semiconductor structure and method to dissipate heat generated by semiconductor devices by utilizing backside thermoelectric devices. In certain embodiments, the semiconductor structure comprises an electronic device formed on a first side of the semiconductor structure. The semiconductor structure also comprises a thermoelectric cooling device formed on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. In other embodiments, the method comprises forming an electronic device on a first side of a semiconductor structure. The method also comprises forming a thermoelectric cooling device on a second side of the semiconductor structure in close proximity to a region of the semiconductor structure where heat dissipation is desired, wherein the thermoelectric cooling device includes a Peltier junction. | 04-30-2015 |
20150115432 | SEMICONDUCTOR DEVICE PACKAGES USING A THERMALLY ENHANCED CONDUCTIVE MOLDING COMPOUND - A heat transportation mechanism that is thermally conductive, but not electrically conductive, is provided so as to permit transportation of heat generated by a semiconductor device die to the exterior of a semiconductor device package. Embodiments can use a thermally conductive polymer structure, added to the package mold compound, to transport heat through the mold compound. The thermally conductive polymer structure can be fixed to the semiconductor device die prior to molding or can be included in an overmolding compound slug prior to performing the overmolding process. Flexibility of placement of the thermally conductive polymer structure is provided by using dielectric compounds. | 04-30-2015 |
20150115433 | SEMICONDUCOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of making a semiconductor device having a chip embedded in a heat spreader and electrically connected to a hybrid substrate. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a heat spreader using an adhesive with the chip inserted into a cavity of the heat spreader. The heat spreader provides thermal dissipation and the interposer provides a CTE-matched interface and primary fan-out routing for the chip. | 04-30-2015 |
20150115434 | EMBEDDED HEAT SPREADER FOR PACKAGE WITH MULTIPLE MICROELECTRONIC ELEMENTS AND FACE-DOWN CONNECTION - A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate. | 04-30-2015 |
20150130045 | THERMALLY CONDUCTIVE STRUCTURE FOR HEAT DISSIPATION IN SEMICONDUCTOR PACKAGES - A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip. | 05-14-2015 |
20150130046 | SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip. | 05-14-2015 |
20150137343 | ENHANCED DIE-UP BALL GRID ARRAY AND METHOD FOR MAKING THE SAME - Methods of assembling a ball grid array (BGA) package is provided. One method includes providing a tape substrate that has a first surface and a second surface, attaching a first surface of a stiffener to the first substrate surface, mounting an IC die to the second stiffener surface, mounting a heat spreader to the IC die, and attaching a plurality of solder balls to the second substrate surface. | 05-21-2015 |
20150137344 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device has a circuit board including an insulation layer, a wiring layer formed on one surface of the insulation layer, and a buffer layer formed on the other surface of the insulation layer, a semiconductor element bonded to the wiring layer, a radiator member bonded to the buffer layer of the circuit board, and a resin member to seal the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board. A method for manufacturing the semiconductor device includes bonding the buffer layer of the circuit board to the radiator member, bonding the semiconductor element to the wiring layer of the circuit board, and sealing the semiconductor element and an entire surface of the circuit board including an outer peripheral surface of the buffer layer in the circuit board with resin after the two bonding steps. | 05-21-2015 |
20150145115 | EMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a carrier, a die including a first surface and a second surface, a plurality of first conductive bumps disposed between the second surface of the carrier and the die, wherein the die is flip bonded on the carrier, and a molding disposed over the carrier and surrounding the die, wherein the molding includes a recessed portion disposed on the first surface of the die thereby leaving a portion of the first surface is uncovered by the molding. Further, a method of manufacturing a semiconductor device includes providing a carrier, flip bonding a die on the carrier, disposing a rubber material on a first surface of the die and within the first surface of the die, and forming a molding surrounding the rubber material and covering the carrier. | 05-28-2015 |
20150145116 | DIE STACKS WITH ONE OR MORE BOND VIA ARRAYS - An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die. | 05-28-2015 |
20150145117 | ENHANCED STACKED MICROELECTRONIC ASSEMBLIES WITH CENTRAL CONTACTS AND IMPROVED THERMAL CHARACTERISTICS - A microelectronic assembly includes a dielectric element having oppositely-facing first and second surfaces and one or more apertures extending between the surfaces, the dielectric element further having conductive elements thereon; a first microelectronic element having a rear surface and a front surface facing the first surface of the dielectric element, the first microelectronic element having a first edge and a plurality of contacts exposed at the front surface thereof; a second microelectronic element including having a rear surface and a front surface facing the rear surface of the first microelectronic element, a projecting portion of the front surface of the second microelectronic element extending beyond the first edge of the first microelectronic element, the projecting portion being spaced from the first surface of the dielectric element, the second microelectronic element having a plurality of contacts exposed at the projecting portion of the front surface; leads extending from contacts of the microelectronic elements through the at least one aperture to at least some of the conductive elements; and a heat spreader thermally coupled to at least one of the first microelectronic element or the second microelectronic element. | 05-28-2015 |
20150303127 | Chip-Scale Packaging With Protective Heat Spreader - A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can be attached to the die and have a holder surface opposite the first die surface. A heat spreader can be configured to cover the second die surface and the packaging surface and can be attached thereto by a layer of adhesive positioned between the heat spreader and the semiconductor die. A semiconductor package array can include an array of semiconductor dies and a heat spreader configured to cover each semiconductor die. A conductive lead can be electrically connected to the integrated circuit in a semiconductor die and can extend from the first die surface. Manufacturing a semiconductor package can include applying thermally conductive adhesive to the heat spreader and placing the heat spreader proximate the semiconductor die. | 10-22-2015 |
20150303174 | Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same - An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. | 10-22-2015 |
20150311136 | HEAT SINK HAVING A RESTRICTIVE REGION - A semiconductor structure includes a heat sink. The heat sink having a first major surface, a second major surface, a first sidewall surface, and a through-opening extending from one of the first sidewall surface or the first major surface of the heat sink to the second surface of the heat sink, and wherein the through-opening has an inflow region, a restrictive region, and an outflow region. The restrictive region is located between the inflow region and the outflow region, wherein the inflow region has an inflow surface opening at the one of the first sidewall or the first major surface, and the outflow region has an outflow surface opening at the second major surface. A cross-sectional area of the restrictive region is less than an area of the inflow surface opening and less than an area of the outflow surface opening. | 10-29-2015 |
20150311137 | Chip Level Heat Dissipation Using Silicon - A semiconductor device that includes a semiconductor chip having a first silicon substrate with opposing first and second surfaces, a semiconductor device formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the semiconductor device, a layer of thermal conductive material on the second surface, and a plurality of first vias formed partially through the layer of thermal conductive material. | 10-29-2015 |
20150325495 | ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND SUBSTRATE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a silicon substrate that includes a heat release mechanism formed on a rear surface thereof; and an element layer that includes a transistor element and is formed on a front surface of the silicon substrate, the heat release mechanism including: a carbon material being a high heat-conducting material such as a CNT that is higher in heat conductivity than the silicon substrate and is formed in a plurality of first holes formed in the rear surface of the silicon substrate; and a carbon material being a heat-conductive film such as a multilayer graphene film that is thermally connected to the CNT in a manner to cover a rear surface side of the silicon substrate. This configuration provides a carbon material-embedded silicon substrate realizing very efficient heat release with a relatively simple configuration to obtain a highly-reliable electronic device. | 11-12-2015 |
20150348865 | MICROELECTRONIC PACKAGES HAVING SIDEWALL-DEPOSITED HEAT SPREADER STRUCTURES AND METHODS FOR THE FABRICATION THEREOF - Microelectronic packages and methods for producing microelectronic packages having sidewall-deposited heat spreader structures are provided. In one embodiment, the method includes providing a package body containing a microelectronic device. A heat spreader structure is printed or otherwise formed over at least one sidewall of the package body. The heat spreader structure is thermally coupled to the microelectronic device and is configured to dissipate heat generated thereby during operation of the microelectronic package. | 12-03-2015 |
20150348928 | WIRE BOND SUPPORT STRUCTURE AND MICROELECTRONIC PACKAGE INCLUDING WIRE BONDS THEREFROM - A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases. | 12-03-2015 |
20150348954 | INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. | 12-03-2015 |
20150357255 | 3D Packages and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure. | 12-10-2015 |
20150357261 | HEAT CONDUCTIVE SILICONE COMPOSITION, HEAT CONDUCTIVE LAYER, AND SEMICONDUCTOR DEVICE - Provided is a heat conductive silicone composition disposed between a heat generating electronic component and a member for dispersing heat, wherein the heat conductive silicone composition contains (A) an organopolysiloxane having at least two alkenyl groups in one molecule and having a dynamic viscosity at 25° C. of 10 to 100,000 mm | 12-10-2015 |
20150357262 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND TRANSFER SHEET AND MANUFACTURING METHOD THEREOF - In a conventional semiconductor device, a pattern serving as a heat dissipating material is formed by applying a phase transition material. Provided is a semiconductor device that can reduce collapse of a pattern shape even if a shock is applied to the pattern formed with the phase transition material that is liquefied when the environmental temperature is not sufficiently controlled. The semiconductor device includes semiconductor elements mounted inside a semiconductor module ( | 12-10-2015 |
20150371917 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 12-24-2015 |
20150371918 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 12-24-2015 |
20150371919 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 12-24-2015 |
20150371921 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device of the present invention includes: a first substrate ( | 12-24-2015 |
20150371922 | HEAT SPREADING LAYER WITH HIGH THERMAL CONDUCTIVITY - Embodiments of the invention comprise a homogeneous heat spreading cap element in chip packages to facilitate better heat spreading and dissipation. The heat spreading cap comprises a single high-K graphite layer supported by a copper frame for increased stability and reduced thermal warpage during handling and operation while minimizing thermal penalty by reducing the amount of material having a relatively low heat conductivity that is needed in conventional heat spreading caps. | 12-24-2015 |
20150371923 | HEAT CONDUCTIVE SHEET AND STRUCTURE - Provided is a heat conductive sheet obtained by including a heat conductive filler in a cured organic resin, in which the heat conductive filler is made of multiple particles obtained by coating surfaces of plastic particles with a heat conductive material, and a coefficient of variation (CV) value of particle diameters of the particles, which is computed using Equation (1) described below, is equal to or less than 10%. | 12-24-2015 |
20150380334 | Advanced Structure for Info Wafer Warpage Reduction - A package (e.g., a wafer level package (WLP)) including one or more redistribution layers to fan out the contact pads of the one or more dies within an integrated circuit structure. An example package includes a die having a contact pad exposed at a frontside thereof. The package also includes a redistribution layer disposed over the frontside of the die. The redistribution layer includes metallization extending through a nano-composite material, which may be formed from a dielectric material with a nano-filler material disposed therein. The metallization is electrically coupled to the contact pad of the die. By incorporating the nano-composite material in the redistribution layer, the coefficient of thermal expansion (CTE) of the redistribution layer more closely matches the CTE of the die, which prevents or eliminates undesirable warpage of the redistribution layers. | 12-31-2015 |
20150380337 | Thermally Enhanced Structure for Multi-Chip Device - A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved. | 12-31-2015 |
20160005673 | Electronic component and method for dissipating heat from a semiconductor die - In an embodiment, an electronic component includes a dielectric core layer having a thickness, at least one semiconductor die embedded in the dielectric core layer and electrically coupled to at least one contact pad arranged on a first side of the dielectric core layer, and a heat dissipation layer arranged on a second side of the dielectric core layer and thermally coupled to the semiconductor die. The semiconductor die has a thickness that is substantially equal to, or greater than, or equal to the thickness of the dielectric core layer. The heat dissipation layer includes a material with a substantially isotropic thermal conductivity. | 01-07-2016 |
20160013117 | Electrically Conductive Element, Power Semiconductor Device Having an Electrically Conductive Element and Method of Manufacturing a Power Semiconductor Device | 01-14-2016 |
20160020202 | APPARATUS FOR CONTROLLING HEAT FLOW - An apparatus configured to control a heat flow is provided. The apparatus may include a semiconductor device region formed in a matrix; a heat rectifier region formed adjacent to the semiconductor device region; and a heat flow blocker formed in at least one region contacting the semiconductor device region and the heat rectifier region. | 01-21-2016 |
20160027714 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element having a rectangular shape in a plan view, and a fixed member to which the semiconductor element is fixed. The semiconductor element is disposed so that a rectangular face of the semiconductor element is faced toward a surface of the fixed member. A part of the rectangular face of the semiconductor element is fixed to the surface of the fixed member. At least corner parts of the rectangular face of the semiconductor element are not fixed to the surface of the fixed member. | 01-28-2016 |
20160027716 | SEMICONDUCTOR MODULE - The semiconductor module includes a pin that is connected to a semiconductor element; a pin wiring substrate that has a second metal film and a first metal film on the upper and lower surfaces, the first metal film and the second metal film being electrically bonded to the pin; solder that bonds the pin and the semiconductor element; a DCB substrate that has a third metal film and a fourth metal film on the upper and lower surfaces, the third metal film being bonded to a lower surface of the semiconductor element; and a first cooler that is connected to the fourth metal film. The ratio H/T of a height H of the solder to a distance T from the semiconductor element to the first metal film is equal to or greater than 0.2 and equal to or less than 0.7. | 01-28-2016 |
20160043058 | SEMICONDUCTOR COOLING STRUCTURE AND METHOD IN A MIXED BONDING PROCESS - The invention provides a semiconductor cooling structure and method in a mixed bonding process, and comprises: providing two wafers which require to be treated by a mixed bonding process, each of the wafers being provided with several metallic device structure layers therein; a heat dissipation layer is set in at least one of the wafer, the heat dissipation layer is arranged in the free area above at least one of the metallic device structure layers, and the heat dissipation layer connects to the adjacent metallic device structure layer which is adjacent to and below the heat dissipation layer; wherein material of each of the heat dissipation layers is good conductors of heat. The invention can make heat generated during bonding process transfer and distribute evenly. | 02-11-2016 |
20160049378 | INTEGRATED DEVICE COMPRISING A HEAT-DISSIPATION LAYER PROVIDING AN ELECTRICAL PATH FOR A GROUND SIGNAL - Provided herein is an integrated device that includes a substrate, a die, a heat-dissipation layer located between the substrate and the die, and a first interconnect configured to couple the die to the heat-dissipation layer. The heat-dissipation layer may be configured to provide an electrical path for a ground signal. The first interconnect may be further configured to conduct heat from the die to the heat-dissipation layer. The integrated device may also include a second interconnect configured to couple the die to the substrate. The second interconnect may be further configured to conduct a power signal between the die and the substrate. The integrated device may also include a dielectric layer located between the heat-dissipation layer and the substrate, and a solder-resist layer located between the die and the heat-dissipation layer. | 02-18-2016 |
20160049383 | DEVICE AND METHOD FOR AN INTEGRATED ULTRA-HIGH-DENSITY DEVICE - A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface. | 02-18-2016 |
20160064300 | FAN-OUT WAFER LEVEL PACKAGE - A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material. | 03-03-2016 |
20160079143 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME - In the present invention, a heat spreader has a sagging surface or a C surface being a chamfered portion at an outer peripheral end portion of a back surface thereof. A plurality of power elements formed into chips are mounted on a surface of the heat spreader with a solder therebetween, and an insulating sheet portion is located on the back surface side of the heat spreader. The insulating sheet portion has a laminated structure of an insulating layer and a metal foil, and the insulating layer being the upper layer is closely bonded to the back surface of the heat spreader. A space region between the sagging surface and the insulating sheet portion is filled with a molding resin. | 03-17-2016 |
20160079155 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR DEVICE - A heat sink has a fixation surface and a heat release surface opposite from the fixation surface. A fin is provided in a central portion of the heat release surface. An insulating member is provided on the fixation surface of the heat sink. An electroconductive member is provided on the insulating member . A semiconductor chip is provided on the electroconductive member. A metal frame is connected to the semiconductor chip. A molding resin covers the heat sink, the insulating member, the electroconductive member, the semiconductor chip, and the metal frame so that the fin is exposed to outside. A hole extends through a peripheral portion of the heat sink and a peripheral portion of the molding resin. The semiconductor module is mounted on a cooling jacket by passing a screw through the hole. | 03-17-2016 |
20160086869 | SEMICONDUCTOR DEVICE HAVING IMPROVED HEAT-DISSIPATION CHARACTERISTICS - A semiconductor device having improved heat-dissipation characteristics is capable effectively discharging heat that is generated inside the semiconductor device of a three-dimensional laminated structure, to the outside of the semiconductor device by utilizing an internal connector used during bonding. | 03-24-2016 |
20160086870 | SEMICONDUCTOR DEVICE - A semiconductor device with improved heat radiation characteristics. It includes: a wiring board having a chip mounting surface and a plurality of electrode pads formed over the chip mounting surface; a semiconductor chip located over the chip mounting surface of the wiring board, having a plurality of bonding pads; a plurality of wires for coupling the electrode pads and the bonding pads; a heat slug located over the semiconductor chip; and a sealing member covering the chip mounting surface of the wiring board, the semiconductor chip, the wires, and the heat slug. A spacer lies between the chip mounting surface of the wiring board and the semiconductor chip and the sealing member lies between the semiconductor chip and the heat slug. | 03-24-2016 |
20160086871 | INTEGRATED HEAT SPREADER FOR MULTI-CHIP PACKAGES - An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive structures secured within the heat spreader frame openings. The thermally conductive structures can be formed to have various thicknesses which compensate for varying heights between at least two microelectronic devices in a multi-chip package. The thermally conductive structures can be secured in the heat spreader frame by sizing the openings and the thermally conductive structures such that the thermally conductive structures can be secured within the openings without requiring welding or adhesives. | 03-24-2016 |
20160099194 | SEMICONDUCTOR MODULE AND ELECTRICALLY-DRIVEN VEHICLE - A semiconductor module includes a first semiconductor element, a second semiconductor element, a first heat spreader electrically and thermally connected to the first semiconductor element, a second heat spreader electrically and thermally connected to the second semiconductor element, a DCB substrate including a first metal foil on a top surface of a ceramic insulating substrate and including a second metal foil on a bottom surface, the first metal foil being electrically and thermally joined to the first heat spreader and the second heat spreader, and a cooler thermally connected to the second metal foil of the DCB substrate. The first semiconductor element is disposed on an upstream side, and the second semiconductor element is disposed on a downstream side with respect to a flowing direction of a refrigerant of the cooler. An area of the second heat spreader is greater than an area of the first heat spreader. | 04-07-2016 |
20160118314 | POWER MODULE AND METHOD OF PACKAGING THE SAME - Provided are a power module having an integrated power semiconductor and a method of packaging the same. The power module according to an aspect of the present invention includes a power semiconductor chip based on silicon and insulating substrates respectively disposed at both surfaces of the power semiconductor chip and including a metal pattern electrically and directly connected to the power semiconductor chip. | 04-28-2016 |
20160118316 | THERMALLY CONDUCTIVE SHEET - A thermally conductive sheet, comprising a curable resin composition, thermally conductive fibers, and thermally conductive particles, wherein the thermally conductive sheet has a compressibility of 40% or more. | 04-28-2016 |
20160118317 | MICROPROCESSOR ASSEMBLY ADAPTED FOR FLUID COOLING - A microprocessor assembly adapted for fluid cooling can include a semiconductor die mounted on a substrate. The semiconductor die can include an integrated circuit with a two-dimensional and/or three-dimensional circuit architecture. The assembly can include a heat sink module in thermal communication with the semiconductor die. The heat sink module can include an inlet port fluidly connected to an inlet chamber, a plurality of orifices fluidly connecting the inlet chamber to an outlet chamber, and an outlet port fluidly connected to the outlet chamber. When pressurized coolant is delivered to the inlet chamber, the plurality of orifices can provide jet streams of coolant into the outlet chamber and against a surface to be cooled to provide fluid cooling suitable to control a semiconductor die temperature during operation. | 04-28-2016 |
20160133602 | Packages with Thermal Management Features for Reduced Thermal Crosstalk and Methods of Forming Same - An embodiment package includes a first die stack on a surface of a package component, a second die stack on the surface of the package component, and a contour lid over the first die stack and second die stack. The contour lid includes a first thermal conductive portion over the first die stack, a second thermal conductive portion over the second die stack, and a thermal barrier portion between the first thermal conductive portion and the second thermal conductive portion. The thermal barrier portion includes a low thermal conductivity material. | 05-12-2016 |
20160141221 | ELECTRONIC DEVICE HAVING HEAT CONDUCTING MEMBER - An electronic device includes a semiconductor module, a wiring substrate, a case member and a heat conducting member. The heat conducting member thermally connects predetermined portions of wiring patterns and a heat conducting pattern of the wiring substrate to a predetermined heat conduction region of a surface of the case member opposing to the wiring substrate. The predetermined heat conduction region is located further from the wiring substrate than a surface of a body portion opposing to the case member. As a result, heat can be radiated and a short can be restricted with the case member having a simple shape. The heat conducting pattern is disposed adjacent to at least one of non-terminal projecting surfaces of the body portion on a surface of the wiring substrate. As a result, an area of a heat conducting passage increases and heat radiation performance can be increased. | 05-19-2016 |
20160141271 | SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME - A semiconductor package including a lower package and an upper package provided may be provided. The lower package includes a lower package substrate, a lower semiconductor chip mounted thereon, and a lower mold layer provided on the lower package substrate. The upper package includes an upper package substrate and an upper semiconductor chip thereon. The lower mold layer includes a guide portion extending along a vertical direction from an edge of the lower package substrate toward the upper package. | 05-19-2016 |
20160141831 | HEAT REMOVAL FROM PHOTONIC DEVICES - Embodiments of the present description relate to mechanisms for transferring heat through a microelectronic substrate from a photonic device to a heat dissipation device. In one embodiment, the microelectronic substrate may comprise a highly thermally conductive dielectric material. In another embodiment, the microelectronic substrate may comprise a conductive insert within the microelectronic substrate wherein the photonic device is in thermal contact with the conductive insert proximate one surface of the microelectronic substrate and the heat dissipation device is thermal contact with the conductive insert proximate an opposing surface of the microelectronic substrate. In still another embodiment, a stepped heat spreader, having a base portion and a pedestal portion, has the pedestal portion inserted through the microelectronic substrate, wherein the photonic device is in thermal contact with the pedestal portion proximate one surface of the microelectronic substrate and the heat dissipation device is thermal contact with the base portion. | 05-19-2016 |
20160155684 | SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD | 06-02-2016 |
20160163618 | HEAT DISSIPATING CIRCUIT BOARD AND ELECTRONIC DEVICE - A heat dissipating circuit board for a power semiconductor includes an electrode material on which a power semiconductor is mounted on a front surface thereof, and a member bonded to a front surface side of the electrode material. The member is made up from a material which exhibits a lower coefficient of thermal expansion than that of the electrode material, and which exhibits a higher Young's modulus than that of the electrode material. | 06-09-2016 |
20160172269 | SEMICONDUCTOR PACKAGE | 06-16-2016 |
20160181176 | SEMICONDUCTOR PACKAGE | 06-23-2016 |
20160190031 | SEMICONDUCTOR PACKAGE WITH CANTILEVER PADS - One or more embodiments are directed to semiconductor packages with one or more cantilever pads. In one embodiment a recess is located in a substrate of the package facing the cantilever pad. The cantilever pad includes a conductive pad on which a conductive ball is formed. The cantilever pad is configured to absorb stresses acting on the package. | 06-30-2016 |
20160190033 | SEMICONDUCTOR MODULE UNIT AND SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor chip; an insulating circuit board that has on one of principal surfaces of an insulating substrate a circuit member electrically connected to the semiconductor chip, and a first metal member disposed in the other principal surface of the insulating substrate; a second metal member that is disposed on a side of an outer edge of the first metal member and is at least partially disposed further toward an outer side than the insulating substrate; a molding resin portion that seals the semiconductor chip, the insulating circuit board, and the second metal member such that a portion of the first metal member and a portion of the second metal member are exposed; a cooler; a first bonding member that bonds the cooler and the first metal member; and a second bonding member that bonds the cooler and the second metal member. | 06-30-2016 |
20160190035 | THERMAL INTERFACE MATERIAL LAYER AND PACKAGE-ON-PACKAGE DEVICE INCLUDING THE SAME - Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package. | 06-30-2016 |
20160204033 | METHOD FOR SEPARATING SUBSTRATES AND SEMICONDUCTOR CHIP | 07-14-2016 |
20160204047 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | 07-14-2016 |
20170238446 | DISPLAY PANEL AND DISPLAY DEVICE | 08-17-2017 |
20180025962 | Power Electronics Assemblies Having a Semiconductor Device with Metallized Embedded Cooling Channels | 01-25-2018 |
20180026110 | POWER ELECTRONIC SWITCHING DEVICE, ARRANGEMENT HEREWITH AND METHODS FOR PRODUCING THE SWITCHING DEVICE | 01-25-2018 |
20190148256 | SEMICONDUCTOR PACKAGES RELATING TO THERMAL TRANSFER PLATE AND METHODS OF MANUFACTURING THE SAME | 05-16-2019 |