Class / Patent application number | Description | Number of patent applications / Date published |
257537000 | Using specific resistive material | 58 |
20080237800 | INTEGRATED CIRCUIT HAVING RESISTOR BETWEEN BEOL INTERCONNECT AND FEOL STRUCTURE AND RELATED METHOD - Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography. | 10-02-2008 |
20080315359 | INTEGRATED CIRCUIT INCLUDING VERTICAL DIODE - An integrated circuit includes a vertical diode, a first electrode coupled to the vertical diode, and a resistivity changing material coupled to the first electrode. The integrated circuit includes a second electrode coupled to the resistivity changing material and a spacer having a first sidewall contacting a first sidewall of the first electrode and a sidewall of the resistivity changing material. | 12-25-2008 |
20090051009 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND RESISTOR - Formed on an insulator are an N | 02-26-2009 |
20090127658 | RESISTOR IN AN INTEGRATED CIRCUIT - A resistive element having two vertical resistive portions placed in two holes formed in the upper portion of a substrate and a horizontal resistive portion placed in a buried cavity connecting the bottoms of the holes. | 05-21-2009 |
20090174033 | ADJUSTIBLE RESISTOR FOR USE IN A RESISTIVE DIVIDER CIRCUIT AND METHOD FOR MANUFACTURING - A method of manufacturing a resistive divider circuit, comprising providing a silicon body ( | 07-09-2009 |
20100078763 | RESISTANCE-CHANGE MEMORY HAVING RESISTANCE-CHANGE ELEMENT AND MANUFACTURING METHOD THEREOF - A resistance-change memory includes an interlayer insulating film, a lower electrode layer, a fixed layer, a first insulating film, a recording layer, a second insulating film, a conducting layer and an interconnect. The interlayer insulating film is formed on a semiconductor substrate and has a step. The lower electrode layer is formed on the interlayer insulating film including the step. The fixed layer is formed on the lower electrode layer and has invariable magnetization. The first insulating film is formed on the fixed layer. The recording layer is formed on part of the first insulating film and has variable magnetization. The second insulating film is over the recording layer and in contact with the first insulating film. The conducting layer is formed on the second insulating film. The interconnect is connected to the conducting layer. | 04-01-2010 |
20100155893 | Method for Forming Thin Film Resistor and Terminal Bond Pad Simultaneously - Disclosed are methods for forming a thin film resistor and terminal bond pad simultaneously. A method includes simultaneously forming a terminal bond pad on a terminal wire and a thin film resistor on two other wires. | 06-24-2010 |
20100320569 | CARBON NANOTUBE RESISTOR, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A process for producing a carbon nanotube resistor that is capable of providing a highly reliable resistor or fuse. The process comprises the step of introducing a carbon nanotube in a volatile solvent to a first concentration and conducting ultrasonic treatment thereof to thereby obtain an initial solution; the dilution step of stepwise diluting the initial solution with a volatile solvent under ultrasonication so as to adjust the same to a second concentration, thereby obtaining a coating solution; and the step of applying the coating solution between a fist electrode and a second electrode, wherein the first concentration is 1(E10 | 12-23-2010 |
20110169136 | CROSSBAR-INTEGRATED MEMRISTOR ARRAY AND METHOD EMPLOYING INTERSTITIAL LOW DIELECTRIC CONSTANT INSULATOR - A memristor crossbar array and method of making employ an interstitial insulator. The memristor crossbar array includes a plurality of memristors in an array. The memristors include columns of memristor material disposed between and connecting to a first plurality of wire electrodes and a second plurality of wire electrodes at cross points between the respective wire electrodes. The memristor crossbar array further includes an insulator of a solid material in an interstitial space between the wire electrodes of the first plurality and between the columns of memristor material. The insulator isolates the memristors from one another and has a dielectric constant that is lower than a dielectric constant of the memristor material. The method of making includes forming the plurality of memristors and filling the interstitial space between adjacent memristors with the insulator material. | 07-14-2011 |
20110221037 | Electronic Component Arrangement Comprising a Varistor and a Semiconductor Component - An electric component arrangement is described, comprising a semiconductor component ( | 09-15-2011 |
20110227196 | ESD PROTECTION DEVICE - An ESD protection device includes a ceramic multilayer substrate, at least one pair of discharge electrodes provided in the ceramic multilayer substrate and facing each other with a space formed therebetween, external electrodes provided on a surface of the ceramic multilayer substrate and connected to the discharge electrodes. The ESD protection device includes a supporting electrode obtained by dispersing a metal material and a semiconductor material and being arranged in a region that connects the pair of discharge electrodes to each other. | 09-22-2011 |
20110248381 | Multilayer Memristive Devices - A multilayer memristive device includes a first electrode ( | 10-13-2011 |
20120161284 | CHIP RESISTOR AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a chip resistor and method for manufacturing the same. The method includes the following steps of: (a) providing a substrate and a resistor layer; (b) attaching the resistor layer to the substrate; (c) forming a first metal layer; (d) forming a plurality of through holes; (e) forming a connecting metal layer in the through holes to electrically connect the resistor layer and the first metal layer; (f) patterning the resistor layer to form a plurality of first resistor bodies; (g) forming a plurality of first protecting layers to protect the first resistor bodies; and (h) proceeding a singulation process along a plurality of cutting lines to form a plurality of chip resistors. Whereby, no alignment problem occurs and the yield can be raised. | 06-28-2012 |
20120199951 | INTEGRATED SHUNT RESISTOR WITH EXTERNAL CONTACT IN A SEMICONDUCTOR PACKAGE - An integrated circuit package that comprises a lead frame | 08-09-2012 |
20120313220 | HIGH-NITROGEN CONTENT METAL RESISTOR AND METHOD OF FORMING SAME - A thin film metal resistor is provided that includes an in-situ formed metal nitride layer that is formed in a lower region of a deposited metal nitride layer. The in-situ formed metal nitride layer, together with the overlying deposited metal nitride layer, from a thin film metal resistor which has a nitrogen content that is greater than 60 atomic % nitrogen. The in-situ formed metal nitride layer is present on a nitrogen enriched dielectric surface layer. In accordance with the present disclosure, the in-situ formed metal nitride layer is formed during and/or after formation of the deposited metal nitride layer by reacting metal atoms from the deposited metal nitride layer with nitrogen atoms present in the nitrogen enriched dielectric surface layer. The presence of the in-situ formed metal nitride layer in the lower region of the metal nitride layer provides a two-component metal resistor having greater than 60 atomic % nitrogen therein. | 12-13-2012 |
20130168817 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first insulating layer (interlayer insulating layer), a resistive element that is disposed over the first insulating layer (interlayer insulating layer) and at least a surface layer of which is a TaSiN layer, and an interlayer insulating layer disposed over the first insulating layer (interlayer insulating layer) and the resistive element. Multiple via plugs having ends coupled to the TaSiN layer are disposed in the interlayer insulating layer. | 07-04-2013 |
20130328169 | RESISTIVE DEVICE AND METHOD OF MANUFACTURING THE SAME - This disclosure is related to a resistive device including a silicide pattern. A resistive device can include a substrate, and a first resistive layer disposed above the substrate. The resistive device can include a second resistive layer disposed on the first resistive layer and has a resistance different from a resistance of the first resistive layer. The resistive device can include a third resistive layer disposed on a first portion of the first resistive layer such that a second portion of the first resistive layer is disposed between the third resistive layer and the second resistive layer. The resistive layer can also include a conductive plug electrically connected to the third resistive layer. | 12-12-2013 |
20140008764 | HIGH-NITROGEN CONTENT METAL RESISTOR AND METHOD OF FORMING SAME - A thin film metal resistor is provided that includes an in-situ formed metal nitride layer formed in a lower region of a metal nitride layer. The in-situ formed metal nitride layer, together with the overlying metal nitride layer, from a thin film metal resistor which has a nitrogen content that is greater than 60 atomic % nitrogen. The in-situ formed metal nitride layer is present on a nitrogen enriched dielectric surface layer. The presence of the in-situ formed metal nitride layer in the lower region of the metal nitride layer provides a two-component metal resistor having greater than 60 atomic % nitrogen therein. | 01-09-2014 |
20140183699 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 07-03-2014 |
20140191367 | SANDWICH DAMASCENE RESISTOR - A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL. | 07-10-2014 |
20150008560 | SEMICONDUCTOR DEVICE AND METHOD FOR LOW RESISTIVE THIN FILM RESISTOR INTERCONNECT - The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction. | 01-08-2015 |
20150054131 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 02-26-2015 |
20150069574 | INTEGRATED CIRCUIT AND MANUFACTURING AND METHOD THEREOF - A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above. | 03-12-2015 |
20150137316 | SEMICONDUCTOR DEVICE INCLUDING A RESISTOR AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer. | 05-21-2015 |
20160197135 | SINGLE PHOTOMASK HIGH PRECISION THIN FILM RESISTOR | 07-07-2016 |
257538000 | Polycrystalline silicon (doped or undoped) | 33 |
20080203532 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a transistor circuit and a bleeder resistance circuit is provided in which fluctuations in resistance value of a bleeder resistor are reduced. In the transistor circuit, a barrier metal film and a interconnect film are layered as a metal film on an interlayer insulating film above transistor structure. In the bleeder resistance circuit, the interconnect film is layered as a metal film on the interlayer insulating film above the bleeder resistor formed from polysilicon film. Alternatively, the metal film in the bleeder resistance circuit includes the barrier metal film only in a portion where the metal film is connected to the bleeder resistor. This reduces stress to the bleeder resistor formed from a polysilicon film, and the resistance value of the bleeder resistor accordingly fluctuates less. In addition, since the metal film used as interconnect of the transistor circuit includes the barrier metal film, interconnect reliability is not impaired. | 08-28-2008 |
20080217741 | Silicide-Interface Polysilicon Resistor - A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multiple semiconductor junctions. The silicide-interface polysilicon resistor also includes a layer of silicide sheets, and at least one of the silicon sheets is in contact with one of the semiconductor junctions located within the polysilicon layer. | 09-11-2008 |
20080224265 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A second insulation film is provided on the high resistance element. A hydrogen diffusion preventing film having a hydrogen diffusion coefficient smaller than that of the second insulation film is provided on the second insulation film. The hydrogen diffusion preventing film covers a part of the high resistance element. | 09-18-2008 |
20080237801 | Semiconductor device - A semiconductor device includes a resistor element formed in a semiconductor layer of an SOI substrate (Silicon On Insulator). The semiconductor device includes a low concentration impurity area formed in the semiconductor layer as the resistor element; a high concentration impurity area formed in the semiconductor layer as a resistor element wiring portion; and a silicide layer selectively formed on the high concentration impurity area. The high concentration impurity area includes one end portion contacting with an end portion of the low concentration impurity area, and the other end portion contacting with an impurity area of another element. | 10-02-2008 |
20080315360 | Resistor of Semiconductor Device and Method for Fabricating the Same - A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer; and a contact electrically connected to the first polysilicon layer and the second polysilicon layer. The portions of the first polysilicon layer that do not have the insulating layer formed thereupon have a higher impurity ion concentration than that of the regions on which the insulating layer is formed. | 12-25-2008 |
20090096064 | METHOD OF FORMING POLY PATTERN IN R-STRING OF LCD DRIVE IC AND STRUCTURE OF THE SAME - A method of forming a poly pattern for minimizing a change in a storage value in the R-string pattern of the LCD panel drive IC (LDI) that includes depositing a poly silicon layer used as a resistor in a R-string structure over a semiconductor substrate; and then forming a poly silicon layer pattern having interconnected H-shaped cross-sections; and then forming a silicide-anti blocking area (SAB) layer over the poly silicon layer pattern and then patterning the SAB layer to thereby form SAB layer patterns over portions of the poly silicon layer pattern while exposing other portions of the poly silicon layer pattern; and then forming a silicide layer over the exposed portions of the poly silicon layer pattern. Therefore, although the size of the SAB pattern is reduced due to problems caused in processing steps, the poly line that occupies most of the resistance does not change so that a change in the resistance is entirely reduced. | 04-16-2009 |
20090152679 | SEMICONDUCTOR DEVICE - A metal electrode is disposed on each of a plurality of resistor groups which are made of polycrystalline silicon resistors and constitute a resistor circuit. The metal electrode is connected to an end of the resistor via another interconnecting layer. Accordingly, the external influence which the metal electrode receives during a semiconductor manufacturing process is prevented from directly acting on the resistor, whereby resistance variation is suppressed. | 06-18-2009 |
20090283860 | HIGH PRECISION SEMICONDUCTOR CHIP AND A METHOD TO CONSTRUCT THE SEMICONDUCTOR CHIP - An embodiment for manufacturing an electronic circuit forms at least one first structure on a semiconductor substrate, determines at least one electrically defined characteristic of the at least one first structure, selects a reticle corresponding to the measured characteristic, and forms at least one additional structure on the semiconductor substrate with the selected reticle. | 11-19-2009 |
20100038754 | Back-End-of-Line Resistive Semiconductor Structures - In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines. | 02-18-2010 |
20100052100 | DEEP TRENCH ELECTROSTATIC DISCHARGE (ESD) PROTECT DIODE FOR SILICON-ON-INSULATOR (SOI) DEVICES - A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region. | 03-04-2010 |
20100164068 | SEMICONDUCTOR STRUCTURES FOR BIASING DEVICES - Semiconductor structures with high impedances for use in biasing for applying voltage bias to part of a device. The semiconductor structure comprises a continuous structure having a plurality of regions of a first semiconductor type (n type or p type) material arranged alternately with at least one region of the opposite type. The structure may be formed from polysilicon and may also include a plurality of intrinsic regions arranged between the n and p type regions. The structure forms a composite diode and provides a high impedance. | 07-01-2010 |
20100200952 | SEMICONDUCTOR DEVICE - Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected. | 08-12-2010 |
20100200953 | ON-CHIP HEATER AND METHODS FOR FABRICATION THEREOF AND USE THEREOF - An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure. | 08-12-2010 |
20110163419 | ALLOTROPIC OR MORPHOLOGIC CHANGE IN SILICON INDUCED BY ELECTROMAGNETIC RADIATION FOR RESISTANCE TURNING OF INTEGRATED CIRCUITS - An electronic device includes a semiconductor substrate and a dielectric layer over the substrate. A resistive link located over the substrate includes a first resistive region and a second resistive region. The first resistive region has a first resistivity and a first morphology. The second resistive region has a second resistivity and a different second morphology. | 07-07-2011 |
20110260290 | MEMORY CELL THAT INCLUDES A CARBON-BASED MEMORY ELEMENT AND METHODS OF FORMING THE SAME - In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided. | 10-27-2011 |
20120038026 | LOW CAPACITANCE PRECISION RESISTOR - A precision low capacitance resistor is formed, e.g., in a bulk substrate. An embodiment includes forming a source/drain region on a substrate, patterning a portion of the source/drain region to form segments, etching the segments to substantially separate an upper section of each segment from a lower section of each segment, and filling the space between the segments with an insulating material. The resulting structure maintains electrical connection between the segments at end pads, but separates the resistor segments from the bottom substrate, thereby avoiding capacitive coupling with the substrate. | 02-16-2012 |
20120146187 | METHODS AND STRUCTURES FOR INCREASED THERMAL DISSIPATION OF THIN FILM RESISTORS - A method of forming a semiconductor structure includes forming at least one trench in an insulator layer formed on a substrate. A distance between a bottom edge of the at least one trench and a top surface of a substrate is shorter than a distance between an uppermost surface of the insulator layer and the top surface of the substrate. The method also includes: forming a resistor on the insulator layer and extending into the at least one trench; forming a first contact in contact with the resistor; and forming a second contact in contact with the resistor such that current is configured to flow from the first contact to the second contact through a central portion of the resistor. | 06-14-2012 |
20120175737 | SEMICONDUCTOR DEVICES WITH GATE-SOURCE ESD DIODE AND GATE-DRAIN CLAMP DIODE - A semiconductor power device integrated with a Gate-Source ESD diode for providing an electrostatic discharge (ESD) protection and a Gate-Drain clamp diode for drain-source avalanche protection. The semiconductor power device further includes a Nitride layer underneath the diodes and a thick oxide layer as an etching stopper layer for protecting a thin oxide layer on top surface of body region from over-etching. | 07-12-2012 |
20120280361 | HIGH VOLTAGE RESISTOR WITH BIASED-WELL - Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L. | 11-08-2012 |
20120319240 | High Voltage Resistor With Pin Diode Isolation - Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions. | 12-20-2012 |
20120319241 | OFFSET REDUCING RESISTOR CIRCUIT - The resistor segments may be placed in a spatial region of an integrated circuit. Junctions formed between the resistor segments and conductors may be placed at locations such that each junction has a paired counterpart of the same type that is spaced to form respective same junction type centroids (i.e., geometric centers). The different type centroids may be substantially coincident, meaning that the centroids substantially overlap. In this manner, junction voltages (or offset voltages) generated by one pair of junctions may cancel out the junction voltages generated by another pair of junctions in the resistor circuit. | 12-20-2012 |
20130032926 | ADJUSTABLE RESISTOR - An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer. | 02-07-2013 |
20130049168 | RESISTOR AND MANUFACTURING METHOD THEREOF - A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor. | 02-28-2013 |
20130056854 | COMPLEMENTARY STRESS LINER TO IMPROVE DGO/AVT DEVICES AND POLY AND DIFFUSION RESISTORS - Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices. | 03-07-2013 |
20130214387 | CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME - The present disclosure provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor. | 08-22-2013 |
20130285207 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device. The semiconductor device includes a functional circuit having a resistor formed by a plurality of polysilicon resistors, and in which the property of the functional circuit can be adjusted by trimming the resistor, and in which the polysilicon resistors are coupled in series or in parallel to each other and arranged in a direction perpendicular to one side of the semiconductor device. | 10-31-2013 |
20130320497 | ON-CHIP RESISTOR - An integrated circuit (IC) is disclosed. The IC includes a substrate with a resistor region and a resistor body disposed on the resistor region. A plurality of first resistor contact strips and a plurality of second resistor contact strips are disposed on the resistor body along a first direction. Two adjacent first and second resistor contact strips are separated by a respective one of contact strip spaces. The IC includes a plurality of first terminals and a plurality of second terminals. Each of the first terminals is coupled to a respective one of the first resistor contact strips while each of the second terminals is coupled to a respective one of the second resistor contact strips. A set of the first terminal and the second terminal forms first and second terminals of an on-chip resistor. | 12-05-2013 |
20140008765 | POLY SILICON RESISTOR, REFERENCE VOLTAGE CIRCUIT COMPRISING THE SAME, AND MANUFACTURING METHOD OF POLY SILICON RESISTOR - The present invention relates to a polysilicon resistor, a reference voltage circuit including the same, and a method for manufacturing the polysilicon resistor. The polysilicon resistor according includes a first polysilicon resistor and at least one of second polusilicon resistors, coupled to the first polysilicon resistor in series. The first polysilicon resistor and the at least one of the second polysilicon resistors are P-type polysilicon, and a doping concentration of the first polysilicon resistor is different from a doping concentration of the at least one of the second polysilicon resistors. The polysilicon resistor formed by serially coupling the first polysilicon resistor and the at least one of the second polysilicon resistors is applied with a constant current such that a reference voltage or a constant voltage is generated. | 01-09-2014 |
20140175609 | PRECISION POLYSILICON RESISTORS - Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both. | 06-26-2014 |
20150061076 | HIGH DENSITY RESISTOR - At least one three dimensional semiconductor fin is formed from a top semiconductor material of a substrate. A dielectric material is formed along vertical sidewalls and an upper surface of the at least one three dimensional semiconductor fin. A polysilicon resistor is formed on exposed surfaces of the dielectric material and surrounding the at least one semiconductor fin. An interconnect dielectric material is formed above the polysilicon resistor. The interconnect dielectric material has at least one contact structure that extends through the interconnect dielectric to an upper surface of the polysilicon resistor. | 03-05-2015 |
20150108608 | POLYSILICON RESISTOR STRUCTURE HAVING MODIFIED OXIDE LAYER - Various embodiments include resistor structures. Particular embodiments include a resistor structure having multiple oxide layers, at least one of which includes a modified oxide. The modified oxide can aid in controlling the thermal capacitance and the thermal time constant of the resistor structure, or the thermal dissipation within the resistor structure. | 04-23-2015 |
20150333188 | TILTED IMPLANT FOR POLY RESISTORS - A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor. | 11-19-2015 |
20160056149 | SEMICONDUCTOR DEVICE - A P-type epitaxial growth layer is formed on a P-type semiconductor substrate with an N-type buried region and a P-type buried region interposed therebetween. A cathode region, an anode region, and an N-type sinker region are formed in P-type epitaxial growth layer. A resistance element is formed on a surface of an isolation region that electrically isolates anode region and N-type sinker region. Resistance element has: one end portion electrically connected to each of anode region and N-type sinker region; and the other end portion electrically connected to a ground potential. | 02-25-2016 |