Entries |
Document | Title | Date |
20080197450 | AMORPHOUS CARBON METAL-TO-METAL ANTIFUSE WITH ADHESION PROMOTING LAYERS - A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising Si | 08-21-2008 |
20080211060 | ANTI-FUSE WHICH WILL NOT GENERATE A NON-LINEAR CURRENT AFTER BEING BLOWN AND OTP MEMORY CELL UTILIZING THE ANTI-FUSE - An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly. | 09-04-2008 |
20080217736 | ELECTRICAL ANTIFUSE, METHOD OF MANUFACTURE AND METHOD OF PROGRAMMING - An antifuse having a link including a region of unsilicided semiconductor material may be programmed at reduced voltage and current and with reduced generation of heat by electromigration of metal or silicide from a cathode into the region of unsilicided semiconductor material to form an alloy having reduced bulk resistance. The cathode and anode are preferably shaped to control regions from which and to which material is electrically migrated. After programming, additional electromigration of material can return the antifuse to a high resistance state. The process by which the antifuse is fabricated is completely compatible with fabrication of field effect transistors and the antifuse may be advantageously formed on isolation structures. | 09-11-2008 |
20080224260 | Programmable Vias for Structured ASICs - A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state. | 09-18-2008 |
20080224261 | Fuse/anti-fuse structure and methods of making and programming same - Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided. | 09-18-2008 |
20080237788 | METHOD AND DEVICE FOR PROGRAMMING ANTI-FUSES - A device includes an anti-fuse including a first electrode that can be selectively coupled to a first voltage reference and a second electrode that can be selectively coupled to a second voltage reference. The device further includes a shunt transistor including a first current electrode coupled to the first electrode of the anti-fuse, a second current electrode coupled to the second electrode of the anti-fuse, and a control electrode. The device additionally includes control logic configured to disable the shunt transistor in response to a first program operation intended for the anti-fuse. The control logic also is configured to enable the shunt transistor in response to a second program operation not intended for the anti-fuse. | 10-02-2008 |
20080251887 | SERIAL SYSTEM FOR BLOWING ANTIFUSES - A serial system and method for blowing antifuses are disclosed. One embodiment of antifuse system includes a plurality of latch devices connected in series from input to output. The system also includes a plurality of antifuses. The antifuses are configured to receive an output signal from a corresponding one of the latch devices. The plurality of latch devices includes a plurality of D flip-flops connected in series. Each of the D flip-flops is configured to receive an output signal from an immediately previous D flip-flop in the serial data flow and to provide an output signal to an immediately subsequent D flip-flop in the flow. In addition, the serial system provides self-detective antifuses, thus creating reliable electrical paths while saving antifuse blowing current resources and time. | 10-16-2008 |
20080283964 | ADOPTING FEATURE OF BURIED ELECTRICALLY CONDUCTIVE LAYER IN DIELECTRICS FOR ELECTRICAL ANTI-FUSE APPLICATION - An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature. | 11-20-2008 |
20080290456 | Electrical Fuse With Metal Silicide Pipe Under Gate Electrode - An electrical fuse (eFuse) has a gate prepared from a conductive or partially conductive material such as polysilicon, a semiconductor substrate having a pipe region in proximity to the gate, and first and second electrode regions adjacent the pipe region. A metal silicide layer is provided on the semiconductor substrate adjacent the pipe region. When a programming voltage is applied, the metal silicide undergoes a thermally induced phase transition in the pipe region. The eFuse has improved reliability and can be programmed with relatively low voltages. | 11-27-2008 |
20080296728 | SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS - A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier. | 12-04-2008 |
20090008741 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND ANTI-FUSE ELEMENT - A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion. | 01-08-2009 |
20090008742 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL AND ANTI-FUSE ELEMENT - A semiconductor device includes an anti-fuse portion and a memory cell portion each including a MOSFET structure having a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; wherein a depletion ratio in the gate electrode of the anti-fuse portion is different from the depletion ratio in the gate electrode of the memory cell portion, and the depletion ratio in the gate electrode of the anti-fuse portion is lower than the depletion ratio in the gate electrode of the memory cell portion. | 01-08-2009 |
20090026576 | ANTI-FUSE - An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions. | 01-29-2009 |
20090026577 | Antifuse element and semiconductor device including same - To provide an antifuse element comprising a gate electrode, a depletion channel region, a gate insulating film between the gate electrode and the channel region, and a diffusion layer region forming a junction with the channel region. An end of the gate electrode coincides substantially with a boundary between the channel region and the diffusion layer region as seen from a planar view, and is formed in a zigzag configuration. The end of the gate electrode is longer than the end with linear configuration and the end of the gate insulating film is likely to be subjected to breakdown. | 01-29-2009 |
20090057820 | ABRUPT METAL-INSULATOR TRANSITION DEVICE WITH PARALLEL CONDUCTING LAYERS - An abrupt MIT (metal-insulator transition) device with parallel conducting layers is provided. The abrupt MIT device includes a first electrode disposed on a certain region of a substrate, a second electrode disposed so as to be spaced a predetermined distance apart from the first electrode, and at least one conducting layer electrically connecting the first electrode with the second electrode and having a width that allows the entire region of the conducting layer to be transformed into a metal layer due to an MIT. Due to this configuration, deterioration of the conducting layer, which is typically caused by current flowing through the conducting layer, is less likely to occur. | 03-05-2009 |
20090057821 | REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL - A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer. | 03-05-2009 |
20090072348 | Integrated Circuits; Methods for Manufacturing an Integrated Circuit and Memory Module - Embodiments of the present invention relate generally to integrated circuits, to methods for manufacturing an integrated circuit and to a memory module. In an embodiment of the invention, an integrated circuit is provided having a programmable arrangement. The programmable arrangement includes a substrate, at least one first electrode disposed in or above the substrate, ion conductor doping material disposed above the at least one first electrode, ion conductor material disposed above the ion conductor doping material, and at least one second electrode disposed above the ion conductor material. | 03-19-2009 |
20090085153 | DIODE ARRAY AND METHOD OF MAKING THEREOF - A method of making a non-volatile memory device includes providing a substrate having a substrate surface, and forming a non-volatile memory array over the substrate surface. The non-volatile memory array includes an array of semiconductor diodes, and each semiconductor diode of the array of semiconductor diodes is disposed substantially parallel to the substrate surface. | 04-02-2009 |
20090085154 | VERTICAL DIODE BASED MEMORY CELLS HAVING A LOWERED PROGRAMMING VOLTAGE AND METHODS OF FORMING THE SAME - In a first aspect, a method for forming a non-volatile memory cell is provided. The method includes (1) forming a metal-insulator-metal (MIM) antifuse stack including (a) a first metal layer; (b) a silicon dioxide, oxynitride or silicon nitride antifuse layer formed above the first metal layer; and (c) a second metal layer formed above the antifuse layer. The method also includes (2) forming a contiguous p-i-n diode above the MIM stack, the contiguous p-i-n diode comprising deposited semiconductor material; (3) forming a layer of a silicide, silicide-germanide, or germanide in contact with the deposited semiconductor material; and (4) crystallizing the deposited semiconductor material in contact with the layer of silicide, silicide-germanide, or germanide. The memory cell comprises the contiguous p-i-n diode and the MIM stack. Other aspects are provided. | 04-02-2009 |
20090096060 | Antifuse structures, antifuse array structures, methods of manufacturing the same - Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array. | 04-16-2009 |
20090102014 | Anti-Fuse Cell and Its Manufacturing Process - An anti-fuse cell includes a standard MOS transistor of an integrated circuit, with source and drain regions covered with a metal silicide layer and at least one track of a resistive layer at least partially surrounding the MOS transistor, and adapted to pass a heating current such that the metal of said metal silicide diffuses across drain and/or source junctions. | 04-23-2009 |
20090108400 | ANTI-FUSE STRUCTURE INCLUDING A SENSE PAD CONTACT REGION AND METHODS FOR FABRICATION AND PROGRAMMING THEREOF - An antifuse structure includes a sense pad contact region that is separate from an anode contact region and a cathode contact region. By including the sense pad contact region that is separate from the anode contact region and the cathode contact region, a programming current flow when programming the antifuse structure may travel a different pathway than a sense current flow when sensing the antifuse structure. In particular a sense current flow may avoid a depletion region created within the cathode contact region when programming the antifuse structure. | 04-30-2009 |
20090115021 | ANTIFUSE ELEMENT IN WHICH MORE THAN TWO VALUES OF INFORMATION CAN BE WRITTEN - An antifuse element includes a plurality of MOS transistors; a first electrode to which source electrodes of the plurality of MOS transistors are commonly connected; a second electrode to which gate electrodes of the plurality of MOS transistors are commonly connected; a third electrode to which at least one of drain electrodes of the plurality of MOS transistors is capable of being connected; and an insulation film provided between the drain electrodes of the plurality of MOS transistors and the third electrode, wherein the insulation on at least one position in said insulation film and that corresponds to one of the drain electrodes is broken down. | 05-07-2009 |
20090189248 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region. | 07-30-2009 |
20090206447 | ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD - Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device. | 08-20-2009 |
20090261451 | CIRCUIT PROTECTION DEVICE INCLUDING RESISTOR AND FUSE ELEMENT - An integral circuit protection device includes a substrate disposed between first and second terminals. The substrate is composed of a resistive material. A first conductive layer is disposed on a first surface of the substrate and in electrical contact with the first terminal. A second conductive layer is disposed on a second surface of the substrate. A first electrically insulating layer is disposed on the second conductive layer and substantially covers the second conductive layer. The first electrically insulating layer includes an aperture. A fuse element is disposed on the first electrically insulating layer and is in electrical contact with the second conductive layer through the aperture and in electrical contact with the second terminal. The fuse element is in electrical series with the resistive material. A second electrically insulating layer is disposed over the fuse element. | 10-22-2009 |
20090273056 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrates. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link. | 11-05-2009 |
20090294903 | ANTI-FUSSE STRUCTURE AND METHOD OF FABRICATING THE SAME - An anti-fuse structure and a method of fabricating the same are described. The anti-fuse structure is disposed over a substrate having at least one device and a copper layer therein. The anti-fuse structure includes a bottom conductive layer, an insulating layer and a top conductive layer. The bottom conductive layer is disposed over and electrically connected with the copper layer. The insulating layer is conformally disposed over the bottom conductive layer covering a corner or a downward turning portion of the bottom conductive layer to form a turning portion of the insulating layer. The top conductive layer is conformally disposed over the insulting layer covering the turning portion of the insulating layer. | 12-03-2009 |
20100078758 | MIIM DIODES - A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises a first electrode comprising a first metal, a first region comprising a first insulating material, a second region comprising a second insulating material, and a second electrode comprising a second metal. The first region and the second region reside between the first electrode and the second electrode. The second insulating material is doped with nitrogen. Note that the second insulating material may have an interface with either the first electrode or the second electrode. | 04-01-2010 |
20100078759 | MIIM DIODES HAVING STACKED STRUCTURE - A metal-insulator diode is disclosed. In one aspect, the metal-insulator diode comprises first and second electrode and first and second insulators arraigned as follows. An insulating region has a trench formed therein. The trench has a bottom and side walls. The first electrode, which comprises a first metal, is on the side walls and over the bottom of the trench. A first insulator has a first interface with the first electrode. At least a portion of the first insulator is within the trench. A second insulator has a second interface with the first insulator. At least a portion of the second insulator is within the trench. The second electrode, which comprises a second metal, is in contact with the second insulator. The second electrode at least partially fills the trench. | 04-01-2010 |
20100187653 | SEMICONDUCTOR DEVICE - A conventional semiconductor device has a problem that an on-current of a parasitic transistor flows through a surface portion of a semiconductor layer and thus a semiconductor element undergoes thermal breakdown. In a semiconductor device according to the present invention, a protection element is formed with use of an isolation region and N type buried layers. A PN junction region in the protection element is formed on a P type buried layer of the isolation region. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of a semiconductor element to be protected. This structure allows an on-current of a parasitic transistor to flow into the protection element, and thereby the semiconductor element is protected. In addition, the on-current of the parasitic transistor flows through a deep portion of the epitaxial layer, and thereby the protection element is prevented from thermal breakdown. | 07-29-2010 |
20100213570 | ANTIFUSE - An antifuse ( | 08-26-2010 |
20100230781 | TRENCH ANTI-FUSE STRUCTURES FOR A PROGRAMMABLE INTEGRATED CIRCUIT - Trench anti-fuse structures, design structures embodied in a machine readable medium for designing, manufacturing, or testing a programmable integrated circuit. The anti-fuse structure includes a trench having a plurality of sidewalls that extend into a substrate, a doped region in the semiconductor material of the substrate proximate to the sidewalls of the trench, a conductive plug in the trench, and a dielectric layer on the sidewalls of the trench. The dielectric layer is disposed between the conductive plug and the doped region. The dielectric layer is configured so that a programming voltage applied between the doped region and the conductive plug causes a breakdown of the dielectric layer within a region of the trench. The trench sidewalls are arranged with a cross-sectional geometrical shape that is independent of position between a bottom wall of the deep trench and a top surface of the substrate. | 09-16-2010 |
20100244186 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film. | 09-30-2010 |
20100320565 | WAFER AND METHOD FOR IMPROVING YIELD RATE OF WAFER - A wafer and a method for improving the yield rate of the wafer are provided. The wafer includes a first and a second circuit units, a first and a second through silicon vias (TSVs), and a first spare TSV. The first and the second circuit units are disposed inside the wafer. The first TSV vertically runs through the wafer and is coupled to the first circuit unit through the front metal of the wafer. The second TSV vertically passes through the wafer and is coupled to the second circuit unit through the front metal of the wafer. When the first or the second TSV has failed, the first spare TSV vertically passes through the wafer to replace the failed first or second TSV. | 12-23-2010 |
20100327403 | Semiconductor chip, semiconductor wafer, method of manufacturing semiconductor chip - One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides. | 12-30-2010 |
20110018093 | PROGRAMMABLE ANTI-FUSE STRUCTURE WITH DLC DIELECTRIC LAYER - In one embodiment an anti-fuse structure is provided that includes a first dielectric material having at least a first anti-fuse region and a second anti-fuse region, wherein at least one of the anti-fuse regions includes a conductive region embedded within the first dielectric material. The anti-fuse structure further includes a first diamond like carbon layer having a first conductivity located on at least the first dielectric material in the first anti-fuse region and a second diamond like carbon layer having a second conductivity located on at least the first dielectric material in the second anti-fuse region. In this embodiment, the second conductivity is different from the first conductivity and the first diamond like carbon layer and the second diamond like carbon layer have the same thickness. The anti-fuse structure also includes a second dielectric material located atop the first and second diamond like carbon layers. The second dielectric material includes at least one conductively filled region embedded therein. | 01-27-2011 |
20110031582 | FIN ANTI-FUSE WITH REDUCED PROGRAMMING VOLTAGE - A method forms an anti-fuse structure comprises a plurality of parallel conductive fins positioned on a substrate, each of the fins has a first end and a second end. A second electrical conductor is electrically connected to the second end of the fins. An insulator covers the first end of the fins and a first electrical conductor is positioned on the insulator. The first electrical conductor is electrically insulated from the first end of the fins by the insulator. The insulator is formed to a thickness sufficient to break down on the application of a predetermined voltage between the second electrical conductor and the first electrical conductor and thereby form an uninterrupted electrical connection between the second electrical conductor and the first electrical conductor through the fins. | 02-10-2011 |
20110079874 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 04-07-2011 |
20110079875 | ANTI-FUSE AND METHOD FOR FORMING THE SAME, UNIT CELL OF NON VOLATILE MEMORY DEVICE WITH THE SAME - There is provided an anti-fuse, including a gate dielectric layer formed over a substrate, a gate electrode, including a body portion and one or more protruding portions extending from the body portion, the body portion and the one or more protruding portions being formed to contact on the gate dielectric layer, and a junction region formed in a portion of the substrate exposed by sidewalls of the one or more protruding portions. | 04-07-2011 |
20110095394 | ANTIFUSE AND METHOD OF MAKING THE ANTIFUSE - A method of making an antifuse includes providing a substrate having a bit line diffusion region and a capacitor diffusion region. A gate dielectric layer is formed over the substrate, and a word line is formed on the gate dielectric layer. An oxide layer is formed on the capacitor diffusion region, in a separate process step from forming the gate dielectric layer. A select line contact is formed above and contacting the oxide layer to form a capacitor having the oxide layer as a capacitor dielectric layer of the capacitor. The select line contact is configured for applying a voltage to cause permanent breakdown of the oxide layer to program the antifuse. | 04-28-2011 |
20110101496 | FOUR-TERMINAL ANTIFUSE STRUCTURE HAVING INTEGRATED HEATING ELEMENTS FOR A PROGRAMMABLE CIRCUIT - The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming. | 05-05-2011 |
20110115049 | Non-volatile memory devices, methods of manufacturing and methods of operating the same - A non-volatile memory device includes: at least one horizontal electrode; at least one vertical electrode disposed to intersect the at least one horizontal electrode at an intersection region; at least one data layer disposed at the intersection region and having a conduction-insulation transition property; and at least one anti-fuse layer connected in series with the at least one data layer. | 05-19-2011 |
20110140236 | Integrated Circuit with Pads Connected by an Under-Bump Metallization and Method for Production Thereof - A semiconductor device includes a semiconductor chip. External connection pads and further pads are disposed over a surface of the semiconductor chip. Selected ones of the further pads are electrically connected to one another so as to activate selected functions within the semiconductor chip. | 06-16-2011 |
20110169129 | ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD - Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device. | 07-14-2011 |
20110221031 | SYSTEM AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ANTI-FUSE IN CONJUNCTION WITH A TUNGSTEN PLUG PROCESS - A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse. | 09-15-2011 |
20110254121 | PROGRAMMABLE ANTI-FUSE STRUCTURES WITH CONDUCTIVE MATERIAL ISLANDS - Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features. | 10-20-2011 |
20110254122 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of one embodiment of the present invention is to provide an antifuse which has low writing voltage. The antifuse is used for a memory element for a read only memory device. The antifuse includes a first conductive layer, an insulating layer, a semiconductor layer, and a second conductive layer. The insulating layer included in the antifuse is a silicon oxynitride layer formed by adding ammonia to a source gas. When hydrogen is contained in the layer at greater than or equal to 1.2×10 | 10-20-2011 |
20110309472 | Anti-Fuse Element - An anti-fuse element that includes first and second electrode films on both of upper and lower surfaces of a dielectric film to form an element body. When an operation voltage is applied to the element body, the first and second electrode films are fused by heat generation by electrification, whereby balled portions are formed, and a crack also occurs in the dielectric film. Then, the balled portions are enlarged, the dielectric film is completely divided, and the first and second electrode films are welded and integrated with each other in a mode of tangling end portions of the dielectric film, and form bonded portions that turn the anti-fuse element into a conducting state. | 12-22-2011 |
20120001296 | P-I-N DIODE CRYSTALLIZED ADJACENT TO A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL - A vertically oriented p-i-n diode is provided that includes semiconductor material crystallized adjacent a silicide, germanide, or silicide-germanide layer, and a dielectric material arranged electrically in series with the diode. The dielectric material has a dielectric constant greater than 8, and is adjacent a first metallic layer and a second metallic layer. Numerous other aspects are provided. | 01-05-2012 |
20120012977 | SECURE ANTI-FUSE WITH LOW VOLTAGE PROGRAMMING THROUGH LOCALIZED DIFFUSION HEATING - An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude. | 01-19-2012 |
20120018841 | SEMICONDUCTOR DEVICE - A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region. | 01-26-2012 |
20120061796 | Programmable anti-fuse wire bond pads - A mechanically programmable anti-fuse is configured in a thick, top metallic layer of a semiconductor. The metallic layer is selected of a material that possesses malleable properties. The metal anti-fuse programming pad is surrounded, either wholly or in part, by a pad segment. An intervening space between the anti-fuse pad and the pad segment is selected from a predetermined value such that capillary pressure, exerted when a ball-bond is placed atop the anti-fuse pad and the pad segment, causes the pads to deform and shorts to the anti-fuse pad to the pad segment. The shorting, created during the wire bonding process, programs the anti-fuse. | 03-15-2012 |
20120061797 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor device including a substrate, and an anti-fuse element including a first insulator formed on the substrate, a conductive film formed on the first insulator, the conductive film including a silicide film, a contact formed on the substrate, the contact being disposed adjacent to the conductive film with a second insulator interposed between the contact and the conductive film, the contact being short-circuited to the silicide film. | 03-15-2012 |
20120091557 | ANTI-FUSE OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An anti-fuse of a semiconductor device and a method for manufacturing the same are disclosed. In order to achieve stable operation of the anti-fuse, a gate rupture prevention film is formed between a gate pattern and a source/drain junction region and a gate oxide film is formed at both ends of a lower edge of the gate pattern. Therefore, when applying a voltage, the overlapped gate oxide film is ruptured so that a current level is stabilized and the anti-fuse is stably operated. | 04-19-2012 |
20120104544 | SEMICONDUCTOR DEVICE - A semiconductor device adapted such that written information cannot be analyzed even by using a method of analyzing the presence or absence of electric charge, accumulated on a gate electrode, in which a substrate is a first conduction type, for example, p-type semiconductor substrate (for example, silicon substrate), an antifuse has a gate electrode and a second conduction type diffusion layer, the second conduction type diffusion layer is formed in the substrate and has, for example, an n-conduction type, a first contact is connected to the gate electrode, second contacts are formed in a layer identical with the first contact and connected to a region of the substrate in which the second conduction type diffusion layer is not formed, and the second contact is adjacent to the first contact. | 05-03-2012 |
20120104545 | Anti-Fuse Element - An anti-fuse element that includes a capacitance unit having an insulation layer and at least a pair of electrode layers formed on upper and lower surfaces of the insulation layer. The capacitance unit has a protection function against electrostatic discharge. Because the capacitance unit has a protection function against electrostatic discharge, an anti-fuse element can be provided which is less likely to cause insulation breakdown due to electrostatic discharge at the time of, for example, mounting a component. | 05-03-2012 |
20120112312 | Integrated Circuit Chip Customization Using Backside Access - An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements. | 05-10-2012 |
20120112313 | Anti-Fuse Element - An anti-fuse element that includes an insulation layer; a pair of electrode layers on the upper and lower surfaces of the insulation layer; and an extraction electrode formed so as to make contact with a section of the electrode layers that form electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section including short circuit sections that are short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by engulfing the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. Furthermore, the extraction electrode has at least two or more sections in contact with the electrode layer. | 05-10-2012 |
20120126365 | Anti-Fuse Element - An anti-fuse element that includes an insulation layer; a pair of electrode layers formed on upper and lower surfaces of the insulation layer; and an extraction electrode contacting a section of the electrode layers forming electrostatic capacitance with the insulation layer. The anti-fuse element is configured to create a structural change section that includes a short circuit section short-circuited such that the pair of electrode layers are fused mutually to engulf the insulation layer, and a dissipation section with the electrode layers and insulation layer dissipated by the engulfing of the insulation layer, when a voltage not less than the breakdown voltage of the insulation layer is applied. The maximum diameter of a section of the extraction electrode in contact with the electrode layer is larger than the maximum diameter of the structural change section. | 05-24-2012 |
20120126366 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 05-24-2012 |
20120126367 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 05-24-2012 |
20120199943 | SEMICONDUCTOR DEVICE INCLUDING ANTIFUSE ELEMENT - An element isolation region exists at a side opposite to a diffusion layer region as seen from a channel region, without another electrode to which the same potential as one applied to the diffusion layer region is applied interposed between the channel region and the element isolation region. The electric field applied to the gate insulating film is not uniform and the magnitude of the electric field is increased when approaching closer to the diffusion layer region. Therefore, breakdown is likely to occur at parts closer to the diffusion layer region. | 08-09-2012 |
20120248568 | METHOD FOR CONTROLLING THE ELECTRICAL CONDUCTION BETWEEN TWO METALLIC PORTIONS AND ASSOCIATED DEVICE - A method for controlling the electrical conduction between two electrically conductive portions may include placing of an at least partially ionic crystal between the two electrically conductive portions. The crystal may include at least one surface region coupled to the two electrically conductive portions. The surface region is insulating under the application of an electrical field to the surface region, and electrically conductive in the absence of the electrical field. An application or not of an electrical field to the at least one surface region reduces or establishes the electrical conduction. | 10-04-2012 |
20120261795 | ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD - Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device. | 10-18-2012 |
20130009278 | STACKED SEMICONDUCTOR DEVICE INCLUDING ESD PROTECTION CIRCUITS AND METHOD OF FABRICATING THE STACKED SEMICONDUCTOR DEVICE - A stacked semiconductor device includes a first semiconductor die that has a front side electrically coupled to a substrate pad, the substrate pad is connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first ESDs, and TSVs, and the TSVs are coupled to the first integrated circuit and the first ESDs. A second semiconductor die is stacked above the backside of the first semiconductor die, the second semiconductor die includes a second integrated circuit that is electrically connected to the TSVs and second ESDs, and the second ESDs is electrically disconnected from the TSVs. The TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die. | 01-10-2013 |
20130020674 | FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE - A semiconductor structure includes a semiconductor substrate; a semiconductor device formed in and over the substrate; a plurality of interconnect layers over the semiconductor device; an interconnect pad over a top surface of the plurality of interconnect layers, wherein the interconnect pad is coupled to the semiconductor device through the plurality of interconnect layers; a contiguous seal ring surrounding the semiconductor device and extending vertically from the substrate to the top surface of the plurality of interconnect layers; and a fuse coupled between the interconnect pad and the seal ring, wherein the fuse is in a non-conductive state. | 01-24-2013 |
20130062728 | BEOL ANTI-FUSE STRUCTURES FOR GATE LAST SEMICONDUCTOR DEVICES - An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure. | 03-14-2013 |
20130093044 | SEMICONDUCTOR DEVICE - A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (≧2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m≧n≧2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal. | 04-18-2013 |
20130119510 | DEVICES INCLUDING A P-I-N DIODE DISPOSED ADJACENT A SILICIDE IN SERIES WITH A DIELECTRIC MATERIAL - A device is provided that includes a vertically oriented p-i-n diode that includes semiconductor material, a silicide, germanide, or silicide-germanide layer disposed adjacent the vertically oriented p-i-n diode, and a dielectric material arranged electrically in series with the vertically oriented p-i-n diode. The dielectric material is disposed between a first conductive layer and a second conductive layer, and is selected from the group consisting of HfO | 05-16-2013 |
20130299940 | BEOL ANTI-FUSE STRUCTURES FOR GATE LAST SEMICONDUCTOR DEVICES - An approach is provided for semiconductor devices including an anti-fuse structure. The semiconductor device includes a first metallization layer including a first portion of a first electrode and a second electrode, the second electrode being formed in a substantially axial plane surrounding the first portion of the first electrode, with a dielectric material in between the two electrodes. An ILD is formed over the first metallization layer, a second metallization layer including a second portion of the first electrode is formed over the ILD, and at least one via is formed through the ILD, electrically connecting the first and second portions of the first electrode. Breakdown of the dielectric material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure. | 11-14-2013 |
20130307115 | ANTI-FUSE STRUCTURE AND FABRICATION - A method and structure of a non-intrinsic anti-fuse structure. The anti-fuse structure has a first electrode, a second electrode, a first dielectric, and second dielectric. The first and second dielectrics have an interface which couples electrodes. The length along the interface which couples the electrodes is called the predetermined length. When the anti-fuse is programmed a conductive link forms along the interface to connect the first and second electrodes. The anti-fuse structure can be single-level or dual-level. The predetermined length can be less than spacing between adjacent electrodes when a dual-level structure is used. The anti-fuse structures have the advantage that they can be programmed at lower voltages than intrinsic structures and no extra steps are needed to integrate the anti-fuses with active structures. | 11-21-2013 |
20130307116 | Method and System for Split Threshold Voltage Programmable Bitcells - A bitcell can include an insulating area, a first doping, a second doping, and a gate terminal for the insulating area. The second doping can be proximate to the first doping and proximate to the insulating area. The second doping can be characterized by a lower threshold voltage than the first doping. The bitcell can be configured for programming by a voltage on the gate terminal that results in a conductive hole selectively burned in the insulating area between the gate terminal and the first doping. | 11-21-2013 |
20140015095 | Dual Anti-Fuse - According to one exemplary implementation, a dual anti-fuse structure includes a first channel in a common semiconductor fin adjacent to a first programmable gate. The dual anti-fuse structure further includes a second channel in said common semiconductor fin adjacent to a second programmable gate. A first anti-fuse is formed between the first channel and the first programmable gate. Furthermore, a second anti-fuse is formed between the second channel and the second programmable gate. The first programmable gate can be on a first sidewall of the common semiconductor fin and can comprise a first gate dielectric and a first electrode. The second programmable gate can be on a second sidewall of the common semiconductor fin and can comprise a second gate dielectric and a second electrode. | 01-16-2014 |
20140015096 | ANTI-FUSE OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE AND SYSTEM EACH INCLUDING THE SEMICONDUCTOR DEVICE, AND METHOD FOR FORMING THE ANTI-FUSE - An anti-fuse based on a Field Nitride Trap (FNT) is disclosed. The anti-fuse includes a first active pillar including a first junction, a second active pillar including a second junction, a selection line buried between the first active pillar and the second active pillar, and a trap layer for electrically coupling the first junction to the second junction by trapping minority carriers according to individual voltages applied to the first junction, the second junction and the selection line. As a result, the fuse can be highly integrated through the above-mentioned structure, and programming of the fuse can be easily achieved. | 01-16-2014 |
20140021581 | LOW COST ANTI-FUSE STRUCTURE - An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. | 01-23-2014 |
20140048905 | LOW COST ANTI-FUSE STRUCTURE - An anti-fuse structure is provided in which an anti-fuse material liner is embedded within one of the openings provided within an interconnect dielectric material. The anti-fuse material liner is located between a first conductive metal and a second conductive metal which are also present within the opening. A diffusion barrier liner separates the first conductive metal from any portion of the interconnect dielectric material. The anti-fuse structure is laterally adjacent an interconnect structure that is formed within the same interconnect dielectric material as the anti-fuse structure. | 02-20-2014 |
20140070363 | ELECTRONIC ANTI-FUSE - An electronic anti-fuse structure, the structure including an M | 03-13-2014 |
20140070364 | ANTI-FUSE DEVICE - An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate. | 03-13-2014 |
20140103485 | ANTIFUSE DEVICE FOR INTEGRATED CIRCUIT - The present disclosure relates to an antifuse for preventing a flow of electrical current in an integrated circuit. One such antifuse includes a reactive material and a silicon region thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. Another such antifuse includes a reactive material, at least one metal and a silicon region adjacent to the at least one metal and thermally coupled to the reactive material, where an electrical current to the reactive material causes the reactive material to release heat which transitions the silicon region from a high resistance state to a low resistance state. | 04-17-2014 |
20140124892 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a semiconductor device is disclosed. An anti-fuse is formed at a buried bit line such that the area occupied by the anti-fuse is smaller than that of a conventional planar-gate-type anti-fuse, and a breakdown efficiency of an insulation film is increased. This results in an increase in reliability and stability of the semiconductor device. A semiconductor device includes a line pattern formed over a semiconductor substrate, a device isolation film formed at a center part of the line pattern, a contact part formed at both sides of the line pattern, configured to include an oxide film formed over the line pattern, and a bit line formed at a bottom part between the line patterns, and connected to the contact part. | 05-08-2014 |
20140175601 | ANTI-FUSE STRUCTURE AND ANTI-FUSE PROGRAMMING METHOD - An anti-fuse structure includes a substrate having at least a shallow trench isolation formed therein, a notch formed between the substrate and the STI, an electrode structure formed on the substrate, the electrode structure filling the notch, and a doped region formed in the substrate on a side of the electrode structure opposite to the notch. | 06-26-2014 |
20140183689 | ANTI-FUSE ARRAY OF SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region. | 07-03-2014 |
20140210043 | INTEGRATED CIRCUIT DEVICE FEATURING AN ANTIFUSE AND METHOD OF MAKING SAME - One feature pertains to an integrated circuit that includes an antifuse having a conductor-insulator-conductor structure. The antifuse includes a first conductor plate, a dielectric layer, and a second conductor plate, where the dielectric layer is interposed between the first and second conductor plates. The antifuse transitions from an open circuit state to a closed circuit state if a programming voltage V | 07-31-2014 |
20140291801 | ANTI-FUSE STRUCTURE AND PROGRAMMING METHOD THEREOF - A method of programming an anti-fuse includes steps as follows. First, an insulating layer is provided. An anti-fuse region is defined on the insulating layer. An anti-fuse is embedded within the anti-fuse region of the insulating layer. The anti-fuse includes at least a first conductor and a second conductor. Then, part of the insulating layer is removed by a laser to form an anti-fuse opening in the insulating layer. Part of the first conductor and part of the second conductor are exposed through the anti-fuse opening. After that, a under bump metallurgy layer is formed in the anti-fuse opening to connect the first conductor and the second conductor electrically. | 10-02-2014 |
20140361400 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide electrostatic discharge protection structures and methods for forming the same. An exemplary structure can include a semiconductor chip including a through hole. The structure can further include a through silicon via (TSV) structure disposed within the through hole and passing through the semiconductor chip. The TSV structure can have a first surface and a second surface. The structure can further include a tunneling dielectric layer disposed on the first surface of the TSV structure. The tunneling dielectric layer can have a surface area covering a top view surface area of the TSV structure and a surface portion of the semiconductor chip surrounding the TSV structure. Yet further, the structure can include a metal material discretely dispersed in the tunneling dielectric layer, a first electrode disposed on the tunneling dielectric layer, and a second electrode disposed on the second surface of the TSV structure. | 12-11-2014 |
20150014811 | ANTIFUSES AND METHODS OF FORMING ANTIFUSES AND ANTIFUSE STRUCTURES - Antifuses having two or more materials with differing work function values may be fabricated as recessed access devices and spherical recessed access devices for use with integrated circuit devices and semiconductor devices. The use of materials having different work function values in the fabrication of recessed access device antifuses allows the breakdown areas of the antifuse device to be customized or predicted. | 01-15-2015 |
20150115401 | TECHNIQUE FOR FABRICATION OF MICROELECTRONIC CAPACITORS AND RESISTORS - A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits. | 04-30-2015 |
20150332980 | PROGRAMMABLE STITCH CHAINING OF DIE-LEVEL INTERCONNECTS FOR RELIABILITY TESTING - A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state. | 11-19-2015 |
20160020172 | Anti-fuse on and/or in Package - A package structure includes an integrated circuit die, a redistribution structure, an anti-fuse, and external connectors. The integrated circuit die is embedded in an encapsulant. The redistribution structure is on the encapsulant and is electrically coupled to the integrated circuit die. The anti-fuse is external to the integrated circuit die and the redistribution structure. The anti-fuse is mechanically and electrically coupled to the redistribution structure. The external connectors are on the redistribution structure, and the redistribution structure is disposed between the external connectors and the encapsulant. | 01-21-2016 |
20160027863 | Integrated Circuitry, Methods of Forming Capacitors, and Methods of Forming Integrated Circuitry Comprising an Array of Capacitors and Circuitry Peripheral to the Array - A method of forming capacitors includes providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings include at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator. Other aspects are disclosed, including integrated circuitry independent of method of manufacture. | 01-28-2016 |
20160163642 | WIRING STRUCTURE FOR TRENCH FUSE COMPONENT WITH METHODS OF FABRICATION - The present disclosure generally relates to a wiring structure for a fuse component and corresponding methods of fabrication. A wiring structure for a fuse component according to the present disclosure can include: a first electrical terminal embedded within a doped conductive layer, the doped conductive layer being positioned between two insulator layers of an integrated circuit (IC) structure; a dielectric liner positioned between the first electrical terminal and the doped conductive layer; a second electrical terminal embedded within the doped conductive layer; wherein each of the first electrical terminal and the second electrical terminal are further embedded in one of the two insulator layers, and the dielectric liner is configured to degrade upon becoming electrically charged. | 06-09-2016 |
20160189791 | Discrete Three-Dimensional One-Time-Programmable Memory - The present invention discloses a discrete three-dimensional one-time-programmable memory (3D-OTP). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures. | 06-30-2016 |
20160189792 | Discrete Three-Dimensional One-Time-Programmable Memory - The present invention discloses a discrete three-dimensional one-time-programmable memory (3D-OTP). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures. | 06-30-2016 |
20160204063 | DIELECTRIC THIN FILM ELEMENT, ANTIFUSE ELEMENT, AND METHOD OF PRODUCING DIELECTRIC THIN FILM ELEMENT | 07-14-2016 |
20180025976 | METHOD FOR PROVIDING ELECTRICAL ANTIFUSE INCLUDING PHASE CHANGE MATERIAL | 01-25-2018 |
20180025977 | ELECTRICAL ANTIFUSE HAVING AIRGAP OR SOLID CORE | 01-25-2018 |
20180025978 | METHOD OF MAKING ELECTRICAL ANTIFUSE | 01-25-2018 |
20180025979 | ELECTRICAL ANTIFUSE | 01-25-2018 |
20180025980 | ELECTRICAL ANTIFUSE HAVING AIRGAP OR SOLID CORE | 01-25-2018 |
20180025981 | METHOD FOR PROVIDING ELECTRICAL ANTIFUSE INCLUDING PHASE CHANGE MATERIAL | 01-25-2018 |