Entries |
Document | Title | Date |
20080197403 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions. | 08-21-2008 |
20080203464 | ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY AND ARRAY - A memory device, array and method of arranging where the memory device includes a memory cell region including a plurality of memory cells. Each memory cell includes a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. Cell lines extend among the memory cells. A connection region is provided for electrically coupling contacts and one or more of the cell lines. A non-memory region has embedded logic. Memory cells are arrayed at a cell pitch, with cell lines extending from cell to cell and arrayed substantially at the cell pitch, and with contacts arrayed substantially at the cell pitch forming a high density memory device. | 08-28-2008 |
20080203465 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor device including the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer. | 08-28-2008 |
20080211008 | MANUFACTURING METHOD OF FLASH MEMORY DEVICE - Embodiments relate to a manufacturing method of a flash memory device which improves electrical characteristics by reducing or preventing void generation. A manufacturing method of a flash memory device according to embodiments includes forming a plurality of gate patterns over a semiconductor substrate including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate. A spacer layer may be formed as a compound insulating layer structure over the side wall of the gate pattern. A source/drain area may be formed over the semiconductor substrate at both sides of the control gate. An insulating layer located at the outermost of the spacer layer may be removed. A contact hole may be formed between the gate patterns by forming and patterning the interlayer insulating layer. A contact plug may be formed in the contact hole. | 09-04-2008 |
20080211009 | Process for manufacturing an electronic device integrated on semiconductor substrate comprising non volatile floating gate memories and an associated circuitry and corresponding electronic device - An embodiment of a process is described for manufacturing a non volatile memory electronic device integrated on a semiconductor substrate which comprises a matrix of non volatile memory cells, the memory cells being organized in rows, called word lines, and columns, called bit lines and an associated circuitry comprising high voltage transistors and low voltage transistors, the process comprising the steps for realizing:
| 09-04-2008 |
20080217675 | Novel profile of flash memory cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 09-11-2008 |
20080217676 | ZIRCONIUM SILICON OXIDE FILMS - Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed. | 09-11-2008 |
20080217677 | Non-volatile semiconductor memory device with alternative metal gate material - A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material. | 09-11-2008 |
20080224202 | NON-VOLATILE MEMORY - A non-volatile memory includes a substrate, a number of isolation layers, a number of active layers, a number of floating gates, a number of control gates and a number of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates. | 09-18-2008 |
20080230828 | GATE STRUCTURE OF A NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A non-volatile memory device includes a substrate that is divided into a field region and an active region by isolation layer patterns. The active region has an active trench for increasing an effective area of the active region. A tunnel oxide layer is formed on the active region. A floating gate pattern is formed on the tunnel oxide layer to fill up the active trench. A dielectric layer pattern is formed on the floating gate pattern. A control gate pattern is formed on the dielectric layer pattern. Thus, the non-volatile memory device has an increased effective area of the active region so that the non-volatile memory device may have improved operational characteristics. | 09-25-2008 |
20080237691 | SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME - A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device. | 10-02-2008 |
20080237692 | Method of forming floating gate, non-volatile memory device using the same, and fabricating method thereof - Provided is a method of forming a floating gate, a non-volatile memory device using the same, and a method of fabricating the non-volatile memory device, in which nano-crystals of nano-size whose density and size can be easily adjusted, are synthesized using micelles so as to be used as the floating gate of the non-volatile memory device. The floating gate is fabricated by forming a tunnel oxide film on the semiconductor substrate, coating a gate formation solution on the tunnel oxide film in which the gate formation solution includes micelle templates into which precursors capable of synthesizing metallic salts in nano-structures formed by a self-assembly method are introduced, and arranging the metallic salts on the tunnel oxide film by removing the micelle templates, to thereby form the floating gate. | 10-02-2008 |
20080237693 | Storage of non-volatile memory device and method of forming the same - There is provided a storage of a non-volatile memory device and a method of forming the same. The storage of example embodiments may include a bottom electrode, a first tunneling insulating layer on the bottom electrode, a middle electrode on the first tunneling insulating layer, a second tunneling insulating layer on the middle electrode, and a top electrode on the second tunneling insulating layer. The first and second tunneling insulating layers may be formed of metal oxide having a thickness from about several Å to about several tens Å and a storage may be formed to have a width of about several tens nm. Therefore, a multi bit storage, increased integration, increased operation speed and decreased power consumption may be realized. | 10-02-2008 |
20080251835 | Semiconductor memory device with charge traps - A memory cell in a semiconductor memory device has a pair of charge traps formed on opposite sides of a control electrode, above variable resistance regions in the semiconductor substrate. Each charge trap includes a tunnel oxide film, a dual-layer charge trapping film, and a top oxide film. The dual-layer charge trapping film includes a silicon-rich silicon nitride layer or amorphous silicon layer adjacent to the tunnel oxide film, and a stoichiometric or nitrogen-rich silicon nitride layer adjacent to the top oxide film. Most charges injected into the charge trapping film are trapped in the layer adjacent to the tunnel oxide film, near the substrate, which facilitates the reading of the data that the trapped charges represent. | 10-16-2008 |
20080272424 | Nonvolatile Memory Device Having Fast Erase Speed And Improved Retention Characteristics And Method For Fabricating The Same - Disclosed herein is a nonvolatile memory device that includes a substrate, a tunneling layer over the substrate, a charge trapping layer over the tunneling layer, an insulating layer for improving retention characteristics over the charge trapping layer, a blocking layer over the insulating layer, and a control gate electrode over the blocking layer. Also disclosed herein is a method of making the device. | 11-06-2008 |
20080272425 | Semiconductor Storage Element and Manufacturing Method Thereof - A semiconductor storage element includes: a semiconductor layer constituted of a line pattern with a predetermined width formed on a substrate; a quantum dot forming an electric charge storage layer formed on the semiconductor layer through a first insulating film serving as a tunnel insulating film; an impurity diffusion layer formed in a surface layer of the semiconductor layer so as to sandwich the quantum dot therebetween; and a control electrode formed on the quantum dot through a second insulating film. | 11-06-2008 |
20080272426 | Nonvolatile Memory Transistors Including Active Pillars and Related Methods and Arrays - Nonvolatile memory transistors including active pillars having smooth side surfaces with an acute inward angle are provided. The transistor has an active pillar having smooth side surfaces with an acute inward angle and protrudes from semiconductor substrate. A gate electrode surrounds the side surfaces of the active pillar. A charge storage layer is provided between the active pillar and the gate electrode. Nonvolatile memory arrays including the transistor and related methods of fabrication are also provided. | 11-06-2008 |
20080277714 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a control gate formed along a first direction over a substrate, an active region formed over the substrate, the active region being defined along a second direction crossing the control gate and including a fin type protruding portion having rounded top corners at a region where the control gate and the active region overlap, a floating gate formed over a surface of the protruding portion of the active region below the control gate and formed to a substantially uniform thickness along the surface profile of the protruding portion of the active region, a tunneling insulation layer formed between the floating gate and the active region, and a dielectric layer formed between the floating gate and the control gate. | 11-13-2008 |
20080277715 | Dielectric film and formation method thereof, semiconductor device, non-volatile semiconductor memory device, and fabrication method for a semiconductor device - In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas. | 11-13-2008 |
20080277716 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having a device formation region, a tunnel insulating film formed on the device formation region, a floating gate electrode formed on the tunnel insulating film, isolation insulating films which cover side surfaces of the device formation region, side surfaces of the tunnel insulating film, and side surfaces of a lower portion of the floating gate electrode, an inter-electrode insulating film which covers an upper surface and side surfaces of an upper portion of the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein upper corner portions of the floating gate electrode are rounded as viewed from a direction parallel with the upper surface and the side surfaces of the upper portion of the floating gate electrode. | 11-13-2008 |
20080283900 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist pattern as a mask, forming an intermediate insulating film on the first conductive film, forming a second conductive film on the intermediate insulating film, and forming, by patterning the first conductive film, the intermediate insulating film, and the second conductive film, a flash memory cell and a structure constructed by forming a lower conductor pattern, a segment of the intermediate insulating film, and a dummy gate electrode in this stacking order. | 11-20-2008 |
20080296655 | MULTI-TIME PROGRAMMABLE MEMORY AND METHOD OF MANUFACTURING THE SAME - A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer. | 12-04-2008 |
20080296656 | SEMICONDUCTOR DEVICE - A semiconductor device includes a tunnel insulation film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulation film, an inter-electrode insulation film formed on the floating gate electrode, a control gate electrode formed on the inter-electrode insulation film, a pair of oxide films which are formed between the tunnel insulation film and the floating gate electrode and are formed near lower end portions of a pair of side surfaces of the floating gate electrode, which are parallel in one of a channel width direction and a channel length direction, and a nitride film which is formed between the tunnel insulation film and the floating gate electrode and is formed between the pair of oxide films. | 12-04-2008 |
20080296657 | Non-Volatile Memory Devices and Methods of Manufacturing Non-Volatile Memory Devices - A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction. | 12-04-2008 |
20080296658 | PROCESS FOR MANUFACTURING A MEMORY DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE AND COMPRISING NANOCRISTAL MEMORY CELLS AND CMOS TRANSISTORS - An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride layer having an initial thickness, placed above a nanocrystal layer, in the memory area and the formation in the circuitry area of at least one submicron gate oxide. The process also provides that the initial thickness is such as to allow a complete transformation of the nitride layer into an oxide layer at upon formation of said at least one submicron gate oxide. | 12-04-2008 |
20080303079 | Non-volatile Memory Cells Including Fin Structures - A method of forming a non-volatile memory device may include forming a fin protruding from a substrate, forming a tunnel insulating layer on portions of the fin, and forming a floating gate on the tunnel insulting layer so that the tunnel insulating layer is between the floating gate and the fin. A dielectric layer may be formed on the floating gate so that the floating gate is between the dielectric layer and the fin, and a control gate electrode may be formed on the dielectric layer so that the dielectric layer is between the control gate and the fin. Related devices are also discussed. | 12-11-2008 |
20080315287 | FLASH MEMORY AND METHOD OF FABRICATING THE SAME - A flash memory comprising a substrate, a stacked structure over the substrate, a source, a drain and a source-side spacer is provided. The stacked structure includes a tunneling oxide layer, a floating gate on the tunneling oxide layer, an inter-gate dielectric layer on the floating gate and a control gate on the inter-gate dielectric layer. The source and the drain are disposed in the substrate on the sides of the floating gate, respectively. The source-side spacer is disposed on a sidewall of the stacked structure near the source, thereby preventing the tunneling oxide layer and the inter-gate dielectric layer near the source from being re-oxidized, resulting in an increased thickness. | 12-25-2008 |
20080315288 | MEMORY CELL OF NONVOLATILE SEMICONDUCTOR MEMORY - A memory cell of a nonvolatile semiconductor memory includes a semiconductor region, source/drain areas arranged separately from each other in the semiconductor region, a tunnel insulating film arranged on a channel region between the diffusion areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulator arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulator. The inter-electrode insulator includes lanthanoid-based metal Ln, aluminum Al, and oxygen O, and a composition ratio Ln/(Al+Ln) between the lanthanoid-based metal and the aluminum takes a value within the range of 0.33 to 0.39. | 12-25-2008 |
20080315289 | ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM) DEVICE AND METHODS OF FABRICATING THE SAME - An EEPROM device includes a device isolation layer disposed at a predetermined region of a semiconductor substrate to define active regions, a pair of control gates crossing the device isolation layers and an active region, a pair of selection gates interposed between the control gates to cross the device isolation layers and the active region and a floating gate and an intergate dielectric pattern stacked sequentially between the control gates and the active region The EEPROM device further includes a gate insulation layer of a memory transistor interposed between the floating gate and the active region and a tunnel insulation layer thinner than the gate insulation layer of the memory transistor and a gate insulation layer of a selection transistor interposed between the selection gates and the active region. The tunnel insulation layer is aligned at one side adjacent to the floating gate. | 12-25-2008 |
20080315290 | MEMORY DEVICE AND METHODS FOR ITS FABRICATION - A semiconductor memory device and a method for its fabrication are provided. In accordance with one embodiment of the invention the method comprises the steps of forming a gate insulator and a gate electrode overlying a semiconductor substrate. The gate insulator is etched to form an undercut opening beneath an edge of the gate electrode and the undercut opening is filled with a layered structure comprising a charge trapping layer sandwiched between layers of oxide and nitride. A region of the semiconductor substrate is impurity doped to form a bit line aligned with the gate electrode, and a conductive layer is deposited and patterned to form a word line coupled to the gate electrode. | 12-25-2008 |
20090001448 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device having a cell size of 60 nm or less includes a tunnel insulation film formed in a channel region of a silicon substrate containing a burying insulation film, a first conductive layer formed on the tunnel insulation film, an inter-electrode insulation film formed on the burying insulation film and the first conductive layer, a second conductive layer formed on the inter-electrode insulation film, a side wall insulation film formed on the side walls of the first conductive layer, the second conductive layer, and the inter-electrode insulation film, and an inter-layer insulation film formed on the side wall insulation film. The tunnel insulation film or the inter-electrode insulation film contains a high-dielectric insulation film. The side wall insulation film contains a predetermined concentration of carbon and nitrogen as well as chlorine having a concentration of 1×10 | 01-01-2009 |
20090008698 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAM - A nonvolatile memory device includes an active region which is defined by an isolation layer formed in a substrate and has a recess therein in a channel width direction, wherein an upper portion of the active region having the recess projects over an upper portion of the isolation layer, a lower insulation layer formed along a surface of the active region and a top surface of the isolation layer, a charge storage layer formed over the lower insulation layer, an upper insulation layer formed over the charge storage layer, and a gate electrode formed over the upper insulation layer. | 01-08-2009 |
20090008699 | Non-volatile semiconductor memory device and method of manufacturing the same - Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate. | 01-08-2009 |
20090008700 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics. | 01-08-2009 |
20090014777 | Flash Memory Devices and Methods of Manufacturing the Same - Provided are flash memory devices. Embodiments of such devices may include a tunnel insulator formed on a substrate, a charge-storage layer formed on the tunnel insulator, a lower buffer layer formed on the charge-storage layer, a blocking layer formed on the lower buffer layer, and a first gate electrode formed on the blocking layer. Such devices may include second gate electrode formed on the first gate electrode, such that the lower buffer layer includes a silicon-free insulator, the blocking layer includes oxides or ternary lanthanum compounds, and | 01-15-2009 |
20090039411 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an aspect of an embodiment, a semiconductor device has a substrate a first insulator formed in a first area of the substrate, and a second insulator formed in the second area of the substrate, a first transistor formed over a first device region surrounded by the first area, the first transistor having a first gate insulating film having a first thickness, the first gate insulating film being formed over the first device region, a first gate electrode formed over the first gate insulating film and the second transistor having a second gate insulating film formed over the second device region, a second gate insulating film having a second thickness less than the first thickness of the first gate insulating film, a second gate electrode formed over the second gate insulating film. | 02-12-2009 |
20090039412 | SEMICONDUCTOR DEVICE INCLUDING NONVOLATILE MEMORY AND METHOD OF FABRICATING THE SAME - A semiconductor device including a nonvolatile memory and the fabrication method of the semiconductor device is described. There is provided a semiconductor device, including a semiconductor substrate, a nonvolatile memory cell including a first MOS transistor having a first gate formed on the semiconductor substrate, and source-drain regions formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the first gate, the first gate being a layered gate structure having a tunnel gate insulating film, a first gate electrode film, an inter-gate insulating film and a second gate electrode film, and a logic circuit including a second MOS transistor having a second gate formed on the semiconductor substrate, and the source-drain regions formed in the semiconductor substrate to interpose a surface region of the semiconductor substrate beneath the second gate, the second gate being a gate structure having a gate insulating film, the first gate electrode film and the second gate electrode film. | 02-12-2009 |
20090039413 | METHOD TO FORM UNIFORM TUNNEL OXIDE FOR FLASH DEVICES AND THE RESULTING STRUCTURES - Thin oxide films are grown on silicon which has been previously treated with a gaseous or liquid source of chloride ions. The resulting oxide is of more uniform thickness than obtained on untreated silicon, thereby allowing a given charge to be stored on a floating gate formed over said oxide for a longer time than previously required for a structure not so treated. | 02-12-2009 |
20090045452 | Structure and Method of Sub-Gate NAND Memory with Bandgap Engineered SONOS Devices - A bandgap engineered SONOS device structure for design with various AND architectures. The BE-SONOS device structure comprises a spacer oxide disposed between a control gate overlaying an oxide-nitride-oxide-nitride-oxide stack and a sub-gate overlaying a gate oxide. In one example, a BE-SONOS sub-gate-AND array architecture has multiple strings of SONONOS devices with sub-gate lines and diffusion bit lines. In another example, a BE-SONOS sub-gate-AND architecture has multiple strings of SONONOS devices with sub-gate lines, relying on the sub-gate lines that create inversions to substitute for the diffusion bit lines. | 02-19-2009 |
20090050952 | FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer. | 02-26-2009 |
20090057750 | NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory element includes a semiconductor substrate, a source region and a drain region which are provided separately in the semiconductor substrate, a tunnel insulating layer which is provided between the source region and the drain region on the semiconductor substrate, a charge storage layer which is provided on the tunnel insulating layer, a block insulating layer which is provided on the charge storage layer and includes a crystallized lanthanum aluminate layer, and a control gate electrode which is provided on the block insulating layer. | 03-05-2009 |
20090057751 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an example of the present invention includes a semiconductor region, source/drain areas arranged separately in the semiconductor region, a tunnel insulating film arranged on a channel region between the source/drain areas, a floating gate electrode arranged on the tunnel insulating film, an inter-electrode insulating film arranged on the floating gate electrode, and a control gate electrode arranged on the inter-electrode insulating film. The inter-electrode insulating film includes La, Al and Si. | 03-05-2009 |
20090065846 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A manufacturing method of a non-volatile memory includes forming a first dielectric layer, a first conductive layer, and a first cap layer sequentially on a substrate to form first gate structures; conformally forming a second dielectric layer on the substrate; forming a first spacer having a larger wet etching rate than the second dielectric layer on each sidewall of each first gate structure; partially removing the first and second dielectric layers to expose the substrate. A third dielectric layer is formed on the substrate between the first gate structures; removing the first spacer; forming a second conductive layer on the third dielectric layer; removing the first cap layer and a portion of the first conductive layer to form second gate structures; and forming doped regions in the substrate at two sides of each second gate structure. | 03-12-2009 |
20090065847 | FLASH MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - An embedded flash memory device and a method for fabricating the same which reduces the size of a memory device using logic CMOS fabricating processes and enhancing a coupling ratio of the memory device. The flash memory device includes a coupling oxide layer on an active area of a semiconductor substrate, a first control gate formed on and/or over the coupling oxide layer and a second control gate formed on and/or over and enclosing lateral sidewalls of the coupling oxide layer and the first control gate. | 03-12-2009 |
20090072294 | Method of manufacturing a non-volatile memory device - A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the tunnel oxide layer using a trisilane (Si | 03-19-2009 |
20090072295 | Flash EEPROM device and method for fabricating the same - In a flash EEPROM device, and method for fabricating the same, no bit line contact is made, thereby minimizing a design rule between a contact and a gate. Thus, cell size may be reduced. The flash EEPROM device includes a semiconductor substrate having an active area defined in a bit line direction and a word line direction, a plurality of floating gates formed in the word line direction, an interlayer polysilicon oxide film formed on a floating gate, a control gate formed on the interlayer polysilicon oxide film, source and drain electrodes disposed between adjacent floating gates in the word line direction, a buried N | 03-19-2009 |
20090085094 | Floating gate having multiple charge storing layers, method of fabricating the floating gate, non-volatile memory device using the same, and fabricating method thereof - Provided is a floating gate having multiple charge storing layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storing layers using metal nano-crystals of nano size is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-crystal film which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of metal nano-crystals for trapping charges are deposited. The floating gate is made by self-assembling the metal nano-crystals on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature. | 04-02-2009 |
20090085095 | Profile Engineered Thin Film Devices and Structures - The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch. | 04-02-2009 |
20090096009 | NONVOLATILE MEMORIES WHICH COMBINE A DIELECTRIC, CHARGE-TRAPPING LAYER WITH A FLOATING GATE - A nonvolatile memory cell stores at least 50% of the charge in a dielectric, charge-trapping layer ( | 04-16-2009 |
20090096010 | NONVOLATILE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A nonvolatile memory device and a fabrication method thereof are disclosed. The nonvolatile memory device comprises a tunnel insulating film formed on an active region of a semiconductor substrate, a first conductive layer for a floating gate formed on the tunnel insulating film, a dielectric layer formed on the first conductive layer, a second conductive layer for a control gate formed on the dielectric layer, an etch-stop layer formed on the second conductive layer, and a gate electrode layer formed on the etch-stop layer. Accordingly, there is no difference in the degree to which the conductive layer under the gate electrode layer is etched when etching the gate electrode layer of the memory cell region and the peri region. | 04-16-2009 |
20090096011 | Non-Volatile Memory Device Having Asymmetric Source/Drain Junction and Method for Fabricating the Same - Disclosed herein are non-volatile memory devices with asymmetric source/drain junctions and a method for fabricating the same. According to the method, a gate stack is formed on a semiconductor substrate, and impurity ions are implanted at a predetermined angle to form a source/drain junction in the semiconductor substrate. Thermal treatment of the semiconductor substrate forms an asymmetrically disposed source/drain junction between adjacent gate stacks. | 04-16-2009 |
20090096012 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A flash memory secures a desired coupling ratio in a target thickness by lowering the leakage current through a high-dielectric (k) layer employing a combination of energy band gaps. The flash memory device includes a tunnel insulating layer formed on a semiconductor substrate, a first conductive layer formed on the tunnel insulating layer, a high-dielectric (k) layer having a stacked structure of first, second and third high-k insulating layers formed on the first conductive layer, and a second conductive layer formed on the high-k layer. The first high-k insulating layer has a first energy bandgap, the second high-k insulating layer has a second energy bandgap greater than the first energy bandgap, and the third high-k insulating layer has a third energy bandgap smaller than the second energy bandgap. | 04-16-2009 |
20090108329 | NON-VOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile semiconductor device includes a tunnel insulating film including a ridge and a valley, and a nano floating gate including a nano dot. The ridge and the valley are alternately arranged by a given interval. The nano dot is disposed over the valley of the tunnel insulating film. | 04-30-2009 |
20090121275 | Non-Volatile Memory Devices Including Blocking and Interface Patterns Between Charge Storage Patterns and Control Electrodes and Related Methods - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 05-14-2009 |
20090121276 | NONVOLATILE MEMORY DEVICES WITH RECESSED WORD LINES - A nonvolatile memory device includes a substrate, a device isolation region disposed in the substrate and abutting a sidewall of an active region defined in the substrate, the device isolation region having a recessed portion and a word line crossing the active region and the recessed portion of the device isolation region and conforming to the sidewall adjacent the recessed portion of the device isolation region. The nonvolatile memory device may further include a sense line crossing the active region and the device isolation region parallel to the word line, the sense line overlying a portion of the device isolation region having a top surface at substantially the same level as a top surface of the active region. An edge of the active region adjacent the sidewall may be rounded. | 05-14-2009 |
20090121277 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 05-14-2009 |
20090134446 | SEMICONDUCTOR DEVICE - A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the inter-electrode insulating film includes a main insulating film and a plurality of nano-particles in the main insulating film. | 05-28-2009 |
20090134447 | Flash Memory Device and Method for Manufacturing the Same - A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region. | 05-28-2009 |
20090140318 | NONVOLATILE MEMORIES WITH HIGHER CONDUCTION-BAND EDGE ADJACENT TO CHARGE-TRAPPING DIELECTRIC - In a nonvolatile memory, the tunnel dielectric ( | 06-04-2009 |
20090140319 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory devices and a method of fabricating the same includes sequentially stacking a tunnel insulating layer, a first nano-grain film, a conductive layer for a floating gate, and a second nano-grain film over a semiconductor substrate, forming a trench by etching the second nano-grain film, the conductive layer for the floating gate, the first nano-grain film, the tunnel insulating layer, and the semiconductor substrate, gap-filling the trench with an insulating layer, thus forming an isolation layer, and forming a third nano-grain film on sidewalls of the conductive layer for the floating gate. | 06-04-2009 |
20090140320 | NONVOLATILE MEMORY DEVICE AND METHOD OF FORMING THE NONVOLATILE MEMORY DEVICE INCLUDING GIVING AN UPPER PORTION OF AN INSULATING LAYER AN ETCHING SELECTIVITY WITH RESPECT TO A LOWER PORTION - A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure. | 06-04-2009 |
20090152616 | Semiconductor Device and Method for Manufacturing the Same - Disclosed are a semiconductor device and a method for manufacturing the same. The method includes forming a gate layer on a semiconductor substrate; forming a first oxide layer on the semiconductor substrate; forming a second oxide layer on the first oxide layer; exposing the first oxide layer by removing the second oxide layer other than on side surfaces of the gate layer by etching using a photoresist as a mask; and forming junctions in source/drain regions by implanting a high concentration of N-type ions and/or a high concentration of P-type ions using the second oxide layer as a sidewall mask. | 06-18-2009 |
20090159955 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer. | 06-25-2009 |
20090159956 | NOR FLASH MEMORY AND METHOD OF MANUFACTURING THE SAME - A NOR flash memory has a plurality of memory cell transistors, wherein each memory cell transistor shares the source diffusion layer with another memory cell transistor adjacent thereto on one side thereof in the column direction and shares the drain diffusion layer with another memory cell transistor adjacent thereto on the other side thereof in the column direction, and the width of the source diffusion layer in the column direction is narrower than the width of the drain diffusion layer in the column direction. | 06-25-2009 |
20090166709 | Flash Memory Device and Method of Fabricating the Same - A flash memory device and method of fabricating thereof. In accordance with the method of the invention, a tunnel dielectric layer and an amorphous first conductive layer are formed over a semiconductor substrate. An annealing process to change the amorphous first conductive layer to a crystallized first conductive layer is performed. A second conductive layer is formed on the crystallized first conductive layer. A first etch process to pattern the second conductive layer is performed. A second etch process to remove an oxide layer on the crystallized first conductive layer is performed. A third etch process to pattern the amorphous first conductive layer is performed. | 07-02-2009 |
20090166710 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory device includes: a semiconductor substrate; and a memory cell. The memory cell includes: a source region and a drain region formed at a distance from each other on the semiconductor substrate; a tunnel insulating film formed on a channel region of the semiconductor substrate, the channel region being located between the source region and the drain region; a charge storage film formed on the tunnel insulating film; a charge block film formed on the charge storage film; and a control electrode that is formed on the charge block film. The control electrode includes a Hf oxide film or a Zr oxide film having at least one element selected from the first group consisting of V, Cr, Mn, and Tc added thereto, and having at least one element selected from the second group consisting of F, H, and Ta added thereto. | 07-02-2009 |
20090166711 | Tunnel Insulating Layer of Flash Memory Device and Method of Forming the Same - The present invention discloses a tunnel insulating layer in a flash memory device and a method of forming the same, the method according to the present invention comprises the steps of forming a first oxide layer on a semiconductor substrate through a first oxidation process; forming a nitride layer on an interface between the semiconductor substrate and the first oxide layer through a first nitridation process; forming a second nitride layer on the first oxide layer through a second nitridation process; forming a second oxide layer on the second nitride layer through a second oxidation process; and forming a third nitride layer on the second oxide layer through a third nitridation process. | 07-02-2009 |
20090166712 | NANOCRYSTAL NON-VOLATILE MEMORY CELL AND METHOD THEREFOR - A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces. | 07-02-2009 |
20090194804 | NON-VOLATILE MEMORY CELL - Disclosed herein are non-volatile cells and methods of manufacturing the same. The nonvolatile memory cells include a high voltage device, a low voltage device, and a memory cell formed on a semiconductor substrate. The high voltage device, low voltage device, and memory cell are all self-aligned by using the gates associated with each of the devices as a mask during formation of the respective sources and drains. | 08-06-2009 |
20090194805 | Non-Volatile Memory Device - A non-volatile memory device includes a substrate, an active region, an isolation layer, a tunnel insulation layer, a floating gate, a dielectric layer and a control gate. The active region includes an upper active region having a first width, and a lower active region beneath the upper active region and having a second width substantially larger than the first width. The isolation layer is adjacent to the active region. The tunnel insulation layer is on the upper active region. The floating gate is on the tunnel insulation layer and has a third width substantially larger than the first width. The dielectric layer is on the floating layer. The control gate is on the dielectric layer. | 08-06-2009 |
20090200598 | FLASH MEMORY STRUCTURE WITH ENHANCED CAPACITIVE COUPLING COEFFICIENT RATIO (CCCR) AND METHOD FOR FABRICATION THEREOF - A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio. | 08-13-2009 |
20090212345 | Semiconductor Device and Method for Manufacturing the Same - Disclosed herein are a semiconductor device and a method for manufacturing the same. A method of manufacturing a semiconductor device includes forming a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a gate electrode layer on a semiconductor substrate; patterning the gate electrode layer to expose the second conductive layer; forming a protective layer on a side wall of the gate electrode layer; and etching the exposed second conductive layer, the dielectric layer, and the first conductive layer to form a gate pattern. | 08-27-2009 |
20090212346 | SEMICONDUCTOR MEMORY ELEMENT - A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film. | 08-27-2009 |
20090230455 | STRUCTURE AND METHOD FOR MANUFACTURING MEMORY - The present invention provides a memory device including at least two of a first dielectric on a semiconductor substrate; a floating gates corresponding to each of the at least two gate oxides; a second dielectric on the floating gates; a control gate conductor formed atop the second gate oxide; source and drain regions present in portions of the semiconducting substrate that are adjacent to each portion of the semiconducting substrate that is underlying the at least two of the first gate oxide, wherein the source and drain regions define a length of a channel positioned therebetween; and a low-k dielectric material that is at least present between adjacent floating gates of the floating gates corresponding to each of the at least two gate oxides, wherein the low-k dielectric material is present along a direction perpendicular to the length of the channel positioned therebetween. | 09-17-2009 |
20090230456 | Semiconductor device - A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer. | 09-17-2009 |
20090236653 | Nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and a control gate electrode. The tunnel insulating film is formed on a selected part of a surface of a semiconductor substrate. The floating gate electrode is formed on the tunnel insulating film. At least that interface region of the floating gate electrode, which is opposite to the substrate, is made of n-type Si or metal-based conductive material. The inter-electrode insulating film is formed on the floating gate electrode and made of high-permittivity material. The control gate electrode is formed on the inter-electrode insulating film. At least that interface region of the control gate electrode, which is on the side of the inter-electrode insulating film, is made of a p-type semiconductor layer containing at least one of Si and Ge. | 09-24-2009 |
20090242960 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate, a memory cell provided on the semiconductor substrate and having a stacked gate structure formed by sequentially stacking a tunnel insulation film, a charge storage layer, a block insulation film, and a control gate electrode, a first transistor having a first gate electrode provided on the semiconductor substrate via a gate insulation film, and a resistor element provided on the semiconductor substrate and formed of polysilicon. The control gate electrode is entirely formed of a silicide layer. An upper portion of the first gate electrode partially includes a silicide layer. | 10-01-2009 |
20090250743 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device has side surfaces of neighboring bit lines that do not face each other to reduce a capacitance of a parasitic capacitor formed between adjacent bit lines. The semiconductor memory device includes contact plugs formed on a semiconductor substrate. Each contact plug is disposed between gate patterns. First and second conductive pads extend in different directions and are connected to the contact plugs. First and second pad contact plugs are formed on extended peripheries of the first and second conductive pads, respectively. Each of the first pad contact plugs has a height which differs from a height of each of the second pad contact plugs. First bit lines are connected to the first pad contact plugs, and second bit lines are connected to the second pad contact plugs. | 10-08-2009 |
20090261400 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage insulating film formed on the tunnel insulating film and including at least two separated low oxygen concentration portions and a high oxygen concentration portion positioned between the adjacent low oxygen concentration portions and having a higher oxygen concentration than the low oxygen concentration portions, a charge block insulating film formed on the charge storage insulating film, and control gate electrodes formed on the charge block insulating film and above the low oxygen concentration portions. | 10-22-2009 |
20090267133 | Flash memory device and method for fabricating the same - A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess surface by interposing a tunnel insulating film; a source line formed on the source region across the active region; and control gate electrodes formed at sidewalls of the source line across a portion of the active region where the floating gates are formed. The floating gates and the control gate electrodes are formed by anisotropically etching a conformal conductive film to have a spacer structure. Cell transistor size can be reduced by forming a deposition gate structure at both sides of the source line, and short channel effects can be minimized by forming the channel between the sidewalls of a recess surface. | 10-29-2009 |
20090283816 | BAND ENGINEERED HIGH-K TUNNEL OXIDES FOR NON-VOLATILE MEMORY - A non-volatile memory cell that has a charge source region, a charge storage region, and a crested tunnel barrier layer that has a potential energy profile which peaks between the charge source region and the charge storage region. The tunnel barrier layer has multiple high-K dielectric materials, either as individual layers or as compositionally graded materials. | 11-19-2009 |
20090283817 | FLOATING GATE STRUCTURES - Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon. | 11-19-2009 |
20090283818 | Flash Memory Device and Method of Fabricating the Same - A flash memory device includes an isolation layer formed on an isolation region of a semiconductor substrate, a tunnel insulating layer formed on an active region of the semiconductor substrate, a first conductive layer formed over the tunnel insulating layer, a dielectric layer formed on the first conductive layer and the isolation layer, the dielectric layer having a groove for exposing the isolation layer, a trench formed on the isolation layer and exposed through the groove, and a second conductive layer formed over the dielectric layer the trench. | 11-19-2009 |
20090289295 | Semiconductor Device and Method of Fabricating the same - The invention relates to semiconductor devices and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer, the second conductive layer, the dielectric layer, and the first conductive layer are patterned so that the first conductive layer partially remains to prevent the tunnel insulating layer from being exposed. Sidewalls of the gate electrode layer are etched. A first passivation layer is formed on the entire surface including the sidewalls of the gate electrode layer. At this time, a thickness of the first passivation layer formed on the sidewalls of the gate electrode layer is thicker than that of the first passivation layer formed in other areas. A cleaning process is performed to thereby remove byproducts occurring in the etch process. A gate pattern is formed by etching the first passivation layer, the first conductive layer, and the tunnel insulating layer. | 11-26-2009 |
20090289296 | Semiconductor Device and Method of Fabricating the same - A semiconductor device and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer and the second conductive layer are patterned. A first passivation layer is formed on sidewalls of the gate electrode layer. Gate patterns are formed by etching the dielectric layer, the first conductive layer, and the tunnel dielectric layer, which have been exposed. A second passivation layer is formed on the entire surface along a surface of the gate patterns including the first passivation layer. | 11-26-2009 |
20090294830 | MEMORY DEVICE WITH HIGH DIELECTRIC CONSTANT GATE DIELECTRICS AND METAL FLOATING GATES - A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator. | 12-03-2009 |
20090321809 | GRADED OXY-NITRIDE TUNNEL BARRIER - Briefly, a tunnel barrier for a non-volatile memory device comprising a graded oxy-nitride layer is disclosed. | 12-31-2009 |
20090321810 | NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM - Provided is a non-volatile memory device including; a substrate having source/drain regions and a channel region between the source/drain regions; a tunneling insulating layer formed in the channel region of the substrate; a charge storage layer formed on the tunneling insulating layer; a blocking insulating layer formed on the charge storage layer, and comprising a silicon oxide layer and a high-k dielectric layer sequentially formed; and a control gate formed on the blocking insulating layer, wherein an equivalent oxide thickness of the silicon oxide layer is equal to or greater than that of the high-k dielectric layer. | 12-31-2009 |
20090321811 | MEMORY CELL TRANSISTORS HAVING BANDGAP-ENGINEERED TUNNELING INSULATOR LAYERS, NON-VOLATILE MEMORY DEVICES INCLUDING SUCH TRANSISTORS, AND METHODS OF FORMATION THEREOF - A memory cell transistor comprises: an active region, the active region being elongated in a first direction of extension; a tunnel layer on the active region, the tunnel layer comprising a first tunnel insulating layer, a second tunnel insulating layer on the first tunnel insulating layer and a third tunnel insulating layer on the second tunnel insulating layer; a charge storage layer on the tunnel layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer, the control gate electrode being elongated in a second direction of extension that is transverse the first direction of extension, the active region having a first width in the second direction of extension, the second tunnel insulating layer having a second width in the second direction of extension, the second width being different than the first width. | 12-31-2009 |
20100006920 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to an embodiment may include a plurality of memory cells arranged on a semiconductor substrate includes a tunneling dielectric film on the semiconductor substrate; a floating gate formed on the tunneling dielectric film and corresponding to each of the memory cells; an inter-gate dielectric film on the floating gate; and a control gate on the inter-gate dielectric film, wherein the floating gate corresponding to a single memory cell has a first gate part, a second gate part, and the floating gate has a part that the tunneling dielectric film contacts the inter-gate dielectric film is provided between the first gate part and the second gate part within the memory cell. | 01-14-2010 |
20100006921 | SEMICONDUCTOR MEMORY, SEMICONDUCTOR MEMORY SYSTEM USING THE SAME, AND METHOD FOR PRODUCING QUANTUM DOTS APPLIED TO SEMICONDUCTOR MEMORY - A semiconductor memory includes a composite floating structure where an insulation film is formed on a semiconductor substrate, Si-based quantum dots covered with an extremely thin Si oxide film is formed on the insulation film, silicide quantum dots covered with a high dielectric insulation film are formed on the extremely thin Si oxide film, and Si-based quantum dots covered with a high dielectric insulation film are formed on the high dielectric insulation film. Multivalued memory operations can be conducted at a high speed and with stability by applying a certain positive voltage to a gate electrode to accumulate electrons in the silicide quantum dots and by applying a certain negative voltage and weak light to the gate electrode to emit the electrons from the silicide quantum dots. | 01-14-2010 |
20100012998 | FLASH MEMORY DEVICE WITH STACKED DIELECTRIC STRUCTURE INCLUDING ZIRCONIUM OXIDE AND METHOD FOR FABRICATING THE SAME - A dielectric structure disposed between a floating gate and a control gate of a flash memory device includes: a first dielectric layer; a third dielectric layer having a k-dielectric constant substantially the same as that of the first dielectric layer; and a second dielectric layer disposed between the first dielectric layer and the third dielectric layer, having a greater k-dielectric constant than that of the first and third dielectric layers and formed by alternately and repeatedly stacking a plurality of aluminum oxide (Al | 01-21-2010 |
20100019308 | ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF - An electrically programmable device with embedded EEPROM and method for making thereof. The method includes providing a substrate including a first device region and a second device region, growing a first gate oxide layer in the first device region and the second device region, and forming a first diffusion region in the first device region and a second diffusion region and a third diffusion region in the second device region. Additionally, the method includes implanting a first plurality of ions to form a fourth diffusion region in the first device region and a fifth diffusion region in the second device region. The fourth diffusion region overlaps with the first diffusion region. | 01-28-2010 |
20100044774 | FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed here in is a flash memory device and a method of fabricating the same. In accordance with one aspect of the invention, a flash memory device includes first contact plugs formed over a semiconductor substrate between gate patterns. Second contact plugs are formed over the semiconductor substrate between gate patterns and disposed alternately with the first contact plugs. The second contact plugs having a height greater than the first contact plugs. First and second conductive pads are connected to the first contact plugs. First and second pad contact plugs are formed on extended edge portions of the first and second conductive pads. First bit lines are connected to the first and second pad contact plugs, and second bit lines are connected to the second contact plugs. | 02-25-2010 |
20100052035 | NONVOLATILE SEMICONDUCTOR MEMORY APPARATUS - A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film. | 03-04-2010 |
20100052036 | MEMORY DEVICE AND MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE - A semiconductor device disposed on a substrate is provided. The semiconductor device includes two isolation structures, a first conductive layer, a charge trapping layer, a second conductive layer and a gate dielectric layer. The two isolation structures are disposed in the substrate to define an active area. The second conductive layer across the two isolation structures is disposed on the substrate. The first conductive layer is disposed between the two isolation structures and between the second conductive layer and the substrate. The second conductive layer electrically connects with the first conductive layer. The charge trapping layer is disposed on the substrate. The gate dielectric layer is disposed between the first conductive layer and the substrate. An interface between the two isolation structures and the first conductive layer is covered by the charge trapping layer to restrain the kink effect. | 03-04-2010 |
20100059808 | NONVOLATILE MEMORIES WITH CHARGE TRAPPING DIELECTRIC MODIFIED AT THE EDGES - A nonvolatile memory cell has charge trapping dielectric ( | 03-11-2010 |
20100078702 | Semiconductor storage device and method for manufacturing the same - A semiconductor storage device according to the present invention includes: a semiconductor substrate; an embedded insulator embedded in a trench formed in the semiconductor substrate and having an upper portion protruding above a top surface of the semiconductor substrate; a first insulating film formed on the top surface of the semiconductor substrate; a floating gate formed on the first insulating film at a side of the embedded insulator, having a side portion arching out above the embedded insulator, and having a side surface made of a flat surface and a curved surface continuing below the flat surface; a second insulating film contacting an upper surface, the flat surface and the curved surface of the floating gate; and a control gate opposing the upper surface, the flat surface and the curved surface of the floating gate across the second insulating film. | 04-01-2010 |
20100109069 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF - A nonvolatile semiconductor storage device including a number of memory cells formed on a semiconductor substrate, each of the memory cells has a tunnel insulating film, a charge storage layer, a block insulating film, and a gate electrode which are formed in sequence on the substrate. The gate electrode is structured such that at least first and second gate electrode layers are stacked. The dimension in the direction of gate length of the second gate electrode layer, which is formed on the first gate electrode layer, is smaller than the dimension in the direction of gate length of the first gate electrode layer. | 05-06-2010 |
20100117136 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device includes a plurality of nonvolatile memory cells formed on a semiconductor substrate, each memory cell including source and drain regions separately formed on a surface portion of the substrate, buried insulating films formed in portions of the substrate that lie under the source and drain regions and each having a dielectric constant smaller than that of the substrate, a tunnel insulating film formed on a channel region formed between the source and drain regions, a charge storage layer formed of a dielectric body on the tunnel insulating film, a block insulating film formed on the charge storage layer, and a control gate electrode formed on the block insulating film. | 05-13-2010 |
20100155815 | AMMONIA PRE-TREATMENT IN THE FABRICATION OF A MEMORY CELL - A method of manufacturing a memory cell | 06-24-2010 |
20100163959 | Etch Stop Structures For Floating Gate Devices - Etch stop structures for floating gate devices are generally described. In one example, a floating gate device includes a semiconductor substrate having a surface on which one or more floating gate devices are formed, a tunnel dielectric coupled with the surface of the semiconductor substrate, a floating gate structure coupled with the tunnel dielectric, the floating gate structure having a first surface, a second surface, and a third surface, wherein the third surface is substantially parallel with the surface of the semiconductor substrate and wherein the first surface is substantially parallel with the second surface and substantially perpendicular with the third surface, an etch stop film coupled with the third surface of the floating gate structure, and an inter-gate dielectric coupled with the first surface and the second surface of the floating gate structure wherein the inter-gate dielectric comprises a material that is less resistant to an etchant that removes material of a control gate structure than the etch stop film. | 07-01-2010 |
20100163960 | FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a flash memory device and a method of manufacturing the same. The flash memory device includes a floating gate formed on a semiconductor substrate, a select gate self-aligned on one sidewall of the floating gate, and an ONO pattern interposed between the floating gate and the select gate. A self-aligned split gate structure is formed for an EEPROM tunnel oxide cell flash memory device employing a split gate structure, so that a cell current is constant and the erasing characteristic between cells is uniform, thereby improving the reliability. | 07-01-2010 |
20100163961 | METHOD FOR MANUFACTURING SEMICONDUCTOR FLASH MEMORY AND FLASH MEMORY CELL - A semiconductor flash memory includes a tunnel oxide film formed over a semiconductor substrate, a first spacer composed of polysilicon formed over the semiconductor substrate including the tunnel oxide film, a second spacer composed of an insulating material formed at sidewalls of the first spacer, a dielectric film formed at the uppermost surface of the first spacer and the second spacer, a control gate formed at the uppermost surface of the dielectric film, and a third spacer composed of an insulating material formed at and contacting sidewalls of the second spacer, the dielectric film and the control gate. A first source/drain region formed may be formed in the semiconductor substrate and self-aligned with the first spacer and a second source/drain region may be formed in the semiconductor substrate and self-aligned with the second spacer. | 07-01-2010 |
20100163962 | Printed Non-Volatile Memory - A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology. | 07-01-2010 |
20100171168 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel. | 07-08-2010 |
20100171169 | Nonvolatile semiconductor memory device, semiconductor device and manufactoring method of nonvolatile semiconductor memory device - A nonvolatile semiconductor memory device includes a gate portion formed by laminating a tunnel insulating film, floating gate electrode, inter-poly insulating film and control gate electrode on a semiconductor substrate, and source and drain regions formed on the substrate. The tunnel insulating film has a three-layered structure having a silicon nitride film sandwiched between silicon oxide films. The silicon nitride film is continuous in an in-plane direction and has 3-coordinate nitrogen bonds and at least one of second neighboring atoms of nitrogen is nitrogen. | 07-08-2010 |
20100187595 | NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer. | 07-29-2010 |
20100200903 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench. | 08-12-2010 |
20100213534 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR THE SAME - In a nonvolatile semiconductor memory device provided with memory cell transistors, each of the memory cell transistors has a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and element isolation insulating films respectively. The floating gate electrode on the tunnel insulating film is provided with a first floating gate electrode and a second floating gate electrode formed sequentially from the bottom, the second floating gate electrode being narrower in a channel-width direction than the first one. Levels of upper surfaces of the element isolation insulating films and the first floating gate electrode are the same. The inter-electrode insulating film continuously covers the upper and side surfaces of the floating gate electrode and the upper surfaces of the element isolation insulating films, and is higher in a nitrogen concentration in a boundary portion to the floating gate electrode than in boundary portions to the element isolation insulating films. | 08-26-2010 |
20100252875 | STRUCTURE AND FABRICATING PROCESS OF NON-VOLATILE MEMORY - A structure of a non-volatile memory is described, including a substrate, isolation structures disposed in and protrudent over the substrate, floating gates as conductive spacers on the sidewalls of the isolation structures protrudent over the substrate, and a tunneling layer between each floating gate and the substrate. A process for fabricating a non-volatile memory is also described. Isolation structures are formed in a substrate protrudent over the same, a tunneling layer is formed over the substrate, and then floating gates are formed as conductive spacers on the sidewalls of the first isolation structures protrudent over the substrate. | 10-07-2010 |
20100276745 | ELECTRICALLY PROGRAMMABLE DEVICE WITH EMBEDDED EEPROM AND METHOD FOR MAKING THEREOF - A semiconductor device includes a substrate and a first gate oxide layer overlying a first device region and a second device region in the substrate, a first gate in the first device region, and a second gate and a third gate in the second device region. The device also has a first dielectric layer with a first portion disposed on the first gate, a second portion disposed adjacent a sidewall of the first gate, and a third portion disposed over the third gate. An inter-gate oxide layer is disposed on the first gate and between the first portion and the second portion of the first dielectric layer. A fourth gate overlies the second gate oxide layer, the inter-gate oxide layer, and the first portion and the second portion of the first dielectric layer in the first device region. A fifth gate overlies the third portion of the first dielectric layer which is disposed over the third gate in the second device region. | 11-04-2010 |
20100289071 | NON-VOLATILE MEMORY DEVICE, METHODS OF FABRICATING AND OPERATING THE SAME - A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data. | 11-18-2010 |
20100308396 | Gate Patterns of Nonvolatile Memory Device and Method of Forming the Same - A method of forming gate patterns of a nonvolatile memory device comprises forming stack patterns each having an insulating layer and a conductive layer stacked over a semiconductor substrate, and forming an anti-oxidation layer on sidewalls of the insulating layer by selectively nitrifying the insulating layer. | 12-09-2010 |
20100314677 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a semiconductor substrate; a semiconductor layer formed on the semiconductor substrate; a first device isolation/insulation film formed in a trench, the trench formed in the semiconductor layer, with a first direction taken as a longitudinal direction; a device formation region formed by separating the semiconductor layer by the first device isolation/insulation film with the first direction taken as a longitudinal direction; and a memory transistor disposed on the device formation region. The first device isolation/insulation film and the device formation region have an impurity of a first conductivity type. An impurity concentration of the impurity of the first conductivity type in the first device isolation/insulation film is higher than that in the device formation region. | 12-16-2010 |
20110001180 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells integrated on a semiconductor substrate, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, a first interelectrode insulating film formed on the upper surface of the floating gate electrode, a second interelectrode insulating film formed to cover the side surfaces of the floating gate electrode and the first interelectrode insulating film, and a control gate electrode formed on the second interelectrode insulating film. | 01-06-2011 |
20110001181 | Nonvolatile Memory Devices - Provided is a nonvolatile memory device. The nonvolatile memory device includes: a tunnel insulation layer on a semiconductor substrate; a floating gate electrode including a bottom gate electrode doped with carbon and contacting the tunnel insulation layer and a top gate electrode on the bottom gate electrode; a gate interlayer insulation layer on the floating gate electrode; and a control gate electrode on the gate interlayer insulation layer. | 01-06-2011 |
20110012187 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes: a semiconductor substrate; an element isolation insulating film dividing the semiconductor substrate into a plurality of element regions; tunnel insulating films formed respectively on the plurality of element regions; floating gate electrodes formed respectively on the tunnel insulating films; a first control-gate electrode formed, on the floating gate electrodes and between each two floating gate electrodes adjacent to each other in a channel-width direction, with a laminated insulating film interposed therebetween; assist insulating films formed on side surface facing in the channel-width direction of the plurality of element regions; and a second control-gate electrode formed between the plurality of element regions with the assist insulating films interposed therebetween. | 01-20-2011 |
20110024822 | ISOLATION REGIONS - A dielectric liner is formed in first and second trenches respectively in first and second portions of a substrate. A layer of material is formed overlying the dielectric liner so as to substantially concurrently substantially fill the first trench and partially fill the second trench. The layer of material is removed substantially concurrently from the first and second trenches to expose substantially all of the dielectric liner within the second trench and to form a plug of the material in the one or more first trenches. A second layer of dielectric material is formed substantially concurrently on the plug in the first trench and on the exposed portion of the dielectric liner in the second trench. The second layer of dielectric material substantially fills a portion of the first trench above the plug and the second trench. | 02-03-2011 |
20110031549 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A memory includes active areas and an isolation on a semiconductor substrate. A tunnel dielectric film is on active areas. Floating gates include lower gate parts and upper gate parts. An upper gate part has a larger width than that of a lower gate part on a cross section perpendicular to an extension direction of an active area, and is provided on the lower gate part. An intermediate dielectric film is on an upper surface and a side surface of each floating gate. The control gate is on an upper surface and a side surface of each floating gate via the intermediate dielectric film. A height of a lower end of each control gate from a surface of the semiconductor substrate is lower than a height of an interface between the upper gate part and the lower gate part from the surface of the semiconductor substrate. | 02-10-2011 |
20110073930 | NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices and methods of forming the same. The semiconductor devices include a tunnel insulation layer on a substrate, a floating gate on the tunnel insulation layer, a gate insulation layer on the floating gate, a low-dielectric constant (low-k) region between the top of the floating gate and the gate insulation layer, the low-k region having a lower dielectric constant than a silicon oxide, and a control gate on the gate insulation layer. | 03-31-2011 |
20110073931 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A plasma nitriding process is followed by a selective etching process which removes a silicon oxynitride film formed on surfaces of both an element separation film and an insulation film while leaving a silicon nitride film formed on an electrode layer. The selective etching process removes the silicon oxynitride film formed on the surfaces of the element separation film and the insulation film. | 03-31-2011 |
20110079839 | Non-Volatile Memory Devices Having Reduced Susceptibility to Leakage of Stored Charges and Methods of Forming Same - Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. | 04-07-2011 |
20110095352 | FLASH MEMORY DEVICE AND FABRICATION METHOD THEREOF - The present invention relates to a flash memory device and a fabrication method thereof. In an embodiment, a flash memory device includes a tunnel insulating film and a floating gate laminated over an active region of a semiconductor substrate, an isolation layer formed in a field region of the semiconductor substrate and projected higher than the floating gate, a dielectric layer formed over the semiconductor substrate including the floating gate and the isolation layer, and a control gate formed on the dielectric layer. | 04-28-2011 |
20110115013 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region. | 05-19-2011 |
20110121381 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an embodiment of the present invention includes a substrate, a first gate insulator formed on the substrate and serving as an F-N (Fowler-Nordheim) tunneling film, a first floating gate formed on the first gate insulator, a second gate insulator formed on the first floating gate and serving as an F-N tunneling film, a second floating gate formed on the second gate insulator, an intergate insulator formed on the second floating gate and serving as a charge blocking film, and a control gate formed on the intergate insulator, at least one of the first and second floating gates including a metal layer. | 05-26-2011 |
20110140189 | ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY AND MANUFACTURING METHOD THEREOF - An electrically erasable programmable read-only memory includes a first polysilicon layer, a second polysilicon layer and a third polysilicon layer, the first polysilicon layer and the third polysilicon layer forming a control gate and the second polysilicon layer forming a floating gate. The first polysilicon layer is horizontally disposed in series with the second polysilicon layer and is connected to the third polysilicon layer, so that the control gate encloses all of the floating gate except for a tunnel surface of the floating gate. | 06-16-2011 |
20110163369 | SURROUNDING STACKED GATE MULTI-GATE FET STRUCTURE NONVOLATILE MEMORY DEVICE - Nonvolatile memory devices having a low off state leakage current and an excellent data retention time characteristics. The present invention provides a surrounding stacked gate fin field effect transistor nonvolatile memory structure comprising a silicon-on-insulator substrate of a first conductivity type and a fin active region projecting from an upper surface of the insulator. The structure further includes a tunnel oxide layer formed on the fin active region and a first gate electrode disposed on the tunnel oxide layer and upper surface of the insulator. Additionally, the structure includes an oxide/nitride/oxide (ONO) composite layer formed on the first gate electrode, a second gate electrode formed on the ONO composite layer and patterned so as to define a predetermined area of the ONO composite layer. The structure further includes a dielectric spacer formed on a sidewall of the second gate electrode and source/drain regions formed in the fin active region on both sides of the second gate electrode. | 07-07-2011 |
20110163370 | SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A semiconductor memory includes memory cell transistors including a tunnel insulating film, a floating gate electrode, a first insulating film, a control gate electrode, and a first metal salicide film; low-voltage transistors having a first p-type source region and a first p-type drain region, a first gate insulating film, and a first gate electrode of an n conductivity type having the same dose of a first p-type impurity as with the first p-type source region; and high-voltage transistors having a second p-type source region and a second p-type drain region, a second gate insulating film thicker than the first gate insulating film, and a second gate electrode of an n conductivity type having the same dose of a second p-type impurity as with the second p-type source region. | 07-07-2011 |
20110169068 | NON-VOLATILE MEMORY DEVICES HAVING A FLOATING GATE CAP BETWEEN A FLOATING GATE AND A GATE INSULATING LAYER - Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern. | 07-14-2011 |
20110220985 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a charge storage structure and a gate. The charge storage structure is formed on a substrate. The gate is formed on the charge storage structure. The gate includes a lower portion formed of silicon and an upper portion formed of metal silicide. The upper portion of the gate has a width greater than that of the lower portion of the gate. | 09-15-2011 |
20110254074 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF - A method of manufacturing a semiconductor integrated circuit device includes defining a first area by forming a separating area on a substrate, and forming a tunnel film in the first area, a floating gate on the tunnel film, a first electrode in the separating area, a first film on the floating gate, a second film on the first electrode, a control gate on the first film, a second electrode on the second film, and source and drain areas in the first area. The method includes forming a first interlayer film to cover the control gate and the second electrode, forming, in the first interlayer film, a conductive via plug reaching the second electrode, and forming, on the first interlayer film, a second wiring electrically coupled to the second electrode via the conductive via plug, and a first wiring that is capacitively-coupled to the second wiring and to the second electrode. | 10-20-2011 |
20110254075 | USE OF DILUTE STEAM AMBIENT FOR IMPROVEMENT OF FLASH DEVICES - A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized. | 10-20-2011 |
20110278659 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming an oxidation film over a first and a second device region, forming an first etching preventing film extending over a first and a second area, removing the first etching preventing film over the first area; removing the oxidation film over the first device region, forming a first gate insulating film over the first device region, removing the oxidation film over the second device region, forming a second gate insulating film over the second device region, forming a first gate electrode over the first gate insulating film, forming a second gate electrode over the second gate insulating film, forming first source and drain regions in the first device region at both sides of the first gate electrode, and forming second source and drain regions in the second device region at both sides of the second gate electrode. | 11-17-2011 |
20110298036 | ISOLATION LAYER STRUCTURE, METHOD OF FORMING THE SAME AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME - An isolation layer structure includes first to fourth oxide layer patterns. The first and third oxide layer patterns are sequentially formed in a first trench defined by a first recessed top surface of a substrate and sidewalls of gate structures on the substrate in a first region. The first trench has a first width, and the first and third oxide layer patterns have no void therein. The second and fourth oxide layer patterns are sequentially formed in a second trench defined by a second recessed top surface of the substrate and sidewalls of gate structures on the substrate in a second region. The second trench has a second width larger than the first width, and the fourth oxide layer pattern has a void therein. | 12-08-2011 |
20110303965 | SEMICONDUCTOR DEVICES - A semiconductor device and method of manufacturing a semiconductor device include a plurality of first active regions and a second active region being formed on a substrate. The second active region is formed between two of the first active regions. A plurality of gate structures is formed on respective first active regions. A dummy gate structure is formed on the second active region, and a first voltage is applied to the dummy gate structure. | 12-15-2011 |
20110303966 | NONVOLATILE SEMICONDUCTOR MEMORY TRANSISTOR, NONVOLATILE SEMICONDUCTOR MEMORY, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory transistor included in a nonvolatile semiconductor memory includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the substrate side, a hollow pillar-shaped floating gate arranged so as to surround the outer periphery of the channel region in such a manner that a tunnel insulating film is interposed between the floating gate and the channel region, and a hollow pillar-shaped control gate arranged so as to surround the outer periphery of the floating gate in such a manner that an inter-polysilicon insulating film is interposed between the control gate and the floating gate. The inter-polysilicon insulating film is arranged so as to be interposed between the floating gate and the upper, lower, and inner side surfaces of the control gate. | 12-15-2011 |
20110303967 | Non-Volatile Memory With Air Gaps - Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation can be provided, at least in part, by bit line air gaps that are elongated in a column direction and/or word line air gaps that are elongated in a row direction. The bit line air gaps may be formed in the substrate, extending between adjacent active areas of the substrate, as well as above the substrate surface, extending between adjacent columns of non-volatile storage elements. The word line air gaps may be formed above the substrate surface, extending between adjacent rows of non-volatile storage elements. | 12-15-2011 |
20110309429 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, in a floating-gate type nonvolatile semiconductor memory device in which a tunnel dielectric film and a control gate electrode are connected between memory cells adjacent via a shallow trench isolation, each of a floating gate electrode and the control gate electrode includes an electric-field concentrated portion having a curvature on the tunnel dielectric film side. The electric-field concentrated portion of the floating gate electrode is formed over a forming position of a channel semiconductor. The electric-field concentrated portion of the control gate electrode is formed over a forming position of the shallow trench isolation. | 12-22-2011 |
20110309430 | Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation - High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction. | 12-22-2011 |
20120001252 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 01-05-2012 |
20120037974 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer. | 02-16-2012 |
20120037975 | SEMICONDUCTOR DEVICES - A semiconductor device has an isolation layer pattern, a plurality of gate structures, and a first insulation layer pattern. The isolation layer pattern is formed on a substrate and has a recess thereon. The gate structures are spaced apart from each other on the substrate and the isolation layer pattern. The first insulation layer pattern is formed on the substrate and covers the gate structures and an inner wall of the recess. The first insulation layer pattern has a first air gap therein. | 02-16-2012 |
20120037976 | NONVOLATILE SEMICONDUCTOR MEMORY AND FABRICATION METHOD FOR THE SAME - A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor. | 02-16-2012 |
20120068249 | Nonvolatile memory device and method of manufacturing the same - The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer. | 03-22-2012 |
20120068250 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film. | 03-22-2012 |
20120126307 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. | 05-24-2012 |
20120132981 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided. | 05-31-2012 |
20120132982 | Non-Volatile Memory Devices - A non-volatile memory device includes gate structures, an insulation layer pattern, and an isolation structure. Multiple gate structures being spaced apart from each other in a first direction are formed on a substrate. Ones of the gate structures extend in a second direction that is substantially perpendicular to the first direction. The substrate includes active regions and field regions alternately and repeatedly formed in the second direction. The insulation layer pattern is formed between the gate structures and has a second air gap therein. Each of the isolation structures extending in the first direction and having a first air gap between the gate structures, the insulation layer pattern, and the isolation structure is formed on the substrate in each field region. | 05-31-2012 |
20120146124 | NON-VOLATILE STORAGE ELEMENT HAVING DUAL WORK-FUNCTION ELECTRODES - A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap. | 06-14-2012 |
20120146125 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A non-volatile memory device comprises a substrate, a control gate electrode on the substrate, and a charge storage region between the control gate electrode and the substrate. A control gate mask pattern is on the control gate electrode, the control gate electrode comprising a control base gate and a control metal gate on the control base gate. A width of the control metal gate is less than a width of the control gate mask pattern. An oxidation-resistant spacer is at sidewalls of the control metal gate positioned between the control gate mask pattern and the control base gate. | 06-14-2012 |
20120187469 | METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE DEVICE AND SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, there is provided a method of manufacturing a semiconductor storage device. In the method, any one of Ge, Sn, C, and N is introduced as impurity to a surface of a semiconductor substrate. In the method, the semiconductor substrate is thermally oxidized so that a tunnel insulating film is formed on the surface of the semiconductor substrate to which the impurity is introduced. In the method, a gate having a charge accumulation layer is formed on the tunnel insulating film. In the method, impurity diffusion regions are formed in the semiconductor substrate in a self-aligned manner using the gate. | 07-26-2012 |
20120187470 | GATE STRUCTURES - A method of forming a gate structure includes forming a tunnel insulation layer pattern on a substrate, forming a floating gate on the tunnel insulation layer pattern, forming a dielectric layer pattern on the floating gate, the dielectric layer pattern including a first oxide layer pattern, a nitride layer pattern on the first oxide layer pattern, and a second oxide layer pattern on the nitride layer pattern, the second oxide layer pattern being formed by performing an anisotropic plasma oxidation process on the nitride layer, such that a first portion of the second oxide layer pattern on a top surface of the floating gate has a larger thickness than a second portion of the second oxide layer pattern on a sidewall of the floating gate, and forming a control gate on the second oxide layer. | 07-26-2012 |
20120217568 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a silicon-containing substrate, a plurality of memory cells, and an insulating film. The substrate includes silicon. The plurality of memory cells is provided on the substrate with a spacing therebetween. The insulating film is provided on a sidewall of the memory cell. The insulating film includes a protrusion protruding toward an adjacent one of the memory cells above a void portion is provided between the memory cells. | 08-30-2012 |
20120217569 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film. | 08-30-2012 |
20120223379 | NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A non-volatile memory device includes a substrate including a plurality of active regions and a plurality of device isolating trenches formed between a respective one of each of the active regions along a first direction in the substrate. A plurality of gate structures each including a tunnel insulating layer pattern, a floating gate electrode, a dielectric layer pattern and a control gate electrode is formed on the substrate. A first insulating layer pattern is provided within the device isolating trenches. A second insulating layer pattern is formed along an inner surface portion of a gap between the gate structures. An impurity doped polysilicon pattern is formed on the second insulating layer pattern in the gap between the gate structures. | 09-06-2012 |
20120223380 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 09-06-2012 |
20120228693 | Highly Reliable NAND Flash memory using a five side enclosed Floating gate storage elements - A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the quantum of charge stored to provide reconstruction of data. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the Automotive specifications even with some area penalty. | 09-13-2012 |
20120267700 | TUNNELING CURRENT AMPLIFICATION TRANSISTOR - The present invention discloses a tunneling current amplification transistor, which relates to an area of field effect transistor logic devices in CMOS ultra large scale semiconductor integrated circuits (ULSI). The tunneling current amplification transistor includes a semiconductor substrate, a gate dielectric layer, an emitter, a drain, a floating tunneling base and a control gate, wherein the drain, the floating tunneling base and the control gate forms a conventional TFET structure, and a doping type of the emitter is opposite to that of the floating tunneling base. A position of the emitter is at the other side of the floating tunneling base with respect to the drain. A type of the semiconductor between the emitter and the floating tunneling base is the same as that of the floating tunneling base. As compared with the conventional TFET, the tunneling current amplification transistor of the present invention can increase the on-current of the device effectively and increase the driving capability of the device. | 10-25-2012 |
20130001672 | SEMICONDUCTOR DEVICE - A semiconductor device includes a main active region provided in a semiconductor substrate and having a first side surface and a second side surface facing each other. A first auxiliary active region adjacent the first side surface of the main active region and spaced apart from the main active region by a first distance is provided. A second auxiliary active region adjacent the second side surface of the main active region and spaced apart from the main active region by the first distance is provided. A first conductive pattern crosses the main active region and includes first and second side portions facing each other. The first side portion of the conductive pattern is disposed between the first auxiliary active region and the main active region, and the second side portion of the conductive pattern is disposed between the second auxiliary active region and the main active region. | 01-03-2013 |
20130015518 | SEMICONDUCTOR MEMORY DEVICEAANM SATO; HiroyasuAACI Kanagawa-kenAACO JPAAGP SATO; Hiroyasu Kanagawa-ken JPAANM NISHIHARA; KiyohitoAACI Kanagawa-kenAACO JPAAGP NISHIHARA; Kiyohito Kanagawa-ken JPAANM NAWATA; HidefumiAACI Kanagawa-kenAACO JPAAGP NAWATA; Hidefumi Kanagawa-ken JPAANM ICHIGE; MasayukiAACI Kanagawa-kenAACO JPAAGP ICHIGE; Masayuki Kanagawa-ken JPAANM OHBA; RyujiAACI Kanagawa-kenAACO JPAAGP OHBA; Ryuji Kanagawa-ken JP - In general, according to one embodiment, a semiconductor memory device includes active areas extending in a first direction, tunnel films provided on the active areas, floating gate electrodes provided on the tunnel films, an interelectrode insulating film provided on the floating gate electrodes and extending in a second direction, a control gate electrode provided on the interelectrode insulating film and extending in the second direction, a lower insulating portion provided between the active areas, between the tunnel films, and between the floating gate electrodes adjacent in the second direction, and an upper insulating portion provided between the lower insulating portion and the interelectrode insulating film. The lower insulating portion includes a void. Relative dielectric constant of the upper insulating portion is higher than that of the lower insulating portion. Relative dielectric constant of the interelectrode insulating film is higher than that of the upper insulating portion. | 01-17-2013 |
20130049095 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a vertical channel layer protruding upward from a semiconductor substrate, a tunnel insulating layer covering a sidewall of the vertical channel layer, a plurality of floating gates separated from each other and stacked one upon another along the vertical channel layer, and surrounding the vertical channel layer with the tunnel insulating layer interposed therebetween, a plurality of control gates enclosing the plurality of floating gates, respectively, and an interlayer insulating layer provided between the plurality of control gates. | 02-28-2013 |
20130056817 | SEMICONDUCTOR DEVICES INCLUDING DEVICE ISOLATION STRUCTURES AND METHOD OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. A device isolation structure in the semiconductor device includes a gap region. A dielectric constant of a vacuum or an air in the gap region is smaller than a dielectric constant of an oxide layer and, as a result coupling and attendant interference between adjacent cells may be reduced. | 03-07-2013 |
20130069138 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 03-21-2013 |
20130134496 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns. | 05-30-2013 |
20130153981 | NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A nonvolatile memory device, and method of forming the same, discloses a semiconductor device including floating gates that each have a first region that overlaps with a corresponding junction and that each have a second region that does not overlap the corresponding junction. The first region and the second region have different work functions. | 06-20-2013 |
20130161722 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include a gate structure on a substrate, the gate structure including a first metal; an insulating interlayer covering the gate structure on the substrate; a resistance pattern in the insulating interlayer, the resistance pattern having a top surface lower than a top surface of the insulating interlayer and including a second metal different from the first metal at least at an upper portion thereof; and/or a first contact plug through a first portion of the insulating interlayer, the first contact plug making direct contact with the upper portion of the resistance pattern. | 06-27-2013 |
20130161723 | Electronic Device Including a Tunnel Structure - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 06-27-2013 |
20130221423 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes an underlayer and a stacked body. The stacked body includes control gate layers and insulating layers. The device includes a channel body layer penetrating through the stacked body, and the control gate layers and the insulating layers are stacked in the stacking direction, a floating gate layer provided between each of the plurality of control gate layers and the channel body layer. The device includes a block insulating layer provided between each of the plurality of control gate layers and the floating gate layer, and includes a tunnel insulating layer provided between the channel body layer and the floating gate layer. A length of a boundary between the floating gate layer and the block insulating layer is shorter than a length of a boundary between the floating gate layer and the tunnel insulating layer. | 08-29-2013 |
20130228846 | NONVOLATILE MEMORY CELLS WITH A VERTICAL SELECTION GATE OF VARIABLE DEPTH - The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line. | 09-05-2013 |
20130228847 | TFT Floating Gate Memory Cell Structures - A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N | 09-05-2013 |
20130234229 | SINGLE POLY ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY (SINGLE POLY EEPROM) DEVICE - A single poly electrically erasable programmable read only memory (single poly EEPROM) device is provided, including: a semiconductor on insulator (SOI) substrate having a P-type semiconductor layer over an insulator layer; a P-well region formed in a portion of the P-type semiconductor layer; a trench isolation formed in the P-type semiconductor layer, surrounding the P-well region; an NMOS transistor formed over a portion of the P-type semiconductor layer of the P-well region; a P+ doping region formed over another portion of the P-type semiconductor layer of the P-well region; and a control gate formed in another portion of the P-type semiconductor layer, adjacent to the trench isolation. | 09-12-2013 |
20130240974 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor substrate, a pair of select gate transistors provided on a first region of the semiconductor substrate, a plurality of memory cell transistors provided on a second region provided between the pair of select gate transistors on the semiconductor substrate, a gate electrode of each of the memory cell transistors, the gate electrode provided on the second region via a first insulating film, and including a charge storage layer, an intermediate insulating film, and a control gate electrode film stacked therein, a groove exposed a sidewall of the semiconductor substrate on the first region; and a gate electrode of each of the select gate transistors, the gate electrode including the control gate electrode film formed on the sidewall via a second insulating film. | 09-19-2013 |
20130248974 | COMPACT THREE DIMENSIONAL VERTICAL NAND AND METHOD OF MAKING THEREOF - A NAND device has at least a 3×3 array of vertical NAND strings in which the control gate electrodes are continuous in the array and do not have an air gap or a dielectric filled trench in the array. The NAND device is formed by first forming a lower select gate level having separated lower select gates, then forming plural memory device levels containing a plurality of NAND string portions, and then forming an upper select gate level over the memory device levels having separated upper select gates. | 09-26-2013 |
20130256779 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprising: forming a first insulating film on a semiconductor substrate; forming an adsorption film on the first insulating film; forming a first film containing germanium on the adsorption film; forming a second insulating film on the first film; forming a floating electrode film on the second insulating film; forming a third insulating film on the floating electrode film; and forming a gate electrode on the third insulating film. | 10-03-2013 |
20130264630 | SEMICONDUCTOR DEVICES HAVING TRANSISTORS CAPABLE OF ADJUSTING THRESHOLD VOLTAGE THROUGH BODY BIAS EFFECT - Semiconductor devices have transistors capable of adjusting threshold voltages through a body bias effect. The semiconductor devices include transistors having a front gate on a substrate, a back gate between adjacent transistors, and a carrier storage layer configured to surround the back gate and to trap a carrier. A threshold voltage of a transistor may be changed in response to voltage applied to the back gate. Related fabrication methods are also described. | 10-10-2013 |
20130307051 | MEMORY STRUCTURE - A memory structure includes a substrate, a source region, a drain region, a gate insulating layer, a floating gate and a control gate. The substrate has a surface and a well extended from the surface to the interior of the substrate. The source region and the drain region are formed in the well and a channel region is formed between the source region and the drain region. The gate insulating layer is formed on the surface of the substrate between the source region and the drain region and covers the channel region. The floating gate disposed on the gate insulating layer to store a bit data. The control gate is disposed near lateral sides of the floating gate. | 11-21-2013 |
20130313626 | Methods and Apparatus for Non-Volatile Memory Cells - Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells. | 11-28-2013 |
20140001533 | NAND Memory Device Containing Nanodots and Method of Making Thereof | 01-02-2014 |
20140015031 | Apparatus and Method for Memory Device - An apparatus comprises a gate stack formed over a substrate, wherein the gate stack comprises a first gate structure, wherein a first dielectric layer is formed between the first gate structure and the substrate and a second gate structure stacked on the first gate structure, wherein a second dielectric layer is formed between the first gate structure and the second gate structure. The apparatus further comprises a first drain/source region and a first recess formed between a top surface of the first drain/source region and the second dielectric layer. | 01-16-2014 |
20140035022 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 02-06-2014 |
20140042518 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes isolation layers formed in isolation regions defined between active regions of a semiconductor substrate, wherein each of the isolation layers includes a first air gap, word lines formed over the semiconductor substrate in a direction crossing the isolation layers, wherein each of the word lines includes a stacked structure of a tunnel insulating layer, a floating gate, a dielectric layer and a control gate, and including insulating layers between the word lines, wherein a width of the floating gate is greater than a width of each active region. | 02-13-2014 |
20140061759 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of gate structures, each gate structure formed over a substrate and including a tunnel insulating layer, a floating gate, an inter-gate dielectric layer, and a control gate, which are sequentially stacked, and an interlayer dielectric layer covering the plurality of gate structures and having an air gap formed between adjacent gate structures, wherein the bottom surface of the air gap is positioned at a lower level than the surface of the tunnel insulating layer. | 03-06-2014 |
20140061760 | NON-VOLATILE MEMORY DEVICE FORMED BY DUAL FLOATING GATE DEPOSIT - A device includes a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an STI material, and further comprising a recess in the STI material, the recess having a bottom and sides; a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by a portion of the STI material; and a gate dielectric layer located over the floating gate, and a control gate located over the gate dielectric layer, wherein a portion of the control gate is located in the recess. | 03-06-2014 |
20140131787 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 05-15-2014 |
20140138759 | INTEGRATED CIRCUIT DEVICE HAVING A RESISTOR AND METHOD OF MANUFACTURING THE SAME - In an integrated circuit device and method of manufacturing the same, a resistor pattern is positioned on a device isolation layer of a substrate. The resistor pattern includes a resistor body positioned in a recess portion of the device isolation layer and a connector making contact with the resistor body and positioned on the device isolation layer around the recess portion. The connector has a metal silicide pattern having electric resistance lower than that of the resistor body at an upper portion. A gate pattern is positioned on the active region of the substrate and includes the metal silicide pattern at an upper portion. A resistor interconnection is provided to make contact with the connector of the resistor pattern. A contact resistance between the connector and the resistor interconnection is reduced. | 05-22-2014 |
20140138760 | THREE DIMENSIONAL NAND DEVICE AND METHOD OF CHARGE TRAP LAYER SEPARATION AND FLOATING GATE FORMATION IN THE NAND DEVICE - A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric. | 05-22-2014 |
20140145255 | NON-VOLATILE MEMORY DEVICES INCLUDING VERTICAL NAND CHANNELS AND METHODS OF FORMING THE SAME - A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device. | 05-29-2014 |
20140175530 | THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers. | 06-26-2014 |
20140197471 | NON-VOLATILE MEMORY DEVICES HAVING REDUCED SUSCEPTIBILITY TO LEAKAGE OF STORED CHARGES AND METHODS OF FORMING SAME - Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. | 07-17-2014 |
20140203345 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device is proposed whereby voltage can be more flexibly set in accumulating electric charges into a selected memory cell transistor in comparison with a conventional device. In a non-volatile semiconductor memory device ( | 07-24-2014 |
20140217491 | DENSE ARRAYS AND CHARGE STORAGE DEVICES - There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing. | 08-07-2014 |
20140239368 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a first isolation region dividing a semiconductor substrate into first regions; memory cells each including a tunnel insulating film, a charge storing layer, an interelectrode insulating film, and a control gate electrode above the first region; a second isolation region dividing the substrate into second regions in a peripheral circuit region; and a peripheral circuit transistor including a gate insulating film and a gate electrode above the second region. The first isolation region includes a first trench, a first element isolation insulating film filled in a bottom portion of the first trench, and a first gap formed between the first element isolation insulating film and the interelectrode insulating film. The second isolation region includes a second trench and a second element isolation insulating film filled in the second trench. The first and the second element isolation insulating films have different properties. | 08-28-2014 |
20140239369 | SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME - A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device. | 08-28-2014 |
20140306280 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In the method, a plurality of gate structures may be formed on a substrate and be spaced apart from each other in a first direction. An insulation layer pattern may be formed by performing a chemical vapor deposition process using SiH | 10-16-2014 |
20140319595 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer. | 10-30-2014 |
20140339623 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A). | 11-20-2014 |
20140346584 | MEMORY DEVICE WITH CONTROL GATE OXYGEN DIFFUSION CONTROL AND METHOD OF MAKING THEREOF - An embodiment relates to a memory device that includes a semiconductor channel, a tunnel dielectric located over the semiconductor channel, a charge storage region located over the tunnel dielectric, a blocking dielectric located over the charge storage region, and a control gate located over the blocking dielectric. An interface between the blocking dielectric and the control gate substantially prevents oxygen diffusion from the blocking dielectric into the control gate. | 11-27-2014 |
20140353738 | FLOATING GATE ULTRAHIGH DENSITY VERTICAL NAND FLASH MEMORY AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric inside the back side recesses and the back side opening. The blocking dielectric has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes in the respective clam shell shaped regions of the blocking dielectric in the back side recesses. | 12-04-2014 |
20140367762 | METHOD OF FORMING AN ACTIVE AREA WITH FLOATING GATE NEGATIVE OFFSET PROFILE IN FG NAND MEMORY - A stack can be patterned by a first etch process to form an opening defining sidewall surfaces of a patterned material stack. A masking layer can be non-conformally deposited on sidewalls of an upper portion of the patterned material stack, while not being deposited on sidewalls of a lower portion of the patterned material stack. The sidewalls of a lower portion of the opening can be laterally recessed employing a second etch process, which can include an isotropic etch component. The sidewalls of the upper portion of the opening can protrude inward toward the opening to form an overhang over the sidewalls of the lower portion of the opening. The overhang can be employed to form useful structures such as an negative offset profile in a floating gate device or vertically aligned control gate electrodes for vertical memory devices. | 12-18-2014 |
20150008502 | THREE DIMENSIONAL NAND DEVICE WITH BIRDS BEAK CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer. | 01-08-2015 |
20150041877 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes: a plurality of memory cells, each of the memory cells including a tunneling insulating film provided on a substrate including silicon, a floating gate provided on the tunneling insulating film, an inter-gate insulating film provided on the floating gate, and a control gate provided on the inter-gate insulating film; and an element separation trench provided between the plurality of memory cells, the element separation trench having a gap in an interior of the element separation trench. The inter-gate insulating film is provided also above the element separation trench. An upper end of the gap is provided in an interior of the inter-gate insulating film provided above the element separation trench. | 02-12-2015 |
20150041878 | METHOD FOR FORMING A FLOATING GATE IN A RECESS OF A SHALLOW TRENCH ISOLATION (STI) REGION - A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate. | 02-12-2015 |
20150048437 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes an insulating film with a recess formed in an upper surface, and a conductive film provided on the insulating film and containing silicon, carbon and an impurity serving as an acceptor or donor for silicon. Carbon concentration of a first portion of the conductive film in contact with the insulating film is lower than carbon concentration of a second portion of the conductive film located in the recess and being equidistant from the insulating film placed on both sides thereof. | 02-19-2015 |
20150054054 | SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns. | 02-26-2015 |
20150060988 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating the same, include forming a trench between a plurality of patterns on a substrate to be adjacent to each other, forming a first sacrificial layer in the trench, forming a first porous insulation layer having a plurality of pores on the plurality of patterns and on the first sacrificial layer, and removing the first sacrificial layer through the plurality of pores of the first porous insulation layer to form a first air gap between the plurality of patterns and under the first porous insulation layer. | 03-05-2015 |
20150069494 | THREE DIMENSIONAL NAND DEVICE AND METHOD OF CHARGE TRAP LAYER SEPARATION AND FLOATING GATE FORMATION IN THE NAND DEVICE - A monolithic three dimensional NAND string includes a vertical semiconductor channel and a plurality of control gate electrodes in different device levels. The string also includes a blocking dielectric layer, a charge storage region and a tunnel dielectric. A first control gate electrode is separated from a second control gate electrode by an air gap located between the major surfaces of the first and second control gate electrodes and/or the charge storage region includes silicide nanoparticles embedded in a charge storage dielectric. | 03-12-2015 |
20150084113 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto. | 03-26-2015 |
20150084114 | NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 03-26-2015 |
20150091075 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device is provided. The element isolation insulating bodies form active areas extending in one direction along a surface of a semiconductor substrate in a surface region of the semiconductor substrate, and partition the surface region into the active areas. The tunnel insulating films are formed on the active areas respectively. The floating gate electrodes are formed on the tunnel insulating films respectively. The inter-gate insulating films are formed on the floating gate electrodes. The control gate electrodes are provided on the inter-gate insulating films. The source regions and drain regions are formed in the active areas respectively. Each of the active areas has steps at side surfaces. A width of a portion of each of the active areas deeper than the steps is larger than that of a portion of each of the active areas shallower than the steps. | 04-02-2015 |
20150123188 | METHODS AND APPARATUSES HAVING STRINGS OF MEMORY CELLS INCLUDING A METAL SOURCE - Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material. | 05-07-2015 |
20150123189 | METHODS AND APPARATUSES HAVING MEMORY CELLS INCLUDING A MONOLITHIC SEMICONDUCTOR CHANNEL - Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material. | 05-07-2015 |
20150123190 | NON-VOLATILE MEMORY DEVICE INTEGRATED WITH CMOS SOI FET ON A SINGLE CHIP - A structure and method provided for integrating SOI CMOS FETs and NVRAM memory devices. The structure includes a SOI substrate containing a semiconductor substrate, a SOI layer, and a BOX layer formed between the semiconductor substrate and the SOI layer. The SOI substrate includes predefined SOI device and NVRAM device regions. A SOI FET is formed in the SOI device region. The SOI FET includes portions of the BOX layer and SOI layers, an SOI FET gate dielectric layer, and a gate conductor layer. The structure further includes a NVRAM device formed in the NVRAM device region. The NVRAM device includes a tunnel oxide, floating gate, blocking oxide, and control gate layers. The tunnel oxide layer is coplanar with the portion of the BOX layer in the SOI device region. The floating gate layer is coplanar with the portion of the semiconductor layer in the SOI device region. | 05-07-2015 |
20150123191 | Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation - High-density semiconductor memory is provided with enhancements to gate-coupling and electrical isolation between discrete devices in non-volatile memory. The intermediate dielectric between control gates and charge storage regions is varied in the row direction, with different dielectric constants for the varied materials to provide adequate inter-gate coupling while protecting from fringing fields and parasitic capacitances. Electrical isolation is further provided, at least in part, by air gaps that are formed in the column (bit line) direction and/or air gaps that are formed in the row (word line) direction. | 05-07-2015 |
20150137208 | NAND STRING CONTAINING SELF-ALIGNED CONTROL GATE SIDEWALL CLADDING - A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates. | 05-21-2015 |
20150349081 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to an embodiment includes: a semiconductor layer; a block insulating film; an organic molecular layer, which is formed between the semiconductor layer and the block insulating film, and provided with a first organic molecular film on the semiconductor layer side containing first organic molecules and a second organic molecular film on the block insulating film side containing second organic molecules, and in which the first organic molecule has a charge storing unit and the second organic molecule is an amphiphilic organic molecule; and a control gate electrode formed on the block insulating film. | 12-03-2015 |
20150364482 | EMBEDDED NONVOLATILE MEMORY AND FORMING METHOD THEREOF - A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process. | 12-17-2015 |
20150380419 | METHOD OF SELECTIVELY DEPOSITING FLOATING GATE MATERIAL IN A MEMORY DEVICE - Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material. | 12-31-2015 |
20150380424 | METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES - A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses. | 12-31-2015 |
20160013310 | NON-VOLATILE FLOATING GATE MEMORY CELLS | 01-14-2016 |
20160027792 | SPLIT GATE MEMORY DEVICE, SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF - A split gate memory device, a semiconductor device and a manufacturing method thereof are provided. In the split gate memory device, an erasing gate is further disposed, wherein the easing gate and a control gate are respectively disposed on two sides of a floating gate. Thus, an erase operation is implemented by the erasing gate instead of the control gate. Accordingly, electric potential applied to the control gate is reduced. Therefore, hot-electron effect in channel region may be avoided, and performance degradation of the memory caused by the hot-electron effect may be avoided as well. Furthermore, as electric potential applied to the control gate is reduced, a gate oxide layer underneath the control gate may be thinner. Accordingly, manufacturing processes of the control gate and the gate oxide layer and that of the gate and the gate oxide layer of a logic transistor in a periphery circuit may be compatible. | 01-28-2016 |
20160064394 | Integrated Circuit for High-Voltage Device Protection - Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET. | 03-03-2016 |
20160064396 | FLASH MEMORY FABRICATION METHOD - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate comprising an active region, and successive layers of a tunnel oxide layer, a floating gate, a gate dielectric layer, a control gate overlying each other. A first portion of the tunnel oxide layer disposed on an edge of the active region has a thickness that is greater than a thickness of a second portion of the tunnel oxide layer disposed away from the edge of the active region. Such features ensure efficient reduction of read disturb errors of a Flash memory device. | 03-03-2016 |
20160071860 | 3D SEMICIRCULAR VERTICAL NAND STRING WITH SELF ALIGNED FLOATING GATE OR CHARGE TRAP CELL MEMORY CELLS AND METHODS OF FABRICATING AND OPERATING THE SAME - A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film contacting a first side of the semiconductor channel, and a second memory film contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film. | 03-10-2016 |
20160079253 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars. | 03-17-2016 |
20160087106 | E-FLASH CELL BAND ENGINEERING FOR ERASING SPEED ENHANCEMENT - The present disclosure relates to a structure and method for forming a flash memory cell with an improved erase speed and erase current. Si dots are used for charge trapping and an ONO sandwich structure is formed over the Si dots. Erase operation includes direct tunneling as well as FN tunneling which helps increase erase speed without compensating data retention. | 03-24-2016 |
20160093708 | METHODS OF FORMING MEMORY CELLS - Memory cells having conductive nanodots between a charge storage material and a control gate are useful in non-volatile memory devices and electronic systems. | 03-31-2016 |
20160099323 | SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION OF SAME - Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods. | 04-07-2016 |
20160104714 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF PRODUCING THE SAME - Provided is a semiconductor integrated circuit that uses a novel vertical MOS transistor that is free of interference between cells, that enables the short-channel effect to be minimized, that does not have hot electron injection, and that does not require the formation of shallow junction. Also provided is a method of producing the semiconductor integrated circuit. A memory cell | 04-14-2016 |
20160104720 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 04-14-2016 |
20160126248 | BAND GAP TAILORING FOR A TUNNELING DIELECTRIC FOR A THREE-DIMENSIONAL MEMORY STRUCTURE - The band gap structure of a tunneling dielectric can be tailored to facilitate programming and erasing of stored information, while enhancing charge storage during states without electrical bias between a semiconductor channel and charge storage elements. The tunneling dielectric includes a layered stack including at least, from outside to inside, a dielectric metal oxide layer and a silicon oxide layer. Upon application of electrical bias for programming or erasing, the band gap structure of the tunneling dielectric provides a lower tunneling barrier than an ONO stack of a comparable effective oxide thickness. Additionally, due to higher capacitive coupling to the channel with high-k metal oxide layer(s) in the tunneling dielectric, the efficiency of program, erase and read operations can be improved. During a zero-bias state, the tunneling dielectric can provide a higher energy barrier than the ONO stack, thereby providing enhanced data retention than the ONO stack. | 05-05-2016 |
20160126359 | SPLIT GATE FLASH CELL SEMICONDUCTOR DEVICE - A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors. | 05-05-2016 |
20160148945 | METAL WORD LINES FOR THREE DIMENSIONAL MEMORY DEVICES - A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions. | 05-26-2016 |
20160155749 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME | 06-02-2016 |
20160163721 | NON-VOLATILE MEMORY CELL AND METHOD OF MANUFACTURE - A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device. | 06-09-2016 |
20160163725 | SELECTIVE FLOATING GATE SEMICONDUCTOR MATERIAL DEPOSITION IN A THREE-DIMENSIONAL MEMORY STRUCTURE - A method of forming a three-dimensional memory device includes forming a stack of alternating first and second material layers over a substrate, forming a memory opening through the stack, forming a memory film and a semiconductor channel in the memory opening, and forming backside recesses by removing the second material layers selective to the first material layers and the memory film, where an outer sidewall of the memory film is physically exposed within each backside recess. The method also includes forming at least one set of surfaces selected from silicon deposition inhibiting surfaces on the first material layers and silicon deposition promoting surfaces over the memory film in the back side recesses, selectively growing a silicon-containing semiconductor portion laterally within each backside recess, forming at least one blocking dielectric within the backside recesses, and forming conductive material layers by depositing a conductive material within the backside recesses. | 06-09-2016 |
20160163729 | THREE-DIMENSIONAL MEMORY STRUCTURE HAVING A BACK GATE ELECTRODE - A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell. | 06-09-2016 |
20160172372 | SEMICONDUCTOR DEVICES | 06-16-2016 |
20160181267 | NON-VOLATILE MEMORY CELL, NAND-TYPE NON-VOLATILE MEMORY, AND METHOD OF MANUFACTURING THE SAME | 06-23-2016 |
20160181435 | FLOATING GATE TRANSISTORS AND METHOD FOR FORMING THE SAME | 06-23-2016 |
20160190334 | MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a memory device including a substrate, a plurality of tunneling dielectric layers, a plurality of isolation structures, and a plurality of cap layers. The tunneling dielectric layers are located on the substrate. Each isolation structure has an upper portion and a lower portion. The lower portions of the isolation structures are located in the substrate and arranged alternately with the tunneling dielectric layers along a first direction. The upper portions of the isolation structures are located on the lower portions. The cap layers are located on the upper portions. A top surface of the cap layer is a planar surface. | 06-30-2016 |
20190148540 | FLOATING GATE NON-VOLATILE MEMORY DEVICE | 05-16-2019 |