Entries |
Document | Title | Date |
20080203458 | Semiconductor Memory Device and Method of Fabricating the Same - This patent relates to a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include a semiconductor substrate in which a tunnel insulating layer, and a first conductive layer. At least a portion of the semiconductor substrate is removed to form a trench. A first insulating layer may be formed on an internal surface of the trench. A shield layer may be made of a conductive material is formed on the first insulating layer. A second insulating layer may be formed on the shield layer and is configured to gap fill the trench. | 08-28-2008 |
20080224199 | Non-volatile memory module package capability of replacing - A non-volatile memory module package capability of replacing, it may connected to a solid memory module, which includes a control unit, a system interface, and a first connector, the control unit may obtains external signals by the system interface, and then transmitted to this non-volatile memory module by the control unit to store or use the memory content. The package includes a substrate; a second connector is arranged on the substrate for inserting the first connector of the solid memory module; at least a non-volatile memory chip located on the substrate, and electrically connected the substrate and the second connector; at least a passive component is arranged on the substrate; and a compound resin is covered on the non-volatile memory chip and passive component. | 09-18-2008 |
20080237679 | SEMICONDUCTOR DEVICES WITH SIDEWALL CONDUCTIVE PATTERNS AND METHODS OF FABRICATING THE SAME - A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern and a sidewall conductive patter. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern. | 10-02-2008 |
20080246072 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor. | 10-09-2008 |
20080246073 | Nonvolatile Memory Devices Including a Resistor Region - Methods of forming a memory device include forming a device isolation layer in a semiconductor substrate including a cell array region and a resistor region, the device isolation layer extending into the resistor region and defining an active region in the semiconductor substrate. A first conductive layer is formed on the device isolation layer in the resistor region. The semiconductor substrate is exposed in the cell array region. A cell insulation layer is formed on a portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. A second conductive layer is formed on the cell insulation layer in the portion of the semiconductor substrate including the exposed cell array region, the active region and the device isolation layer in the resistor region. The second conductive layer is etched to form a cell gate electrode in the cell array region and to concurrently remove the second conductive layer from the resistor region and the first conductive layer is etched in the resistor region to form a resistor. | 10-09-2008 |
20080251830 | SEMICONDUCTOR STORAGE DEVICE AND DRIVING METHOD THEREOF - This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction. | 10-16-2008 |
20080258198 | STABILIZATION OF FLATBAND VOLTAGES AND THRESHOLD VOLTAGES IN HAFNIUM OXIDE BASED SILICON TRANSISTORS FOR CMOS - The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising:
| 10-23-2008 |
20080272422 | Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof - A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor. | 11-06-2008 |
20080272423 | Conductive structures, non-volatile memory device including conductive structures and methods of manufacturing the same - Conductive structures in an integrated circuit device including an integrated circuit substrate and first conductive layer patterns on the substrate. Second conductive layer patterns are on the substrate extending between respective ones of the first conductive layer patterns. Adjacent ones of the first and second conductive layer patterns are on different horizontal planes relative to the substrate to reduce parasitic capacitance therebetween. | 11-06-2008 |
20080283893 | ILLUMINATING EFFICIENCY-INCREASABLE AND LIGHT-ERASABLE EMBEDDED MEMORY STRUCTURE AND FABRICATING METHOD THEREOF - An illuminating efficiency-increasable and light-erasable embedded memory structure including a substrate, a memory device, many dielectric layers, many cap layers and at least three metal layers is described. The substrate includes a memory region and a core circuit region. The memory device includes a select gate and a floating gate, and the select gate and the floating gate are disposed adjacently on the substrate in the memory region. The dielectric layers are disposed on the substrate and cover the memory device. The dielectric layers have a first opening located above the floating gate. Each of the cap layers is disposed on each of the dielectric layers, respectively. The metal layers are disposed in the dielectric layers in the core circuit region. | 11-20-2008 |
20080283894 | Forming floating body RAM using bulk silicon substrate - A method for forming Z-RAM cells and the resulting semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate; a dielectric layer on the semiconductor substrate; an opening in the dielectric layer, wherein the semiconductor substrate is exposed through the opening; a semiconductor strip on the dielectric layer and adjacent the opening; a gate dielectric over a surface of the semiconductor strip; a gate electrode over the gate dielectric; and a source/drain region in the semiconductor strip and adjacent the gate electrode. | 11-20-2008 |
20080308855 | Memory devices with isolation structures and methods of forming and programming the same - Memory devices and methods of programming and forming the same are disclosed. In one embodiment, a memory device has memory cells contained within dielectric isolation structures to isolate them from at least those memory cells in communication with other bit lines, such as to facilitate forward-bias write operations. The dielectric isolation structures contain an upper well having a first conductivity type and a buried well having a second conductivity type. By forward biasing the junction from the buried well to the upper well, electrons can be injected into charge-storage nodes of memory cells that are contained within the dielectric isolation structures. | 12-18-2008 |
20080315278 | Insulated Gate Field Effect Transistors - The invention relates to FETs with stripe cells ( | 12-25-2008 |
20080315279 | NANOWIRE TRANSISTOR WITH SURROUNDING GATE - One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein. | 12-25-2008 |
20090001439 | Flash Memory Device and Method of Manufacturing the Same - Disclosed is a flash memory device. The flash memory device includes a plurality of trench lines in an isolation region of a semiconductor device, a common source region along a word line (WL) direction under a surface portion of the semiconductor substrate, a plurality of gate lines along a vertical direction of the trench line, a drain region on an opposite side of the gate line to the common source region, a drain contact over the drain region, and a uniform by-product layer on the common source region. | 01-01-2009 |
20090014769 | SUSPENDED-GATE MOS TRANSISTOR WITH NON-VOLATILE OPERATION - A transistor device with a mobile suspended gate, the device comprising means for piezoelectric actuation of the gate, and a method for producing such a device. | 01-15-2009 |
20090014770 | SEMICONDUCTOR DEVICE - A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode. | 01-15-2009 |
20090020799 | Semiconductor device and method of manufacturing the same - One embodiment in accordance with the invention can include a semiconductor device that includes: a groove that is formed in a semiconductor substrate; bottom oxide films that are formed on both side faces of the groove; two charge storage layers that are formed on side faces of the bottom oxide films; top oxide films that are formed on side faces of the two charge storage layers; and a silicon oxide layer that is formed on the bottom face of the groove, and has a smaller film thickness than the top oxide films. | 01-22-2009 |
20090026519 | Capacitorless dram and methods of manufacturing and operating the same - A capacitorless DRAM and methods of manufacturing and operating the same are provided. The capacitorless DRAM includes a source, a drain and a channel layer, formed on a substrate. A charge reserving layer is formed on the channel layer. The capacitorless DRAM includes a gate that contacts the channel layer and the charge reserving layer. | 01-29-2009 |
20090026520 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF FOR REDUCING THE AREA OF THE MEMORY CELL REGION - A structure is adopted for a layout of an SRAM cell which provides a local wiring | 01-29-2009 |
20090026521 | SELF-BIASING TRANSISTOR STRUCTURE AND AN SRAM CELL HAVING LESS THAN SIX TRANSISTORS - By providing a self-biasing semiconductor switch, an SRAM cell having a reduced number of individual active components may be realized. In particular embodiments, the self-biasing semiconductor device may be provided in the form of a double channel field effect transistor that allows the formation of an SRAM cell with less than six transistor elements and, in preferred embodiments, with as few as two individual transistor elements. | 01-29-2009 |
20090032858 | LAYOUT AND STRUCTURE OF MEMORY - A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on. | 02-05-2009 |
20090045447 | COMPLEX OXIDE NANODOTS - Methods and devices are disclosed, such as those involving forming a charge trap for, e.g., a memory device, which can include flash memory cells. A substrate is exposed to temporally-separated pulses of a titanium source material, a strontium source material, and an oxygen source material capable of forming an oxide with the titanium source material and the strontium source material to form the charge trapping layer on the substrate. | 02-19-2009 |
20090045448 | Non-volatile memory device and methods of forming the same - Example embodiments provide a non-volatile memory device and methods of forming the same. The non-volatile memory device may define an active region in a semiconductor substrate, and may include a device isolation layer extending in a first direction, bit lines in the semiconductor substrate, the bit lines extending in a second direction which intersects the first direction; word lines extending in the first direction and covering the active region; and charge storage patterns between the word lines and active region, wherein the charge storage patterns may be in pairs on both edges of the bit lines, and a pair of charge storage patterns may be spaced apart from each other by the word lines. | 02-19-2009 |
20090057743 | Integrated Circuit Including Structures Arranged at Different Densities and Method of Forming the Same - A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures. | 03-05-2009 |
20090057744 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 03-05-2009 |
20090065840 | FLASH MEMORY AND MANUFACTURING METHOD OF THE SAME - A flash memory and a manufacturing method of the same includes a shallow trench isolation and an active region formed at a substrate, a plurality of stacked gates formed on and/or over the active region, a deep implant region formed at a lower portion of the shallow trench isolation and the active region between the stacked gates and a shallow implant region formed at a surface of the active region between the stacked gates. | 03-12-2009 |
20090085087 | LINER FOR TUNGSTEN/SILICON DIOXIDE INTERFACE IN MEMORY - A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off. | 04-02-2009 |
20090085088 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME AS WELL AS DATA PROCESSING SYSTEM INCLUDING THE SEMICONDUCTOR DEVICE - A semiconductor device includes low voltage and high voltage transistors over a substrate. The low voltage transistor is configured by at least one unit transistor. The high voltage transistor is configured by a greater number of the unit transistors than the at least one unit transistor that configures the low voltage transistor. Each of the unit transistors may include a vertically extending portion of semiconductor providing a channel region and having a uniform height, a gate insulating film extending along a side surface of the vertically extending portion of semiconductor, a gate electrode separated by the gate insulating film from the vertically extending portion of semiconductor, and upper and lower diffusion regions being respectively disposed near the top and bottom of the vertically extending portion of semiconductor. The greater number of the unit transistors are connected in series to each other and have gate electrodes eclectically connected to each other. | 04-02-2009 |
20090090952 | PLASMA SURFACE TREATMENT FOR SI AND METAL NANOCRYSTAL NUCLEATION - A device, such as a nonvolatile memory device, and methods for forming the device in an integrated process tool are provided. The method includes depositing a tunnel oxide layer on a substrate, exposing the tunnel oxide layer to a plasma so that the plasma alters a morphology of a surface and near surface of the tunnel oxide to form a plasma altered near surface. Nanocrystals are then deposited on the altered surface of the tunnel oxide. | 04-09-2009 |
20090090953 | FLASH MEMORY DEVICE WITH STRAIGHT WORD LINES - Embodiments of the present invention disclose a memory device having an array of flash memory cells with source contacts that facilitate straight word lines, and a method for producing the same. The array is comprised of a plurality of non-intersecting shallow trench isolation (STI) regions that isolate a plurality of memory cell columns. A source column is implanted with n-type dopants after the formation of a tunnel oxide layer and a first polysilicon layer. The implanted source column is coupled to a plurality of common source lines that are coupled to a plurality of source regions associated with memory cells in the array. A source contact is coupled to the implanted source column for providing electrical coupling with the plurality of source regions. The source contact is collinear with a row of drain contacts that are coupled to drain regions associated with a row of memory cells. The arrangement of source contacts collinear with the row of drain contacts allows for straight word line formation. | 04-09-2009 |
20090096004 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that the quantum dot elements are connected with a bit line in series, wherein each quantum dot element forms a single electron memory. | 04-16-2009 |
20090101959 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar. | 04-23-2009 |
20090108321 | FLASH MEMORY - A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate. | 04-30-2009 |
20090108322 | SEMICONDUCTOR MEMORY HAVING BOTH VOLATILE AND NON-VOLATILE FUNCTIONALITY AND METHOD OF OPERATING - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor memory cell includes a fin structure extending from a substrate, the fin structure including a floating substrate region having a first conductivity type configured to store data as volatile memory; first and second regions interfacing with the floating substrate region, each of the first and second regions having a second conductivity type; first and second floating gates or trapping layers positioned adjacent opposite sides of the floating substrate region; a first insulating layer positioned between the floating substrate region and the floating gates or trapping layers, the floating gates or trapping layers being configured to receive transfer of data stored by the volatile memory and store the data as nonvolatile memory in the floating gates or trapping layers upon interruption of power to the memory cell; a control gate wrapped around the floating gates or trapping layers and the floating substrate region; and a second insulating layer positioned between the floating gates or trapping layers and the control gate; the substrate including an isolation layer that isolates the floating substrate region from a portion of the substrate below the isolation layer. | 04-30-2009 |
20090140312 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surface thereof above the opening, a memory cell unit provided on the semiconductor layer and including a plurality of memory cells, current paths of the memory cells being connected in series, a selecting transistor adjacent to the memory cell unit and arranged on a region of the semiconductor layer including the recess, the selecting transistor including a gate insulating film provided on the region of the semiconductor layer including the recess and a gate electrode provided on the gate insulating film. | 06-04-2009 |
20090140313 | Nonvolatile memory devices and methods of forming the same - A method of forming nonvolatile memory devices according to example embodiments of the present invention includes forming a device isolation layer defining active regions in a semiconductor substrate; forming a plurality of transistors on the active regions, the plurality of transistors comprising a pair of adjacent string selection transistors, a pair of adjacent ground selection transistors, and a plurality of memory cell transistors connected in series between the string selection transistors and ground selection transistors; forming a common source line using SEG between a pair of adjacent ground selection transistors so that the common source line has a top surface lower than a top surface of the pair of adjacent ground selection transistors. | 06-04-2009 |
20090146201 | WORK FUNCTION ENGINEERING FOR FN ERAS OF A MEMORY DEVICE WITH MULTIPLE CHARGE STORAGE ELEMENTS IN AN UNDERCUT REGION - A memory device comprised of a plurality of memory cells that can each include multiple charge storage elements in undercut regions that are formed under a tunneling barrier and adjacent to a gate oxide layer of each memory cell. The tunneling barrier can be formed from a high work function material, such as P+ polycrystalline silicon or a P-type metal, and/or a high-K material. The memory cell can reduce the likelihood of gate electron injection through the gate electrode and into the charge storage elements during a Fowler-Nordheim erase by employing such tunneling barrier. Systems and methods of fabricating memory devices having at least one such memory cell are provided. | 06-11-2009 |
20090159949 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MEMORY CELL HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and a voltage generator. In the memory cell unit, memory cells having a charge accumulation layer and a control gate are connected in series. The word lines are connected to the control gates. The driver circuit selects the word lines. The voltage generator generates a first voltage and a second voltage lower than the first voltage. The first voltage is used by the first driver circuit to transfer a voltage to the unselected word line. The second voltage is used by circuits other than the first driver circuit. | 06-25-2009 |
20090173983 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity. | 07-09-2009 |
20090230450 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers. | 09-17-2009 |
20090236650 | TANTALUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film. | 09-24-2009 |
20090250740 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a semiconductor substrate in which a plurality of device regions and a plurality of device isolation regions are alternately formed to extend in a first direction; and a plurality of contact plugs formed on the semiconductor substrate, connected to the device regions and arranged on the semiconductor substrate in a zigzag pattern in a second direction perpendicular to the first direction, wherein the contact plugs have a rectangular cross section. | 10-08-2009 |
20090256186 | SPLIT GATE NON-VOLATILE MEMORY CELL - A non-volatile memory (NVM) cell comprising a layer of discrete charge storing elements, a control gate, and a select gate is provided. The control gate has a first sidewall with a lower portion being at least a first angle 10 degrees away from 90 degrees with respect to substrate. Further, the select gate has a second sidewall with a lower portion being at least a second angle at least 10 degrees away from 90 degrees with respect to the substrate. The NVM cell further comprises a layer of dielectric material located between the first sidewall and the second sidewall. | 10-15-2009 |
20090256187 | SEMICONDUCTOR DEVICE HAVING VERTICAL PILLAR TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes vertical pillar transistors formed in respective silicon pillars of a silicon substrate. The gates of the vertical pillar transistor are selectively formed on a single surface of lower portions of the silicon pillars, and drain areas of the vertical pillar transistors are connected with one another. | 10-15-2009 |
20090267127 | Single Poly NVM Devices and Arrays - A single-poly non-volatile memory includes a PMOS select transistor ( | 10-29-2009 |
20090267128 | THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY - A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks. | 10-29-2009 |
20090278184 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE IN WHICH DECREASE IN COUPLING RATIO OF MEMORY CELLS IS SUPPRESSED - A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer. | 11-12-2009 |
20090283811 | Flash memory device and methods of forming the same - A flash memory device and/or methods of forming the flash memory device are provided, the flash memory device including a charge storage gate, a gate pattern over the charge storage gate, and a charge storage metal layer disposed between a side surface of the charge storage gate and the gate pattern. The methods include forming a preliminary charge storage gate pattern and forming a metal layer over a side surface of the preliminary charge storage gate pattern. | 11-19-2009 |
20090294821 | SEMICONDUCTOR DEVICE HAVING DRIVING TRANSISTORS - One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion. | 12-03-2009 |
20090294822 | CIRCUIT WITH TRANSISTORS INTEGRATED IN THREE DIMENSIONS AND HAVING A DYNAMICALLY ADJUSTABLE THRESHOLD VOLTAGE VT - A microelectronic device comprising:
| 12-03-2009 |
20090294823 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT USING A SELECTIVE DISPOSAL SPACER TECHNIQUE AND SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURED THEREBY - Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby. The method includes providing a semiconductor substrate; forming gate patterns on the semiconductor substrate, wherein a first space and a second space wider than the first space are disposed between the gate patterns; forming a first impurity region in the semiconductor substrate under the first space and forming a second impurity region in the semiconductor substrate under the second space; forming insulation spacers on sidewalls of the gate patterns, wherein a portion of the second impurity region is exposed and the first impurity region is covered with the insulation spacers; etching the insulation spacers, wherein an opening width of the second impurity region is enlarged and wherein the etching is carried out with a wet etching process; and forming an interlayer insulating layer on the overall structure including the gate patterns. | 12-03-2009 |
20090309148 | SEMICONDUCTOR STRUCTURE INCLUDING GATE ELECTRODE HAVING LATERALLY VARIABLE WORK FUNCTION - A semiconductor structure, such as a CMOS structure, includes a gate electrode that has a laterally variable work function. The gate electrode that has the laterally variable work function may be formed using an angled ion implantation method or a sequential layering method. The gate electrode that has the laterally variable work function provides enhanced electrical performance within an undoped channel field effect transistor device. | 12-17-2009 |
20090315093 | ATOMIC LAYER DEPOSITION OF METAL CARBIDE FILMS USING ALUMINUM HYDROCARBON COMPOUNDS - Methods of forming metal carbide films are provided. In some embodiments, a substrate is exposed to alternating pulses of a transition metal species and an aluminum hydrocarbon compound, such as TMA, DMAH, or TEA. The aluminum hydrocarbon compound is selected to achieve the desired properties of the metal carbide film, such as aluminum concentration, resistivity, adhesion and oxidation resistance. In some embodiments, the methods are used to form a metal carbide layer that determines the work function of a control gate in a flash memory. | 12-24-2009 |
20090315094 | Nonvolatile Memory Device - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string. | 12-24-2009 |
20090315095 | Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof - In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs. | 12-24-2009 |
20100001333 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR - The present invention provides semiconductor device and a fabrication method therefor. The semiconductor device includes trenches ( | 01-07-2010 |
20100019303 | METHOD FOR FORMING CONDUCTIVE PATTERN, SEMICONDUCTOR DEVICE USING THE SAME AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating conductive patterns includes forming a conductive layer over a substrate, etching the conductive layer to a first thickness to form first patterns, forming spacers on sidewalls of the first patterns, and etching the conductive layer to a second thickness using the spacers as an etch barrier to form second patterns. Thus, conductive patterns can be formed with vertical sidewalls without being damaged, and lean and collapse of the conductive patterns are prevented. | 01-28-2010 |
20100019304 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains. | 01-28-2010 |
20100044768 | REDUCED-EDGE RADIATION-TOLERANT NON-VOLATILE TRANSISTOR MEMORY CELLS - An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. | 02-25-2010 |
20100044769 | METHOD OF MANUFACTURE OF CONTACT PLUG AND INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas. | 02-25-2010 |
20100052030 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory of an aspect of the present invention including a plurality of first active areas which are provided in the memory cell array side-by-side in a first direction and which have a dimension smaller than a fabrication limit dimension obtained by lithography, a second active area provided between the first active areas adjacent in the first direction, a memory cell unit which is provided in each of the plurality of first active areas and which has memory cells and select transistors, and a linear contact which is connected to one end of the memory cell unit and which extends in the first direction, wherein an area in which the linear contact is provided is one semiconductor area to which the plurality of first active areas are connected by the plurality of second active areas, and the bottom surface of the linear contact is planar. | 03-04-2010 |
20100065899 | SEMICONDUCTOR DEVICES INCLUDING AUXILIARY GATE ELECTRODES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode may be provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes may be configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed. | 03-18-2010 |
20100065900 | SEMICONDUCTOR DEVICE INCLUDING RESISTANCE ELEMENT - A semiconductor device includes a resistance element. The resistance element includes a first and second conductive films, second insulating film, and contact plugs. The first conductive film is formed on a semiconductor substrate with a first insulating film interposed therebetween. The second insulating film is formed on the first conductive film. The second conductive film is formed on the second insulating film. In the first connection portion, the second insulating film is removed. The first connection portion connects the first conductive film and the second conductive film together. The contact plugs are formed on the second conductive film. The contact plugs are arranged such that a region located on the second conductive film and immediately above the connection portion is sandwiched between the contact plugs. | 03-18-2010 |
20100072533 | ASYMMETRIC CHANNEL DOPING FOR IMPROVED MEMORY OPERATION FOR FLOATING BODY CELL (FBC) MEMORY - An improved dynamic memory cell using a semiconductor fin or body is described. Asymmetrical doping is used in the channel region, with more dopant under the back gate to improve retention without significantly increasing read voltage. | 03-25-2010 |
20100078701 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING REPEATING LAYER PATTERNS OF DIFFERENT THICKNESSES - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 04-01-2010 |
20100096682 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device has a memory string including a plurality of electrically rewritable memory cells connected in series. The non-volatile semiconductor storage device also has a protruding layer formed to protrude upward with respect to a substrate. The memory string includes: a plurality of first conductive layers laminated on the substrate; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and an electric charge storage layer formed between the first conductive layers and the first semiconductor layer, and configured to be able to store electric charges. Each of the plurality of first conductive layers includes: a bottom portion extending in parallel to the substrate; and a side portion extending upward with respect to the substrate along the protruding layer at the bottom portion. The protruding layer has a width in a first direction parallel to the substrate that is less than or equal to its length in a lamination direction. | 04-22-2010 |
20100109065 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES - Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar. | 05-06-2010 |
20100117134 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A dielectric film is formed on a silicon substrate made of single crystal silicon, an opening is formed in the dielectric film, an amorphous silicon film is formed on the dielectric film, the amorphous silicon film being in contact with the silicon substrate through the opening, solid-phase epitaxial growth of this amorphous silicon film is caused to start at the silicon substrate, and thereafter patterning is performed. Thereby, a seed layer made of the single crystal silicon is formed in part of a region deviated from immediately above the opening. Next, the amorphous silicon film is deposited so as to cover the seed layer, forming a single crystal silicon film by solid-phase epitaxial growth of the amorphous silicon film starting at the seed layer. The silicon pillar is formed by patterning the single crystal silicon film. | 05-13-2010 |
20100117135 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer. | 05-13-2010 |
20100133598 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, and a plurality of gate electrodes. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicular to the semiconductor substrate. The gate electrodes include a first gate electrode and a second gate electrode. The first gate electrode is disposed on the memory cell region to intersect the active pillars. The second gate electrode is disposed on the contact region, connected to the first gate electrode and comprising metal material. | 06-03-2010 |
20100140678 | FLASH MEMORY DEVICE AND MANUFACRUTING METHOD THE SAME - A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include a device isolation layer and/or an active area formed on and/or over a semiconductor substrate. A flash memory device may include a memory gate formed on and/or over an active area and/or a control gate formed on and/or over a semiconductor substrate including a memory gate. Active areas may be formed having substantially the same interval with bit lines. A common source line area where a common source line contact may be formed may include a bridge formed between active areas. Neighboring active areas may be connected. | 06-10-2010 |
20100163951 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A flash memory device is disclosed including: a device isolation layer and an active area formed on a semiconductor substrate in which a source plate and a bit line area are defined; a memory gate formed over the active area of the bit line area; a control gate formed on the semiconductor substrate including the memory gate; a common source area and a drain area disposed on both sides of the control gate; and a common source line contact formed over the common source area of the semiconductor substrate at the active area of the source plate, wherein the active area of the source plate is formed having the same interval with the active area of the bit line area, and the control gate is formed to cross the source plate and the bit line area disposed at both sides of the source plate. | 07-01-2010 |
20100171161 | DOUBLE-IMPLANT NOR FLASH MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a double-implant NOR flash memory structure, a phosphorus ion implantation process is performed, so that a P-doped drain region is formed in a semiconductor substrate between two gate structures to overlap with a highly-doped drain (HDD) region and a lightly-doped drain (LDD) region. Therefore, the electric connection at a junction between the HDD region and the LDD region is enhanced and the carrier mobility in the memory is not lowered while the problems of short channel effect and punch-through of LDD region are solved. | 07-08-2010 |
20100171162 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement. | 07-08-2010 |
20100171163 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES INCLUDING SELECT GATE PATTERNS HAVING DIFFERENT WORK FUNCTION FROM CELL GATE PATTERNS - A three-dimensional semiconductor device includes a vertical channel pattern on the substrate, a plurality of cell gate patterns and a select gate pattern stacked on the substrate along the sidewall of the vertical channel pattern, a charge storage pattern between the vertical channel pattern and the cell gate pattern and a select gate pattern between the vertical channel pattern and the select gate pattern. The select gate pattern has a different work function from the cell gate pattern | 07-08-2010 |
20100181608 | FLASH MEMORY DEVICE AND METHOD MANUFACTURING THE SAME - According to the present disclosure, a flash memory device includes a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers. | 07-22-2010 |
20100181609 | Flash Memory Device and Method of Manufacturing the Same - Disclosed herein are flash memory devices and methods of making the same. According to one embodiment, a flash memory device includes first trenches formed in a semiconductor substrate and arranged in parallel, second trenches discontinuously formed in the semiconductor substrate and arranged between the first trenches, first isolation structures respectively formed within the first trenches, second isolation structures respectively formed within the second trenches, and active regions defined by the first isolation structures and the second isolation structures. | 07-22-2010 |
20100181610 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE - Provided are nonvolatile memory devices with a three-dimensional structure and methods of fabricating the same. The nonvolatile memory device includes conductive patterns three-dimensionally arranged on a semiconductor substrate, semiconductor patterns that extend from the semiconductor substrate and intersect one-side walls of the conductive patterns, charge storage layers interposed between the semiconductor patterns and one-side walls of the conductive patterns, and seed layer patterns interposed between the charge storage layers and one-side walls of the conductive patterns. | 07-22-2010 |
20100187590 | Semiconductor device including metal insulator semiconductor transistor - A semiconductor device includes a plurality of metal insulator semiconductor (MIS) transistors. The plurality of MIS transistors each includes a gate electrode formed above a channel region of a semiconductor substrate via a gate insulating film and source/drain regions formed on both sides of the channel region. The gate electrode is electrically connected to an interconnect via a first plug. The interconnect has a plurality of vias formed thereon. The plurality of MIS transistors have threshold voltages different from one another due to variations in quantities of electric charges trapped by the gate insulating films respectively corresponding to the plurality of MIS transistors. | 07-29-2010 |
20100187591 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction. | 07-29-2010 |
20100193854 | NON-VOLATILE MEMORY DEVICE USING HOT-CARRIER INJECTION - Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation). | 08-05-2010 |
20100193855 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SAME - A non-volatile semiconductor memory device of small size and high reliability includes a semiconductor substrate; a charge storage film disposed on the semiconductor substrate; a first gate electrode disposed on the charge storage film; a gate insulating film disposed on the semiconductor substrate; a second gate electrode disposed on the gate insulating film; and an inter-gate insulating film disposed between the first gate electrode and the second gate electrode. The length of the first gate electrode is smaller than the length of the second gate electrode. The top surface of the first gate electrode is neither curved nor inclined with respect to the semiconductor substrate. | 08-05-2010 |
20100200902 | NAND Flash Memory Device - A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices. | 08-12-2010 |
20100207182 | Implementing Variable Threshold Voltage Transistors - A circuit and method for implementing variable threshold voltage transistors in a complementary metal oxide semiconductor (CMOS) semiconductor chip, and a design structure on which the subject circuit resides are provided. Variable threshold voltage transistors are provided utilizing the NWELL and PWELL proximity effects of the CMOS semiconductor chip without any additional mask steps. A distance between an adjacent field effect transistor (FET) and an NWELL edge or PWELL edge is adjusted to selectively provide a needed threshold voltage for the FET. | 08-19-2010 |
20100207183 | SRAM Cell with Asymmetrical Pass Gate - A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region ( | 08-19-2010 |
20100207184 | Semiconductor devices and methods of forming the same - A semiconductor device includes insulating patterns and gate patterns alternately stacked on a substrate; an active pattern on the substrate, which extends upward along sidewalls of the insulating patterns and the gate patterns; data storage patterns interposed between the gate patterns and the active pattern; and a source/drain region disposed in the active pattern between a pair of gate patterns adjacent to each other. | 08-19-2010 |
20100207185 | Nonvolatile Memory Device and Method of Manufacturing the Same - A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the semiconductor substrate and crossing sidewalls of the gate electrodes, a metal liner pattern formed between the semiconductor pattern and formed on a top surface and a bottom surface of each of the gate electrodes, and a charge storage layer formed between the semiconductor pattern and the metal liner pattern. | 08-19-2010 |
20100207186 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A first region comprises: a semiconductor layer including a columnar portion, a charge storage layer, and a plurality of first conductive layers. The second region comprises: a plurality of second conductive layers formed in the same layer as the plurality of first conductive layers. The plurality of first conductive layers configure a stepped portion at an end vicinity of the first region. The stepped portion is formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The plurality of second conductive layers is formed such that positions of ends thereof at an end vicinity of the second region surrounding the first region are aligned in substantially the perpendicular direction to the substrate. | 08-19-2010 |
20100213526 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof. | 08-26-2010 |
20100213527 | Integrated Circuit Memory Devices Having Selection Transistors with Nonuniform Threshold Voltage Characteristics - Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region. | 08-26-2010 |
20100213528 | METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING AN ARRAY STRUCTURE COMPRISING THE SAME DEVICES - The present invention discloses a metal oxide semiconductor (MOS) device and a method for operating an array structure comprising the same devices. The MOS device of the present invention comprises a device layer; an ion-implanted layer formed on the device layer and providing the source, the drain and the channel; and a gate structure formed on the ion-implanted layer. Via applying a bias voltage to the gate, the carrier density in the channel region is different from that in the source region or the drain region; thereby, the MOS device of the present invention can undertake programming, erasing and reading activities. The present invention can simplify the MOS device fabrication process, reduce the operating voltage, and promote the integration density of a 2-dimensional or 3-dimensional MOS device array. | 08-26-2010 |
20100230738 | NOR FLASH MEMORY STRUCTURE WITH HIGHLY-DOPED DRAIN REGION AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a NOR flash memory structure, a highly-doped ion implantation process is performed to form a highly-doped drain region to overlap with a lightly-doped drain region. Therefore, the flash memory structure can have a reduced drain junction depth to improve the short channel effect while protecting the lightly-doped drain region from being punched through during an etching process for forming a contact hole. | 09-16-2010 |
20100244114 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile memory device includes: at least one first interconnection extending in a first direction; at least one second interconnection disposed above the first interconnection and extending in a second direction nonparallel to the first direction; a memory cell disposed between the first interconnection and the second interconnection at an intersection of the first interconnection and the second interconnection and including a memory element; and an element isolation layer disposed between the memory cells. At least one dielectric film with a higher density than the element isolation layer is disposed on a sidewall surface of the memory cell. | 09-30-2010 |
20100244115 | ANTI-FUSE MEMORY CELL - An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor. | 09-30-2010 |
20100283095 | Flash Memory Device - A method of manufacturing a flash memory device is disclosed. The method includes the steps of providing a semiconductor substrate in which a cell region and a select transistor region are defined, etching the semiconductor substrate in the select transistor region so that there is a first step between the cell region and the select transistor region, forming a cell gate in the cell region, and forming a transistor in the select transistor region. | 11-11-2010 |
20100295111 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor element and a protection diode formed on a semiconductor substrate. Over the semiconductor substrate, a first interlayer dielectric layer is formed so as to cover the semiconductor element and the protection diode. In the first interlayer dielectric layer, a first plug electrically connected to the semiconductor element and a second plug electrically connected to the protection diode are formed. The area of the top surface of the second plug is greater than the area of the top surface of the first plug. | 11-25-2010 |
20100308391 | SEMICONDUCTOR DEVICE - Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed. | 12-09-2010 |
20100327338 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 12-30-2010 |
20110006354 | METAL GATE STRUCTURE OF A SEMICONDUCTOR DEVICE - A semiconductor device structure, for improving the metal gate leakage within the semiconductor device. A structure for a metal gate electrode for a n-type Field Effect Transistor includes a capping layer; a first metal layer comprising Ti and Al over the capping layer; a metal oxide layer over the first metal layer; a barrier layer over the metal oxide layer; and a second metal layer over the barrier layer. | 01-13-2011 |
20110018046 | METHOD OF MANUFACTURE OF CONTACT PLUG AND INTERCONNECTION LAYER OF SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming two first gate electrodes along a first direction on a first surface of a semiconductor substrate and source/drain areas sandwiching a channel region under each of the first gate electrodes, forming a first interlayer insulating layer to fill a region between the first gate electrodes, lowering a top of the first interlayer insulating layer, depositing a second interlayer insulating layer on the first interlayer insulating layer and the first gate electrodes, planarizing a surface of the second interlayer insulating layer, and forming an interconnect layer in the second interlayer insulating layer and a contact plug in the first interlayer insulating layer and the second interlayer insulating layer so that the contact plug is in contact with the interconnect layer and one of the source/drain areas. | 01-27-2011 |
20110024816 | FLASH MEMORY DEVICE HAVING VERTICLE CHANNEL STRUCTURE - A flash memory device having a vertical channel structure. The flash memory device includes a substrate having a surface that extends in a first direction, a channel region having a pillar shape and extending from the substrate in a second direction that is perpendicular to the first direction, a gate dielectric layer formed around the channel region, a memory cell string comprising a plurality of transistors sequentially formed around the channel region in the second direction, wherein the gate dielectric layer is disposed between the plurality of transistors and the channel region, and a bit line connected to one of the plurality of transistors, and surrounding a side wall and an upper surface of one end of the channel region so as to directly contact the channel region. | 02-03-2011 |
20110024817 | FLASH MEMORY DEVICE AND MASK FOR FABRICATING THE SAME - A flash memory device includes an active region, drain contacts, a source contact line, and source contacts. The active regions are formed on a substrate extend at least from a source region to a drain region of the substrate. The drain contacts are formed over the active regions in the drain region. The source contact line is formed in the source region of the semiconductor substrate. The source contact line intersects the active regions and is continuously line-shaped. The source contact line includes source contacts formed at locations where the source contact line and the active regions intersect. The source contacts are zigzag-shaped and are separated from corresponding drain contacts by a given distance. | 02-03-2011 |
20110024818 | VERTICAL CHANNEL TYPE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench. | 02-03-2011 |
20110037112 | NONVOLATILE MEMORY DEVICES WITH OBLIQUE CHARGE STORAGE REGIONS AND METHODS OF FORMING THE SAME - A nonvolatile memory device includes an active region defined by a device isolation layer in a semiconductor substrate, a word line passing over the active region and a charge storage region defined by a crossing of the active region and the word line and disposed between the active region and the word line. The charge storage region is disposed at an oblique angle with respect to the word line. | 02-17-2011 |
20110042735 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device in accordance with an exemplary aspect of the present invention includes a state storage element and a transistor. In the state storage element, a first conductive region, a first insulating film, and a first electrode are successively formed on a semiconductor substrate. Further, a second insulating film and a second electrode are successively formed on the semiconductor substrate. The transistor includes the first conductive region, a second conductive region, a second insulating film, and a second electrode. The second insulating film and the second electrode are successively formed between the first and second conductive regions on the semiconductor substrate. The withstand voltage against dielectric breakdown of the first insulating film is lower than that of the second insulating film. | 02-24-2011 |
20110057241 | FORMING SILICON TRENCH ISOLATION (STI) IN SEMICONDUCTOR DEVICES SELF-ALIGNED TO DIFFUSION - Silicon trench isolation (STI) is formed between adjacent diffusions in a semiconductor device, such as between bitlines in a memory array. The STI may be self-aligned to the diffusions, and may prevent misaligned bitline (BL) contacts from contacting silicon outside of the corresponding bitlines. The bitline contacts may have sufficient overlap of the bitlines to ensure full coverage by the bitlines. Bitline oxides formed over buried bitlines may be used to self-align trenches of the STI to the bitlines. The STI trenches may be lined with a CMOS spacer, salicide blocking layer and/or a contact etch stop layer. STI may be formed after Poly-2 etch or after word line salicidation. The memory cells may be NVM devices such as NROM, SONOS, SANOS, MANOS, TANOS or Floating Gate (FG) devices. | 03-10-2011 |
20110057242 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device having a source-side-injected split-gate type of nonvolatile memory cell which can be formed by a one-layer polysilicon CMOS process is provided. A memory cell includes a first memory cell unit including first and second diffusion regions formed on a semiconductor substrate surface, and first and second gate electrodes separately formed through a gate insulation film on a first channel region between the first and second diffusion regions, a second memory cell unit including third and fourth diffusion regions formed on the semiconductor substrate surface, and a third gate electrode formed through a gate insulation film on a second channel region between the third and fourth diffusion regions, and a control terminal. The first to third gate electrodes are formed of the same electrode material layer. The second and third gate electrodes are electrically connected to form a floating gate capacitively coupled to the control terminal. | 03-10-2011 |
20110057243 | NON-VOLATILE MEMORY WITH A STABLE THRESHOLD VOLTAGE ON SOI SUBSTRATE - A non-volatile memory disposed in a SOI substrate is provided. The non-volatile memory includes a memory cell and a first conductive type doped region. The memory cell includes a gate, a charge storage structure, a bottom dielectric layer, a second conductive type drain region, and a second conductive type source region. The gate is disposed on the SOI substrate. The charge storage structure is disposed between the gate and the SOI substrate. The bottom dielectric layer is disposed between the charge storage layer and the SOI substrate. The second conductive type drain region and the second conductive type source region are disposed in a first conductive type silicon body layer next to the two sides of the gate. The first conductive type doped region is disposed in the first conductive type silicon body layer and electrically connected to the first conductive type silicon body layer beneath the gate. | 03-10-2011 |
20110068385 | SEMICONDUCTOR DEVICE - It is an object of the invention to provide semiconductor devices which can protect privacy of consumers or holders of commercial products and control the communication range according to use, even when the semiconductor device which can exchange data without contact is mounted on the commercial products. A semiconductor device of the invention includes an element group including a plurality of transistors over a substrate; a first conductive film functioning as an antenna over the element group; a second conductive film surrounding the first conductive film; an insulating film covering the first and second end portions; and a third conductive film over the insulating film. The first conductive film is provided in the shape of a coil, and each end portion of the first conductive film is connected to the element group. First and second end portions of the second conductive film are not connected to each other. | 03-24-2011 |
20110073926 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes a memory cell array and plural transfer transistors. The plural transfer transistors include: a gate electrode formed on a semiconductor substrate via a gate insulating film; a first diffused region formed in a surface of the semiconductor substrate located under the gate electrode; a second diffused region formed in a surface of the semiconductor substrate adjoining the first diffused region; and a third diffused region formed in a surface of the semiconductor substrate sandwiching the first diffused region with the second diffused region. The third diffused region includes an overlapping region overlapping the first diffused region. A first wire is disposed above the overlapping region. The first wire is supplied with at least a certain voltage for preventing formation of a depletion region in the third diffused region when the transfer transistor transfers the voltage used for writing. | 03-31-2011 |
20110073927 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a non-volatile memory device includes a stacked structure including a memory portion and an electrode having a surface facing the memory portion; and a voltage application portion to apply a voltage to the memory portion to change resistance. The surface includes first and second regions. The first region contains a first nonmetallic element and at least one element of a metallic element, Si, Ga, and As. The second region contains a second nonmetallic element and the at least one element. The second region has a content ratio of the second nonmetallic element higher than that in the first region. A difference in electronegativity between the second nonmetallic element and the at least one element is greater than that between the first nonmetallic element and the at least one element. At least one of the first and second regions has an anisotropic shape. | 03-31-2011 |
20110115009 | CONTROL GATE - A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation. | 05-19-2011 |
20110115010 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level. | 05-19-2011 |
20110115011 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE - The object of the invention is to provide a semiconductor device realizing high-speed operation of surrounding gate transistors (SGTs), which are three-dimensional semiconductors, by increasing the ON current of the SGTs. This object is achieved by a semiconductor element being provided in which a source, a drain and a gate are positioned in layers on a substrate, the semiconductor element being provided with: a silicon column; an insulating body surrounding the side surface of the silicon column; a gate surrounding the insulating body; a source region positioned above or below the silicon column; and a drain region positioned below or above the silicon column; wherein the contact surface of the silicon column with the source region is smaller than the contact surface of the silicon column with the drain region. | 05-19-2011 |
20110127597 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device with charge storage layers with high reliability is provided. A plurality of insulating films and a plurality of electrode films 14 are alternately stacked on a substrate 11, and a plurality of selection gate electrodes 17 extending in the X direction and a plurality of bit lines BL extending in the Y direction are provided thereon. U-shaped silicon members 33 are provided, each of which is constituted by a plurality of silicon pillars 31 passing through the electrode films 14 and the selection gate electrode 17, whose upper ends are connected to the bit lines BL, and a connective member 32 connecting lower parts of one pair of the silicon pillars 31 disposed in diagonal positions. The electrode film 14 of each layer is divided for the respective selection gate electrodes 17. One pair of the silicon pillars 31 connected to one another through the connective member 32 are caused to pass through the different electrode films 14 and the different selection gate electrodes 17. All of the U-shaped silicon members 33 connected commonly to one bit line BL are commonly connected to another bit line BL. | 06-02-2011 |
20110147818 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes: a substrate; a memory multilayer body with a plurality of insulating films and electrode films alternately stacked therein, the memory multilayer body being provided on a memory array region of the substrate; a semiconductor pillar buried in the memory multilayer body and extending in stacking direction of the insulating films and the electrode films; a charge storage film provided between one of the electrode films and the semiconductor pillar; a dummy multilayer body with a plurality of the insulating films and the electrode films alternately stacked therein and a dummy hole formed therein, the dummy multilayer body being provided on a peripheral circuit region of the substrate; an insulating member buried in the dummy hole; and a contact buried in the insulating member and extending in the stacking direction. | 06-23-2011 |
20110156121 | MEMORY CELL WITH IMPROVED RETENTION - A method for forming a device is presented. A substrate prepared with a feature having first and second adjacent surfaces is provided. A device layer is formed on the first and second adjacent surfaces of the feature. A first portion of the device layer over the first adjacent surface includes nano-crystals, whereas a second portion of the device layer over the second adjacent surface is devoid of nano-crystals. | 06-30-2011 |
20110156122 | High Density NOR Flash Array Architecture - In one embodiment of the invention, a memory includes wordline jogs and adjacent spacers. Spacers from different wordlines may contact one another on either side of a drain contact and consequently isolate and self-align the contact in the horizontal and vertical directions. | 06-30-2011 |
20110198680 | Non-Volatile Memory Device Including Quantum Dots Embeded in Oxide Thin Film, and Fabrication Method of the Same - A non-volatile memory device is provided in which quantum dots are embedded in an oxide thin film formed on a substrate. A conventional Si CMOS process can be used to manufacture the non-volatile memory device in a cost-effective way. Also, a photonic device and an electronic/photonic device, which can store a light signal or emit a stored signal as light, can be produced on a Si wafer in a cost-effective manner. | 08-18-2011 |
20110233636 | Semiconductor Memory Device and Method of Manufacturing the Same - A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures. | 09-29-2011 |
20110266604 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of strings each having vertically-stacked active layers over a plurality of word lines, at least one bit line connection unit vertically formed over one end of the word lines and having a stairway shape, and a plurality of bit lines each coupled to each of a plurality of active regions of the bit line connection unit. | 11-03-2011 |
20110266605 | Memristive Transistor Memory - A memory device ( | 11-03-2011 |
20110266606 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE MANUFACTURED BY THE METHOD - A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions. | 11-03-2011 |
20110266607 | Integrated Circuit Memory Devices Having Vertically Arranged Strings of Memory Cells Therein and Methods of Operating Same - Nonvolatile memory devices include a first NAND-type string of EEPROM cells having a first plurality of string selection transistors therein electrically connected in series within the string. This first plurality of string selection transistors includes a first plurality of depletion-mode transistors and a first enhancement-mode transistor. A second NAND-type string of EEPROM cells is also provided with a second plurality of string selection transistors therein that are electrically connected in series. The second plurality of string selection transistors includes a second plurality of depletion-mode transistors and a second enhancement-mode transistor. According to these embodiments of the invention, the first enhancement-mode transistor is stacked vertically relative to one of the second plurality of depletion-mode transistors and the second enhancement-mode transistor is stacked vertically relative to one of the first plurality of depletion-mode transistors. A first string selection plug is configured to electrically connect a gate electrode of the first enhancement-mode transistor to a gate electrode of one of the second plurality of depletion-mode transistors. Similarly, a second string selection plug is configured to electrically connect a gate electrode of the second enhancement-mode transistor to a gate electrode of one of the first plurality of depletion-mode transistors. | 11-03-2011 |
20110272754 | MEMORIES AND THEIR FORMATION - Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array. | 11-10-2011 |
20110284942 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction. | 11-24-2011 |
20110284943 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: a plurality of conductive patterns stacked on a substrate and spaced apart from each other and a pad pattern including a flat portion extending in a first direction parallel to the substrate from one end of any one of the plurality of conductive patterns, and a landing sidewall portion extending upward from a top surface of the flat portion, wherein a width of a portion of the landing sidewall portion in a second direction parallel to the substrate and perpendicular to the first direction is less than a width of the flat portion. | 11-24-2011 |
20110291172 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant. | 12-01-2011 |
20110298031 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 12-08-2011 |
20110303958 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction. | 12-15-2011 |
20110309421 | ONE-TIME PROGRAMMABLE MEMORY AND METHOD FOR MAKING THE SAME - A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate. | 12-22-2011 |
20110309422 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first resistance element including a first conductive material, an inter-gate insulation film formed on both ends of the first conductive material in a first direction, and a second conductive material formed above the first conductive material and configured to connect with the first conductive material via a first connection region from which the inter-gate insulation film is removed, and a second resistance element including a third conductive material, the inter-gate insulation film formed on both ends of the third conductive material in the first direction, and a fourth conductive material formed above the third conductive material and configured to connect with the third conductive material via a second connection region from which the inter-gate insulation film is removed, wherein a length of the second connection region is greater than a length of the first connection region in the first direction. | 12-22-2011 |
20110316063 | THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME - Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. | 12-29-2011 |
20110316064 | Semiconductor Memory Devices And Methods Of Forming The Same - Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region. | 12-29-2011 |
20110316065 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor. | 12-29-2011 |
20120001246 | MEMORY DEVICE AND METHOD OF FABRICATING THEREOF - Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device. | 01-05-2012 |
20120007161 | Semiconductor Non-volatile Memory - A method of forming a charge-storing layer in a non-volatile memory cell in a logic process includes forming a select gate over an active region of a substrate, forming long polysilicon gates partially overlapping the active region of the substrate, and filling the charge-storing layer between the long polysilicon gates. | 01-12-2012 |
20120032245 | Vertical Structure Non-Volatile Memory Device - A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings. | 02-09-2012 |
20120043599 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion. | 02-23-2012 |
20120061741 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 03-15-2012 |
20120061742 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory includes a memory cell array area provided with first and second memory cells and having a first active area and a first element isolation area constituting a line & space structure, and having a floating gate electrode and a control gate electrode in the first active area, a word line contact area adjacent to the memory cell array area and having a second active area, first and second word lines with a metal silicide structure, functioning respectively as the control gate electrodes of the first and second memory cells and arranged to straddle the memory cell array area and the word line contact area. A dummy gate electrode is arranged just below the first and second word lines in the second active area. | 03-15-2012 |
20120068240 | Semiconductor Device and Method using a Sacrificial Layer - A method of manufacturing a semiconductor device is disclosed. The method includes forming a first conductive layer over a substrate. The first conductive layer has a top surface and sidewalls, wherein the first conductive layer comprises an overhang of a non-conductive material along the sidewalls. The method further includes forming an insulating layer on the first conductive layer, and forming a sacrificial layer over the insulating layer and the overhang of the first conductive layer. The sacrificial layer is partially removed wherein a residue of the sacrificial layer remains beneath the overhang, and a second conductive layer is formed on the insulating layer. | 03-22-2012 |
20120068241 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a memory device includes first and second fin type stacked structures each includes first to i-th memory strings (i is a natural number except 1) that are stacked in a first direction, the first and second fin type stacked structures which extend in a second direction and which are adjacent in a third direction, a first portion connected to one end in the second direction of the first fin type stacked structure, a width in the third direction of the first portion being greater than a width in the third direction of the first fin type stacked structure, and a second portion connected to one end in the second direction of the second fin type stacked structure, a width in the third direction of the second portion being greater than a width in the third direction of the second fin type stacked structure. | 03-22-2012 |
20120074480 | METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES - Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control. | 03-29-2012 |
20120074481 | SECURITIES, CHIP MOUNTING PRODUCT, AND MANUFACTURING METHOD THEREOF - The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design. | 03-29-2012 |
20120080736 | SEMICONDUCTOR DEVICE - An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact. | 04-05-2012 |
20120132975 | DATA RETENTION IN A SINGLE POLY EPROM CELL - An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region. | 05-31-2012 |
20120139023 | METHOD AND APPARATUS FOR NAND MEMORY WITH RECESSED SOURCE/DRAIN REGION - A method and apparatus for a flash memory is provided. A NAND flash memory array includes a cell body, a first selective gate, and a first edge line. The cell body includes recessed doped source/drain region between the first selective gate and the first edge word line. | 06-07-2012 |
20120146120 | Non-Volatile Memory Device - A non-volatile memory device includes memory cell active regions and common source active regions extending in parallel on a semiconductor substrate, a self aligned source active region disposed on the semiconductor substrate that intersects the memory cell active regions and the common source active regions and connects the memory cell active regions to the common source active regions, word lines disposed on the memory cell active regions and the common source active regions that intersect the memory cell active regions and the common source active regions, and memory cell transistors formed by the intersection of the word lines and the memory cell active regions, and common source line transistors formed by the intersection of the word lines and the common source active regions, wherein source and drain regions of each of the common source line transistors are separated from each other in the semiconductor substrate. | 06-14-2012 |
20120153372 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon. | 06-21-2012 |
20120168841 | Multiple Patterning Method - An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions. | 07-05-2012 |
20120175695 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to an embodiment includes a memory cell comprising a charge accumulate layer above a semiconductor substrate and a control gate above the charge accumulate layer. The charge accumulate layer is capable of accumulating charges therein. The control gate is configured to control an amount of the charges accumulated in the charge accumulate layer. The control gate comprises a lower-layer control gate part of metal or metallic silicide which is processable by etching, and an upper-layer control gate part of a material different from that of the lower-layer control gate part. | 07-12-2012 |
20120181591 | NON-VOLATILE FINFET MEMORY ARRAY AND MANUFACTURING METHOD THEREOF - An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction. | 07-19-2012 |
20120181592 | METHODS AND STRUCTURES FOR CUSTOMIZED STI STRUCTURES IN SEMICONDUCTOR DEVICES - A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed. | 07-19-2012 |
20120181593 | Semiconductor Device - Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections. | 07-19-2012 |
20120187466 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conductive layers as the first memory string. At least one of either the memory transistors or the back-gate transistor in the first memory string and at least one of either the memory transistors or the back-gate transistor in the second memory string are connected to the independent first or fifth conductive layers, respectively. | 07-26-2012 |
20120199897 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICES - Three-dimensional semiconductor devices are provided. The three-dimensional semiconductor device includes a substrate, a buffer layer on the substrate. The buffer layer includes a material having an etching selectivity relative to that of the substrate. A multi-layer stack including alternating insulation patterns and conductive patterns is provided on the buffer layer opposite the substrate. One or more active patterns respectively extend through the alternating insulation patterns and conductive patterns of the multi-layer stack and into the buffer layer. Related fabrication methods are also discussed. | 08-09-2012 |
20120211816 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a stacked body including insulating films stacked alternately with electrode films, a memory hole is made in one portion of the stacked body to extend in a stacking direction, a charge storage layer is provided on an inner surface of the memory hole, a semiconductor member is provided in the memory hole; forming a hard mask on the stacked body, the hard mask has a plurality of holes of mutually different sizes; | 08-23-2012 |
20120211817 | Flash Memory Device - A flash memory device including a semiconductor substrate that includes selection transistor regions and a memory cell region defined between the selection transistor region, first isolation layers formed in the selection transistor regions, and second isolation layers formed in the memory cell region. The second isolation layers have a lower height than the first isolation layers. | 08-23-2012 |
20120217561 | Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors - A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate. | 08-30-2012 |
20120217562 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of maximizing a channel area in a pillar and a method of manufacturing the same are provided. The semiconductor device includes a pillar disposed on a semiconductor substrate and having first to fourth side surfaces, a first bit line disposed in the first side surface, a storage node junction region disposed in the third side surface facing the first side surface, and a gate disposed in the second side surface or a fourth side surface facing the second surface. | 08-30-2012 |
20120217563 | METHOD AND SYSTEM FOR PROVIDING CONTACT TO A FIRST POLYSILICON LAYER IN A FLASH MEMORY DEVICE - A method and system for providing at least one contact in a flash memory device is disclosed. The flash memory device includes a plurality of gate stacks and at lease one component including a polysilicon layer as a top surface. The method and system further include forming a silicide on the top surface of the polysilicon layer and providing an insulating layer covering the plurality of gate stacks, the at least one component and the silicide. The method and system also include etching the insulating layer to provide at least one contact hole. The insulating layer etching step uses the silicide as an etch stop layer to ensure that the insulating etching step does not etch through the polysilicon layer. The method and system also include filling the at least one contact hole with a conductor. | 08-30-2012 |
20120223377 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 09-06-2012 |
20120235218 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well. | 09-20-2012 |
20120235219 | SEMICONDUCTOR MEMORY - In one embodiment, there is provided a semiconductor memory that includes: a semiconductor substrate having a channel region; a first tunnel insulating film on the channel region; a first fine particle layer on the first tunnel insulating film, the first fine particle layer including first conductive fine particles; a second tunnel insulating film on the first fine particle layer; a second fine particle layer on the second tunnel insulating film, the second fine particle layer including second conductive fine particles; a third tunnel insulating film on the second fine particle layer; a third fine particle layer on the third tunnel insulating film, the third fine particle layer including third conductive fine particles. A mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles and that of the third conductive fine particles. | 09-20-2012 |
20120273862 | SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS - Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments. | 11-01-2012 |
20120273863 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode. | 11-01-2012 |
20120280298 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively. | 11-08-2012 |
20120280299 | Three-Dimensional Semiconductor Memory Devices and Method of Fabricating the Same - Provided are three-dimensional semiconductor memory devices and methods of fabricating the same. The device may include an electrode structure extending in a first direction and including electrodes and insulating patterns which are alternately and repeatedly stacked on a substrate, and vertical active patterns penetrating the electrode structure. At least an uppermost electrode of the electrodes is divided into a plurality of physically isolated segments arranged in the first direction. The segments of the uppermost electrode are electrically connected to each other. | 11-08-2012 |
20120286344 | NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - A non-volatile may include a plurality of device isolation patterns disposed in a substrate to define an active region extending in a first direction, a gate pattern disposed on the substrate to extend in a second direction crossing the first direction, a charge storing pattern disposed between the active region and the gate pattern, a blocking dielectric layer disposed between the charge storing pattern and the gate pattern, and a tunnel dielectric layer disposed between the active region and the charge storing pattern. A center area of a top surface of the active region includes one of a rounded surface or a tip, and the center area of the top surface of the active region corresponds to an uppermost portion of the active region and the uppermost portion of the active region is disposed at a level lower than a lowermost portion of the gate pattern. | 11-15-2012 |
20120299076 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region. | 11-29-2012 |
20120299077 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate including a first region and a second region, a gate group disposed in the first region of the substrate, the gate group including a plurality of cell gate patterns and at least one selection gate pattern, a first gate pattern disposed in the second region of the substrate, a group spacer covering a top surface and a side surface of the gate group, the group spacer having a first inflection point, and a first pattern spacer covering a top surface and a side surface of the first gate pattern, the first pattern spacer having a second inflection point. | 11-29-2012 |
20120299078 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, there is disclosed a semiconductor storage device comprising a semiconductor substrate and a plurality of electrical rewritable nonvolatile memory cells. Each of the memory cells includes a floating gate and a control gate on the semiconductor substrate. Each of the memory cells shares a source/drain region with an adjacent memory cell. The memory cells are connected serially and configure a NAND cell unit. The source/drain region includes silicide layer. | 11-29-2012 |
20120319185 | NAND STRUCTURE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a NAND gate structure, comprising: a substrate; a gate insulation layer formed on the substrate; a source/drain region formed in the substrate; a middle gate formed on the gate insulator layer, a first gate and a second gate on each side of the middle gate, first sidewall spacers between the first gate and the middle gate and between the second gate and the middle gate, and second sidewall spacers outside the first gate and the second gate, wherein, a first contact hole region is provided on the middle gate, second contact hole regions are provided respectively on the first gate and the second gate, and the first contact hole region and the second contact hole regions are in staggered arrangement. The present invention proposes a new NAND structure and a method of manufacturing the same. With the NAND structure, about 30-50% area of the chip may be effectively reduced. | 12-20-2012 |
20120326220 | Integrated Circuits With Sidewall Nitridation - Semiconductor devices are provided with encapsulating films for protection of sidewall features during fabrication processes, such as etching to form isolation regions. In a non-volatile flash memory, for example, a trench isolation process is divided into segments to incorporate an encapsulating film along the sidewalls of charge storage material. A pattern is formed over the layer stack followed by etching the charge storage material to form strips elongated in the column direction across the substrate, with a layer of tunnel dielectric material therebetween. Before etching the substrate, an encapsulating film is formed along the sidewalls of the strips of charge storage material. The encapsulating film can protect the sidewalls of the charge storage material during subsequent cleaning, oxidation and etch processes. In another example, the encapsulating film is simultaneously formed while etching to form strips of charge storage material and the isolation trenches. | 12-27-2012 |
20130001665 | MOSFET AND METHOD FOR MANUFACTURING THE SAME - The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate. | 01-03-2013 |
20130001666 | Memory Cells, Arrays Of Memory Cells, And Methods Of Forming Memory Cells - A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a channel region elevationally between the inner and outer source/drain regions. The inner source/drain region has opposing laterally outer sides. One of a pair of data/sense lines is electrically coupled to and against one of the outer sides of the inner source/drain region. The other of the pair of data/sense lines is electrically coupled to and against the other of the outer sides of the inner source/drain region. An access gate line is elevationally outward of the pair of electrically coupled data/sense lines and is operatively adjacent the channel region. A charge storage device is electrically coupled to the outer source/drain region. Other embodiments and additional aspects, including methods, are disclosed. | 01-03-2013 |
20130009229 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels. | 01-10-2013 |
20130009230 | OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE - A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region. | 01-10-2013 |
20130020624 | MEMORY STRUCTURE - A memory structure having a memory cell region and a non-memory cell region is provided. The memory structure includes a plurality of memory cells and a conductive material. The plurality of memory cells are disposed in the memory cell region, wherein a plurality of first concave portions are present in the plurality of memory cells. The conductive material extends across the memory cell region and the non-memory cell region, covers the plurality of memory cells, and extends into the plurality of first concave portions. | 01-24-2013 |
20130032869 | SPLIT-GATE FLASH MEMORY WITH IMPROVED PROGRAM EFFICIENCY - A split gate memory cell is fabricated with a word gate extending below an upper surface of a substrate having the channel region. An embodiment includes providing a band engineered channel with the word gate extending there through. Another embodiment includes forming a buried channel with the word gate extending below the buried channel. | 02-07-2013 |
20130037874 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 02-14-2013 |
20130037875 | SEMICONDUCTOR MEMORY DEVICE INCLUDING MULTI-LAYER GATE STRUCTURE - A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion. | 02-14-2013 |
20130056814 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a substrate, a first stacked body, a second stacked body, a memory film, a gate insulating film, and a channel body. The first stacked body has a plurality of electrode layers and a plurality of first insulating layers. The second stacked body has a selector gate and a second insulating layer. The memory film is provided on a sidewall of a first hole. The gate insulating film is provided on a sidewall of a second hole. The channel body is provided on an inner side of the memory film and on an inner side of the gate insulating film. A step part is provided between a side face of the selector gate and the second insulating layer. A region positioned near a top end of the selector gate of the channel body is silicided. | 03-07-2013 |
20130056815 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body; a memory film; a first channel body layer provided inside the memory film; an interlayer insulating flm provided on the first stacked body; a second stacked body having a select gate electrode layer, and a second insulating layer; a gate insulating film provided on a side wall of a second hole communicating with the first hole and penetrating the second stacked body and the interlayer insulating flm in a stacking direction of the second stacked body; and a second channel body layer provided inside the gate insulating film in the second hole. A first pore diameter of the second hole at an upper end of the select gate electrode layer is smaller than a second pore diameter of the second hole at an lower end of the select gate electrode layer. | 03-07-2013 |
20130069133 | SEMICONDUCTOR DEVICE - A semiconductor device, includes: a semiconductor substrate; a first conductivity type well and a second conductivity type well; a first active area; a second active area; a first well contact layer; a plurality of first source/drain layers; a first gate insulating film; a first gate electrode; a second well contact layer; a plurality of second source/drain layers; a second gate insulating film; and a second gate electrode. The first well contact layer is formed in the first active area at one end part in the one direction. The one end parts in each of the first active areas and in each of the second active areas are mutually on the same side. | 03-21-2013 |
20130075802 | CONTACT ARCHITECTURE FOR 3D MEMORY ARRAY - A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines. | 03-28-2013 |
20130092994 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region. | 04-18-2013 |
20130105876 | Memory Devices With Three-Dimensional Selection Structures for Memory Cell Arrays | 05-02-2013 |
20130105877 | NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME | 05-02-2013 |
20130119450 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Provided is a non-volatile semiconductor storage device including a memory cell which is disposed on a semiconductor substrate and where a control gate electrode is disposed on a charge storage layer, a select gate transistor where a select gate electrode is disposed between a source region and a drain region and which shares the source region with the memory cell, a first air gap which is disposed between the charge storage layers and between the source regions adjacent to each other in a word line direction and which is formed continuously over the memory cell and the select gate transistor adjacent to each other in a bit line direction so as to be concealed under the word line and under the select gate electrode, and a back-filling insulating film which back-fills an air gap between the drain electrodes adjacent to each other in the word line direction. | 05-16-2013 |
20130126957 | 3D Non-Volatile Memory With Metal Silicide Interconnect - A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays. | 05-23-2013 |
20130134492 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Example embodiments of inventive concepts relate to semiconductor memory devices and/or methods for fabricating the same. The semiconductor memory device may include a plurality of gates vertically stacked on a substrate, a vertical channel penetrating the plurality of gates and a data storage layer between the vertical channel and the plurality of gates. The vertical channel may include a lower channel connected to the substrate and an upper channel on the lower channel. The upper channel may include a vertical pattern penetrating some of the plurality of gates and defining an inner space filled with an insulating layer, and a horizontal pattern horizontally extending along a top surface of the lower channel. The horizontal pattern may be in contact with the top surface of the lower channel. | 05-30-2013 |
20130134493 | VERTICAL CHANNEL MEMORY DEVICES WITH NONUNIFORM GATE ELECTRODES - A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers. | 05-30-2013 |
20130140620 | Flash Memory and Manufacturing Method Thereof - The present invention discloses a flash memory. The flash memory includes a substrate and a memory string, a plurality of landing pads, a plurality of common source lines, a plurality of bit line contacts and at least a bit line, which are disposed on the substrate in sequence. The memory string includes a plurality of storage transistors. The landing pads are disposed between each of the storage transistors. The common source lines and the bit line contact are electrically connected to the landing pads alternatively. The common line is disposed on the common line contacts and is electrically connected thereto. The present invention further provides a manufacturing method of making the same. | 06-06-2013 |
20130146960 | MEMORY CELLS HAVING A PLURALITY OF CONTROL GATES AND MEMORY CELLS HAVING A CONTROL GATE AND A SHIELD - Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described. | 06-13-2013 |
20130146961 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern. | 06-13-2013 |
20130153978 | 3D NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer. | 06-20-2013 |
20130153979 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF MANUFACTURING THE SAME - A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures. | 06-20-2013 |
20130161716 | SEMICONDUCTOR DEVICE WITH SELECTIVELY LOCATED AIR GAPS AND METHOD OF FABRICATION - A non-volatile semiconductor memory device comprises a semiconductor substrate and a plurality of gate structures formed on a cell region of the semiconductor substrate. The plurality of gate structures include a first select-gate and a second select-gate disposed on the cell region, the first select-gate and the second select-gate spaced apart from each other. A plurality of cell gate structures are disposed between the first select-gate and the second select-gate. The first select-gate and an adjacent cell gate structure have no air gap defined therebetween. At least a pair of adjacent cell gate structures have an air gap defined therebetween. | 06-27-2013 |
20130161717 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate contact sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate. | 06-27-2013 |
20130168752 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers. | 07-04-2013 |
20130168753 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - The technology of the present invention relates to a non-volatile memory device and a fabrication method thereof. The non-volatile memory device includes channel layers protruding vertically from a substrate, a plurality of hole-supply layers and a plurality of gate electrodes, which are alternately stacked along the channel layers, and a memory film interposed between the channel layers and the gate electrodes and between the hole-supply layers and the gate electrodes. According to this technology, the hole-supply layers are formed between the memory cells such that sufficient holes are supplied to the memory cells during the erase operation of the memory cells, whereby the erase operation of the memory cells is smoothly performed without using the GIDL current, and the properties of the device are protected from being deteriorated due to program/erase cycling. | 07-04-2013 |
20130181273 | METHOD OF MAKING A NON-VOLATILE DOUBLE GATE MEMORY CELL - A method of making a non-volatile double-gate memory cell. A gate of the control transistor is formed with a relief on a substrate. A control gate of the memory transistor is formed with a layer of a semiconductor material covering relief. The method includes chemical mechanical polishing (CMP) so as to strip, above the relief another layer and part of the layer of a semiconductor material; stripping of the remaining other layer on both sides of the relief, etching of the layer of a semiconductor material so as to strip this material above the relief and to leave only a pattern on at least one sidewall of the relief. | 07-18-2013 |
20130181274 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers. | 07-18-2013 |
20130187213 | METHOD OF MAKING A NON-VOLATILE DOUBLE GATE MEMORY CELL - A method of making a non-volatile double-gate memory cell. The gate of the control transistor is formed with a relief of a semiconductor material on a substrate. The control gate of the memory transistor is formed with a sidewall of the relief of a semiconductor material configured to store electrical charge. A first layer is deposited so as to cover the stack of layers. The first layer is etched so as to form a first pattern juxtaposed on the relief. A second layer is formed on the first pattern. The second layer is etched so as to form on the first pattern a second pattern having a substantially plane upper face. | 07-25-2013 |
20130187214 | MULTI-SEMICONDUCTOR MATERIAL VERTICAL MEMORY STRINGS, STRINGS OF MEMORY CELLS HAVING INDIVIDUALLY BIASABLE CHANNEL REGIONS, MEORY ARRAYS INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSSING AND FORMING THE SAME - Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed that utilize NAND strings of serially-connected non-volatile memory cells. One such string can include two or more serially connected non-volatile memory cells each having a channel region. Each memory cell of the two or more serially connected non-volatile memory cells shares a common control gate and each memory cell of the two or more serially connected non-volatile memory cells is configured to receive an individual bias to its channel region. | 07-25-2013 |
20130193503 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity. | 08-01-2013 |
20130214340 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure. | 08-22-2013 |
20130228841 | METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing nonvolatile semiconductor memory device including forming a stacked body by alternately stacking an electrode layer and a layer-to-be-etched, and forming an oxidized layer between the layer-to-be-etched provided at least in any side of an upper side and a lower side of the electrode layer and the electrode layer. The method can include forming a groove which passes through the stacked body. The method can include embedding an insulating body within the groove. The method can include forming a hole which passes through the stacked body. The method can include selectively removing the layer-to-be-etched via the hole. The method can include forming a charge storage layer in an inner side of the hole. The method can include forming a channel body layer in an inner side of the charge storage layer. | 09-05-2013 |
20130234222 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a substrate, a structure body, a semiconductor layer, and a memory film. The memory film is provided between the semiconductor layer and the plurality of electrode films. The memory film includes a charge storage film, a block film, and a tunnel film. The block film is provided between the charge storage film and the plurality of electrode films. The tunnel film is provided between the charge storage film and the semiconductor layer. The tunnel film includes a first film containing silicon oxide, a second film containing silicon oxide, and a third film provided between the first film and the second film and containing silicon oxynitride. When a composition of the silicon oxynitride contained in the third film is expressed by a ratio x of silicon oxide and a ratio (1−x) of silicon nitride, 0.5≦x<1 holdes. | 09-12-2013 |
20130248959 | PROGRAMMABLE LOGIC SWITCH - According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line. | 09-26-2013 |
20130256774 | SEMICONDUCTOR MEMORY DEVICES - Semiconductor memory devices may include a write transistor including a first write gate controlling a first source/drain terminal and a second write gate controlling a channel region, and a read transistor including a memory node gate connected to the first source/drain terminal of the write transistor. The first write gate may have a first work function and the second write gate may have a second work function different from the first work function. The first source/drain terminal of the write transistor may not have a PN junction. | 10-03-2013 |
20130256775 | THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS - A vertical NAND flash memory device includes a substrate having a face and a string of serially connected flash memory cells on the substrate. A first flash memory cell is adjacent the face, and a last flash memory cell is remote from the face. The flash memory cells include repeating layer patterns that are stacked on the face, and a pillar that extends through the series of repeating layer patterns. The pillar includes at least one oblique wall. At least two of the series of repeating layer patterns in the string are of different thicknesses. Other vertical microelectronic devices and related fabrication methods are also described. | 10-03-2013 |
20130264622 | SEMICONDUCTOR CIRCUIT STRUCTURE AND PROCESS OF MAKING THE SAME - A semiconductor circuit structure and process of making the same is provided in the present invention, comprising the steps of providing a substrate having a target layer and a hard mask layer, forming a patterned small core body group and a large core body group on the hard mask layer, forming a spacer material layer conformally on the substrate and the core body groups, forming filling bodies in each recess of the spacer material layer, performing a first etching process to remove exposed spacer material layer, using the filling bodies as a mask to perform a second etching process for patterning the hard mask layer, and using the patterned hard mask layer as a mask to perform a third etching process for patterning the conductive layer. | 10-10-2013 |
20130264623 | SEMICONDUCTOR DEVICE WITH BURIED BIT LINES - A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction. | 10-10-2013 |
20130270621 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND FABRICATION METHOD THEREOF - A nonvolatile semiconductor storage device has a plurality of memory strings in which electrically rewritable memory cells are connected in series. The memory strings have word-line electroconductive layers laminated at a prescribed interval to sandwich an interlayer insulating film onto a semiconductor substrate and through holes that penetrate through the word-line electroconductive layers and the interlayer insulating films. The gate insulating film is formed along an inner wall of the through holes and includes a charge-accumulating film. The columnar semiconductor layer is formed inside the through holes to sandwich the gate insulating film along with the word-line electroconductive layer. The columnar semiconductor layer contains carbon, oxygen, or nitrogen. | 10-17-2013 |
20130307044 | Selective Air Gap Isolation In Non-Volatile Memory - Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. A blocking layer can be introduced to inhibit the formation of materials in the air gaps during subsequent process steps. The blocking layer may result in selective air gap formation or varying dimension of air gaps at cell areas relative to select gate areas in the memory. The blocking layer may result in a smaller vertical dimension for air gaps formed in the isolation regions at select gate areas relative to cell areas. The blocking layer may inhibit formation of air gaps at the select gate areas in other examples. Selective etching, implanting and different isolation materials may be used to selectively define air gaps. | 11-21-2013 |
20130313624 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A first connection portion and a second connection portion connect a first control gate to a second control gate, and are separated from each other. The first control gate includes a first disconnection portion between the first connection portion and a source diffusion layer closest to the first connection portion. The second control gate includes a second disconnection portion between the second connection portion and the source diffusion layer closest to the second connection portion. A first word gate and a second word gate are not disconnected in portions overlapping the first disconnection portion and the second disconnection portion. | 11-28-2013 |
20130320424 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer. | 12-05-2013 |
20130341696 | METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF - The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor faults a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 12-26-2013 |
20130341697 | TUNNEL TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND A MANUFACTURING METHOD THEREOF - The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 12-26-2013 |
20140001529 | Silicide Process Using OD Spacers | 01-02-2014 |
20140001530 | NONVOLATILE MEMORY DEVICE, FABRICATION METHOD THEREOF AND MEMORY SYSTEM COMPRISING THE SAME | 01-02-2014 |
20140021524 | NON-VOLATILE MEMORY DEVICES HAVING AIR GAPS AND METHODS OF MANUFACTURING THE SAME - Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction. | 01-23-2014 |
20140027832 | FORMING AIR GAPS IN MEMORY ARRAYS AND MEMORY ARRAYS WITH AIR GAPS THUS FORMED - A memory array has first and second memory cells over a semiconductor and an isolation region extending into the semiconductor. The isolation region includes an air gap between charge-storage structures of the first and second memory cells and a thickness of dielectric over the air gap and contained between the first and second memory cells. | 01-30-2014 |
20140042512 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes word lines stacked in a cell region of a substrate and each of the word lines includes a first conductive layer. At least one selection line is stacked on top of the word lines and includes a second conductive layer. At least one gate line is formed in a peripheral region of the substrate and includes the second conductive layer. | 02-13-2014 |
20140042513 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - Provided is a non-volatile semiconductor storage device including a memory cell which is disposed on a semiconductor substrate and where a control gate electrode is disposed on a charge storage layer, a select gate transistor where a select gate electrode is disposed between a source region and a drain region and which shares the source region with the memory cell, a first air gap which is disposed between the charge storage layers and between the source regions adjacent to each other in a word line direction and which is formed continuously over the memory cell and the select gate transistor adjacent to each other in a bit line direction so as to be concealed under the word line and under the select gate electrode, and a back-filling insulating film which back-fills an air gap between the drain electrodes adjacent to each other in the word line direction. | 02-13-2014 |
20140042514 | CONTACTS FOR SEMICONDUCTOR DEVICES - A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts. | 02-13-2014 |
20140048862 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device according to an embodiment, includes a first dielectric film, a floating gate, a second dielectric film, and a third dielectric film. The first dielectric film is formed above a semiconductor substrate. The floating gate is formed above the first dielectric film by using a silicon film. The third dielectric film is formed to cover an upper surface of the floating gate and a side face portion of the floating gate. The floating gate includes an impurity layer formed on an upper surface of the floating gate and a side face of the floating gate along an interface between the floating gate and the third dielectric film formed to cover the upper surface of the floating gate and a side face portion of the floating gate and containing at least one of carbon (C), nitrogen (N), and fluorine (F) as an impurity. | 02-20-2014 |
20140054665 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device includes a tunnel insulating layer formed on an active region defined by an isolation layer, a polysilicon pattern including a first portion formed on the tunnel insulating layer on the active region and a second portion protruding from the first portion beyond the isolation layer, wherein the second portion has a narrower width than the first portion, and a doped region formed near a surface of the polysilicon pattern and including p-type dopants. | 02-27-2014 |
20140061747 | MEMORY ARRAY HAVING CONNECTIONS GOING THROUGH CONTROL GATES - Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates. | 03-06-2014 |
20140061748 | NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device and a method of manufacturing the same are provided. The device includes a substrate including a cell region and a peripheral region, a gate pattern formed over the substrate in the peripheral region, a multilayered structure formed over the gate pattern in the peripheral region, the multilayered structure including interlayer insulating layers and material layers for sacrificial layers, and a capping layer formed between the gate pattern and the multilayered structure in the peripheral region to cover the substrate, the capping layer configured to prevent diffusion of impurities from the material layers for the sacrificial layers into the substrate in the peripheral region. | 03-06-2014 |
20140061749 | TRANSPARENT NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - Disclosed are transparent non-volatile memory devices and methods of manufacturing the same. The method may include forming an active layer on a substrate, forming a source and a drain spaced apart from each other on the active layer, forming a gate insulating layer having quantum dots on the source, the drain, and the active layer, and forming a gate on the gate insulating layer between the source and the drain. The quantum dots and the gate insulating layer may be formed simultaneously. | 03-06-2014 |
20140061750 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a first substrate on which a cell region is defined. In the cell region, memory cells are stacked. A second substrate is located above the first substrate, and a peripheral region is defined on the second substrate. One or more conductive lines are located in the peripheral region. The one or more lines extend through the second substrate and couple to the cell region. | 03-06-2014 |
20140061751 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region provided with a plurality of memory cells, and a peripheral region provided around the memory cell region. The device includes: a foundation layer provided in the memory cell region and in the peripheral region, the foundation layer including a plurality of wiring layers and a plurality of device elements; and a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers and a plurality of intermediate layers alternately stacked. The peripheral region includes an interlayer insulating film provided on the stacked body; and an electrode pad provided on the interlayer insulating film and electrically connected to one of the plurality of wiring layers. | 03-06-2014 |
20140061752 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole. | 03-06-2014 |
20140070296 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor storage device according to the present embodiment includes a semiconductor substrate. A memory cell array includes a plurality of memory cells provided on the semiconductor substrate in an array direction. A selection gate transistor is provided on an end of the memory cell array, and is used to select the memory cells from the memory cell arrays. A dummy cell is provided between a gate electrode of one of the memory cells on the end of the memory cell array and a gate electrode of the selection gate transistor. The width of a gate electrode of the dummy cell in the array direction of the memory cells and the dummy cell is twice or more as large as the width of the gate electrode of one of the memory cells. | 03-13-2014 |
20140084353 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device with a first region including a memory cell array of a plurality of memory cells arrayed in three dimensions and a second region with a peripheral circuit for controlling the memory cell array is described. The peripheral circuit includes an insulating film and a template region. The template region has a length and a width and the insulating film is spaced from (does not overlap) the edges of the template region and is arranged in the template region so that a coverage ratio of the template region is at least above a minimum coverage ratio of 30-50%. Satisfying the minimum coverage ratio allows the device layers above the second region to be formed with sufficient flatness to allow the memory device to be functional. | 03-27-2014 |
20140091380 | Split Gate Flash Cell - In one aspect, a disclosed method of fabricating a split gate memory device includes forming a gate dielectric layer overlying an channel region of a semiconductor substrate and forming an electrically conductive select gate overlying the gate dielectric layer. The method further includes forming a counter doping region in an upper region of the substrate. A proximal boundary of the counter doping region is laterally displaced from a proximal sidewall of the select gate. The method further includes forming a charge storage layer comprising a vertical portion adjacent to the proximal sidewall of the select gate and a lateral portion overlying the counter doping region and forming an electrically conductive control gate adjacent to the vertical portion of the charge storage layer and overlying the horizontal portion of the charge storage layer. | 04-03-2014 |
20140091381 | SUPPORT LINES TO PREVENT LINE COLLAPSE IN ARRAYS - Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings. | 04-03-2014 |
20140097480 | METHOD FOR MANUFACTURING A MEMORY CELL, A METHOD FOR MANUFACTURING A MEMORY CELL ARRANGEMENT, AND A MEMORY CELL - A method for manufacturing a memory cell in accordance with various embodiments may include: forming at least one charge storing memory cell structure over a substrate, the charge storing memory cell structure having a first sidewall and a second sidewall opposite the first sidewall; forming an electrically conductive layer over the substrate and the charge storing memory cell structure; patterning the electrically conductive layer to form a spacer at the first sidewall and a blocking structure at the second sidewall of the charge storing memory cell structure; implanting first dopant atoms to form a first doped region in the substrate proximate the spacer, wherein the first dopant atoms are blocked by the blocking structure; removing the blocking structure after implanting the first dopant atoms; implanting second dopant atoms to form a second doped region in the substrate proximate the second sidewall of the charge storing memory cell structure. | 04-10-2014 |
20140124846 | SEMICONDUCTOR MEMORY DEVICES HAVING SELECTION TRANSISTORS WITH NONUNIFORM THRESHOLD VOLTAGE CHARACTERISTICS - Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region. | 05-08-2014 |
20140131783 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first conductive layer, at least one first slit through the first conductive layer, and configured to divide the first conductive layer in the unit of a memory block, second conductive layers stacked on the first conductive layer, and a second slit through the second conductive layers at a different location from the first slit and configured to divide the second conductive layers in the unit of the memory block. | 05-15-2014 |
20140138754 | MEMORY CELLS HAVING A PLURALITY OF CONTROL GATES AND MEMORY CELLS HAVING A CONTROL GATE AND A SHIELD - Various embodiments comprise apparatuses having a number of memory cells. In one such apparatus, each cell has a plurality of control gates. For example, each of two control gates is adjacent a respective side of a charge storage structure. In another apparatus, each cell has a control gate and a shield, such as where the control gate is adjacent one side of a charge storage structure and the shield is adjacent another side of the charge storage structure. Additional apparatuses and methods are described. | 05-22-2014 |
20140151774 | NAND FLASH MEMORY WITH VERTICAL CELL STACK STRUCTURE AND METHOD FOR MANUFACTURING SAME - Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars. | 06-05-2014 |
20140151775 | CONTROL GATE - A method for forming a semiconductor device is disclosed. The method includes providing a substrate prepared with a second gate structure. An inter-gate dielectric is formed on the substrate and over the second gate. A first gate is also formed. The first gate is adjacent to and separated from the second gate by the inter-gate dielectric. The substrate is patterned to form a split gate structure with the first and second adjacent gates. The split gate structure is provided with an e-field equalizer adjacent to the first gate. The e-field equalizer improves uniformity of e-field across the first gate during operation. | 06-05-2014 |
20140159132 | MEMORY ARRAYS WITH AIR GAPS BETWEEN CONDUCTORS AND THE FORMATION THEREOF - Memory arrays and their formation are disclosed. The formation of one such memory array includes forming first and second spacers respectively adjacent to sidewalls of first and second conductors so that the first and second spacers extend into an opening between the first and second conductors and terminate above bottoms of the first and second conductors, and closing the opening with a material that extends between the first and second spacers so that an air gap is formed in the closed opening. | 06-12-2014 |
20140167128 | Memory Gate Landing Pad Made From Dummy Features - Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact. | 06-19-2014 |
20140167129 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a bit line and a common source line formed on a cell array region of a substrate, a first channel layer coupled to the common source line and extending higher than the common source line, a second channel layer coupled to the bit line and extending higher than the bit line, and a coupling pattern coupling a top of the first channel layer opposite to the common source line and a top of the second channel layer opposite to the bit line. | 06-19-2014 |
20140197470 | METHODS FOR FORMING ETCH STOP LAYERS, SEMICONDUCTOR DEVICES HAVING THE SAME, AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A plurality of vertical channels of semiconductor material are formed to extend in a vertical direction through the plurality of insulation layers and the plurality of conductive patterns, a gate insulating layer between the conductive pattern and the vertical channels that insulates the conductive pattern from the vertical channels. Conductive contact regions of the at least two of the conductive patterns are in a stepped configuration. An etch stop layer is positioned on the conductive contact regions, wherein the etch stop layer has a first portion on a first one of the plurality of conductive patterns and has a second portion on a second one of the plurality of conductive patterns, wherein the first portion is of a thickness that is greater than a thickness of the second portion. | 07-17-2014 |
20140209989 | ANTI-FUSE MEMORY CELL - An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide is formed by depositing a first oxide over a channel region of the anti-fuse memory cell, removing the first oxide in a thin oxide area of the channel region, and then thermally growing a second oxide in the thin oxide area. The remaining first oxide defines a thick oxide area of the channel region. The second oxide growth occurs under the remaining first oxide, but at a rate less than thermal oxide growth in the thin oxide area. This results in a combined thickness of the first oxide and the second oxide in the thick oxide area being greater than second oxide in the thin oxide area. | 07-31-2014 |
20140217488 | 3-D Memory Arrays - A 3-D memory array comprises a plurality of elevationally extending strings of memory cells. An array of select devices is elevationally over and individually coupling with individual of the strings. The select devices individually comprise a channel, gate dielectric proximate the channel, and gate material proximate the gate dielectric. The individual channels are spaced from one another. The gate material comprises a plurality of gate lines running along columns of the spaced channels elevationally over the strings. Dielectric material is laterally between immediately adjacent of the gate lines. The dielectric material and the gate lines have longitudinally non-linear edges at an interface relative one another. Additional embodiments are disclosed. | 08-07-2014 |
20140252443 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer. | 09-11-2014 |
20140264524 | 3D SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a plurality of stacked strips on a substrate and a plurality of conductive lines on the stacked strips. The stacked strips and the conductive lines are arranged orthogonally to each other and a conductive liner is formed there between. A first air gap fills the space between the two adjacent stacked strips and under one of the conductive lines, which is positioned on top of said two adjacent stacked strips, whereas a second air gap is between the two adjacent conductive lines. The material of the conductive liner is different from that of the conductive lines. The distance between the two adjacent stacked strips is below 200 nm, and the aspect ratio of the stacked strip is at least 1. | 09-18-2014 |
20140264525 | VERTICAL NAND AND METHOD OF MAKING THEREOF USING SEQUENTIAL STACK ETCHING AND LANDING PAD - A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. | 09-18-2014 |
20140264526 | GETTERING AGENTS IN MEMORY CHARGE STORAGE STRUCTURES - Methods of forming memory cells including a charge storage structure having a gettering agent therein can be useful for non-volatile memory devices. Providing for gettering of oxygen from a charge-storage material of the charge storage structure can facilitate a mitigation of detrimental oxidation of the charge-storage material. | 09-18-2014 |
20140284675 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a foundation layer; and a stacked body provided on the foundation layer, each of a plurality of electrode layers and each of a plurality of insulating layers being stacked alternately in the stacked body; a select gate electrode provided on the stacked body; and a semiconductor layer extending from an upper end of the select gate electrode to a lower end of the stacked body. The stacked body includes a plurality of staircase regions. The each of the plurality of electrode layers includes an exposed portion. The exposed portion is not covered with the plurality of electrode layers other than the each of the plurality of electrode layers and the plurality of insulating layers. And the exposed portion of each of the plurality of electrode layers is disposed in one of the plurality of staircase regions. | 09-25-2014 |
20140284676 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - Plural first charge accumulation layers are arranged on a first gate-insulating film, and divided in the first direction and the second direction. Plural second charge accumulation layers are arranged on a second gate-insulating film and divided in the first direction and the second direction. An intermediate insulating film is arranged on the side surface of the first charge accumulation layers and on the side surface of the second charge accumulation layers. The control electrode includes a side-surface portion, which is arranged on the side surface of the intermediate insulating film, extends in the second direction, and faces via the intermediate insulating film to the side surface of the first charge accumulation layer and the side surface of the second charge accumulation layer, and a pad portion arranged monolithically on the lower portion of the side-surface portion and having a width larger than the film thickness of the side-surface portion. | 09-25-2014 |
20140284677 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In a non-volatile semiconductor memory device, it is only necessary that, at the time of data writing, a voltage drop is caused in a high resistance region. Therefore, the value of voltage applied to a gate electrode can be reduced as compared with a conventional device. In correspondence with the reduction in the value of applied voltage, it is possible to reduce the film thickness of a gate insulating film of memory transistors, and further the film thickness of the gate insulating film of a peripheral transistor for controlling the memory transistors. As a result, the circuit configuration of the non-volatile semiconductor memory device can be reduced in size as compared with the conventional device. | 09-25-2014 |
20140299930 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a gate structure including a select gate formed over a substrate and a memory gate formed on one sidewall of the select gate and having a P-type channel, a drain region formed in the substrate at one sidewall of the gate structure and overlapping a part of the memory gate, and a source region formed in the substrate at the other sidewall of the gate structure and overlapping a part of the select gate. The memory gates include a grid of rows and columns with bits of 1's and 0's selectively forming a memory in a nonvolatile memory device. | 10-09-2014 |
20140306279 | SEMICONDUCTOR DEVICES INCLUDING WORD LINE INTERCONNECTING STRUCTURES - A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads. | 10-16-2014 |
20140327065 | CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum. | 11-06-2014 |
20140332873 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least one channel layer, insulating layers stacked on top of one another while surrounding the at least one channel layer, first grooves and second grooves alternately interposed between the insulating layers, wherein the first groves have a greater width than the second grooves having a second width, and conductive layers formed in the first grooves. | 11-13-2014 |
20140339620 | Integrated Circuitry and Methods of Forming Transistors - Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped. | 11-20-2014 |
20140361357 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING PILLARS BURIED INSIDE THROUGH HOLES SAME - In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate. | 12-11-2014 |
20140367758 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating layers on the substrate, a channel body provided inside a hole piercing the stacked body, and a memory portion provided between the channel body and each of the plurality of electrode layers. The hole has a large diameter portion and a small diameter portion. The diameter of the hole is smaller at the small diameter portion than at the large diameter portion. A thickness of the electrode layer adjacent to the small diameter portion is thicker than a thickness of the electrode layer adjacent to the large diameter portion. | 12-18-2014 |
20140367759 | MULTI-LEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING - A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers. | 12-18-2014 |
20140374810 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a plurality of first channel columns including a plurality of first channel layers that are arranged in a direction and offset by their centers; a plurality of second channel columns alternately arranged with the plurality of first channel columns and having a plurality of second channel layers that are arranged in the direction and offset by their centers; first insulating layers and first conductive layers alternately stacked to surround the first channel layers; second insulating layers and second conductive layers stacked to surround the second channel layers; and spacers placed between the first channel columns and the second channel columns and interposed between the first conductive layers and the second conductive layers. | 12-25-2014 |
20150008499 | VERTICAL SEMICONDUCTOR DEVICE - A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction. | 01-08-2015 |
20150008500 | NON-VOLATILE SEMICONDUCTOR MEMORY AND METHOD FOR PRODUCING NON-VOLATILE SEMICONDUCTOR MEMORY - A non-volatile semiconductor memory free from adverse effects due to process charge is provided. The non-volatile semiconductor memory includes: a silicon substrate; a first silicon oxide film; a second silicon oxide film; a first silicon nitride film; and a second silicon nitride film, wherein the first silicon oxide film is layered on the silicon substrate, the first silicon nitride film is layered on the first silicon oxide film, the second silicon oxide film is layered on the first silicon nitride film, and the second silicon nitride film is layered to have a first part that is in contact with the first silicon nitride film and a second part that is in contact with the silicon substrate. | 01-08-2015 |
20150014760 | VERTICAL GATE NAND MEMORY DEVICES - In an example, a device comprises a vertical stack of memory cells. Each memory cell of the vertical stack may include more than one memory element. A first vertical gate line may be coupled to a first one of the memory elements in each memory cell, and a second vertical gate line may be coupled to a second one of the memory elements in each memory cell. The first vertical gate line may be electrically isolated from the second vertical gate line. | 01-15-2015 |
20150035034 | SPLIT GATE NON-VOLATILE MEMORY CELL - A method of making a semiconductor structure uses a substrate having a background doping of a first type. A gate structure has a gate dielectric on the substrate and a select gate layer on the gate dielectric. Implanting is performed into a first portion of the substrate adjacent to a first end with dopants of a second type. The implanting is prior to any dopants being implanted into the background doping of the first portion which becomes a first doped region of the second type. An NVM gate structure has a select gate, a storage layer having a first portion over the first doped region, and a control gate over the storage layer. Implanting at a non-vertical angle with dopants of the first type forms a deep doped region under the select gate. Implanting with dopants of the second type forms a source/drain extension. | 02-05-2015 |
20150035035 | NON-VOLATILE MEMORY DEVICE - According to one embodiment, a non-volatile memory device includes abase layer, a first stacked unit and a second stacked unit disposed above the base layer and arranged in parallel to each other and spaced apart from each other in a first direction, in a plane parallel to the base layer, a first semiconductor layer penetrating the first stacked unit, a second semiconductor layer penetrating in the second stacked unit, the first memory film disposed between the first semiconductor layer and the first stacked unit, and a connecting portion disposed between the base layer and the first stacked unit and between the base layer and the second stacked unit and electrically connecting the first semiconductor layer and the second semiconductor layer. An end portion of the first semiconductor layer is positioned between the connecting portion and the base layer. | 02-05-2015 |
20150035036 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to an aspect of the invention, a first insulating layer is buried in a first trench provided in at least one of an interstice between first and second semiconductor pillars, a side surface portion of the first semiconductor pillar opposed to the second semiconductor pillar, and a side surface portion of the second semiconductor pillar opposed to the first semiconductor pillar. A first trench penetrates each stack from an uppermost portion of the stack to a first conductive layer in a lowermost portion of the stack. The first trench is arranged away from a first connection portion. Each of the first conductive layers in contact with the first insulating layer includes a silicide layer. | 02-05-2015 |
20150035037 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, the select transistor is provided between a memory array region and the layer selection portion. The channel body and the charge storage film are provided in the memory array region. The select transistor includes a gate electrode provided on a side wall of one of the line portions between the memory array region and the layer selection portion; and a gate insulator film provided between the gate electrode and the line portions. The gate electrode extends in the stacking direction. | 02-05-2015 |
20150041875 | Nonvolatile Memory Bitcell With Inlaid High K Metal Select Gate - A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates ( | 02-12-2015 |
20150048433 | Contact Formation for Split Gate Flash Memory - An integrated circuit structure includes a plurality of flash memory cells forming a memory array, wherein each of the plurality of flash memory cells includes a select gate and a memory gate. A select gate electrode includes a first portion including polysilicon, wherein the first portion forms select gates of a column of the memory array, and a second portion electrically connected to the first portion, wherein the second portion includes a metal. A memory gate electrode has a portion forming memory gates of the column of the memory array. | 02-19-2015 |
20150048434 | Structure and Method of Manufacturing a Stacked Memory Array for Junction-Free Cell Transistors - A three-dimensional NAND memory device and an associated method for manufacturing this device are provided. The three-dimensional NAND memory device includes a source contact electrically isolated from a conductive gate material. The source contact also electrically connects a conductive source line to a first silicon strip and a second silicon strip through the conductive gate material. | 02-19-2015 |
20150048435 | SEMICONDUCTOR DEVICE - A semiconductor device comprising four semiconductor pillars extending in a direction perpendicular to a substrate, a connection channel formed on the substrate and connected to one ends of the four semiconductor pillars, a source line connected to the other ends of first and second semiconductor pillars adjacent to each other among the four semiconductor pillars, a bit line connected to the other ends of third and fourth semiconductor pillars among the four semiconductor pillars, first to fourth stack structures, which are formed along the first to fourth semiconductor pillars, respectively, between the source and bit lines and the substrate, and each includes a pass word line, at least one word line and a select line which are stacked over the substrate, and a memory layer interposed between the word line and each of the first to fourth semiconductor pillars. | 02-19-2015 |
20150054044 | Method to Form a Polysilicon Nanocrystal Thin Film Storage Bitcell within a High K Metal Gate Platform Technology Using a Gate Last Process to Form Transistor Gates - A process integration is disclosed for fabricating non-volatile memory (NVM) cells ( | 02-26-2015 |
20150054045 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Technique of improving a manufacturing yield of a semiconductor device including a non-volatile memory cell in a split-gate structure is provided. A select gate electrode of a CG shunt portion is formed so that a second height d2 from the main surface of the semiconductor substrate of the select gate electrode of the CG shunt portion positioned in the feeding region is lower than a first height d1 of the select gate electrode from the main surface of the semiconductor substrate in a memory cell forming region. | 02-26-2015 |
20150054046 | 3D Non-Volatile Memory With Metal Silicide Interconnect - A stacked non-volatile memory cell array include cell areas with rows of vertical columns of NAND cells, and an interconnect area, e.g., midway in the array and extending a length of the array. The interconnect area includes at least one metal silicide interconnect extending between insulation-filled slits, and does not include vertical columns of NAND cells. The metal silicide interconnect can route power and control signals from below the stack to above the stack. The metal silicide interconnect can also be formed in a peripheral region of the substrate. Contact structures can extend from a terraced portion of the interconnect to at least one upper metal layer, above the stack, to complete a conductive path from circuitry below the stack to the upper metal layer. Subarrays can be provided in a plane of the array without word line hook-up and transfer areas between the subarrays. | 02-26-2015 |
20150060974 | FLASH MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a word line cell disposed over the substrate. The semiconductor device further includes a memory gate disposed over the substrate and adjacent to the word line cell and a spacer on a sidewall of the memory gate. The spacer and the word line cell are at opposite sides of the memory gate. In addition, an angle between a top surface of the memory gate and a sidewall of the memory gate is in a range from about 75° to about 90°. | 03-05-2015 |
20150060975 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes first and second memory blocks which are disposed adjacent to each other in a first direction. The first and second memory blocks each include a plurality of bit lines, a plurality of word lines, which are disposed to extend in a second direction, and a memory cell, which is connected to any of the plurality of word lines. The first memory block includes a first selection gate line which is connected to one end of the memory cell, and the second memory block includes a second selection gate line in the same manner. An end portion of one end of the first selection gate line includes an L-shaped portion, and an end portion of one end of the second selection gate line includes a linear portion. A first contact is disposed on the L-shaped portion of the first selection gate. | 03-05-2015 |
20150060976 | NON-VOLATILE STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to an embodiment, a solid state storage device includes a first gate; a plurality of conductive layers having insulating layers therebetween, one of the insulating layers located on the first gate, an interconnection region extending inwardly of the first gate, a first semiconductor layer extending through the plurality of conductive layers and insulating layers, a second semiconductor layer extending through the plurality of conductive layers and insulating layers; a third semiconductor layer extending through the interconnection region and electrically connecting the first and second semiconductor layers, and an insulator extending through the plurality of conductive layers and insulating layers at a location intermediate of the first and second semiconductor layers, and also extending inwardly of the interconnection region. | 03-05-2015 |
20150060977 | SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL STRUCTURES - Semiconductor devices are provided. The semiconductor devices may include a substrate, a ground selection gate electrode, and a channel structure. The channel structure may extend the ground selection gate electrode in a first direction perpendicular to a top surface of the substrate, and include a channel layer, a channel contact layer, and a stepped portion. The channel contact layer may contact the substrate and include a first width in a second direction perpendicular to the first direction. The channel layer may contact the channel contact layer, include a bottom surface between a bottom surface of the ground selection gate electrode and the top surface of the substrate in the first direction, and include a second width in the second direction different from the first width. | 03-05-2015 |
20150060978 | SEMICONDUCTOR DEVICE - To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to each other in the bit line direction is connected to a bit line through a common contact hole. The pair of memory cells adjacent to each other in the bit line direction shares an electrode connected to the bit line. An oxide semiconductor layer included in the memory cell is provided to overlap with a word line and a capacitor line. A transistor and a capacitor included in the memory cell are each provided to overlap with the bit line connected to the memory cell. | 03-05-2015 |
20150060979 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel and gate electrodes. The channel extends in a vertical direction with respect to a top surface of a substrate. The gate electrodes are disposed on an outer sidewall of the channel. The gate electrodes includes a ground selection line (GSL), a word line, a string selection line (SSL) and a first dummy word line sequentially stacked from the top surface of the substrate in the vertical direction to be spaced apart from each other. The channel includes an impurity region at a portion adjacent to the SSL. | 03-05-2015 |
20150069484 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes stacked groups each including interlayer insulating patterns and conductive patterns and stacked in at least two tiers, wherein the insulating patterns and the conductive patterns are alternately stacked over a substrate and separated by slits, and a support body including holes and formed between the stacked groups. | 03-12-2015 |
20150069485 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes memory cell units, each including memory cell transistors, a first transistor at a first end of the memory cell transistors, and a second transistor at a second end of the memory cell transistors. The memory cell units are arranged so that adjacent memory cell units have first transistors thereof facing each other or second transistors thereof facing each other, and so that a distance between the first transistors of the adjacent memory cell units is larger than a distance between the second transistors of the adjacent memory cell units. The semiconductor device further includes a first silicon nitride layer covering a first diffusion layer of the first transistors, a second silicon nitride layer covering a second diffusion layer of the second transistors. A thickness of the second silicon nitride layer is smaller than a thickness of the first silicon nitride layer. | 03-12-2015 |
20150076579 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in a semiconductor memory device, a block selection transistor is provided between a stacked body and a word line in a hierarchy selection area. The block selection transistor includes a plurality of semiconductor bodies, a plurality of gate insulating films, and a gate electrode. The plurality of semiconductor bodies respectively extend from the end portions of the respective electrode layers to the respective word lines. The plurality of gate insulating films are provided on the side walls of the respective semiconductor bodies. The gate electrode faces the side wall of the semiconductor body through the gate insulating film. | 03-19-2015 |
20150076580 | METHOD OF INTEGRATING SELECT GATE SOURCE AND MEMORY HOLE FOR THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening. | 03-19-2015 |
20150076581 | MEMORY ARRAY AND NON-VOLATILE MEMORY DEVICE OF THE SAME - A non-volatile memory device is provided. The non-volatile memory device includes a substrate area, two storage units, a spacer structure and two control units. The storage units include two anti-fuse gates each having a gate dielectric layer between the anti-fuse gate and the substrate area and two diffusion areas. The spacer structure is formed on the substrate area and between the two anti-fuse gates and contacts thereto. Each of the diffusion areas is a first doping area doped with a first type dopant contacting one of the two anti-fuse gates. Each of the control units includes a select gate formed on the substrate area and a second doping area. A first side of the select gate contacts one of the diffusion areas of the storage unit. The second doping area is doped with the first type dopant and contacts a second side of the select gate. | 03-19-2015 |
20150084108 | TRANSISTOR STRUCTURE AND METHOD WITH AN EPITAXIAL LAYER OVER MULTIPLE HALO IMPLANTS - A transistor structure having an epitaxial layer deposited over an implanted substrate in order to reduce process variability. The epitaxial layer is able to be deposited doped, un-doped or lightly doped via up-diffusion from the implanted substrate, and used to form the channel for the transistor structure. As a result, this use of un-doped epitaxial layer provides the benefit of reducing process variability (e.g. random dopant fluctuation) and thus the transistor performance variability despite the small physical size of the transistors. | 03-26-2015 |
20150097222 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A channel layer is formed on a substrate. The channel layer is extended in a first direction substantially perpendicular to an upper surface of the substrate. A ground selection line is formed on a first region of the channel layer. A plurality of word lines is formed on a second region of the channel layer. A plurality of string selection lines is formed on a third region of the channel layer. The second region of the channel layer includes a first conductivity type dopant. The first, second and third regions of the channel layer are disposed along the first direction. | 04-09-2015 |
20150115344 | THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - A 3D stacked semiconductor structure is provided, comprising a plurality of stacks formed on a substrate; at least a contact hole formed vertically in one of the stacks; a conductor formed in the contact hole; and a charging trapping layer at least formed at sidewalls of the stacks. One of the stacks comprises a multi-layered pillar, including a plurality of insulating layers and a plurality of conductive layers arranged alternately, and a dielectric layer formed on the multi-layered pillar. The contact hole is formed vertically in one of the stacks, and the contact hole penetrates the dielectric layer, the insulating layers and the conductive layers of the corresponding stack. Also, a top surface of the conductor is higher than a top surface of the multi-layered pillar for the corresponding stack. | 04-30-2015 |
20150115345 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel, a conductive pattern, gate electrodes, a bit line and a conductive line. A plurality of the channels and the conductive patterns extend in a vertical direction from a top surface of a substrate. The gate electrodes surround outer sidewalls of the channels and the conductive patterns. The gate electrodes are stacked in the vertical direction to be spaced apart from each other. The bit line is electrically connected to the channels. The conductive line is electrically connected to the conductive patterns. | 04-30-2015 |
20150123182 | TRANSISTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Provided is a semiconductor device including a pillar, a gate electrode having a first conductive pattern surrounding the pillar and a plurality of second conductive patterns which protrude from the first conductive pattern and are arranged to be spaced apart from each other, and an insulating pattern interposed between the pillar and the first conductive pattern. | 05-07-2015 |
20150123183 | SEMICONDUCTOR DEVICE - A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved. | 05-07-2015 |
20150129947 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a NAND string including memory cells disposed in a first direction and a select gate disposed first-directionally adjacent to a first memory cell located at an end of the memory cells. A first gap is disposed between the memory cells and a second gap is disposed between the first memory cell and the select gate. Further, in a cross sectional shape, an upper end of the second gap is higher than an upper end of a first gap and an upper portion of the second gap is curved. | 05-14-2015 |
20150137203 | FORMING FINFET CELL WITH FIN TIP AND RESULTING DEVICE - Methods for forming a variable fin FinFET cell that can withstand a larger voltage without gate oxide breakdown at a fin tip and the resulting devices are disclosed. A plurality of fins is formed above a substrate, a portion of a fin is removed, forming a fin tip, a first area of a gate oxide layer is formed above the fin tip, and a second area of the gate oxide layer is formed above at least a remaining portion of the plurality of fins, wherein the first area is thicker than the second area. | 05-21-2015 |
20150137204 | MEMORY CIRCUIT STRUCTURE AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME - A semiconductor process for manufacturing particular patterns includes the steps of forming a target layer and evenly-spaced core bodies on a substrate, conformally forming a hard mask layer, forming a first photoresist covering a predetermined region on the hard mask layer wherein the predetermined region encompasses at least two core bodies, performing a first etch process to remove a portion of the hard mask layer outside the predetermined region and expose a number of core bodies, removing the exposed core bodies, forming a second photoresist at least encompassing all the recesses in the predetermined region, and performing a second etch process to pattern the target layer. | 05-21-2015 |
20150137205 | MEMORY DEVICE - According to example embodiments, a memory device includes a substrate, a channel region on the substrate, a plurality of gate electrode layers stacked on each other on the substrate, and a plurality of contact plugs. The gate electrode layers are adjacent to the channel region and extend in one direction to define a pad region. The gate electrode layers include first and second gate electrode layers. The contact plugs are connected to the gate electrode layers in the pad region. At least one of the contact plugs is electrically insulated from the from the first gate electrode layer and electrically connected to the second gate electrode layer by penetrating through the first gate electrode layer. | 05-21-2015 |
20150145012 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME - A semiconductor structure is provided. The semiconductor structure includes a first stacked structure. The first stacked structure includes a first stacked portion disposed along a first direction, at least one second stacked portion connected with the first stacked portion and disposed along a second direction perpendicular to the first direction, and at least one third stacked portion connected with the first direction and arranged alternately with the second stacked portion along the first direction. The width of the third stacked portion is smaller than the width of the second stacked portion along the second direction. | 05-28-2015 |
20150145013 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device includes an active region tilted at an angle with respect to a buried bit line. The buried bit line includes a metal silicide pattern and a metal pattern. The metal silicide pattern has a plurality of metal silicide films each disposed at a lower portion of the active region and corresponding to a bit line contact region. The metal pattern has a plurality of metal films. The metal silicide films and the metal films are alternately arranged and electrically coupled to each other. | 05-28-2015 |
20150145014 | VERTICAL MEMORY DEVICES - A vertical memory device includes a substrate, a first cell block and a second cell block. The substrate includes a central region and a peripheral region. At least one first cell block is on the central region. The first cell block includes a first channel and first gate lines. At least one second cell block is on the peripheral region. The second cell block includes a second channel and second gate lines. The second cell block has a width greater than a width of the first cell block. The first and second channel extend in a first direction vertical to a top surface of the substrate. The first gate lines surround the first channel and the first gate lines are spaced apart from each other in the first direction. The second gate lines surround the second channel and are spaced apart from each other in the first direction. | 05-28-2015 |
20150145015 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure. | 05-28-2015 |
20150294977 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a memory cell array including a plurality of cell strings each having a plurality of memory cells stacked in a direction perpendicular to a substrate, and a peripheral circuit region including a plurality of transistors electrically connected to the memory cell array through a plurality of conductive lines. Each of the transistors includes a gate electrode crossing an active region of the substrate in a first direction and source and drain regions in the active region at the opposite sides of the gate electrode. In at least one of the transistors, the number of source contact plugs connected to the source region is different from the number of drain contact plugs connected to the drain region. | 10-15-2015 |
20150295062 | VERTICALLY MOVABLE GATE FIELD EFFECT TRANSISTOR (VMGFET) ON A SILICON-ON-INSULATOR (SOI) WAFER AND METHOD OF FORMING A VMGFET - Methods for forming a vertically movable gate field effect transistor (VMGFET) on a silicon-on-insulator (SOI) wafer are described. The methods include providing a process of making VMGFET devices without critical alignment of masks between sequential etch and diffusion steps. The oxide layer of the SOI wafer is used for a self-limiting etch stop layer and for a sacrificial layer to form an insulating layer between a gate electrode and a substrate. The proper location of the gate electrode with respect to the source and drain junctions is insured by using a silicon gate structure as a mask layer for the diffusion process for defining the source and drain junctions. | 10-15-2015 |
20150303212 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate, a plurality of NAND strings each of which includes a plurality of memory cells provided on the semiconductor substrate and disposed in a first direction, and a select gate provided adjacent to the memory cell at an end portion of the plurality of memory cells, such that two select gates face each other at the ends of their respective memory cells, and a first spacer layer formed on a side wall between the select gates of the NAND strings disposed adjacent to each other. The first spacer layer includes a recess therein at the portion thereof located adjacent to the semiconductor substrate. | 10-22-2015 |
20150303215 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A 3D semiconductor device includes an electrode structure has electrodes stacked on a substrate, semiconductor patterns penetrating the electrode structure, charge storing patterns interposed between the semiconductor patterns and the electrode structure, and blocking insulating patterns interposed between the charge storing patterns and the electrode structure. Each of the blocking insulating patterns surrounds the semiconductor patterns, and the charge storing patterns are horizontally spaced from each other and configured in such a way as to each be disposed around a respective one of the semiconductor patterns. Also, each of the charge storing patterns includes a plurality of horizontal segments, each interposed between vertically adjacent ones of the electrodes. | 10-22-2015 |
20150311167 | Semiconductor Device Having Features to Prevent Reverse Engineering - An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device. | 10-29-2015 |
20150311221 | INTEGRATED CIRCUITS HAVING NICKEL SILICIDE CONTACTS AND METHODS FOR FABRICATING THE SAME - Integrated circuits having nickel silicide contacts and methods for fabricating integrated circuits with nickel silicide contacts are provided. An exemplary method for fabricating an integrated circuit includes providing a semiconductor substrate and forming a nonvolatile memory structure over the semiconductor substrate. The nonvolatile memory structure includes a gate surface. The method further includes depositing a nickel-containing material over the gate surface. Also, the method includes annealing the nonvolatile memory structure and forming a nickel silicide contact on the gate surface from the nickel-containing material. | 10-29-2015 |
20150318298 | TRENCH VERTICAL NAND AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string includes providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, etching the stack to form at least one trench in the stack, forming a blocking dielectric over a side wall of the at least one trench, forming a charge storage layer over the blocking dielectric in the at least one trench, forming a tunnel dielectric over the charge storage layer in the at least one trench and forming a semiconductor channel over the tunnel dielectric in the at least one trench. | 11-05-2015 |
20150325581 | INTEGRATED CIRCUIT PROTECTED FROM SHORT CIRCUITS CAUSED BY SILICIDE - An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region. | 11-12-2015 |
20150325587 | 3D STACKED IC DEVICE WITH STEPPED SUBSTACK INTERLAYER CONNECTORS - A stepped substack interlayer connector structure on a multilayer integrated circuit includes N steps on the substrate from a surface of the substrate at a first level to a surface of the substrate at a second level. A stack of active layers alternating with insulating layers on the substrate, including a plurality of substacks disposed in relation to the N step(s) to form respective contact regions in which the substacks are disposed at a common level. Interlayer connectors are formed by conductors in the respective regions connected to landing areas on active layers in each of the plurality of substacks. The maximum depth of the interlayer connectors is equal to, or less than, the thickness of one of the substacks. | 11-12-2015 |
20150333081 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode. | 11-19-2015 |
20150333143 | Memory Arrays - Some embodiments include a memory array which has a stack of alternating first and second levels. Channel material pillars extend through the stack, and vertically-stacked memory cell strings are along the channel material pillars. A common source is under the stack and electrically coupled to the channel material pillars. The common source has conductive protective material over and directly against metal silicide, with the conductive protective material being a composition other than metal silicide. Some embodiments include methods of fabricating integrated structures. | 11-19-2015 |
20150340377 | VERTICAL MEMORY DEVICES WITH VERTICAL ISOLATION STRUCTURES AND METHODS OF FABRICATING THE SAME - A vertical memory device includes a substrate, a column of vertical channels on the substrate and spaced apart along a direction parallel to the substrate, respective charge storage structures on sidewalls of respective ones of the vertical channels and gate electrodes vertically spaced along the charge storage structures. The vertical memory device further includes an isolation pattern disposed adjacent the column of vertical channels and including vertical extension portions extending parallel to the vertical channels and connection portions extending between adjacent ones of the vertical extension portions. | 11-26-2015 |
20150348985 | METHOD OF MAKING A SPLIT GATE NON-VOLATILE MEMORY (NVM) CELL AND A LOGIC TRANSISTOR - Semiconductor structures and methods for making semiconductor structures include a split gate non-volatile memory (NVM) cell in an NVM region. A charge storage layer, a first conductive layer, and a capping layer are formed over the substrate, which are patterned to form a control gate stack in the NVM region of the substrate. A high-k dielectric layer, a metal layer, and a second conductive layer are formed over the substrate. The second conductive layer and the metal layer are patterned to form remaining portions of the second conductive layer and the metal layer over and adjacent to a first side of the control gate stack. The remaining portion of the second conductive layer is removed to form a select gate stack, which includes the remaining portion of the metal layer. A stressor layer is formed over the substrate. | 12-03-2015 |
20150348988 | SEMICONDUCTOR MEMORY ELEMENT AND PRODUCTION METHOD THEREFOR - Provided is a semiconductor memory device including a vertical electrode provided on a substrate and a blocking insulating layer provided on a sidewall of the vertical electrode. A plurality of active patterns are provided spaced apart from the vertical electrode by the blocking insulating layer, and memory patterns are provided between the active patterns. | 12-03-2015 |
20150349109 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include interlayer insulating layers stacked in a first direction and separated from each other, word lines formed between the interlayer insulating layers, and sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed. The semiconductor device may also include cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths. | 12-03-2015 |
20150357339 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region. | 12-10-2015 |
20150357344 | MEMORY HAVING MEMORY CELL STRING AND COUPLING COMPONENTS - Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described. | 12-10-2015 |
20150364488 | THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE HAVING A SILICIDE SOURCE LINE AND METHOD OF MAKING THEREOF - A memory device and a method of making a memory device that includes a stack of alternating layers of a first material and a second material different from the first material over a substrate, where the layers of the second material form a plurality of conductive control gate electrodes. A plurality of NAND memory strings extend through the stack, where each NAND memory string includes a semiconductor channel which contains at least a first portion which extends substantially perpendicular to a major surface of the substrate and at least one memory film located between the semiconductor channel and the plurality of conductive control gate electrodes. A source line including a metal silicide material extends through the stack. | 12-17-2015 |
20150371999 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a plurality of wires provided on an insulating layer. Each of the wires includes one or more metal crystal grains. An average width of each of the wires and an average interval between the wires adjacent to each other are nearly equal to or less than a mean free path of free electrons in a bulk crystal of the metal. A specific crystal orientation in which size effect of electrical resistivity weakens due to anisotropy of Fermi velocity in the metal is substantially parallel to a current direction in at least a part of the crystal grains in each of the wires. | 12-24-2015 |
20150372000 | MEMORY DEVICE - There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate. | 12-24-2015 |
20150372003 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device, includes: a foundation layer; a stacked body provided on the foundation layer, each of a plurality of first insulating layers and each of a plurality of electrode layers being stacked alternately in the stacked body; a first layer provided between the stacked body and the foundation layer, the first layer including semiconductor, one portion of the first layer on a side of the stacked body including metal; a pair of first semiconductor members extending through the stacked body in a stacking direction of the stacked body; a memory film provided between each of the first semiconductor members and each of the plurality of electrode layers; a second semiconductor member provided inside the first layer and connected to the pair of first semiconductor members; and an insulating film provided between the second semiconductor member and the first layer. | 12-24-2015 |
20150372006 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state. | 12-24-2015 |
20150372101 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, channels, a gate stack, and a pad separating region. The substrate has a pad region adjacent to a cell region. The channels extend in a direction crossing an upper surface of the substrate in the cell region. The gate stack includes a plurality of gate electrode layers spaced apart from each other on the substrate and enclosing the channels in the cell region. The pad separating region separates the gate stack into two or more regions in the pad region. The gate electrode layers have different lengths in the pad region. | 12-24-2015 |
20150372136 | Pattern Layout to Prevent Split Gate Flash Memory Cell Failure - A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate including a first source/drain region and a second source/drain region. The first and second source/drain regions form a channel region therebetween. The semiconductor structure further includes a select gate and a memory gate spaced between the first and second source/drain regions over the channel region. The select gate extends over the channel region and terminates at a line end having a top surface asymmetric about an axis that extends along a length of the select gate and that bisects a width of the select gate. Even more, the semiconductor structure includes a charge trapping dielectric arranged between neighboring sidewalls of the memory gate and the select gate, and arranged under the memory gate. A method of manufacturing the semiconductor structure is also provided. | 12-24-2015 |
20150380301 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of convex portions on a substrate, forming a first film on upper faces and side faces of the convex portions, and forming a second film on the upper faces and the side faces of the convex portions via the first film. The method further includes removing the second film formed on upper faces of the first film to expose the upper faces of the first film. The method further includes implanting impurities into the convex portions in a state where side faces of the first film are covered with the second film and the upper faces of the first film are exposed. The method further includes annealing the convex portions after implanting the impurities into the convex portions. | 12-31-2015 |
20150380428 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a source layer; a stacked body; a columnar section; and a contact section extending in the stacking direction and piercing through the stacked body and connected to the source layer. The columnar section including: a channel body extending in the stacking direction and including a lower end, the lower end projecting into the source layer; and a charge storage film provided between the channel body and each of the electrode layers. The source layer including: a first film including metal; and a second film having electric conductivity provided between the first film and the lower end of the channel body, the second film being in contact with the lower end and covering the lower end. | 12-31-2015 |
20150380429 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel pillars protruding from the second portion of the pipe channel layer, and second channel pillars protruding from the first portion of the pipe channel layer. | 12-31-2015 |
20150380430 | JUNCTION FORMATION FOR VERTICAL GATE 3D NAND MEMORY - A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes. A film of second semiconductor material is deposited over the holes and into the pull-back regions. Portions of the film are removed from the holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material. The holes are filled with insulating material. Layers in the plurality of layers have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles. The second doping concentration profiles establish a higher conductivity in the elements of second semiconductor material. | 12-31-2015 |
20160005753 | Three Dimensional Semiconductor Memory Devices - A semiconductor memory device includes a semiconductor substrate including a common source region and a drain region, a lower structure provided on the semiconductor substrate and including a plurality of lower transistors connected in series between the common source region and the drain region, a stack including a plurality of word lines stacked on the lower structure, and semiconductor pillars penetrating the stack and controlling gate electrodes of respective ones of the lower transistors. | 01-07-2016 |
20160005759 | THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns. | 01-07-2016 |
20160005882 | NONVOLATILE MEMORY DEVICE INCLUDING PROGRAMMABLE MEMORY CELL AND METHOD OF FABRICATING THE SAME - Disclosed is a nonvolatile memory device including a memory cell having a transistor in which a structure is formed to be programmable and a method of fabricating the memory device. The memory cell includes one transistor serving as a basic structure, a gate insulating layer is formed of an insulating layer or a variable resistor, and a channel region includes a diode region, a source-drain connecting region, or an insulating isolation layer. The diode region, source-drain connecting region, or insulating isolation layer is formed in a region including a channel region between the source and drain regions in the semiconductor substrate. The gate includes a conductive layer, and the gate insulating layer includes an insulating layer or a variable resistor, a portion of the gate insulating layer between the gate and the diode region serves as a storage layer. | 01-07-2016 |
20160013201 | NON-VOLATILE MEMORY DEVICE | 01-14-2016 |
20160013202 | SEMICONDUCTOR DEVICES INCLUDING VERTICAL CELL STRINGS THAT ARE COMMONLY CONNECTED | 01-14-2016 |
20160013203 | SEMICONDUCTOR DEVICE | 01-14-2016 |
20160027796 | SEMICONDUCTOR DEVICES - According to example embodiments, a semiconductor device includes a substrate, a plurality of word lines spaced apart from each other in a first direction on the substrate, a channel layer in a channel hole defined by the plurality of word lines, a gate insulating layer in the channel hole along an inner wall of the channel hole; and a self-aligned contact on an upper portion of the channel layer in the channel hole. The gate insulating layer is between the plurality of word lines and the channel layer. The first direction is perpendicular to an upper surface of the substrate. The channel hole exposes the upper surface of the substrate. | 01-28-2016 |
20160027882 | SEMICONDUCTOR DEVICES AND STRUCTURES - Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region. | 01-28-2016 |
20160035733 | SEMICONDUCTOR CIRCUIT STRUCTURE - A NAND flash circuit structure includes two select gates disposed on a substrate, and an even number of spaced-apart word lines disposed between the two select gates. The select gate is provided with a first portion and a second portion. The thickness of the first portion and the second portion are different. | 02-04-2016 |
20160035738 | Contact Hole Collimation Using Etch-Resistant Walls - Contact holes are constrained to their designated active areas by etch-resistant walls so that they cannot contact adjacent active areas. Etch-resistant walls provide outer limits for any contact hole bending that may occur and thus keep contact holes substantially vertical. Mask openings for contact hole formation may be large so that they overlap etch-resistant walls. | 02-04-2016 |
20160035740 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a non-volatile memory device includes electrodes, an inter-layer insulating film between the electrodes and at least one semiconductor layer extending through the electrodes and the inter-layer insulating film. The device includes a charge storage layer between the semiconductor layer and each electrode, a first insulating film between the charge storage layer and the semiconductor layer, and a second insulating film. The second insulating film includes a first portion between the charge storage layer and each electrode, a second portion between each electrode and the inter-layer insulating film, and a third portion that links the first portion and the second portion. In a cross-section of the third portion parallel to the first direction and a second direction toward each electrode from the charge storage layer, a curved surface on the charge storage layer side has a curvature radius larger than a surface on the electrodes side. | 02-04-2016 |
20160035848 | METHOD OF FORMING SPLIT GATE MEMORY WITH IMPROVED RELIABILITY - A first doped region extends from a top surface of a substrate to a first depth. Implanting into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions. | 02-04-2016 |
20160043093 | THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF - A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses. | 02-11-2016 |
20160049346 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 02-18-2016 |
20160049419 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform. | 02-18-2016 |
20160049421 | THREE DIMENSIONAL NAND DEVICE HAVING DUMMY MEMORY HOLES AND METHOD OF MAKING THEREOF - A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, a memory opening extending substantially perpendicular to the major surface of the substrate and filled with a memory opening material including a memory film, and a dummy opening extending substantially perpendicular to the major surface of the substrate and filled with a dummy channel material which is different from the memory opening material. The dummy channel material has a higher Young's modulus than the memory opening material to offset warpage of the substrate due to the one of compressive and tensile stress imposed by the plurality of control gate electrodes on the substrate. | 02-18-2016 |
20160056167 | TUNGSTEN SEPARATION - Methods of selectively etching tungsten from the surface of a patterned substrate are described. The etch electrically separates vertically arranged tungsten slabs from one another as needed, for example, in the manufacture of vertical flash memory devices. The tungsten etch may selectively remove tungsten relative to films such as silicon, polysilicon, silicon oxide, aluminum oxide, titanium nitride and silicon nitride. The methods include exposing electrically-shorted tungsten slabs to remotely-excited fluorine formed in a capacitively-excited chamber plasma region. The methods then include exposing the tungsten slabs to remotely-excited fluorine formed in an inductively-excited remote plasma system. A low electron temperature is maintained in the substrate processing region during each operation to achieve high etch selectivity. | 02-25-2016 |
20160064389 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode. | 03-03-2016 |
20160064390 | NON-VOLATILE MEMORY WITH IMPROVED SENSING WINDOW - A semiconductor device may include: a substrate. First and second gate electrode patterns are disposed on first and second fin type active patterns. The first and second fin type active patterns include a first channel region disposed between a first impurity region and a second impurity region. The second gate electrode pattern crosses a first gate-separating region included in the second fin type active region. The first gate-separating region includes a trench and an embedded insulator filling at least a portion of the trench. | 03-03-2016 |
20160064507 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device having a memory cell equipped with a control gate electrode and a memory gate electrode adjacent to each other via a charge storage layer and having improved performance. | 03-03-2016 |
20160071855 | Semiconductor Device - A semiconductor device includes gate stacks disposed on a substrate and spaced apart from each other in a first direction, with a separation region interposed between the gate stacks; channel regions penetrating through the gate stacks and disposed within each of the gate stacks; and a guide region adjacent to the separation region, penetrating through at least a portion of the gate stack, and having a bent portion that is bent toward the separation region. | 03-10-2016 |
20160071863 | METHOD OF MANUFACTURING SEMICONDUCTOR STORAGE APPARATUS, AND SEMICONDUCTOR STORAGE APPARATUS - A method of manufacturing a semiconductor storage apparatus according to an embodiment includes forming an array of a plurality of memory cells. The method includes forming an interlayer insulating film that covers the memory cells. The method includes forming a first nitride film that covers an upper part of the interlayer insulating film. The method includes ion-implanting a first impurity into the first nitride film. | 03-10-2016 |
20160071866 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, the first columnar part includes a first channel body and a first charge storage film. The second columnar part includes a second channel body and a second charge storage film. The second columnar part is provided adjacent in the first direction to the first columnar part. The connection part connects a lower end of the first channel body and a lower end of the second channel body. Each of the source layers is connected to an upper end of the first columnar part. Each of the bit lines is connected to an upper end of the second columnar part of every (n+1)-th memory string of a plurality of memory strings arranged in the first direction. | 03-10-2016 |
20160071867 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a semiconductor device including a substrate and a stack layer. The substrate includes a first region, a second region, and a third region. The third region is disposed between the first region and the second region. Since a top surface of the substrate in the first region is lower than the top surface of the substrate in the second region, the substrate in the third region has a first step height. The stack layer is disposed on the substrate in the first and third regions. The top surface of the stack layer in the first region and the third region and the top surface of the substrate in the second region are substantially coplanar. | 03-10-2016 |
20160071869 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor memory device includes a stacked structure including conductive patterns and interlayer insulating patterns which are alternately stacked, a through-hole configured to pass through the stacked structure; a channel pattern formed inside the through-hole, a first capping conductive pattern formed on the channel pattern, a second capping conductive pattern formed on a sidewall of the first capping conductive pattern and surrounding the first capping conductive pattern, and a contact plug formed on the first capping conductive pattern and the second capping conductive pattern. | 03-10-2016 |
20160071870 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions. | 03-10-2016 |
20160071871 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of inter-layer insulating layers each provided between the plurality of electrode layers; and a columnar portion penetrating the stacked body and extending in a stacking direction of the stacked body. The columnar portion includes a channel body extending in the stacking direction; and a charge storage film provided between the channel body and each of the electrode layers. Each of the electrode layers includes an edge portion provided closer on a central axis side of the columnar portion than the inter-layer insulating layers. The charge storage film covers the edge portion of each of the electrode layers and separated from each other in the stacking direction. | 03-10-2016 |
20160071872 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first portion including a semiconductor element, a second portion surrounding the semiconductor element. The second portion includes a stack of conductive layers and insulating layers, and at least one groove through the conductive layers and the insulating layers. | 03-10-2016 |
20160071875 | SEMICONDUCTOR MEMORY DEVICE - In general, according to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a memory film, a partitioning member, a first interlayer insulating film, and a first plug. The stacked body is provided on the substrate, and including a plurality of electrode films and a plurality of insulating films. The semiconductor pillar is provided in the stacked body. The partitioning member is provided in the stacked body. The first plug is connected to the semiconductor pillar. A central axis of the first plug is shifted from a central axis of the semiconductor pillar so as to approach the nearest partitioning member. | 03-10-2016 |
20160071877 | SEMICONDUCTOR DEVICES INCLUDING CELL ON PERIPHERAL EPI-SUBSTRATE AND METHODS OF MANUFACTURING THE SAME - A semiconductor device can include a single crystalline silicon substrate and a plurality of peripheral region circuits on the single crystalline silicon substrate. An insulating layer can be on the plurality of peripheral region circuits and a polycrystalline silicon substrate can be on the insulating layer, where the polycrystalline silicon substrate can include a first layer of the polycrystalline silicon substrate and an epi-second layer of the polycrystalline silicon substrate on the first layer. A plurality of memory cell circuits can be on the polycrystalline silicon substrate. | 03-10-2016 |
20160071880 | THREE-DIMENSIONAL STRUCTURED MEMORY DEVICES - A 3D structured nonvolatile semiconductor memory devices and methods for manufacturing are disclosed. One such device includes an n+ region at a source/drain region; a p+ region at the source/drain region; and a diffusion barrier material between the n+ region and the p+ region. The n+ region is substantially isolated from the p+ region. | 03-10-2016 |
20160071881 | DOUBLE-SOURCE SEMICONDUCTOR DEVICE - A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. The semiconductor device may include a second source layer including a first region interposed between the first source layer and the first insulating layer and second regions interposed between the first channel layers and the first insulating layer, wherein the second regions of the second source layer directly contact each other. | 03-10-2016 |
20160071926 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers separately stacked each other; a plurality of columnar sections provided in the stacked body and extending in a stacking direction of the stacked body; and a first insulating section separating the stacked body. The respective columnar sections include a semiconductor body extending in the stacking direction; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The first insulating section includes a first air gap. | 03-10-2016 |
20160079068 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device includes a stack structure including first insulating films and first electrode films stacked alternately, the stack structure having a first through hole extending therethrough; a second electrode film provided above the stack structure, the second electrode film having a second through hole extending therethrough and communicating with the first through hole; a second insulating film provided above the second electrode film and having a third through hole extending therethrough and communicating with the second through hole; a semiconductor film provided along inner surfaces of the first and the second through holes; a memory film provided between the first electrode film and the semiconductor film; and a gate insulating film provided between the second electrode film and the semiconductor film; the third through hole becoming narrower toward an upper side of the stack direction and wider toward a lower side of a stack direction. | 03-17-2016 |
20160079185 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof. | 03-17-2016 |
20160079264 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a stacked body including electrode layers and first insulating layers; first semiconductor members extending in the stacked body; a second semiconductor member including first portions and a second portion, the second semiconductor member being connected commonly to lower ends of the first semiconductor members; a memory film provided between a first electrode layer of the first electrode layers and one of the first semiconductor members; and an insulating film provided between the second semiconductor member and the stacked body. A second electrode layer of the electrode layers is provided on the second portion of the second semiconductor member via the insulating film. A third electrode layer of the electrode layers is provided under the second portion of the second semiconductor member via the insulating film. One of the first insulating layers is provided between the second electrode layer and the third electrode layer. | 03-17-2016 |
20160079265 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - This nonvolatile semiconductor memory device includes a semiconductor substrate and a first semiconductor layer formed on a surface of the semiconductor substrate. A memory cell array is formed by coupling a plurality of memory cells in series, and includes a memory string formed to extend in a first direction vertical to the surface of the semiconductor substrate. A contact extends in a direction vertical to the semiconductor substrate, and has one end coupled to the first semiconductor layer. The contact includes: a second semiconductor layer that is formed in the first semiconductor layer and has a higher impurity concentration than that of the first semiconductor layer; a silicide film that has one end coupled to the second semiconductor layer and extends in the first direction; and a metal film formed on an inner wall of the silicide film. | 03-17-2016 |
20160079266 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a stacked body, a selection gate electrode, a semiconductor pillar, a first insulating member, a second insulating member, a third insulating member. The stacked body is provided on the substrate. The selection gate electrode is provided on the stacked body. The first insulating member divides the stacked body in a first direction. The second insulating member is provided in an area directly above the first insulating member and dividing the selection gate electrode in the first direction. The third insulating member is provided in a region other than the area directly above the first insulating member and dividing the selection gate electrode in the first direction. An average width of the second insulating member in the first direction is larger than an average width of the third insulating member in the first direction. | 03-17-2016 |
20160079267 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a first layer; a stacked body provided above the first layer and including a plurality of electrode layers separately stacked each other; a second layer provided between the first layer and the stacked body; an intermediate layer provided between the first layer and the second layer; a semiconductor body provided in the stacked body, the second layer, the intermediate layer and the first layer, the semiconductor body extending in a stacking direction of the stacked body; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The semiconductor body includes a side surface connected with the intermediate layer in the vicinity of a boundary between the first layer and the second layer. At least one of the first layer and the second layer has conductivity and is connected with the intermediate layer. | 03-17-2016 |
20160079269 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment, a nonvolatile semiconductor memory device comprises a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer. In addition, the nonvolatile semiconductor memory device comprises: a semiconductor layer having the first direction as a longer direction; a tunnel insulating layer contacting a side surface of the semiconductor layer; a charge accumulation layer contacting a side surface of the tunnel insulating layer; and a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer. Moreover, the portion facing the conductive layer, of the charge accumulation layer is thinner compared to a portion facing the inter-layer insulating layer, of the charge accumulation layer. | 03-17-2016 |
20160079270 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - An integrated circuit device according to one embodiment includes a plurality of first electrode films stacked spaced from each other, a plurality of second electrode films stacked spaced from each other on the plurality of first electrode films and extending in one direction, a semiconductor pillar penetrating the first electrode films and the second electrode films, a memory film provided between the first electrode films and the semiconductor pillar and capable of storing charge, a gate insulating film provided between the second electrode films and the semiconductor pillar, and a spacer film electrically connecting width-direction edges of the plurality of second electrode films to each other. | 03-17-2016 |
20160079273 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including a plurality of pillar columns, each of the plurality of pillar columns including a plurality of pillars arranged in one direction to be offset from each other, wherein an mth pillar and an (m+1)th pillar, among the plurality of pillars included in each pillar column, are aligned with each other (m is an integer of 0 or more). | 03-17-2016 |
20160079274 | Transistors, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string. | 03-17-2016 |
20160086964 | HIGH STACK 3D MEMORY AND METHOD OF MAKING - A method of making a monolithic three dimensional NAND device includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming a mask layer over the stack and patterning the mask layer to form at least on opening in the mask layer to expose a top layer of the stack. The method also includes forming a metal block in the at least one opening in the mask layer, etching the stack by metal induced localized etch using the metal block in the at least one opening in the mask layer to form at least one opening in the stack and forming at least one layer of the NAND device in the at least one opening. | 03-24-2016 |
20160086969 | THREE DIMENSIONAL NAND DEVICE HAVING NONLINEAR CONTROL GATE ELECTRODES AND METHOD OF MAKING THEREOF - A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region. | 03-24-2016 |
20160087058 | INTEGRATION OF A NON-VOLATILE MEMORY (NVM) CELL AND A LOGIC TRANSISTOR AND METHOD THEREFOR - A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate. | 03-24-2016 |
20160093631 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions. | 03-31-2016 |
20160093633 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a plurality of memory cell transistors that are formed above a semiconductor substrate and are connected to each other in series, first and second selection transistors formed respectively on either side of the memory cell transistors above the semiconductor substrate, a source line contact formed adjacent the first selection transistor and having a bottom thereof in contact with the semiconductor substrate, and a bit line contact formed adjacent the second selection transistor and having a bottom thereof in contact with the semiconductor substrate at a position higher than the bottom of the source line contact. | 03-31-2016 |
20160093635 | VERTICAL MEMORY DEVICE WITH BIT LINE AIR GAP - A structure includes a three-dimensional semiconductor device including a plurality of unit device structures located over a substrate. Each of the unit device structures includes a semiconductor channel including at least a portion extending vertically along a direction perpendicular to a top surface of the substrate, and a drain region contacting a top end of the semiconductor channel. The structure also includes a combination of a plurality of contact pillars and a contiguous volume that laterally surrounds the plurality of contact pillars. The plurality of contact pillars is in contact with the drain regions, and the contiguous volume has a dielectric constant less than 3.9. | 03-31-2016 |
20160099252 | MEMORY HAVING A CONTINUOUS CHANNEL - The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate. | 04-07-2016 |
20160099305 | Integrated Circuitry and Methods of Forming Transistors - Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped. | 04-07-2016 |
20160104721 | VERTICAL TYPE MEMORY DEVICE - A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections. | 04-14-2016 |
20160111431 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided. | 04-21-2016 |
20160111432 | SINGLE-SEMICONDUCTOR-LAYER CHANNEL IN A MEMORY OPENING FOR A THREE-DIMENSIONAL NON-VOLATILE MEMORY DEVICE - A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device. | 04-21-2016 |
20160111434 | THREE DIMENSIONAL NAND STRING MEMORY DEVICES AND METHODS OF FABRICATION THEREOF - Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface. In another embodiment, layers of oxide material exposed in a front side opening of a material layer stack are surface nitrided and etched to provide convexly-rounded corner portions, and a blocking dielectric is formed over the convexly-rounded corner portions. | 04-21-2016 |
20160111436 | VERTICAL NAND DEVICE CONTAINING PERIPHERAL DEVICES ON EPITAXIAL SEMICONDUCTOR PEDESTAL - A multilevel structure includes a stack of an alternating plurality of electrically conductive layers and insulator layers located over a semiconductor substrate, and an array of memory stack structures located within memory openings through the stack. An epitaxial semiconductor pedestal is provided, which is in epitaxial alignment with a single crystalline substrate semiconductor material in the semiconductor substrate and has a top surface within a horizontal plane located above a plurality of electrically conductive layers within the stack. The contact via structures for the semiconductor devices on the epitaxial semiconductor pedestal can extend can be less than the thickness of the stack. | 04-21-2016 |
20160111438 | BATCH CONTACTS FOR MULTIPLE ELECTRICALLY CONDUCTIVE LAYERS - A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers. | 04-21-2016 |
20160111440 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 04-21-2016 |
20160118395 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a pipe gate, a multi-layered word line formed over the pipe gate, a first channel including a first pipe channel buried in the pipe gate and a first side channel coupled to both sides of the first pipe channel to pass through the word line, a second channel including a second pipe channel buried in the pipe gate and disposed over the first pipe channel and a second side channel coupled to both sides of the second pipe channel to pass through the word line, and an insulation pattern disposed between the first pipe channel and the second pipe channel. | 04-28-2016 |
20160118396 | THREE DIMENSIONAL NAND DEVICE CONTAINING FLUORINE DOPED LAYER AND METHOD OF MAKING THEREOF - A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming an at least one front side opening in the stack and forming at least a portion of a memory film in the at least one front side opening. The method also includes forming a semiconductor channel in the at least one front side opening and doping at least one of the memory film and the semiconductor channel with fluorine in-situ during deposition or by annealing in a fluorine containing atmosphere. | 04-28-2016 |
20160118398 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF FABRICATING THE SAME - Provided are a three dimensional semiconductor memory device and a method of fabricating the same. In the three dimensional semiconductor memory device, a stack of gate electrodes and insulating layers may be formed on a substrate, a channel structure may extend through the stack and connect to the substrate. A blocking insulating layer, a charge storing layer and a tunnel insulating layer may be formed between each gate electrode and the channel structure. The tunnel insulating layer may include a high-k dielectric layer with a low charge trap site density. The tunnel insulating layer may also include a first and a second tunnel insulating layers, and the high-k dielectric layer is provided between the first and second tunnel insulating layers. | 04-28-2016 |
20160126252 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method for manufacturing a semiconductor memory device includes simultaneously forming a plurality of first holes and a plurality of second holes in a stacked body. The stacked body includes a plurality of first layers and a plurality of second layers. The method includes etching a portion between the second holes next to each other in the stacked body, and connecting at least two or more second holes to form a groove. The method includes forming a film including a charge storage film on a sidewall of the first holes. The method includes forming a channel film on a sidewall of the film including the charge storage film. | 05-05-2016 |
20160126311 | STACKED THIN CHANNELS FOR BOOST AND LEAKAGE IMPROVEMENT - A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same. | 05-05-2016 |
20160133317 | NEUROMORPHIC DEVICE WITH EXCITATORY AND INHIBITORY FUNCTIONALITIES - Provided is a neuromorphic device including first and second lower electrodes formed on a substrate to be electrically separated, first and second lower insulating film stacks formed at least on respective surfaces of the first and second lower electrodes, first, second, and third doped regions formed at left and right sides of the first and second lower electrodes, first and second semiconductor regions formed on the first and second lower insulating film stacks, an upper insulating film stack formed on the first and second semiconductor regions and the first, second, and third doped regions, and an upper electrode formed on the upper insulating film stack. Accordingly, a specified neuromorphic device can be reconfigured to have arbitrarily inhibitory or excitatory functionality by using the first and second lower electrodes and the lower insulating film stacks including charge storage layers formed on the surfaces of the electrodes. | 05-12-2016 |
20160133568 | Contact Structure for Nand Based Non-Volatile Memory Device and a Method of Manufacture - A NAND-based non-volatile memory contact structure includes a trench located adjacent to layered alternating conducting and insulating layers, the layers lining sides and bottom of the trench. A portion of the trench is removed to expose a surface in which electrical connections to the conducting layers are provided on one level. | 05-12-2016 |
20160133638 | MEMORY CELL PILLAR INCLUDING SOURCE JUNCTION PLUG - Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug. | 05-12-2016 |
20160133644 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ASYMMETRIC WORD LINE PADS - Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed. | 05-12-2016 |
20160141300 | THREE-DIMENSIONAL MEMORY AND METHOD FOR MANUFACTURING THE SAME - A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a source region and a drain region disposed separately. The source region comprises a first source region and a second source region disposed between the first source region and the drain region. The first source region is p-type of doping, the second source region is n-type of doping, and the drain region is n-type of doping. | 05-19-2016 |
20160141419 | THREE DIMENSIONAL NAND DEVICE HAVING REDUCED WAFER BOWING AND METHOD OF MAKING THEREOF - A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate, and at least one trench extending substantially perpendicular to the major surface of the substrate. The trench is filled with at least a first trench material and a second trench material. The first trench material includes a material under a first magnitude of a first stress type, and the second trench material includes a material under no stress, a second stress type opposite the first stress type, or a second magnitude of the first stress type lower than the first magnitude of the first stress type to offset warpage of the substrate due to the stress imposed by at least one of the first trench material or the plurality of control gate electrodes on the substrate. | 05-19-2016 |
20160148835 | SET OF STEPPED SURFACES FORMATION FOR A MULTILEVEL INTERCONNECT STRUCTURE - A trench can be formed through a stack of alternating plurality of first material layers and second material layers. A dielectric material liner and a trench fill material portion can be formed in the trench. The dielectric material liner and portions of first material layer can be simultaneously etched to form laterally-extending cavities having level-dependent lateral extents. A set of stepped surfaces can be formed by removing unmasked portions of the second material layers. Alternately, an alternating sequence of processing steps including vertical etch processes and lateral recess processes can be employed to laterally recess second material layers and to form laterally-extending cavities having level-dependent lateral extents. Lateral cavities can be simultaneously formed in multiple levels such that levels having laterally-extending cavities of a same lateral extent are offset across multiple integrated cavities. | 05-26-2016 |
20160148943 | METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY - Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors. | 05-26-2016 |
20160149002 | MEMORY DEVICE CONTAINING STRESS-TUNABLE CONTROL GATE ELECTRODES - A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile-stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress-generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material. | 05-26-2016 |
20160149049 | RUTHENIUM NUCLEATION LAYER FOR CONTROL GATE ELECTRODES IN A MEMORY STRUCTURE - A memory film and a semiconductor channel can be formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, a ruthenium portion can be formed in each backside recess, and a polycrystalline conductive material portion can be formed on each ruthenium portion. Each ruthenium portion can be employed in lieu of a tungsten seed layer to function as a lower resistivity seed layer that enables subsequent deposition of a polycrystalline conductive material. The resulting electrically conductive lines can have a lower resistivity than conductive lines of comparable dimensions that employ tungsten seed layers. | 05-26-2016 |
20160155813 | METHODS AND STRUCTURES FOR SPLIT GATE MEMORY CELL SCALING WITH MERGED CONTROL GATES | 06-02-2016 |
20160163686 | SEMICONDUCTOR DEVICES HAVING DUMMY PATTERNS AND METHODS OF FABRICATING THE SAME - Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other. | 06-09-2016 |
20160163726 | APPARATUSES INCLUDING MEMORY ARRAYS WITH SOURCE CONTACTS ADJACENT EDGES OF SOURCES - Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge. | 06-09-2016 |
20160163730 | SEMICONDUCTOR DEVICE - A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region. | 06-09-2016 |
20160163732 | SEMICONDUCTOR DEVICES - Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern including an opening on a semiconductor substrate. A peripheral transistor and a peripheral interconnection structure may be disposed between the semiconductor substrate and the semiconductor pattern. The peripheral interconnection structure may be electrically connected to the peripheral transistor. Cell gate conductive patterns may be disposed on the semiconductor pattern. The cell vertical structures may extend through the cell gate conductive patterns and may be connected to the semiconductor pattern. Cell bit line contact plugs may be disposed on the cell vertical structures. A bit line may be disposed on the cell bit line contact plugs. A peripheral bit line contact structure may be disposed between the bit line and the peripheral interconnection structure. The peripheral bit line contact structure may extend through the opening of the semiconductor. | 06-09-2016 |
20160172294 | HIGH ASPECT RATIO STRUCTURE | 06-16-2016 |
20160172366 | THREE DIMENSIONAL MEMORY DEVICE WITH BLOCKING DIELECTRIC HAVING ENHANCED PROTECTION AGAINST FLUORINE ATTACK | 06-16-2016 |
20160172368 | Contact For Vertical Memory With Dopant Diffusion Stopper And Associated Fabrication Method | 06-16-2016 |
20160172369 | FORMING MEMORY USING DOPED OXIDE | 06-16-2016 |
20160172370 | SELECTIVE BLOCKING DIELECTRIC FORMATION IN A THREE-DIMENSIONAL MEMORY STRUCTURE | 06-16-2016 |
20160181264 | THREE DIMENSIONAL NAND MEMORY HAVING IMPROVED CONNECTION BETWEEN SOURCE LINE AND IN-HOLE CHANNEL MATERIAL AS WELL AS REDUCED DAMAGE TO IN-HOLE LAYERS | 06-23-2016 |
20160181268 | BOUNDARY SCHEME FOR EMBEDDED POLY-SiON CMOS OR NVM IN HKMG CMOS TECHNOLOGY | 06-23-2016 |
20160181270 | MEMORY ARCHITECTURE OF ARRAY WITH SINGLE GATE MEMORY DEVICES | 06-23-2016 |
20160181274 | SEMICONDUCTOR MEMORY DEVICE | 06-23-2016 |
20160190153 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, a plurality of fin structures, a plurality of conductor liner layers, a charge storage layer, a plurality of first conductor layers, and a plurality of filling pillars. The fin structures are disposed on the substrate, and a trench is formed between two adjacent fin structures. Each of the conductor liner layers covers a portion of sidewalls and a portion of top surfaces of the fin structures. The charge storage layer is disposed between the fin structures and the conductor liner layers. The first conductor layers cover the conductor liner layers and are electrically connected to the conductor liner layers. The filling pillars are disposed in the trenches and between the conductor liner layers and the first conductor layers. | 06-30-2016 |
20160190313 | LOCAL BURIED CHANNEL DIELECTRIC FOR VERTICAL NAND PERFORMANCE ENHANCEMENT AND VERTICAL SCALING - A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel. | 06-30-2016 |
20160197041 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME | 07-07-2016 |
20160197092 | VERTICAL MEMORY DEVICES AND RELATED METHODS OF MANUFACTURE | 07-07-2016 |
20160204205 | SOURCE MATERIAL FOR ELECTRONIC DEVICE APPLICATIONS | 07-14-2016 |
20160254271 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF | 09-01-2016 |
20160254272 | THREE-DIMENSIONAL (3D) SEMICONDUCTOR DEVICE | 09-01-2016 |
20160379989 | DIFFERENTIAL ETCH OF METAL OXIDE BLOCKING DIELECTRIC LAYER FOR THREE-DIMENSIONAL MEMORY DEVICES - A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion. | 12-29-2016 |
20160379990 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer. | 12-29-2016 |
20170236746 | MULTI-TIER MEMORY DEVICE WITH THROUGH-STACK PERIPHERAL CONTACT VIA STRUCTURES AND METHOD OF MAKING THEREOF | 08-17-2017 |
20170236834 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 08-17-2017 |
20170236835 | MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICES CONTAINING ANNULAR DIELECTRIC SPACERS WITHIN MEMORY OPENINGS AND METHODS OF MAKING THE SAME | 08-17-2017 |
20170236896 | SELF-ALIGNED ISOLATION DIELECTRIC STRUCTURES FOR A THREE-DIMENSIONAL MEMORY DEVICE | 08-17-2017 |
20180026044 | SEMICONDUCTOR MEMORY DEVICE | 01-25-2018 |
20180026046 | MEMORY DEVICE | 01-25-2018 |
20180026047 | MEMORY DEVICE | 01-25-2018 |
20180026050 | Semiconductor Devices with Vertical Channel Structures | 01-25-2018 |
20190146330 | METHOD FOR FORMING AN ALIGNED MASK | 05-16-2019 |
20190148395 | COST-EFFECTIVE METHOD TO FORM A RELIABLE MEMORY DEVICE WITH SELECTIVE SILICIDATION AND RESULTING DEVICE | 05-16-2019 |
20190148401 | THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF | 05-16-2019 |
20190148404 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF | 05-16-2019 |
20190148405 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 05-16-2019 |
20220139779 | Integrated Assemblies and Methods of Forming Integrated Assemblies - Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies. | 05-05-2022 |
20220139946 | SEMICONDUCTOR DEVICE HAVING A DAM STRUCTURE - A semiconductor device includes a memory stack on a substrate, the memory stack including gate electrodes, insulating layers and mold layers, the mold layers being disposed at the same levels as the gate electrodes in a through electrode area, a channel structure extending vertically through the gate electrodes in a cell array area, and a dam structure disposed between the isolation insulating layers and surrounding the through electrode area in a top view. The dam structure includes a dam insulating layer having a dam shape, an inner insulating layer inside the dam insulating layer, and an outer insulating layer outside the dam insulating layer. The inner insulating layer includes first protrusions protruding in a horizontal direction, and the outer insulating layer includes second protrusions protruding in the horizontal direction. | 05-05-2022 |
20220139952 | SEMICONDUCTOR DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A semiconductor device is disclosed. The semiconductor device may include gate stacks that are on a substrate, are spaced apart from each other in a first direction, and include electrodes and cell insulating layers alternately stacked, a separation structure between the gate stacks and extending in a second direction crossing the first direction, vertical structures penetrating the gate stacks and having conductive pads on upper portions thereof, a supporting structure on the gate stacks, bit lines on the supporting structure, and contact plugs penetrating the supporting structure and electrically connecting the bit lines to the vertical structures. A bottom surface of a portion of the supporting structure on the separation structure may be lower than top surfaces of the conductive pads. | 05-05-2022 |
20220139953 | THREE-DIMENSIONAL FLASH MEMORY HAVING IMPROVED DEGREE OF INTEGRATION, AND MANUFACTURING METHOD THEREFOR - Provided are a 3-dimensional (3D) flash memory with an improved degree of integration and a method of manufacturing the same. The 3D flash memory may include at least one vertical string formed to extend in one direction on a substrate and comprising a channel layer formed to extend in the one direction and a charge storage layer formed to extend in the one direction so as to surround the channel layer; a plurality of electrode layers stacked to be vertically connected to the at least one vertical string; and a source line formed to be buried in the substrate. | 05-05-2022 |
20220139958 | MICROELECTRONIC DEVICES INCLUDING VARYING TIER PITCH, AND RELATED ELECTRONIC SYSTEMS - A microelectronic device comprises a first set of tiers, each tier of the first set of tiers comprising alternating levels of a conductive material and an insulative material and having a first tier pitch, a second set of tiers adjacent to the first set of tiers, each tier of the second set of tiers comprising alternating levels of the conductive material and the insulative material and having a second tier pitch less than the first tier pitch, a third set of tiers adjacent to the second set of tiers, each tier of the third set of tiers comprising alternating levels of the conductive material and the insulative material and having a third tier pitch less than the second tier pitch, and a string of memory cells extending through the first set of tiers, the second set of tiers, and the third set of tiers. Related microelectronic devices, electronic systems, and methods are also described. | 05-05-2022 |