Patent application number | Description | Published |
20080216313 | Method For Fabricating IC Board Without Ring Structure - A method for fabricating an IC board without a ring structure is provided, in which after the completion of the core board (including the core through hole), the second pattern photoresist layer is used to mask over the first depositing metal layer, and portion of the second depositing metal layer (this portion of the second depositing metal layer is to electrically couple to the conductive circuit of the core through hole). Later, the second depositing metal layer, the first depositing metal layer, the metal layer, and even to the substrate at the innermost layer which are for the portion that are not masked by the second pattern photoresist layer are removed. As a result, the substrate is exposed to form the ringless structure, but which is to couple a conductive line to the core board through hole. | 09-11-2008 |
20080251386 | Manufacturing Method Of Non-Etched Circuit Board - A manufacturing method of a non-etched circuit board is disclosed herein, which employs a metal substrate having a metal barrier layer and an electroplated copper layer to transmit an electrical current to form a circuit layer. A patterned photoresist layer is formed on the electroplated copper layer to define the location of the circuit layer and form circuits or conductive via on the board by electroplating. An electroplated nickel layer or an electroplated gold layer is further formed on the circuit layer for protecting the circuits and improving the fine line capability. During or after the process, the metal substrate, the metal barrier layer, and the electroplated copper layer are removed to enlarge the wiring space, so that a high-density circuit board can be obtained. | 10-16-2008 |
20080285245 | Embedded Passive Device Structure And Manufacturing Method Thereof - Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased. | 11-20-2008 |
20080303150 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line circuit structure mainly includes: a first semiconductor device, an insulated layer on the same surface, an outer circuit layer above the first semiconductor device, and a solder mask formed on the outer circuit layer. The surface which is not covered by the solder mask can be made to be a pad, and electrically connected with a second semiconductor device. The fine line circuit layer, which is exposed, is to be a tin ball pad where a tin ball is filled. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 12-11-2008 |
20080314622 | Method Of Fabricating Board Having High Density Core Layer And Structure Thereof - Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product. | 12-25-2008 |
20090001547 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes: two packaged semiconductor devices installed on a circuit layer and a power/ground layer formed therebetween, to realize the objective of high-density and ground connection. On an outer circuit, the part, which is not covered by a solder mask, can be made into a pad for electrically connecting with one of the semiconductor devices. The other semiconductor device may be installed on the fine line circuit layer. The fine line circuit layer, which is exposed, is to be a tin ball pad where a tin ball is filled. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 01-01-2009 |
20090001603 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 01-01-2009 |
20090008766 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes two semiconductor devices formed on the same surface, without stacking to each other. One of the semiconductor devices is directly installed on a fine line circuit layer, and the other semiconductor device is installed on the fine line circuit layer within a dielectric layer cavity. In the method of the present invention, electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 01-08-2009 |
20090078576 | Embedded Passive Device Structure And Manufacturing Method Thereof - Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased. | 03-26-2009 |
20090111213 | High-Density Fine Line Structure And Method Of Manufacturing The Same - A high-density fine line structure mainly includes: two boards with similar structures and a dielectric film for combing the two boards. Semiconductor devices respectively in two boards are opposite to each other after the two boards are combined. The two boards each include a fine line circuit, an insulated layer on the same surface, and the semiconductor device installed above the fine line circuit. The surface of the circuit, which is not covered by a solder mask, is made into a pad. The pad is filled with the tin balls for electrically connecting with another semiconductor device. Electroplating rather than the etching method is used for forming the fine line circuit layer, and a carrier and a metal barrier layer, which are needed during or at the end of the manufacturing process, are removed to increase the wiring density for realizing the object of high-density. | 04-30-2009 |
20090154127 | PCB Embedded Electronic Elements Structure And Method Thereof - Structure of embedded electronic elements in a PCB (printed circuit board) and the method for embedding the structure include assembling the electronic elements (such as a capacitor, a resistor, a diode) on the PCB, and then laminating other circuit layers. A group of electrodes of the electronic elements are aligned to a group of junctions on the PCB, respectively; the electronic elements are assembled on the group of junctions on the PCB; and then a metal layer is laminated on the PCB using gel film (dielectric gel) in which the PCB includes already embedded electronic elements. | 06-18-2009 |
20090294052 | Method For Fabricating Component-Embedded Printed Circuit Board - A method for fabricating a component-embedded PCB includes: providing a carrier plate having a plating metal layer plated thereon; disposing an electronic component on the plating metal layer of the carrier plate; laminating a metal layer onto the plating metal layer having the electronic component disposed thereon and the carrier plate by a dielectric film; removing the carrier plate and exposing the plating metal layer; and patterning at least one of the metal layer and the plating metal layer to be a circuit layer. | 12-03-2009 |
20090308527 | Method For Fabricating Circuit Trace On Core Board Having Buried Hole - A method for fabricating a circuit trace on a core board having a buried hole is provided. The method includes: providing a carrier plate having a detachable metal layer, an etching barrier layer, and a metal layer sequentially stacked thereon; roughening the metal layer which can be completely roughened; laminating the bonded metal layer, the etching barrier layer, the detachable metal layer and the carrier plate onto a dielectric, wherein the metal layer faces and contacts with the dielectric; and then removing the carrier plate therefrom. As such, even if the dielectric is difficult to be completely roughened, the roughened metal layer can enhance the bondability between the metal layer and the dielectric. The metal layer is processed to become the circuit trace later. | 12-17-2009 |
20100075495 | Method Of Selectively Plating Without Plating Lines - A method of selectively plating without plating lines is provided. The method employs a loading plate having a metalized temporary conductive layer. The loading plate and the temporary conductive layer are adapted for transmitting a plating current. A patterning photoresist layer is accorded for selectively and sequentially plating a separating metal layer, a plating protection layer, and a connection pad layer on to the temporary conductive layer. Then, the loading plate is further used for supplying current to form other circuit layers by a pressing lamination process. And when the plate process is completed or it is not need to plate, the loading plate and the temporary conductive layer can be removed, for further completing for example the solder mask process, and thus achieving the objective of plating without plating lines. | 03-25-2010 |
20100075497 | Non-Plating Line Plating Method Using Current Transmitted From Ball Side - A non-plating line (NPL) plating method is provided. The NPL plating method is featured in that at first it forms a circuit layer on a bump side only, and therefore a plating current can be transmitted via a plating metal layer on a ball side to the circuit layer (enclosed by an insulation layer, e.g., a solder resist or a photoresist) on the bump side, and thus forming a protection layer, e.g., plating gold, on the plating metal layer on the circuit layer and the ball side. In such a way, the plating gold is formed after the insulation layer, so that there won't be any plating gold existed beneath the insulation layer of the bump side (connected with dies). Hence, the insulation layer can be prevented from dropping off from the protection layer, i.e., the plating gold, and thus the reliability of the products can be improved. | 03-25-2010 |
20100170088 | Method Of Fabricating Board Having High Density Core Layer And Structure Thereof - Structure and method of making a board having plating though hole (PTH) core layer substrate and stacked multiple layers of blind vias. More stacking layers of blind vias than conventional methods can be achieved. The fabrication method of the board having high-density core layer includes the following: after the making of the PTH, the filling material filled inside the PTH of the core layer is partially removed until the PTH has reached an appropriate flattened depression using etching; then image transfer and pattern plating are performed to fill and to level the depression portion up to a desired thickness to form a copper pad (overplating) as the core layer substrate is forming a circuit layer; finally using electroless copper deposition and the pattern plating to make the product. | 07-08-2010 |
20100283145 | Stack structure with copper bumps - A stack structure with copper bumps on an integrated circuit board is disclosed. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which are stacked alternately. The uppermost conductive layer has copper bumps as copper pillar pins for soldering the chip pins of an integrated circuit chip. Because the copper bumps have a certain height, the distance between the copper bumps and the chip pins is shortened, and therefore the solders needed for soldering may be reduced. Also, the shape of the solders is a long strap instead of spheroid due to the cohesion force between the copper bump surfaces and the solders so that the distance between the solders is scaled down and the gaps between the pins are reduced. Thus, the entire size of the integrated circuit board may also be miniatured. | 11-11-2010 |
20100307666 | Method For Fabricating Buried Capacitor Structure - A method for fabricating a buried capacitor structure includes: laminating a first dielectric layer having a capacitor embedded therein with a second dielectric layer to bury the capacitor therebetween; forming a first circuit pattern on a first metal layer of the first dielectric layer and a second circuit pattern on a second metal layer of the second dielectric layer; depositing a first insulating layer and a second insulating layer on the first metal layer and the second metal layer, respectively; electrically connecting a positive electrode end and a negative electrode end of the capacitor to the second metal layer by a positive through-hole and a negative through-hole, thereby manufacturing the buried capacitor structure. | 12-09-2010 |
20100309608 | Buried Capacitor Structure - A buried capacitor structure including a first conductive metal layer, a first dielectric film, a capacitor, a second dielectric film, and a second conductive metal layer, which are stacked in sequence, wherein the capacitor is buried between the first dielectric film and the second dielectric film, the first conductive metal layer is formed into a first circuit pattern, the second conductive metal layer is formed into a second circuit pattern. The capacitor is a planar comb-shaped capacitor with a positive electrode, a negative electrode, and a capacitor paste filled between the positive electrode and the negative electrode, wherein the positive electrode includes a positive electrode end and a plurality of positive comb branches, the negative electrode includes a negative electrode end and a plurality of negative comb branches, and the positive branches and the negative branches are parallel to and separated from each other. | 12-09-2010 |
20110048777 | Component-Embedded Printed Circuit Board - A component-embedded printed circuit board includes: a carrier plate having a metalized layer disposed thereon, an electronic component disposed on the metalized layer of the carrier plate, and a metal layer laminated onto the metalized layer having the electronic component disposed thereon by a dielectric film. The carrier plate is then removed to expose the metalized layer. At least one of the metal layer and the metalized layer is patterned to be a circuit layer. | 03-03-2011 |
20110083323 | Method For Fabricating An Interlayer Conducting Structure Of An Embedded Circuitry - A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value. | 04-14-2011 |
20120228011 | Semiconductor Load Board - Disclosed is a semiconductor load board, including a substrate, a plurality of connection pads, a patterned circuit layer, a dielectric layer, a plurality of solder pads, and a plurality of solders. The connection pads and the patterned circuit layer are located on the substrate. The dielectric layer is formed on the substrate, the connection pads and the patterned circuit layer, and has a plurality of openings corresponding to the plurality of connection pads. The solder pads are formed in the openings, and the width of the solder pads is smaller than or equals to the maximum width of the openings of the dielectric layer, and a protruding portion which has a width smaller than the minimum width of the openings of the dielectric layer can also be formed, such that the problems of short-circuit failure and electrical interference can be reduced. | 09-13-2012 |
20120231621 | Manufacturing Method Of A Semiconductor Load Board - A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced. | 09-13-2012 |
20130233602 | SURFACE TREATMENT STRUCTURE OF CIRCUIT PATTERN - A surface treatment structure formed on a circuit pattern on a printed circuit board is provided, which includes a first gold layer, a palladium layer, and a second gold layer stacked from bottom to top, respectively, or includes a palladium layer, and a second gold layer stacked from bottom to top, respectively. The palladium layer is used to prevent the diffusion of the copper ions from the circuit pattern. Only a thin surface treatment structure of the circuit pattern of the present invention is required to achieve excellent wire bonding, so that the overall thickness is reduced, and the manufacture cost is also reduced. Furthermore, the uniformness of palladium is better than that of nickel, and thereby the surface treatment structure of the circuit pattern of the present invention is suitably used for manufacturing the fine-line circuits, thereby having a wider industrial applicability. | 09-12-2013 |
20140115888 | METHOD OF MANUFACTURING A CHIP SUPPORT BOARD STRUCTURE - A method of manufacturing a chip support board structure which includes the steps of forming a metal substrate structure, forming a photo resist pattern, etching the metal substrate structure to form a paddle, removing the photo resist pattern, pressing an insulation layer against the paddle, polishing the insulation layer, forming a circuit layer and forming a solder resist is disclosed. The metal substrate structure is formed by sandwiching a block layer with two metal substrate layers, multilayer. The metal substrate structure is etched under control to an effective depth such that each paddle thus formed has the same shape and depth. Therefore, the method of the present invention can be widely applied to the general mass production processes to effectively solve the problems in the prior arts due to depth differences, such offset, position mismatch and peeling off in the chip support board. | 05-01-2014 |
20140115889 | METHOD OF MANUFACTURING A LAMINATE CIRCUIT BOARD - A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 μm. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem. | 05-01-2014 |
20140116755 | LAMINATE CIRCUIT BOARD STRUCTURE - A laminate circuit board structure which includes a first circuit metal layer, a first insulation layer, at least one second circuit metal layer, at least one second insulation layer and a support frame is disclosed. The total thickness of the laminate circuit board structure is less than 150 μm. The support frame provided at the outer edge of the co-plane surface formed by the first circuit metal layer and the first insulation layer does not cover the first circuit metal layer, and is formed of at least one metal material. The support frame provides physical support for the entire board structure without influence on the circuit connection so as to prevent the laminate circuit board structure from warping. | 05-01-2014 |
20140116757 | CHIP SUPPORT BOARD STRUCTURE - A chip support board structure which includes at least a metal substrate, a block layer, a paddle, an insulation layer, a circuit layer and a solder resist is disclosed. The circuit layer connects with the paddle. The material of the block layer is different from that of the metal substrate and the block layer is provided between the metal substrate and the paddle such that the shape and the depth of the paddle is maintained constant and the problem of different depth and easily peeling off is avoided, thereby improving the yield rate of the chip support board. | 05-01-2014 |
20140290057 | METHOD OF MANUFACTURING A STACKED MULTILAYER STRUCTURE - Disclosed is a method of manufacturing a stacked multilayer structure, including the steps of forming a first circuit layer with bumps on a substrate, punching an aluminum plate to form recesses corresponding to the bumps, forming openings in a plastic film including a glass fiber layer corresponding to the bumps, pressing the aluminum plate, the plastic film and the substrate, removing the aluminum plate, polishing to level the resulting surface, forming a second circuit layer connected to the first circuit layer, and finally removing the substrate to form the stacked multilayer structure. Because the glass fiber layer in the plastic film is not exposed after polishing, the thickness of the dielectric layer is uniform and the reliability of the circuit layer is improved so as to increase the yield. | 10-02-2014 |
20140290983 | STACKED MULTILAYER STRUCTURE - Disclosed is a stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed. The adhesion between plastic film and the second circuit layer is greatly improved because the glass fiber layer of the plastic film filling up the space among the bumps is not deformed and exposed outwards. Therefore, the yield and reliability of the stacked multilayer structure is increased. | 10-02-2014 |
20140291853 | PACKAGE STRUCTURE OF A CHIP AND A SUBSTRATE - A package structure includes a thin chip substrate, a stabilizing material layer, a chip and a filling material. A first circuit metal layer of the substrate is inlaid into a dielectric layer and a co-plane is defined by the first circuit metal layer and the dielectric layer and is exposed from the dielectric layer. The bonding pads of the substrate are on the co-plane, have a height higher than the co-plane and connected to the first circuit metal layer. The stabilizing material layer is provided on two sides of the co-plane to define a receiving space for accommodating the chip. The filling material is injected into the receiving space to fasten the pins of the chip securely with bonding pads. Since no plastic molding is required, a total thickness of the package structure and the cost is reduced. The stabilizing material layer prevents the substrate from warping and distortion. | 10-02-2014 |
20140295623 | METHOD OF PACKAGING A CHIP AND A SUBSTRATE - Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 μm, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 μm; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 μm. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure. | 10-02-2014 |