Patent application number | Description | Published |
20080247245 | WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS - Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal. | 10-09-2008 |
20110304370 | PROGRAMMABLE CONTROL CLOCK CIRCUIT INCLUDING SCAN MODE - A programmable clock control circuit includes a base block configured to control operation of the programmable clock control circuit and a chop block configured to control the width of an output clock signal of the programmable clock control circuit. The circuit also includes a pulse width variation block providing a pulse width variation output to the base block, the base block output being variable to provide at least three different output pulse widths. The circuit also includes a launch clock delay block coupled to delay the output of the base block and a scan clock delay block to delay the output pulse and a selector that causes either the scan clock delay block or the launch clock delay block to be active based on a value of a scan gate signal. | 12-15-2011 |
20110317496 | JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA - A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter. | 12-29-2011 |
20110317499 | SPLIT VOLTAGE LEVEL RESTORE AND EVALUATE CLOCK SIGNALS FOR MEMORY ADDRESS DECODING - A method of implementing voltage level shifting for a memory device includes coupling one or more evaluation clock signals to a memory address decode circuit, the one or more evaluation clock signals operating at a first voltage supply level; and coupling a restore clock signal to the memory address decode circuit, the restore clock signal operating at a second voltage supply level that is higher than the first voltage supply level; wherein one or more outputs of the memory address decode circuit operate at the second voltage supply level. | 12-29-2011 |
20110317505 | INTERNAL BYPASSING OF MEMORY ARRAY DEVICES - An output control circuit for a memory array includes a latched output node precharged to a first logic state prior to both a read and write operation; first logic that couples memory cell data from a memory read path to the output node during the read operation, the first logic controlled by a timing signal; second logic that internally bypasses the memory read path during a write operation by decoupling it from the output node, such that a logical derivative of write data written to the memory array is also coupled to the output node, the second logic also controlled by the timing signal; and wherein a transition of the output node from the first logic state to a second logic state during the write operation occurs within a time range as that of the same transition during the read operation. | 12-29-2011 |
20110320851 | PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT - A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node. | 12-29-2011 |
20140078833 | INCREASING MEMORY OPERATING FREQUENCY - A memory apparatus includes a plurality of memory arrays, each memory array including a plurality of memory cells. The apparatus includes a plurality of global bit lines and each one of the global bit lines is connected to a plurality of local bit lines, which are in turn connected to a plurality of memory cells. The apparatus includes a plurality of global bit line (GBL) latches and each GBL latch is located along a separate global bit line to latch a signal along the respective global bit line. The apparatus further includes a plurality of solar bit lines configured to connect the global bit lines to an output latch via a plurality of logic gates. | 03-20-2014 |
20140078835 | HIGH FREQUENCY MEMORY - Embodiments of the disclosure include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation. | 03-20-2014 |
20140082390 | CACHE ARRAY WITH REDUCED POWER CONSUMPTION - Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched. | 03-20-2014 |
20150019890 | CACHE ARRAY WITH REDUCED POWER CONSUMPTION - Embodiments of the disclosure include a cache array having a plurality of cache sets grouped into a plurality of subsets. The cache array also includes a read line configured to receive a read signal for the cache array and a set selection line configured to receive a set selection signal. The set selection signal indicates that the read signal corresponds to one of the plurality subsets of the cache array. The read line and the set selection line are operatively coupled to the plurality of cache sets and based on the set selection signal the subset that corresponds to the set selection signal is switched. | 01-15-2015 |
20150302902 | WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH - A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation. | 10-22-2015 |
20150302908 | WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH - A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation. | 10-22-2015 |
Patent application number | Description | Published |
20080282770 | MEMS emissions sensor system for a turbine engine - Aspects of the invention are directed to the use of microelectromechanical systems (MEMS) based emissions sensors in a turbine engine system to measure one or more emissions values associated with a gas flow in the system. The emissions value can be, for example, the temperature of a gas flow and/or the amount of a particular compound, such as carbon monoxide, in the gas flow. Due to their small size, a plurality of MEMS emissions sensors can readily be incorporated at various locations in a turbine engine system. For example, the MEMS emissions sensors can be operatively positioned in an exhaust stack, downstream of the last row of blades in the turbine section, or in the leading edge of a turbine vane. The MEMS sensors can be operatively connected to a data acquisition system, which can statistically analyze the emissions values measured by the MEMS sensors. | 11-20-2008 |
20120078579 | SELF VALIDATING GAS TURBINE ENGINE FLAME DETECTION SYSTEM USING DUEL OPTICAL VERIFICATION - A self validating flame detection system ( | 03-29-2012 |
20120150413 | GAS TURBINE ENGINE CONTROL USING ACOUSTIC PYROMETRY - A method and apparatus for operating a gas turbine engine including determining a temperature of a working gas at a predetermined axial location within the engine. Acoustic signals are transmitted from a plurality of acoustic transmitters and are received at a plurality of acoustic receivers. Each acoustic signal defines a distinct line-of-sound path from one of the acoustic transmitters to an acoustic receiver corresponding to the line-of-sound path. A time-of-flight is determined for each of the signals traveling along the line-of-sound paths, and the time-of-flight for each of the signals is processed to determine a temperature in a region of the predetermined axial location. | 06-14-2012 |
Patent application number | Description | Published |
20100274131 | Balance Body Ultrasound System - The present invention relates to a hand held ultrasound system having a balance body, a transducer assembly connected to said balance body via a communication means and a plurality of control elements arranged in an ergonomic fashion on said balance body, such that a user may hold said system and operate at least one of said control elements with the same hand. In particular a medical ultrasound system comprising a balance body incorporating system electronics, a power supply and a user interface wherein the user interface comprises a D-controller and a touch screen and a transducer assembly attached to the balanced body by a cable. The present invention relates to a hand held ultrasound system having a balance body, a transducer assembly connected to said balance body via a communication means and a plurality of control elements arranged in an ergonomic fashion on said balance body, such that a user may hold said system and operate at least one of said control elements with the same hand. In particular a medical ultrasound system comprising a balance body incorporating system electronics, a power supply and a user interface wherein the user interface comprises a D-controller and a touch screen and a transducer assembly attached to the balanced body by a cable. | 10-28-2010 |
20120289829 | BALANCE BODY ULTRASOUND SYSTEM - A hand held ultrasound system includes a balance body incorporating system electronics and a transducer assembly connected to the balance body. The hand held ultrasound system also includes control elements that are arranged in an ergonomic fashion on the balance body so that a user can hold the system and operate at least one of the control elements with the same hand. The system may also include a user interface that comprises a D-controller and a touch screen. | 11-15-2012 |
20130245449 | BALANCE BODY ULTRASOUND SYSTEM - The present invention relates to a hand held ultrasound system having a balance body, a transducer assembly connected to said balance body via a communication means and a plurality of control elements arranged in an ergonomic fashion on said balance body, such that a user may hold said system and operate at least one of said control elements with the same hand. In particular a medical ultrasound system comprising a balance body incorporating system electronics, a power supply and a user interface wherein the user interface comprises a D-controller and a touch screen and a transducer assembly attached to the balanced body by a cable. The present invention relates to a hand held ultrasound system having a balance body, a transducer assembly connected to said balance body via a communication means and a plurality of control elements arranged in an ergonomic fashion on said balance body, such that a user may hold said system and operate at least one of said control elements with the same hand. In particular a medical ultrasound system comprising a balance body incorporating system electronics, a power supply and a user interface wherein the user interface comprises a D-controller and a touch screen and a transducer assembly attached to the balanced body by a cable. | 09-19-2013 |
20130331694 | BALANCE BODY ULTRASOUND SYSTEM - The present invention relates to a hand held ultrasound system having a balance body, a transducer assembly connected to said balance body via a communication means and a plurality of control elements arranged in an ergonomic fashion on said balance body, such that a user may hold said system and operate at least one of said control elements with the same hand. In particular a medical ultrasound system comprising a balance body incorporating system electronics, a power supply and a user interface wherein the user interface comprises a D-controller and a touch screen and a transducer assembly attached to the balanced body by a cable. | 12-12-2013 |