38th week of 2013 patent applcation highlights part 24 |
Patent application number | Title | Published |
20130241585 | INVERTER TEST APPARATUS - There is provided an inverter test apparatus for testing an inverter interconnected with an alternating-current power system, the apparatus including an alternating-current power output unit configured to output alternating-current power, and an alternating-current power controller configured to control the alternating-current power output from the alternating-current power output unit to simulate an alternating-current load of the inverter. | 2013-09-19 |
20130241586 | INDUSTRIAL AUTOMATIC-DIAGNOSTIC DEVICE - An industrial automatic-diagnostic device connected to an FA system in which a plurality of FA devices are connected to each other, the industrial automatic-diagnostic device includes: an engineering tool; and a display unit. Based on interface connection information and device configuration information of a corresponding FA device held by each of the FA devices, the engineering tool creates overall configuration information of the FA system and displays an overall configuration of the FA system on the display unit based on the overall configuration information. When an abnormality occurs in the FA device, diagnosis information about an abnormal part self-diagnosed by the FA device and abnormality contents with respect to the abnormality occurred in a corresponding abnormal part is obtained. Based on the obtained diagnosis information, occurrence of an abnormality is displayed in an abnormal part in an overall configuration of the FA system displayed on the display unit. | 2013-09-19 |
20130241587 | WAFER STAGE - A wafer stage and a method of supporting a wafer for inspection. the wafer stage comprises a platform for supporting a wafer such that a backside of the wafer is suspended above a cavity of the platform; and a support structure disposed substantially within the cavity for supporting a portion of the wafer; wherein the wafer stage is adapted for relative movement of the platform with respect to the support structure for alignment of the wafer with respect to a probe. | 2013-09-19 |
20130241588 | WAFER INSPECTION APPARATUS - An inspection chamber | 2013-09-19 |
20130241589 | WIRING BASE PLATE AND METHOD FOR MANUFACTURING THE SAME - In a method for manufacturing a circuit board, as a photomask adapted to form an etching mask for selective removal of a seed layer covering a conductive portion exposed on an insulating film, a photomask whose opening area has an outline having two sides along two straight lines approaching to each other as the two straight lines extend from a center portion of the opening area in an extending direction of a wiring path is used. | 2013-09-19 |
20130241590 | CONDUCTIVE FILM STRUCTURE AND CONDUCTIVE FILM TYPE PROBE DEVICE FOR ICS - A method for forming a conductive film structure is provided, which includes: providing an insulating substrate having a surface; forming a plurality of trenches in the surface of the insulating substrate, wherein the trenches are extended substantially parallel to each other; disposing the insulating substrate into a plating solution and plating conducting layers within the trenches to form a plurality of micro-wires; and stacking a plurality of the insulating substrates or winding or folding the insulating substrate along an axis substantially parallel to an extended direction of the micro-wires to form a conducting lump. | 2013-09-19 |
20130241591 | Apparatus and Method for Screening Electrolytic Capacitors - A method for screening electrolytic capacitors places a capacitor in series with a resistor, applying a test voltage and following the charge curve for the capacitor. A high voltage drop across the capacitor indicates high reliability and a low voltage drop is used to reject the piece. The leakage current is not adversely affected during the test. | 2013-09-19 |
20130241592 | SERVER WITH CURRENT MONITORING SYSTEM - A current monitoring system for monitoring at least one current terminal of a motherboard includes at least one current monitoring unit and an indication device connected to the at least one current monitoring unit. Each current monitoring unit determines whether a current output from a corresponding current terminal is abnormal. The indication device encodes and displays a determination of the current monitoring unit and alarms according to the determination. | 2013-09-19 |
20130241593 | INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES - Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool. | 2013-09-19 |
20130241594 | SCAN FLIP-FLOP CIRCUITS AND SCAN TEST CIRCUITS INCLUDING THE SAME - A scan flip-flop circuit includes an input unit and an output unit. The data output unit is configured to provide a data output terminal with a data output signal in response to a data input signal and a first control signal in a first operation mode, and the data output unit is configured to prohibit the data output terminal from being provided with a power supply voltage and a ground voltage applied to the scan flip-flop circuit in response to the data input signal and the first control signal in a second operation mode. The scan output unit is configured to provide a scan output terminal with a scan output signal in response to a scan input signal and a second control signal in the second operation mode. | 2013-09-19 |
20130241595 | Data-Driven Integrated Circuit Architecture - The exemplary embodiments provide a reconfigurable integrated circuit architecture comprising: a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts; a plurality of input queues; a plurality of output queues; one or more configuration and control registers to store, for each context of the plurality of contexts, a plurality of configuration bits, a run status bit, and a plurality of bits designating at least one data input queue and at least one data output queue; and an element controller coupled to the configurable circuit element and to the one or more configuration and control registers, the element controller to allow loading of a context configuration and execution of a data operation upon the arrival of input data in the context-designated data input queue when the context run status is enabled and the context-designated data output queue has a status to accept output data. | 2013-09-19 |
20130241596 | PROGRAMMABLE LOGIC DEVICE - One embodiment provides a programmable logic device in which a logic switch includes: a first memory having a first terminal connected to a first wire, a second terminal connected to a second wire, and a third terminal connected to a third wire; a second memory having a fourth terminal connected to the first wire, a fifth terminal connected to a fourth wire, and a sixth terminal connected to a fifth wire; and a pass transistor having a gate connected to the first terminal, and a source and a drain respectively connected to a sixth wire and a seventh wire. A source or drain of a first select gate transistor is connected the sixth wire, and a source or drain of a second select gate transistor is connected to the seventh wire. | 2013-09-19 |
20130241597 | INTEGRATED CIRCUIT WITH TIMING AWARE CLOCK-TREE AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT - An integrated circuit includes a clock-tree with a plurality of clock buffers, a plurality of clocked storage elements, and a plurality of logic circuits. Each clocked storage element has a clock input terminal connected to one of the plurality of clock buffers and a weight. Each of the logic circuits is associated with two of the plurality of clocked storage elements and is characterized as having a logic depth. The weight of each clocked storage element is equal to a sum of an inverse of a logic depth of each of the plurality of logic circuits associated therewith. A first clocked storage element which has a highest weight and is adjacent to and interacts with a second clocked storage element via one of the plurality of logic circuits. A first clock buffer provides a common clock signal to the first and second clocked storage elements. | 2013-09-19 |
20130241598 | FREQUENCY DIFFERENCE CALCULATION CIRCUIT, A SATELLITE SIGNAL RECEIVING APPARATUS AND FREQUENCY DIFFERENCE CALCULATION METHOD - In a frequency difference calculation circuit, a first frequency difference calculation section calculates a difference between the first input frequency and an oscillation frequency of the non-integer multiple oscillation section of which an oscillation frequency is a non-integer multiple of the first input frequency. Meanwhile, a second frequency difference calculation section calculates a difference between a second input frequency in which a difference between frequency having an integer multiple of the first input frequency and the second input frequency being within a predetermined error range, and the oscillation frequency of the non-integer multiple oscillation section and an addition section calculates a difference between the first input frequency and the second input frequency adding a calculation result of the first calculation section and a calculation result of the second calculation section. | 2013-09-19 |
20130241599 | COMPARATOR CIRCUIT HAVING A CALIBRATION CIRCUIT - A comparator has a first terminal, a second terminal, and an output terminal. A selection circuit is coupled to the first terminal. A calibration circuit is coupled to the output terminal and the second terminal. The comparator is configured to operate in a first mode when the selection circuit provides a first input signal to the first terminal and the calibration circuit provides a second input signal to the second terminal. The comparator is configured to operate in a second mode when the selection circuit provides a first calibration signal to the first terminal and the calibration circuit provides a second calibration signal to the second terminal based on an output signal at the output terminal. The comparator generates the output signal based on the first calibration signal and the second calibration signal. | 2013-09-19 |
20130241600 | RANDOM SPREAD SPECTRUM MODULATION - Representative implementations of devices and techniques provide a spread spectrum clocking signal. In a frequency synthesizer, a sequence of values may be generated and used to modulate a frequency of an input signal to the frequency synthesizer. | 2013-09-19 |
20130241601 | High-side driver circuit - The present invention provides a high-side driver circuit including a power transistor, the first transistor, the second transistor, the second capacitor, the second diode, a start-up circuit. The start-up circuit is coupled between a resistor and the second capacitor to complete a gate driving circuit. And, the aforementioned resistor can either be the gate resistance of the power transistor or an external resistor. The design of start-up circuit enables the functionality of the bootstrap capacitor of being charged to a designate voltage level. Thus, the depletion-mode transistor can be controlled to turn on/off without a floating voltage source or a negative voltage source. | 2013-09-19 |
20130241602 | TRANSMISSION CIRCUIT - A transmission circuit includes a first drive part capable of switching to one of an on state that is driven by current and an off state, i.e., a high impedance state in accordance the value of a first input signal; and a first termination resistor part connected in series with the first drive part. The resistance values of the first drive part are switched in accordance with the state of the first drive part. | 2013-09-19 |
20130241603 | Current limit circuit apparatus - The present invention provides a current limit circuit apparatus, coupled with the gate of a GaN transistor. The current limit circuit comprises a diode, a first transistor, a second transistor, a first resistor, a second resistor, a third resistor and a fourth resistor. The source and the drain of the first transistor couple with the diode. The source of the second transistor couples with the gate of the first transistor. The source of the first transistor couples with the first transistor. The source of the second transistor couples with the second resistor. The third resistor couples with the fourth resistor and the gate of the first transistor. The first transistor turned off and the gate current is limited. When the current of the gate of the GaN transistor exceeds the predetermined value, the breakdown voltage is increased by limiting the gate current. | 2013-09-19 |
20130241604 | POWER MODULE INCLUDING LEAKAGE CURRENT PROTECTION CIRCUIT - A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator. | 2013-09-19 |
20130241605 | Method for compensation of manufacturing tolerances of at least one electric parameter of a power transistor and associated system - The system ( | 2013-09-19 |
20130241606 | INTEGRATED CIRCUIT AND A METHOD OF POWER MANAGEMENT OF AN INTEGRATED CIRCUIT - An integrated circuit includes a plurality of power gating elements for controlling power applied to a first module which is in a powered off state, while a second module is in a powered on state, the second module being coupled to receive at least one signal from the first module when the first module is powered on. A a synchronization controller is provided for controlling the power gating elements to ramp up the power gated to the first module in order to power it up and, for a time while the power gated to the first module is below a first level, reducing the power gated to the second module, and for a time when the power gated to the first module is above the first level, increasing the power gated to the second module. | 2013-09-19 |
20130241607 | PHASE LOCKED LOOP AND PHASE COMPARISON METHOD - In a phase locked loop, a first frequency divider divides the frequency of an input signal. A low-pass filter receives a frequency-divided signal output from the first frequency divider and having an average phase difference calculated by a calculation unit, cuts off high-frequency components of the received signal, and outputs a resultant signal. A voltage controlled oscillator varies the frequency of a signal to be output based on the signal output from the low-pass filter. A second frequency divider divides the frequency of the signal output from the voltage controlled oscillator. The calculation unit calculates a phase difference between signals individually output from the first frequency divider and the second frequency divider for each phase in one cycle of the signal output from the first frequency divider, and calculates an average phase difference based on the calculated phase differences. | 2013-09-19 |
20130241608 | HIGH SPEED, WIDE FREQUENCY-RANGE, DIGITAL PHASE MIXER AND METHODS OF OPERATION - The present disclosure is directed to a unit phase mixer in combination with an input buffer. The unit phase mixer has a pull-up path for pulling an output terminal up to a first voltage. The pull-up path has a first transistor responsive to a first enable signal and a series connected second transistor responsive to a first clock signal. The unit phase mixer has a pull-down path for pulling the output terminal down to a second voltage. The pull-down path has a third transistor responsive to a second clock signal and a series connected fourth transistor responsive to a second enable signal. The input buffer skews the first and second clock signals by different amounts to enable a break-before-make method of operation so that the first voltage is not connected to the second voltage. The unit phase mixer can be used as a building block in more complex mixers which may include the ability to weight the input clocks as well as providing feed-forward paths for certain of the signals. Because of the rules governing abstract, this abstract should not be used to construe the claims. | 2013-09-19 |
20130241609 | SEMICONDUCTOR DEVICE - A semiconductor device for ignition performing a current control function and a self shut down function can include a pulse generating circuit, a switching circuit, and a current source circuit, the three circuits together generating a pulse current that discharges a capacitor in the self shut down process. This construction can serve to suppress oscillation of a collector current Ic of the output stage IGBT in the operating processes of the current control circuit and the self shut down circuit, thus preventing or minimizing the likelihood of the ignition plug from erroneous ignition. In addition, the discharge of the capacitor in a pulsed mode can allow for down-sizing of the capacitor, which can contribute to minimization of the semiconductor device. | 2013-09-19 |
20130241610 | PLL CIRCUIT, METHOD OF CONTROLLING PLL CIRCUIT, AND DIGITAL CIRCUIT - A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value. | 2013-09-19 |
20130241611 | FREQUENCY GENERATOR FOR RADIOFREQUENCY EQUIPMENT AND METHOD FOR GENERATING AN OUTPUT SIGNAL - A frequency generator generating an output signal having a predetermined output frequency, including: a local oscillator generating a reference signal having a reference frequency, and a phase-locked loop, the phase-locked loop provided with a controlled oscillator generating the output signal having the output frequency as a function of the signal at its input, and a comparator providing a signal to the controlled oscillator as a function of a phase and/or frequency comparison of a first comparison signal based on an input signal applied to a first input of the phase-locked loop with a second comparison signal based on the output signal, the frequency generator further including at least one harmonic generator generating, from the reference signal, a harmonic signal including a predetermined harmonic of the reference signal, the frequency generator applying the harmonic signal of one of the harmonic generators to the first input of the phase-locked loop. | 2013-09-19 |
20130241612 | APPARATUS AND METHODS FOR ADJUSTING PHASE-LOCKED LOOP GAIN - Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations. | 2013-09-19 |
20130241613 | I/O CIRCUIT WITH PHASE MIXER FOR SLEW RATE CONTROL - An apparatus includes a terminal, a first plurality of driver lines, and a first phase mixer. The driver lines drive the terminal to a first logic state responsive to a first enable signal. The first phase mixer is coupled to a first one of the first plurality of driver lines. The first phase mixer is operable to receive the first enable signal and a first delayed enable signal derived from the first enable signal and generate a first signal on the first driver line having a first configurable delay with respect to the first enable signal by mixing the first enable signal and the first delayed enable signal. | 2013-09-19 |
20130241614 | TWO LEAD ELECTRONIC SWITCH SYSTEM ADAPTED TO REPLACE A MECHANICAL SWITCH SYSTEM - Systems and methods for a two lead electronic switch adapted to replace a mechanical switch are provided. In one embodiment, a method comprises, in an electronic switch having a sensor, an electronic circuit, a first terminal and a second terminal, receiving, by the electronic circuit, from the sensor, a sensed voltage proportional to an amount sensed by the sensor; operating the electronic circuit in a first state when the sensed voltage is greater than or equal to a threshold voltage associated with a threshold pressure sensed by the sensor; operating the electronic circuit in a second state when the sensed voltage is less than the threshold voltage associated with the threshold pressure sensed by the sensor; receiving, across the first terminal and the second terminal, an input voltage used to provide power for the electronic switch; and wherein the first terminal and the second terminal are also used to couple the electronic switch to a device. | 2013-09-19 |
20130241615 | HIGH VOLTAGE SWING DECOMPOSITION METHOD AND APPARATUS - A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit. | 2013-09-19 |
20130241616 | Keeper Circuit And Electronic Device Having The Same - A keeper circuit includes a first latch and a second latch, each of the first latch and the second latch being configured to latch output data determined by input data during an evaluation phase, and the second latch, during a high-impedance phase, being configured to maintain output data of the second latch using output data of the first latch. | 2013-09-19 |
20130241617 | SCAN FLIP-FLOP, METHOD THEREOF AND DEVICES HAVING THE SAME - A scan flip-flop, which performs a normal operation latching a data input and a scan operation latching a scan input, includes a first circuit, a second circuit and a latch. The first circuit determines a voltage of an intermediate node based on a clock signal, one of the data input and the scan input, and data of a latch input node. The second circuit determines the data based on the clock signal, the voltage of the intermediate node and the data input during the normal operation, and determines the data based on the clock signal and the voltage of the intermediate node during the scan operation. The latch latches the data based on the clock signal. | 2013-09-19 |
20130241618 | SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS - The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree. | 2013-09-19 |
20130241619 | POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION - Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response. | 2013-09-19 |
20130241620 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors. The output circuit is configured so as to be able to adjust the value of current which flows through the first termination resistor and the second termination resistor or the value of resistance of the first termination resistor and the second termination resistor. | 2013-09-19 |
20130241621 | System and Apparatus for Driver Circuit for Protection of Gates of GaN FETs - A half-bridge power circuit comprises a first gallium nitride field effect transistor (GaN FET); a first driver coupled to a gate of the first GaN FET; an anode of a capacitor coupled to an output of the driver and a source of the first GaN FET; a diode having a cathode coupled to the cathode of the capacitor; and a bootstrap capacitor clamp (BCC) controller, including: a field effect transistor (FET) coupled to an anode of the diode, and a comparator coupled to a gate of the FET, the comparator configured to receive as inputs: a) a signal representative of an input voltage (VDRV) applied to the FET; b) a ground; c) a boot signal representative of a voltage at the anode of the capacitor (Boot); and d) a signal representative of a voltage at the source of the first GaN FET (SW). | 2013-09-19 |
20130241622 | RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE - A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system. | 2013-09-19 |
20130241623 | LEVEL SHIFT CIRCUIT - A level shift circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a latch-type level shifter, a first current source and a second current source. The first input terminal receives an input signal; the second input terminal receives an inverse signal of the input signal; the first output terminal outputs an output signal; and the second output terminal outputs an inverse signal of the output signal. The latch-type level shifter is connected to the first input terminal, the second input terminal, the first output terminal and the second output terminal. The first current source is connected between a first high voltage input terminal of the latch-type level shifter and a voltage source. The second current source is connected between a second high voltage input terminal of the latch-type level shifter and the voltage source. | 2013-09-19 |
20130241624 | Dual Path Level Shifter - Dual path level shifter methods and devices are described. The described level shifter devices can comprise voltage-to-current and current-to-voltage converters. | 2013-09-19 |
20130241625 | Multiway Lossless Power Combining and Outphasing Incorporating Transmission Lines - A power combining and outphasing system and related techniques for simultaneously providing both wide-bandwidth linear amplification and high average efficiency is described. Providing linear amplification encompasses the ability to dynamically control an RF output power level over a wide range while still operating over a wide frequency bandwidth. The system and techniques described herein also operate to maintain high efficiency across a wide range of output power levels, such that a high average efficiency can be achieved for highly modulated output waveforms. | 2013-09-19 |
20130241626 | INPUT CAPTURE PERIPHERAL WITH GATING LOGIC - A microcontroller has an input capture peripheral, wherein the input capture peripheral is configured to store timer values of an associated timer in a memory and wherein the input capture peripheral has a gating input which controls whether an input capture function is activated. | 2013-09-19 |
20130241627 | POWER SWITCH CIRCUIT - A power switch circuit includes a pulse width modulation (PWM) control circuit having a first frequency control terminal and a second frequency control terminal for outputting predetermined frequency signals, a first switch circuit, a second switch circuit, a first resistor connected between the first frequency control terminal and the first switch circuit, a second resistor connected between the first frequency control terminal and the second switch circuit, a first filtering circuit having a third resistor and a first capacitor, and a second filtering circuit having a fourth resistor and a second capacitor. A first terminal of the first capacitor is connected to the first switch circuit and a second terminal of the first capacitor is grounded via the third resistor. A first terminal of the second capacitor is connected to the second switch circuit and a second terminal of the second capacitor is grounded via the fourth resistor. | 2013-09-19 |
20130241628 | METHODS AND SYSTEMS FOR IMPLEMENTING AN SCR TOPOLOGY IN A HIGH VOLTAGE SWITCHING CIRCUIT - In accordance with an embodiment, a high voltage switching and control circuit for an implantable medical device (IMD) is provided that comprises a high voltage positive (HVP) node configured to receive a positive high voltage signal from a high energy storage source; and a high voltage negative (HVN) node configured to receive a negative high voltage signal from a high energy storage source. First and second output terminals are configured to be connected to electrodes for delivering high voltage energy. First and second Silicon Controlled Rectifiers (SCR) switches are connected to the HVP node, the first and second SCR switches connected to the first and second output terminals respectively, wherein the first and second SCR switches each include a Darlington transistor pair having a first transistor stage joined to a second stage transistor at a common collector node. | 2013-09-19 |
20130241629 | Actuator and Method of Manufacture Thereof - An actuator for controlling the operation of an apparatus comprises a panel ( | 2013-09-19 |
20130241630 | Touch Sensor Driver With Selectable Charge Source - An apparatus may include an internal charge pump within an integrated circuit package, an external pin positioned at an exterior of the integrated circuit package, and a select circuit configured to operate independently from the internal charge pump and located within the integrated circuit package, wherein the select circuit is configurable to selectively couple at least one of the internal charge pump and the external pin to a transmit (TX) sensor electrode. | 2013-09-19 |
20130241631 | OUTPUT STAGE CIRCUIT - An output stage circuit includes: a first transistor, including a first terminal coupled to a first node, a second terminal coupled to an output terminal, a third terminal coupled to an input terminal for receiving an input voltage, and a fourth terminal coupled to a first power terminal for receiving a first voltage; a second transistor, including a first terminal coupled to a second node, a second terminal coupled to the output terminal, a third terminal coupled to the input terminal for receiving the input voltage, and a fourth terminal coupled to ground; and a current source, coupled to the output terminal for providing a constant current. | 2013-09-19 |
20130241632 | BIAS VOLTAGE GENERATION CIRCUIT AND DIFFERENTIAL CIRCUIT - A bias voltage generation circuit includes a first current source connected to a first power source; a first transistor which is diode connected and is connected to the first current source; a second transistor connected between the first transistor and a second power source; a second current source connected to the first power source; a third transistor connected to the second current source; a fourth transistor connected between the third transistor and the second power source; a first output point connected to the first transistor and the third transistor and outputs a first bias voltage; a second output point connected to the fourth transistor and the second current source and outputs a second bias voltage; and a bias voltage adjusting circuit which adjusts the first bias voltage in accordance with a control input. | 2013-09-19 |
20130241633 | Method and Apparatus for Signal Processing - Signal processing method and apparatus having a first filter storage portion in which first filters are correlatively stored; a second filter storage portion in which second filters are correlatively stored; a first filter selection portion for selecting a first filter based on the power spectrum of the input image; a second filter selection portion for selecting a second filter based on the S/N of the input image; a third filter creation portion for creating a third filter by summing up the first and second filters; and a convolutional processing portion for convolving the input image using the created third filter. | 2013-09-19 |
20130241634 | RF CALIBRATION THROUGH-CHIP INDUCTIVE COUPLING - An integrated circuit includes a first chip and a second chip coupled to the first chip in a vertical stack. The first chip includes a radio frequency circuit and a first coil electrically coupled to the radio frequency circuit. The second chip includes a calibration circuit and a second coil electrically coupled to the calibration circuit. The calibration circuit is configured to calibrate the radio frequency circuit disposed on the first chip through inductive coupling between the first and second coils. | 2013-09-19 |
20130241635 | Capacitor Amplifying Circuit and Operating Method Thereof - A capacitor amplifying circuit and an operating method thereof are disclosed. The capacitor amplifying circuit includes a first current source, a second current source, a current mirror unit, and an output capacitor. There is a proportion relationship between a first current of the first current source and a second current of the second current source. The current mirror unit is coupled between the first current source and the second current source. The current mirror unit includes N stages of current mirror circuit in series, wherein N is larger than or equal to 1. Each of the N stages of current mirror circuit has a proportional constant respectively. Two terminals of the output capacitor are coupled to the current mirror unit and a ground terminal respectively. The equivalent capacitance magnification of the output capacitor is related to the proportional constants based on the proportion relationship. | 2013-09-19 |
20130241636 | Magnetic Logic Units Configured as an Amplifier - An apparatus includes a circuit and a field line. The circuit includes a magnetic tunnel junction including a storage layer and a sense layer. The field line is configured to generate a magnetic field based on an input signal, where the magnetic tunnel junction is configured such that a magnetization direction of the sense layer and a resistance of the magnetic tunnel junction vary based on the magnetic field. The circuit is configured to amplify the input signal to generate an output signal that varies in response to the resistance of the magnetic tunnel junction. | 2013-09-19 |
20130241637 | Auto-Zeroed Amplifier with Low Input Leakage - An amplifier having an inverting input and a non-inverting input; a capacitor coupled to inverting input of the amplifier; an input voltage conveyance control circuit, having a first switch and a second switch, the first switch coupled to the capacitor, and the second switch coupled to the non-inverting input of the amplifier; a reference voltage conveyance control circuit having a third switch and a fourth switch, a shared node coupled between third switch and fourth switch, the fourth switch coupled to the non-inverting input of the amplifier; a fifth switch coupled to an output of the amplifier; a leakage control circuit having a sixth switch and seventh switch, the sixth switch coupled between the inverting amplifier input and the fifth switch, the seventh switch coupled to the sixth switch and the capacitor; and a first resistor coupled from the output of the amplifier to the first switch. | 2013-09-19 |
20130241638 | SIGNAL AMPLIFIER CIRCUIT FOR USB PORT - A signal amplifier circuit for USB port includes a USB controller, an amplifier circuit, a USB port and a signal regulator circuit. The USB controller includes a super speed transmitter differential pair and a super speed receiver differential pair. The amplifier circuit includes two first input terminals, two second input terminals, two first output terminals, and two second output terminals. The USB port includes two first differential signal receiving terminals and two first differential signal transmitting terminals. The super speed transmitter differential pair and the super speed receiver differential pair are electrically connected to the first input terminals and the second output terminals. The first output terminals and the second input terminals are electrically connected to the first differential signal receiving terminals and the first differential signal transmitting terminals. The signal regulator circuit regulates amplitude and jitter of differential signals amplified by the amplifier circuit. | 2013-09-19 |
20130241639 | IMPEDANCE SPREADING WIDEBAND DOHERTY AMPLIFIER CIRCUIT WITH PEAKING IMPEDANCE ABSORPTION - A wideband Doherty amplifier circuit includes a main amplifier configured to operate in a linear mode, a peaking amplifier configured to operate in a non-linear mode and a Doherty combiner directly connected to an output of each amplifier so that no output match devices are in the path between the amplifier outputs and the Doherty combiner. The Doherty combiner is configured to present the same load impedance to each amplifier when both amplifiers are conducting and present a modulated load impedance to the main amplifier when the peaking amplifier is non-conducting so that a variation in the VSWR seen by the main amplifier is less than 5% over a plurality of frequency bands and/or so that the peaking amplifier has an off-state impedance spreading of 20 degrees or less over the plurality of frequency bands. | 2013-09-19 |
20130241640 | RECONFIGURABLE INPUT POWER DISTRIBUTION DOHERTY AMPLIFIER WITH IMPROVED EFFICIENCY - A novel Doherty amplifier with improved efficiency is disclosed. In an exemplary embodiment an apparatus includes a phase shifter configured to generate a phase shifted first millimeter (MM) wave signal based on a selected phase shift, and a hybrid plus coupler comprising output terminals and configured to adjust output power levels at the output terminals based on combinations of the phase shifted first MM wave signal and a second MM wave signal. | 2013-09-19 |
20130241641 | SIGNAL AMPLIFIER CIRCUIT FOR USB PORT - A signal amplifier circuit for USB port includes a USB controller, an amplifier circuit and a USB port. The USB controller includes a super speed transmitter differential pair and a super speed receiver differential pair. The amplifier circuit includes two first input terminals, two second input terminals, two first output terminals, and two second output terminals. The USB port includes two first differential signal receiving terminals and two first differential signal transmitting terminals. The super speed transmitter differential pair and the super speed receiver differential pair are electrically connected to the first input terminals and the second output terminals. The first output terminals and the second input terminals are electrically connected to the first differential signal receiving terminals and the first differential signal transmitting terminals. The amplifier circuit amplifies differential signals transmitted between the USB controller and the USB port. | 2013-09-19 |
20130241642 | AMPLIFYING APPARATUS AND CONTROL METHOD - An amplifying apparatus includes an amplifying unit that includes multiple amplifiers coupled in parallel; a measuring unit that measures in a predetermined period, frequency distribution of any one among instantaneous power and instantaneous voltage of a signal amplified by the amplifying unit; a calculating unit that calculates for multiple candidate values of a predetermined parameter of the amplifying unit, efficiency of amplification that is performed by the amplifying unit and based on the frequency distribution; and a controller that controls the predetermined parameter, based on the efficiency calculated for the candidate values by the calculating unit. | 2013-09-19 |
20130241643 | SYSTEMS AND METHODS FOR ADAPTIVE EQUALIZATION CONTROL FOR HIGH-SPEED WIRELINE COMMUNICATIONS - Methods and systems for conditioning wireline communications to remove intersymbol interference are provided that used adaptive equalization. The method and systems include using a digital finite state machine to control two feedback loops that adjust the gain and power of the input signal relative to a supplied reference. The eye height of the input signal is conditioned by a gain feedback loop so that signal equalization can be performed in a known state. The digital finite state machine allows the loops to be flexibly run in sequence or concurrently. The adaptation functions can be shut off when adequate signal equalization has been achieve, thus saving power. | 2013-09-19 |
20130241644 | Dynamic Power Control Method and Circuit thereof - The present invention discloses a dynamic power control method utilized in an amplifier. The dynamic power control method includes detecting an absolute difference between a positive supply voltage of the amplifier and an output voltage of the amplifier, to acquire a positive voltage difference; detecting an absolute difference between a negative supply voltage of the amplifier and the output voltage of the amplifier, to acquire a negative voltage difference; and adjusting the positive supply voltage and the negative supply voltage according to the positive voltage difference, the negative voltage difference and a threshold. | 2013-09-19 |
20130241645 | MULTI-LAYER MEMORY STRUCTURE FOR BEHAVIORAL MODELING IN A PRE-DISTORTER - A method and system for modeling distortion of a non-linear electronic device are disclosed. According to one aspect, the invention provides a layered memory structure that includes a plurality of memory structure layers. Each memory structure layer has an input to receive an input signal and has a memory function. Each memory function has at least one delay element that provides a pre-determined delay of the input signal of the memory structure layer. The pre-determined delay is different for each of at least two memory structure layers and is based at least in part on an evaluation period corresponding to the memory structure layer. | 2013-09-19 |
20130241646 | Dual Loop Adaptation Digital Predistortion Architecture for Power Amplifiers - One or more embodiments of a method and apparatus taught herein provide a predistortion system to compensate for the non-linearity of a power amplifier. The system includes an outer predistorter, an inner predistorter, and a first adaptation circuit. The predistorter predistorts an input signal to generate a first output signal, and uses a first memory model that models power amplifier memory effects within a first range of time constants. The inner predistorter predistorts the first output signal to generate a second output signal, and uses a second memory model that models power amplifier memory effects within a second range of time constants that is greater than the first range of time constants. The second output signal is provided as an input to the power amplifier, and the first adaptation circuit adapts the outer predistorter responsive to feedback from the power amplifier. | 2013-09-19 |
20130241647 | Distortion Correction in Class-D Amplifiers - The present application describes an apparatus and method for reducing distortion in a class-D amplifier. The power output section of the amplifier is driven by an adjusted PWM signal, rather than by a PWM signal created directly from the input analog signal. A reference output, designed to closely track the input analog signal, is compared to the amplifier output. The resulting difference is an error signal which is inverted and summed with a second analog signal corresponding to the directly created PWM signal and changes the timing of the voltage transitions of the second analog signal. The changed voltage transitions are used to create the adjusted PWM signal. The inversion of the error signal causes negative feedback which results in the adjustment of the PWM signal being in a direction which reduces the error signal and thus the distortion of the amplifier. | 2013-09-19 |
20130241648 | DRIVING CIRCUIT, OPERATIONAL AMPLIFIER, AND DATA TRANSMITTING METHOD THEREOF - A data transmitting method is provided, wherein an operational amplifier is coupled with a channel and includes a positive switch, a negative switch, and a coupling end; the positive switch includes a positive control unit and a positive switch unit; the negative switch includes a negative control unit and a negative switch unit. The data transmitting method includes: transmitting an analog data to a first node and a second node from the coupling end; and by the positive control unit and the negative control unit, respectively according to a positive control signal and a negative control signal, selectively activating or deactivating the positive switch unit and the negative switch unit to control transmission of the analog data to an output end, wherein the output end is coupled between the negative switch unit and the positive switch unit. | 2013-09-19 |
20130241649 | Regulator with Low Dropout Voltage and Improved Stability - The regulator with a low dropout voltage comprises an error amplifier comprising a differential pair of input transistors and a circuit with folded cascode structure connected to the output of the said differential pair, an output stage connected to the output node of the error amplifier, and a Miller compensation capacitor connected between the output stage and the cascode node on the output side (XP) of the cascode circuit; the error amplifier furthermore comprises at least one inverting amplifier module in a feedback loop between the said cascode node and the gate of the cascode transistor of the cascode circuit connected between the said cascode node and the said output node. | 2013-09-19 |
20130241650 | MULTI-STAGE AMPLIFIER - There is disclosed a power supply stage, and a corresponding method, comprising: a plurality of amplifiers for amplifying an input signal, each amplifier receiving a power supply voltage; a common selection means for selecting one of a plurality of power supply voltages in dependence on a reference signal representing a desired power supply voltage; and a plurality of adjusting means, corresponding to the plurality of amplifiers, adapted to generate an adjusted selected power supply voltage for a respective amplifier tracking the reference signal in dependence on the one selected power supply voltage and the reference signal. | 2013-09-19 |
20130241651 | AMPLIFIERS AND RELATED RECEIVER SYSTEMS - Apparatus are provided for amplifier circuits and related receiver systems. An amplifier circuit includes a first common-source amplification stage and a second common-source amplification stage. The input of the second common-source amplification stage is coupled to the output of the first common-source amplification stage such that the first common-source amplification stage generates a first amplified signal, and the second common-source amplification stage generates a second amplified signal based on the first amplified signal. The first common-source amplification stage is coupled to a first node and the second common-source amplification stage is coupled to a second node, wherein the common-source amplification stages are configured such that a current between the first node and the second node flows in series through the common-source amplification stages. | 2013-09-19 |
20130241652 | UTILIZING A SENSE AMPLIFIER TO SELECT A SUITABLE CIRCUIT - Embodiments of the present invention provide an approach for utilizing a sense amplifier to select a suitable circuit, wherein a suitable circuit generates a voltage that is greater than or equal to a configurable reference voltage. An amplifier gain selector selects a voltage gain of a sense amplifier having input terminals, auxiliary inputs, an output, an array of resistive loads, and the amplifier gain selector. Auxiliary inputs are utilized to nullify direct current (DC) offset voltage of the sense amplifier. Combinatorial logic circuitry connects the input terminals of the sense amplifier to output terminals of a circuit that is within a group of circuits. A comparator circuit determines if the circuit generates a voltage greater than or equal to a configurable reference voltage, based on the output of the sense amplifier. | 2013-09-19 |
20130241653 | INSTRUMENTATION INPUT SYSTEMS - A variable gain amplifier has an attenuator having an input and a series of tap points, and a series of low-inertia switches, each switch coupled to a corresponding one of the tap points to steer outputs from the attenuator to an output terminal. An amplifier has an input cell, a load coupled to an output of the input cell, a buffer having an input coupled to the load, a feedback network coupled between an output of the buffer and the input cell, and a variable filter cell coupled to the input cell. | 2013-09-19 |
20130241654 | GAIN CONTROL SYSTEM - A gain control system may include an input terminal that receives an input signal. The gain control system may include a first transistor having a source connected with the input terminal and a drain connected with an output terminal. The gain control system may include a second transistor having a gate connected with the input terminal and the source of the first transistor. The second transistor may have a drain connected with the output terminal. The second transistor may generate a reduction signal. The output terminal may output an output signal based on the input signal and the reduction signal. | 2013-09-19 |
20130241655 | Linearization Circuit and Related Techniques - Circuits and techniques to linearize the operation of an RF power amplifier are described. A linearizer circuit may include a non-amplification signal path which includes a delay line and an amplification signal path which includes at least one amplifier stage. In some embodiments, the amplification signal path may include an odd number of amplification stages. The linearizer may be used to precondition an input signal of an RF power amplifier in a manner that improves the overall linearity of operation. | 2013-09-19 |
20130241656 | Power Amplification System Using Doherty Amplifier with Linearization Circuit and Related Techniques - A power amplification system includes a linearizer circuit feeding a power amplifier to linearize the operation of the power amplifier. The linearizer circuit may shape the input signal of the power amplifier in a manner that complements the output power versus input power characteristic of the power amplifier. In some embodiments, the linearizer may increase the relative magnitude of higher power portions of the input signal while decreasing the relative magnitude of lower power portions of the input signal to provide an overall increase in the linearity of the power amplification system. The power amplifier may include a Doherty amplifier in some implementations. | 2013-09-19 |
20130241657 | MULTI-MODE DOHERTY POWER AMPLIFIER - The present invention relates to a Doherty power amplifier in which a new operation mode for accomplishing high efficiency at a lower output power level is added to operation of a conventional Doherty power amplifier, thereby achieving high efficiency at various output power levels of the power amplifier. The multi-mode Doherty power amplifier to which a second power mode is added may be reduced in size so as to be integrated into a chip. | 2013-09-19 |
20130241658 | POWER SUPPLY CIRCUIT AND POWER SUPPLY CONTROL METHOD - In a power supply circuit which uses a switching amplifier in combination with a linear amplifier, in order to be capable of correcting errors of operation of the switching amplifier and the linear amplifier, that is to say, in order to cause the switching amplifier and the linear amplifier to operate in coordination in a near-ideal state, the power supply circuit is provided with first amplification unit for delaying an input signal by a predetermined set time and amplifying the input signal, current detection unit for detecting a current value of an output signal of the first amplification unit, predicted signal generation unit for generating a pulse signal on a basis of an output signal of the current detection unit and the input signal, second amplification unit for amplifying the pulse signal and signal output unit for combining current of the output signal of the first amplification unit and current of the output signal of the second amplification unit to output the combined current, wherein the set time is time for reducing an effect of delay times generated at the current detection unit, the predicted signal generation unit and the second amplification unit. | 2013-09-19 |
20130241659 | POWER AMPLIFIER - A power amplifier includes: a first amplifying element amplifying an input signal; a second amplifying element amplifying an output signal of the first amplifying element; a third amplifying element amplifying the input signal; a first switch connected between an output of the first amplifying element and an input of second amplifying element; a second switch connected between an output of the first amplifying element and an output of the third amplifying element; a third switch connected between an output of the first amplifying element and an output of the second amplifying element; a reference voltage generating a circuit generating reference voltage; a bias circuit supplying a bias current, based on the reference voltage, to inputs of the first, second, and third amplifying elements; and a control circuit controlling the first, second and third switches and the reference voltage generating circuit. | 2013-09-19 |
20130241660 | Buck Up Power Converter - Generally, this disclosure provides an apparatus, method and system for DC-DC conversion. The apparatus may include a switch network including a first plurality of switches configured to operate in a Buck mode to generate an output voltage that is less than an input voltage, and a second plurality of switches configured to operate in an Up mode to generate an output voltage that is greater than the input voltage. The apparatus of this example may further include controller circuitry configured to generate control signals to control the conduction state of the first plurality of switches and the second plurality of switches based on a variable reference signal indicative of power demands from a load coupled to the switch network. | 2013-09-19 |
20130241661 | VOLTAGE-CONTROLLED OSCILLATOR MODULE AND METHOD FOR GENERATING OSCILLATOR SIGNALS - A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided. | 2013-09-19 |
20130241662 | INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR - A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up. | 2013-09-19 |
20130241663 | PULSE WIDTH MODULATION SCHEME WITH REDUCED HARMONICS AND SIGNAL IMAGES - A method is provided. An input signal is received, and a noise-shaped signal is generated from the input signal. The noise-shaped signal is formed from a plurality of noise-shaping levels. A pulse stream is generated from the noise-shaped signal over a plurality of periods, where each period has a plurality of frames. The pulse stream also includes a plurality of pulse sets, where each pulse set is associated with at least one of the noise-shaping levels, and, for each pulse set having a total pulse width for its period that is less than its period and greater than zero, each pulse set includes at least one pulse in each frame for its period. | 2013-09-19 |
20130241664 | ADAPTIVE MATCHING NETWORK - A system that incorporates teachings of the present disclosure can include, for example, an apparatus having a matching network adapted to reduce a magnitude of a signal reflection at a port of the matching network. The matching network can have one or more controllable variable reactive elements. A controller can be adapted to determine reflection coefficient information from incident and reflected waves sampled at the port of the matching network, and follow at least one cycle of a coarse tune process for generating one or more control signals to tune one or more reactances of the one or more controllable variable reactive elements. Additional embodiments are disclosed. | 2013-09-19 |
20130241665 | VARIABLE CAPACITOR, IMPEDANCE MATCHING DEVICE, MOBILE TERMINAL THEREOF AND METHOD FOR MATCHING IMPEDANCE - Disclosed is an impedance matching device. Variable devices of the impedance matching device installed in a mobile terminal, such as a portable terminal, are configured to have a MEMS structure. The MEMS structure and other components are integrated as one package, so the manufacturing cost is reduced and the manufacturing efficiency is improved. | 2013-09-19 |
20130241666 | BAND SWITCH WITH SWITCHABLE NOTCH FOR RECEIVE CARRIER AGGREGATION - A band switch with a switchable notch for receive carrier aggregation is disclosed. The band switch has at least one input and an output with at least one series switch coupled between the at least one input and the output. The at least one series switch is adapted to selectively couple the input to the output in response to a first control signal. The band switch also includes at least one shunt switch coupled between the at least one input and a voltage node. The at least one shunt switch is adapted to selectively couple the at least one input to the voltage node in response to a second control signal. In addition, at least one notch filter is selectively coupled to the output in a shunt configuration, wherein the at least one notch filter is configured to attenuate signals within a stop band to attenuate harmonics and distortion. | 2013-09-19 |
20130241667 | DIRECTIONAL COUPLER - A directional coupler includes in a laminate block, a first main line, a first sub-line, a second sub-line, and a second main line sequentially provided in a lamination direction of layers. Further, each of the first main line, the first sub-line, the second sub-line, and the second main line is divided into at least two divided coil conductors. Furthermore, at least two divided ground conductors are provided between the first sub-line and the second sub-line. | 2013-09-19 |
20130241668 | DIRECTIONAL COUPLER - In a directional coupler, even when parasitic inductance exists, an increase in device size can be suppressed while obtaining good isolation characteristics. A transmission line type directional coupler includes a main line and a sub line that is coupled to the main line through electric field coupling and magnetic field coupling. The main line includes a signal input port and a signal output port, and the sub line includes a coupling port and an isolation port. A series capacitor is connected to only one of the signal output port and the coupling port. | 2013-09-19 |
20130241669 | ADJUSTABLE DUPLEXER SYSTEM - A duplexing system may be used with an electronic device. The duplexing system may include a duplexer connected with an antenna. The duplexing system may include a balancing network. The balancing network may be connected with the duplexer, have an adjustable network impedance, and include an active component. The balancing network may be configured to adjust the network impedance to match an antenna impedance of the antenna. | 2013-09-19 |
20130241670 | POWER DISTRIBUTING DUPLEXER SYSTEM - A power distributing duplexer system is provided. In some aspects, the system includes a duplexer configured to couple an antenna to a transmitter and a receiver. The system also includes a balancing network coupled to the duplexer. The balancing network includes a network impedance. The balancing network is configured to adjust the network impedance to match an antenna impedance of the antenna. The balancing network includes a plurality of balancing network modules coupled to the duplexer. Each of the plurality of balancing network modules is configured to receive a portion of an output voltage from the duplexer. | 2013-09-19 |
20130241671 | Splitter - A splitter includes an input terminal, a first output terminal, a second output terminal, a first transmitting unit including a first microstrip coupled between the input terminal and a first node, a second microstrip coupled between the input terminal and a second node, and a first resistor coupled between the first node and the second node, and a second transmitting unit including a third microstrip coupled between the first node and the first output terminal, a fourth microstrip coupled between the second node and the second output terminal, and a second resistor coupled between the first output terminal and the second output terminal, wherein lengths of the first microstrip and the second microstrip are related to a first frequency, and lengths of the third microstrip and the fourth microstrip are related to a second frequency. | 2013-09-19 |
20130241672 | MULTILAYER BANDPASS FILTER - A multilayer bandpass filter includes a first capacitor electrode of a first stage LC parallel resonator, a second capacitor electrode of a second stage LC parallel resonator, and a third capacitor electrode of a third stage LC parallel resonator. Via electrodes and a line electrode define an inductor electrode of the first stage LC parallel resonator. Via electrodes and a line electrode define an inductor electrode of the second stage LC parallel resonator. Via electrodes and a line electrode define an inductor electrode of the third stage LC parallel resonator. The inductor electrodes of the three LC parallel resonators are arranged so loop planes thereof are disposed about a center axis extending in a stacking direction of dielectric layers. This permits setting of electromagnetic coupling between the LC parallel resonators of an input and an output stage, and allows a filter's attenuation characteristics to be freely set. | 2013-09-19 |
20130241673 | ACOUSTIC WAVE DEVICE - An acoustic wave device includes: a piezoelectric film made of an aluminum nitride film containing a divalent element and a tetravalent element, or a divalent element and a pentavalent element; and an electrode that excites an acoustic wave propagating through the piezoelectric film. | 2013-09-19 |
20130241674 | ELASTIC WAVE FILTER DEVICE AND COMMUNICATION APPARATUS EQUIPPED WITH THE SAME - An elastic wave filter device has a center frequency of a reception frequency band. A plurality of parallel arms are connected to a portion of a series arm on a second signal terminal side of a portion in which a first series-arm resonator is provided. Series-arm resonators among the plurality of series-arm resonators other than the first series-arm resonator include a series-arm resonator having a resonant frequency higher than the resonant frequency of the first series-arm resonator. The resonant frequency of the first series-arm resonator is equal to the reception frequency band. | 2013-09-19 |
20130241675 | Solenoid Coil Having an Enhanced Magnetic Field - An improved solenoid having an enhanced magnetic field and failsafe operation is provided, wherein a primary winding and a secondary winding are constructed such that the combined force imparted on a plunger by both windings energized together is greater than the sum of the forces imparted by the primary and secondary windings energized separately, resulting in a smaller solenoid capable of providing a predetermined force, and providing a solenoid capable of tripping a circuit interrupting latch even if one of the windings is broken. | 2013-09-19 |
20130241676 | CIRCUIT PROTECTION DEVICE AND TRIP UNIT FOR USE WITH A CIRCUIT PROTECTION DEVICE - A trip unit for use with a circuit protection device including a trip mechanism includes a support bracket and a magnet member coupled to the support bracket. The magnet member is configured to emit a magnetic field when a current is transmitted through the trip mechanism. The magnet member includes a first side portion, a second side portion, and a rear portion coupled between the first side portion and the second side portion. The trip unit also includes a pivot arm pivotally coupled to the support bracket. The pivot arm includes a first end, a second end, and a curved portion coupled to the first end and the second end. The pivot arm is configured to pivot towards the magnet member to cause the trip mechanism to interrupt the current when the current exceeds a first threshold. | 2013-09-19 |
20130241677 | Compact Latching Mechanism for Switched Electrical Device - A resettable switching apparatus, useful in a GFCI receptacle, has a space-efficient coaxial configuration in which a mechanical latching arrangement for resetting (i.e., closing) main switch contacts is disposed inside the trip solenoid. A movable carriage for the main contacts spans one end of the solenoid and has a latching portion in the solenoid that engages the inner end of a reset plunger in two sequential states (i.e., unlatched and latched). An electrical miswire feature is included to prevent the device from being reset until the AC power is properly connected to the device and inadvertent failure of the miswire feature due, for example, to dropping the device prior to installation is avoided. Also, an enhanced self-test, or auto-monitoring, feature is provided that is more robust than that which has been previously disclosed. | 2013-09-19 |
20130241678 | Reinstallable Circuit Interrupting Device with Vibration Resistant Miswire Protection - A GFCI device includes a latch assembly provided with a rigid electrically conducting bar connected thereto such that when a user presses a reset button the latch assembly is moved toward a pair of contacts provided as part of a reset circuit to initiate a reset operation. When the electrically conducting bar on the latch assembly connects the pair of contacts, the reset circuit is closed and an actuator is activated to place the GFCI device in the latched, reset, condition. If the GFCI device is correctly wired, the latch assembly enters the latched state. If the device is not properly wired no power is provided to the actuator and the device remains in the tripped, or open, state. | 2013-09-19 |
20130241679 | ELECTROMAGNETIC RELAY - Provided is an electromagnetic relay which can sufficiently dissipate heat generated from a coil to secure desired attracting force even when the electromagnetic relay is miniaturized. The electromagnetic relay includes an electromagnet block and a contact switching mechanism. A movable contact piece of the contact switching mechanism includes a contact attaching portion to which a movable contact is attached, and a first fixed portion attached to a first movable iron piece of the electromagnet block. The first fixed portion is in surface contact with the movable iron piece and is substantially equal in width dimension to the movable iron piece. | 2013-09-19 |
20130241680 | SPRINGLESS ELECTROMAGNET ACTUATOR HAVING A MODE SELECTABLE MAGNETIC ARMATURE - A standard solenoid body and coils are combined with a non-magnetic armature tube containing a permanent magnet, preferably neodymium. The magnet is located in one of three positions within the armature. When biased toward the stop end of the solenoid, it may be configured to act as a push solenoid. When biased toward the collar end of the solenoid, it may be configured to act as a pull solenoid. In either case, no spring is required to return the armature to its de-energized position. Positioning the magnet in the middle of the armature defines a dual-latching solenoid requiring no power to hold it in a given state. A positive coil pulse moves the armature toward the stop end, whereas a negative coil pulse moves the armature toward the collar end. The armature will remain at the end to which it was directed until another pulse of opposite polarity comes along. | 2013-09-19 |
20130241681 | PERMANENT MAGNET, AND MOTOR AND POWER GENERATOR USING THE SAME - In one embodiment, a permanent magnet includes a composition expressed by R | 2013-09-19 |
20130241682 | PERMANENT MAGNET, AND MOTOR AND POWER GENERATOR USING THE SAME - In one embodiment, a permanent magnet includes: a composition expressed by R | 2013-09-19 |
20130241683 | Inductor for Post Passivation Interconnect - An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member. | 2013-09-19 |
20130241684 | METHOD FOR MANUFACTURING COMMON MODE FILTER AND COMMON MODE FILTER - Disclosed herein are a method for manufacturing common mode filter and a common mode filter. The method includes: performing electroplating on first coil patterns made of a conductive material to form second coil patterns having a cross-sectional area increased as compared to the first coil patterns. Therefore, the common mode filter fulfilling a miniaturization demand and having the improved characteristics such as the inductance, the DC resistance, and the like, may be implemented. | 2013-09-19 |