15th week of 2016 patent applcation highlights part 47 |
Patent application number | Title | Published |
20160105127 | POWER CONVERSION DEVICE CONTROL DEVICE AND POWER CONVERSION DEVICE CONTROL METHOD - Provided are a power conversion device control device and a power conversion device control method, which are capable of reducing harm to other electronic devices and electromagnetic noise due to a switching frequency compared to the related art. Carrier change patterns of the respective phases, which are defined by parameters of an average switching frequency, a spectral diffusion index, and a repetition frequency, are generated so that at least the carrier change pattern of one phase differs from the carrier change patterns of the other phases. Semiconductor switching elements are controlled as instructed by duty command values while the switching frequency is switched for each phase separately, from one frequency to another sequentially based on carriers output in patterns that follow the generated carrier change patterns. | 2016-04-14 |
20160105128 | Robust single-phase DC/AC inverter for highly varying DC voltages - A single-phase DC/AC inverter has a single-phase inverter bridge with binary switches connected to an RLC low-pass filter. Digital control logic in a control circuit (or in a microcontroller) determines and controls a logic state q determining the position of the switches in the inverter bridge from sensed i | 2016-04-14 |
20160105129 | TRANSFORMER ELECTRICAL CIRCUIT AND INSTALLATION COMPRISING SUCH A CIRCUIT - An electric transformer circuit for connecting electrical equipment, such as a renewable energy-based generator or an energy storage system, to an electric grid. The circuit includes a first voltage converter connected to the equipment; a transformer connected to the first converter and a second voltage converter connected to the transformer and the electric grid. The transformer is a weakly coupled transformer, the magnetic coupling between the first coil and the second coil being less than 0.7. The transformer includes a first and second capacitor respectively associated with a first and second coil so as to form, with the corresponding coil, a circuit resonating at frequency f | 2016-04-14 |
20160105130 | SEMICONDUCTOR DEVICE AND INVERTER SYSTEM - A semiconductor device includes first and second resistor groups, first and second switch groups, a register, and an amplifier. The first resistor group includes plural first resistors connected in series between a first terminal and an output of the amplifier. The first switch group includes plural first switches. Each of the first switches is connected between a corresponding one of the connection point between the first resistors and the inverting input terminal of the amplifier. The second resistor group includes plural second resistors connected in series between a second terminal of the amplifier and a reference voltage source. The second switch group includes plural second switches. Each of the second switches is connected between a corresponding one of the connection point between the second resistors and a positive input terminal of the amplifier. The register selects each of first and second switches. | 2016-04-14 |
20160105131 | VIBRATION GENERATING DEVICE - There is provided a vibration generating device including: a housing having an internal space; a first vibrating part having one end which is fixed to one end of the housing to be a fixed end and the other end which is a free end; a second vibrating part disposed to face the first vibrating part and having one end which is fixed to the other end of the housing to be a fixed end and the other end which is a free end; and a mass body having one end which is fixed to the free end of the first vibrating part and the other end which is fixed to the free end of the second vibrating part to be vibrated vertically by the first and second vibrating parts. | 2016-04-14 |
20160105132 | SYSTEM AND METHOD FOR CONTROLLING REGENERATIVE BRAKING OF ELECTRIC VEHICLE - A system and a method for controlling regenerative braking of an electric vehicle are provided. The system and method calculate an available torque considering a battery system and an available torque considering a motor system to improve an accuracy of regenerative braking amount. The method includes calculating an available torque considering a battery system and an available torque considering a motor system when regenerative braking of the electric vehicle is required and calculating a regenerative braking capacity based on the available torque considering the battery system and the available torque considering the motor system. | 2016-04-14 |
20160105133 | METHODS AND SYSTEMS FOR RECORDING OPERATING INFORMATION OF AN ELECTRONICALLY COMMUTATED MOTOR - A unit for recording operating information of an electronically commutated motor (ECM) is described. The unit includes a system controller communicatively coupled to an ECM. The system controller includes a processing device configured to control the unit. The unit also includes a memory device communicatively coupled to the system controller. The memory device is configured to receive and store ECM operating information provided by the processing device. | 2016-04-14 |
20160105134 | Controlling a Motor with Two or More Hall Sensors - A motor system includes a motor including two Hall sensors configured to output binary values, and a controller configured to control the motor. The two Hall sensors are placed 120 or 60 electrical degrees apart. The controller is operable to monitor output signals of the two Hall sensors and to determine a third Hall sensor output binary value. The controller is operable to fulfill the commanded requirements to operate in a servo system, by controlling commutation of a drive current into the motor, and by keeping track of the motor rotor position based on the third generated signal and the outputs of the two Hall sensors. | 2016-04-14 |
20160105135 | CONTROL METHOD FOR REDUCING TORQUE RIPPLE IN AN ELECTRICAL MACHINE - A method of controlling torque ripple in an electrical machine that includes a field winding for creating nominally constant field current using DC current and an armature winding for creating a rotating magnetic field using AC current, calls for superimposing a spatially varying current component on to the DC current of the field winding. Other methods are also disclosed that are suitable for electrical machines that have a winding that is excited with nominal DC current including SRMs, FSMs, and wound-field synchronous motors. | 2016-04-14 |
20160105136 | METHOD AND A GENERATOR SYSTEM FOR OPERATING A GENERATOR - The present disclosure relates to a method and a generator system for operating a generator. The method for operating the generator includes exciting the field winding of a rotor of the generator by a first exciter device, driving a second exciter device while operating the generator with the first exciter device, and switching the second exciter device to excite the generator in case the first exciter device feeds to the generator not sufficient energy for operating the generator during a malfunction of the first exciter device. Further, a corresponding generator system is described. | 2016-04-14 |
20160105137 | CONTROL DEVICE FOR AN ASYNCHRONOUS MACHINE AND METHOD FOR OPERATING AN ASYNCHRONOUS MACHINE - The present invention provides a method and a device to determine the rotor field angle of an asynchronous machine even during the magnetising phase, in which the rotor field of a rotor of the asynchronous machine is built up. The asynchronous machine can then be actuated in a controlled operating mode even during the magnetising phase. The startup properties of the asynchronous machine can thus be improved, the magnetising phase of the asynchronous machine is shortened and it is possible to set a desired torque even during the magnetising phase. | 2016-04-14 |
20160105138 | MOTOR DRIVE DEVICE - When a control device determines, based on a sampling number in one period of a target modulation factor waveform, that the sampling number is less than a predetermined value in a case where a two-phase modulation scheme is selected and the target rotation number increases, the control device switches a modulation scheme from the two-phase modulation scheme to a three-phase modulation scheme. | 2016-04-14 |
20160105139 | Phantom Electric Motor System with Parallel Coils - A method and apparatus for operating an electric motor is presented. A transmit magnetic field is received at a group of receive coils having a group of axes oriented substantially parallel to magnetic field lines from a transmit coil and having a group of resonant frequencies. A resonant frequency in the group of resonant frequencies is different from other receive coils in the group of receive coils. A receive magnetic field is generated at a receive coil in the group of receive coils having the resonant frequency when the transmit magnetic field has a selected frequency matching the resonant frequency. The receive magnetic field attracts a rotor in the electric motor. | 2016-04-14 |
20160105140 | DEMAND ADJUSTMENT PLAN GENERATION APPARATUS, METHOD, AND RECORDING MEDIUM - A demand adjustment plan generation includes a first memory device storing expected success probabilities of a power demand adjustment, a second memory device storing combinations of power generation amounts and power demand amounts; and a processor executing a process including, referring to the first memory device and the second memory device, forming a distribution of discharge amounts of power, the distribution being formed for each of time periods, selecting a maximum discharge amount from among the discharge amounts in the distribution, allocating an insufficient amount of the charge amount to the time periods in a manner such that the allocated amount does not exceed the maximum value of each of the time periods and generating the operation plan which includes the insufficient amount allocated to the time periods as adjustment amounts. | 2016-04-14 |
20160105141 | SOLAR PANEL RACK - A solar panel rack may comprise one or more sheet metal brackets configured to attach solar panels to the solar panel rack. The sheet metal brackets may include clinching tabs configured to be clinched to features on the solar panels to attach the solar panels to the solar panel rack. The sheet metal brackets may further include protrusions configured to facilitate electrical contact between the brackets and the solar panels when the clinching tabs are clinched to features on the solar panels. The sheet metal brackets may additionally or alternatively include positioning tabs configured to contact features on the solar panels to position the solar panels in desired locations on the solar panel rack. | 2016-04-14 |
20160105142 | PHOTOVOLTAIC ARRAY MOUNTING SYSTEM - A system for mounting a photovoltaic array onto short sections of mounting rails such that a section of mounting rail is only installed fewer than all the photovoltaic modules in the array. A single section of mounting rail may support one, two or three photovoltaic modules depending on it's length and position respect to the edge of each module frame. | 2016-04-14 |
20160105143 | INTEGRATED HOOK AND FLASHING FOR PHOTOVOLTAIC MODULE INSTALLATION ON TILE ROOFS - A bracket for installing photovoltaic modules on a tile roof. The bracket can have a base portion adapted to sit on a flat roof surface below a tile. A pair of curved portions above the base portion can be supported by a pair of vertical portions. A riser portion can be connected to the pair of curved portion and rising in a direction perpendicular to a roof surface. A flange can be connected to and be perpendicular to the riser portion and parallel to the base. | 2016-04-14 |
20160105144 | PHOTOVOLTAIC SYSTEMS - This invention relates to a roofing panel for interconnection with one or more additional roofing panels. The roofing panel comprises a PV cell coupled to an inverter, and wireless (or optionally wired) power transfer circuitry for transmitting power to another roofing panel and/or the AC grid and/or to an AC inverter, and/or for receiving power from another roofing panel. | 2016-04-14 |
20160105145 | System and Method for Transparent Solar Panels - An apparatus includes a transparent photovoltaic cell, a roof decoration located under and viewable through the transparent photovoltaic cell, and a mounting frame sized to receive said photovoltaic cell and the roof decoration. The mounting frame is configured to be securely fastened to a roof of a structure. | 2016-04-14 |
20160105146 | Input Power Capacity Detector embodying a method for measuring the maximum power (Pmax) available from a photo voltaic panel or array of photo voltaic panels without requirement that a connected AC powered device draws power at the time of measurement - A method of measuring the maximum power available from a photo voltaic array without the requirement of connected AC devices drawing power at time of measurement. Such a method allows for the design of systems which may prevent the unnecessary or potentially damaging startup of said AC devices at times at which power is not sufficient to power them safely. This is achieved by use of a power converter which converts the variable DC input voltage from the PV to a known, fixed DC voltage, then disabling the power converter at defined intervals for very short periods, taking a measurement of the Voc, when risen, and then shorting the current through a resistor and measuring Isc. Measurements are communicated to a central processing unit, which calculates Pmax. | 2016-04-14 |
20160105147 | CRYSTAL OSCILLATOR START-UP CIRCUIT - A crystal oscillator start-up circuit capable of reducing a start-up time of a crystal oscillator is disclosed. The crystal oscillator start-up circuit is provided with a crystal oscillation unit including a crystal oscillator, a converter and an external oscillator. The crystal oscillation unit generates an output signal corresponding to the impedance characteristic of the crystal oscillator. The converter converts the output signal of the crystal oscillation unit to a voltage signal. The external oscillator outputs to the crystal oscillation unit an oscillation signal whose frequency is adjusted by the voltage signal to approach a resonance frequency of the crystal oscillator. | 2016-04-14 |
20160105148 | RC OSCILLATOR - A method includes using a current source to provide a charging current to a capacitor of a resistor-capacitor (RC) tank of an RC oscillator. The method includes using a resistor of the current source as a resistor for the RC tank. | 2016-04-14 |
20160105149 | ATOMIC CELL, ATOMIC CELL MANUFACTURING METHOD, QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC DEVICE, AND MOVING OBJECT - An atomic cell includes: alkaline metallic atoms, a body portion and window portions forming an inner space in which alkaline metallic atoms are sealed, and a getter material disposed in the inner space. The getter material is an alloy including at least one of titanium, barium, tantalum, zirconium, aluminum, vanadium, indium, and calcium, or an Al—Zr—V—Fe based alloy. | 2016-04-14 |
20160105150 | QUANTUM INTERFERENCE DEVICE, ATOMIC OSCILLATOR, ELECTRONIC DEVICE, AND MOVING OBJECT - An atomic oscillator includes an atom cell, a first light source device, a second light source device, and a reception section. The atom cell is filled with alkali metal. The first light source device emits a light beam that includes a resonance light beam pair configured to be circularly polarized with each other in the same direction and configured to cause the alkali metal to resonate. The second light source device emits a light beam that includes adjustment light beam configured to be circularly polarized in a reverse direction to the resonance light beam pair. The reception device receives the resonance light beam pair that pass through the atom cell. The adjustment light beam may include the resonance light beam that causes the alkali metal to resonate. In addition, the resonance light beam pair may be a line and the adjustment light beam is a line. | 2016-04-14 |
20160105151 | Switchable Dual Core Power Amplifier - A dual mode, dual core power amplifier (PA) device includes a plurality of PA chains that generate output power according to an envelope tracking mode and a non-envelope tracking mode. The different modes can be selected to generate output power based on a set of predetermined criteria, which can be related to an input signal received by the system and related to a target power. A first PA chain with one or more PA cores is configured to operate in the envelope tracking mode based on at least a portion of the predetermined criteria being identified in the input signal and to generate output power with an envelope voltage supply that changes with an envelope of the input signal. In addition, a second PA chain with one or more PA cores can operate in a constant voltage supply mode or the non-envelope tracking mode according to the predetermined criteria. | 2016-04-14 |
20160105152 | Reconfigurable Power Amplification Device and an Integrated Circuit Including Such a Device - This reconfigurable power amplification device ( | 2016-04-14 |
20160105153 | Band-Reconfigurable and Load-Adaptive Power Amplifier - A tunable amplifier includes continuous tunability for both frequency and power levels. The tunable amplifier includes a combination of a tunable series resonator and a multi-stage LC network as the output matching network. The tunable amplifier incorporates a variable diode varactor with high breakdown voltage and high tuning range into a tunable resonator. The tunable resonator is connected to a fixed output matching network to enable a wide range of operating frequencies. The tunable amplifier enables high power, high efficiency, broadband and load-modulated power amplification, which is greatly desired for next-generation wireless communication systems and other high-frequency applications. | 2016-04-14 |
20160105154 | HIGH-FREQUENCY GENERATOR - The power stage at the output of a high-frequency generates operates in class D and comprises a voltage supply and a common earth, a first and a second switch linked to the common earth and periodically switched on at a high frequency F; these switches are linked to two common-mode inductors connected in a Guanella balun. Each common-mode inductor comprises two inductive lines with strong mutual coupling. The first switch is linked to the input of the first inductive line but not to the second, third and fourth lines and the second switch is linked to the input of the fourth inductive line but not to the first, second and third lines, the output of the first inductive line is linked to an output of the generator, the output of the fourth inductive line is linked to an internal resistor, the inputs of the second and third inductive lines are linked to the supply voltage source, the output of the third inductive line is linked to the output of the first inductive line and the output of the second inductive line is linked to the output of the fourth inductive line. | 2016-04-14 |
20160105155 | AUTOMATIC ADJUSTMENTS OF AUDIO ALERT CHARACTERISTICS OF AN ALERT DEVICE USING AMBIENT NOISE LEVELS - The automatic adjustment of audio alert characteristics of an alert device using ambient noise levels is described. In one aspect of the invention, a machine-readable medium has executable instructions to cause a machine to perform a method to receive an audio sample of ambient noise and adjust a characteristic of the audio alert, such as, the volume level of the audio alert, based on the ambient noise level. | 2016-04-14 |
20160105156 | INTEGRATED RESONATOR WITH A MASS BIAS - An integrated resonator apparatus includes a piezoelectric resonator and an acoustic Bragg reflector formed adjacent the piezoelectric resonator. The integrated resonator apparatus also includes a mass bias formed over the Bragg reflector on a side of the piezoelectric resonator opposite the piezoelectric resonator. | 2016-04-14 |
20160105157 | CIRCUITS AND METHODS FOR PROVIDING AN IMPEDANCE ADJUSTMENT - An apparatus includes a signal generator and a control circuit. The signal generator includes a control terminal and includes a current electrode coupled to a terminal that is configured to couple to a power line to receive direct current (DC) power from a power generator. The control circuit is coupled to the current electrode and the control terminal of the signal generator. The control circuit determines an impedance associated with the power generator and applies a control signal to the control terminal of the signal generator to produce an impedance adjustment signal on the current electrode for communication to the power generator through the power line in response determining the impedance. | 2016-04-14 |
20160105158 | ELECTRONIC DEVICE INCLUDING FILTER - An electronic device includes a main circuit connected between an input terminal and an output terminal, and an auxiliary circuit connected in parallel to the main circuit between the input terminal and the output terminal. The main circuit includes a filter having a first passband and a stopband. The auxiliary circuit has a passing characteristic that allows a signal having a frequency in a certain frequency band inside the stopband to pass through the auxiliary circuit. The main circuit is configured to output a main signal in response to an input signal. The auxiliary circuit is configured to output an auxiliary signal in response to the input signal. The main signal and the auxiliary signal contain phase components opposite to each other in the certain frequency band inside the stopband. This electronic device has an attenuation amount in the stopband. | 2016-04-14 |
20160105159 | CONFIGURABLE RADIO FREQUENCY ATTENUATOR - RF attenuator circuitry includes an RF attenuator and a control system. The RF attenuator is configured to provide an attenuation response between an input node and an output node. The control system is coupled to the RF attenuator and configured to adjust one or more control signals provided to the RF attenuator based on either the temperature of the circuitry or an externally applied test signal provided to the control system. The control signals are provided such that the attenuation response of the RF attenuator is substantially linear-in-dB with respect to either the temperature or the test signal provided to the control system. Because the control system is configured to adjust the control signals based either on a temperature of the circuitry or the test signal, the response of the RF attenuator can be easily and quickly tested to ensure linear-in-dB operation thereof. | 2016-04-14 |
20160105160 | DIGITAL FILTER DEVICE AND SIGNAL PROCESSING METHOD - Provided is a digital filter device including data rearrangement means for executing rearrangement of input data and outputting rearranged data, intermediate data calculation means for processing the rearranged data input at a specific time and generating intermediate data, filter output first calculation means for calculating a first output value at the specific time by use of the intermediate data, delay means for delaying the rearranged data by processing time taken in the intermediate data calculation means and the file output first calculation means, and filter output second calculation means for inputting output values from the delay means and the filter output first calculation means, calculating a second output value at a time other than the specific time, and outputting a filter output value obtained by adding up the first and second output values. Consequently, it becomes feasible to reduce a circuit scale without impairing performance of a digital filter used in nonlinear compensation and realize nonlinear compensation by an LSI. | 2016-04-14 |
20160105161 | IMPLEMENTING BROADBAND RESONATOR FOR RESONANT CLOCK DISTRIBUTION - A method and circuit for implementing a broadband resonator for resonant clock distribution, and a design structure on which the subject circuit resides are provided. The circuit includes a pair of first inductors, and a second inductor and a capacitor coupled between a respective first end of the respective first inductors. An opposite free end of the respective first inductors is connected to a respective clock transmission line and connected in parallel to a load capacitance. A frequency response of the circuit includes two poles and a zero in a frequency band of the resonant clock distribution system. | 2016-04-14 |
20160105162 | METHODS AND APPARATUSES FOR ULTRA-LOW-POWER SYSTEM ON A CHIP (SoC) ACTIVITY WEARABLE DEVICES - An always-on chip incorporated inside an activity wearable device implemented as a System-On-a-Chip (SoC). The device includes a MCU and DSP and audio CODEC and a BLE circuit to detect user activation commands. | 2016-04-14 |
20160105163 | LOW-VOLTAGE TO HIGH-VOLTAGE LEVEL SHIFTER CIRCUIT - A low-voltage to high-voltage level shifter circuit includes an input circuit, a voltage shifting circuit, and an output circuit. The input circuit is configured to receive an input signal having a voltage range between a first voltage and a ground voltage, and to provide an inverted input signal and a delayed version of the inverted input signal. The voltage shifting circuit is coupled to the input circuit and is configured to receive the input signal, the inverted input signal, and the delayed version of the inverted input signal. The voltage shifting circuit is configured to provide an internal signal having a voltage range between a second voltage and the ground voltage, the second voltage being higher than the first voltage. The output circuit provides an output voltage in the high-voltage range for the corresponding input voltage in the low-voltage range. | 2016-04-14 |
20160105164 | APPARATUS FOR GENERATING SWITCHING SIGNAL FOR ANALOG CONTROLLER - An apparatus for generating a switching signal for an analog controller includes: a voltage setting unit configured to set voltages V | 2016-04-14 |
20160105165 | DUTY CYCLE ERROR DETECTION DEVICE AND DUTY CYCLE CORRECTION DEVICE HAVING THE SAME - In a duty cycle error detection device, a first digital code generator is configured to generate high and low codes corresponding to a lengths of high level low level periods, respectively, of a clock signal, generate a sign signal representing the longer period between the high level period and the low level period, and output one of the high and low digital codes corresponding to the shorter period as a first digital code. A clock delay circuit is configured to generate a delay clock signal by delaying the clock signal for a time corresponding to the first digital code, and a second digital code generator is configured to generate a duty error digital code corresponding to a length from a start of the longer period of the delay clock signal to an end of the longer period of the clock signal based on the sign signal. | 2016-04-14 |
20160105166 | BIDIRECTIONAL DELAY CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A bidirectional delay circuit includes an input driving circuit and a delay switch circuit. The input driving circuit is connected between an input node and an intermediate node, and the input driving circuit amplifies an input signal received through the input node to generate an intermediate signal through the intermediate node. The delay switch circuit is connected between the intermediate node and a delay node, and the delay switch circuit delays both of rising edges and falling edges of the intermediate signal in response to a gate signal to generate a delay signal through the delay node. The gate signal may transition in response to the input signal. | 2016-04-14 |
20160105167 | ELECTRONIC DEVICE AND METHOD OF CONTROLLING CLOCK FREQUENCY OF ELECTRONIC DEVICE - A method of controlling a clock frequency of an electronic device and an electronic device using the same is provided. The electronic device includes a check module that is configured to check a clock frequency of at least one Radio Frequency (RF) band, and a control module that is configured to shift a clock frequency of a high speed signal such that a noise generation clock frequency and the clock frequency of the at least one RF band checked by the check module are not identical, when an interface of the high speed signal is used. | 2016-04-14 |
20160105168 | CHIP AND CHIP CONTROL METHOD - Provided is a chip in which operation state information on a main logic unit operating in response to an enable signal is acquired, and determining whether a toggling condition of the main logic unit is satisfied based on the operation state information. | 2016-04-14 |
20160105169 | LOW POWER EXTERNALLY BIASED POWER-ON-RESET CIRCUIT - Various methods and devices that involve power-on-reset (POR) circuits are disclosed herein. An exemplary POR circuit for generating a POR signal upon detecting that a supply voltage has reached a desired level comprises a sense circuit and a delayed buffer. The sense circuit comprises: (i) an inverter powered by a known bias voltage; (ii) a feedback circuit powered by the supply voltage; and (iii) an output node of the sense circuit that experiences a voltage transition when the supply voltage has reached the desired level. The delayed buffer is coupled to the output node of the sense circuit that generates the POR signal in response to the voltage transition. The feedback circuit shuts off the sense circuit in response to the voltage transition. The POR circuit generates the POR signal for a local system. The known bias voltage is provided by an external system. | 2016-04-14 |
20160105170 | RESET SIGNAL GENERATOR AND INTEGRATED CIRCUIT HAVING THE SAME - A reset signal generator may include a voltage divider dividing a voltage level of a driving voltage, a reference voltage generator generating a reference voltage by performing a switching operation on the driving voltage depending on a voltage level of the divided driving voltage from the voltage divider, and a comparator comparing the voltage level of the divided driving voltage and the reference voltage to output a reset signal depending on the comparison result. The integrated circuit includes the reset signal generator and a controller resetting a control operation depending on the reset signal. | 2016-04-14 |
20160105171 | SEMICONDUCTOR DEVICE HAVING THROUGH CHIP VIA - A semiconductor device includes a plurality of chips; a first through-chip via vertically passing through the chips, a power-saving unit suitable for being precharged to a precharge voltage during a precharge period; and a driving unit suitable for driving data using the precharge voltage outputted from the power-saving unit, during a driving period. | 2016-04-14 |
20160105172 | ACTIVE DIODE HAVING IMPROVED TRANSISTOR TURN-OFF CONTROL METHOD - An active diode that features improved control of transistor turn-off is provided. Such an active diode may include a comparator to compare voltages between opposite ends of a parasitic diode, and a gate driver to control a gate terminal of the transistor according to the comparison result of the comparator. Furthermore, the active diode may further include an off-timing controller to control the transistor to be turned off at a point in time when voltages of the opposite ends of the parasitic diode turn positive. Thus, the active diode may be turned off when required. | 2016-04-14 |
20160105173 | HIGH VOLTAGE ZERO QRR BOOTSTRAP SUPPLY - An electrical circuit arranged in a half bridge topology. The electrical circuit includes a high side transistor; a low side transistor; a gate driver and level shifter electrically coupled to a gate of the high side transistor; a gate driver electrically coupled to a gate of the low side transistor; a capacitor electrically coupled in parallel with the gate driver and level shifter; a voltage source electrically coupled to an input of the gate driver and level shifter and an input of the gate driver; and, a bootstrap transistor electrically coupled between the voltage source and the capacitor. A GaN field-effect transistor is synchronously switched with a low side device of the half bridge circuit. | 2016-04-14 |
20160105174 | LOGIC CIRCUIT, PROCESSING UNIT, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor. | 2016-04-14 |
20160105175 | POWER SEMICONDUCTOR DRIVE CIRCUIT, POWER SEMICONDUCTOR CIRCUIT, AND POWER MODULE CIRCUIT DEVICE - A power semiconductor drive circuit includes a parallel circuit connected to a gate of a power semiconductor element and constituted by two transistors for setting gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate of the power semiconductor element and the parallel circuit, wherein a monitoring voltage is set in the gate voltage monitoring circuit to monitor a gate voltage of the power semiconductor element; a signal delay circuit to delay an output signal of the gate voltage monitoring circuit; and a gate control circuit to change the magnitude of combined resistance of the parallel circuit based on an output signal output from the signal delay circuit. | 2016-04-14 |
20160105176 | SPIN WAVE DEVICE AND LOGIC CIRCUIT USING SPIN WAVE DEVICE - As a technique for attaining a reduction in power consumption, there is a technique for reducing power consumption using a spin wave. No specific proposal concerning spin wave generation, spin wave detection, and a latch technique for information has been made. | 2016-04-14 |
20160105177 | CLOCK BUFFERS WITH PULSE DRIVE CAPABILITY FOR POWER EFFICIENCY - A clock driver is provided. The clock driver includes a multi-stage delay cell having an input, a positive pulse driving branch, a negative pulse driving branch, and an output. The input is for receiving an original version of a reference clock signal input to the clock driver and used to generate a global clock signal. The output is connected to the positive pulse driving branch and the negative pulse driving branch. The clock driver further includes a pulse generator having positive and negative pulse generator portions respectively connected to outputs of the positive and negative pulse driving branches. The pulse generator generates, at any given time, one of a positive pulse and a negative pulse responsive to a positive pulse enable signal and a negative pulse enable signal, respectively, and the original version of the reference clock signal input to the clock driver without modification. | 2016-04-14 |
20160105178 | METHODS AND APPARATUSES FOR MULTIPLE CONCURRENT SUB-THRESHOLD VOLTAGE DOMAINS FOR OPTIMAL POWER PER GIVEN PERFORMANCE - A method and flow for implementing an ASIC using sub-threshold technology with optimized selection of voltage and process for a given application performance. An embodiment may also implement concurrently used multiple voltage domains inside a single place and route block. The voltage domain is dynamically changed between the cells at the placement time based on the timing path requirements. | 2016-04-14 |
20160105179 | LEVEL SHIFTING AN I/O SIGNAL INTO MULTIPLE VOLTAGE DOMAINS - Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device. | 2016-04-14 |
20160105180 | RECEIVING AN I/O SIGNAL IN MULTIPLE VOLTAGE DOMAINS - Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device. | 2016-04-14 |
20160105181 | RECEIVING AN I/O SIGNAL IN MULTIPLE VOLTAGE DOMAINS - Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device. | 2016-04-14 |
20160105182 | LEVEL SHIFTING AN I/O SIGNAL INTO MULTIPLE VOLTAGE DOMAINS - Embodiments disclosed herein include an I/O module with multiple level shifters that establish a plurality of voltage domains. Using the level shifters, the I/O module converts data signals in a core logic voltage domain to data signals in an external voltage domain. In one embodiment, when transmitting data signals to an external device, the I/O module level shifts the data signals from a core logic voltage domain to a low voltage domain. The I/O module then level shifts the data signals from the low voltage domain to an intermediate voltage domain. The I/O module may further shift the data signals from the intermediate voltage domain to both a low voltage domain and a high voltage domain. Using the data signals from both of these domains, the I/O module outputs the data signals in a voltage domain corresponding to a communication technique used to transmit data to the external device. | 2016-04-14 |
20160105183 | RECEIVER CIRCUIT AND SIGNAL RECEIVING METHOD THEREOF - Provided is a receiver circuit which receives an input signal. A first restriction circuit provides a first reference voltage or an input signal higher than the first reference voltage to a first node. A second restriction circuit provides a second reference voltage or the input signal lower than the second reference voltage to a second node. A first PMOS transistor pulls up an output node based on a voltage of the first node, and a first NMOS transistor pulls down the output node based on a voltage of the second node. A second PMOS transistor is connected between the output node and the first PMOS transistor, and a second NMOS transistor is connected between the output node and the first NMOS transistor. At least one compensation resistor is connected between a power supply voltage and the first PMOS transistor or between the first NMOS transistor and a ground. | 2016-04-14 |
20160105184 | INVERTER, DRIVING CIRCUIT AND DISPLAY PANEL - An inverter includes first, second, third, fourth, and fifth transistors, and first and second capacitors. The transistors and capacitors are connected in such way that the reverse conduction of the second transistor is prevented through controlling the gate electrode of the second transistor and maintaining the electrical potential at the gate electrode of the fifth transistor by the second capacitor. The electrical potential at the gate electrode of the fifth transistor is maintained stable when a first clock signal changes from high to low (when the first to fifth transistors are NMOS transistors) or from low to high (when the first to fifth transistors are PMOS transistors), so that the output signal of the inverter may not be affected by a change of the first clock signal, thus enabling the inverter to generate a stable output signal and a display panel comprising the inverter to obtain a better display effect. | 2016-04-14 |
20160105185 | Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof - An integrated circuit includes a plurality of logic tiles, wherein each logic tile is configurable to connect with at least one adjacent logic tile; a first logic tile includes: (i) an input clock path which is associated with an edge and to receive a tile input clock signal, (ii) a plurality of output clock paths, each output clock path is associated with an edge of the tile and includes at least one u-turn circuit to: (a) receive a tile clock signal having a predetermined skew relative to the tile input clock signal and (b) output a tile clock signal having a predetermined skew relative to a tile output clock signal, (iii) a tile clock generation path which includes a plurality of the u-turn circuits to generate a tile clock based on the tile clock signals, and (iv) programmable logic circuitry to perform operations using the tile clock. | 2016-04-14 |
20160105186 | SYSTEM LEVEL INTERCONNECT WITH PROGRAMMABLE SWITCHING - Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers. | 2016-04-14 |
20160105187 | FLL OSCILLATOR/CLOCK WITH AN FLL CONTROL LOOP INCLUDING A SWITCHED CAPACITOR RESISTIVE DIVIDER - An FLL (frequency locked loop) oscillator/clock generator includes a free-running oscillator (such as a ring oscillator), and generates an FLL_clk with an FLL-controlled frequency f | 2016-04-14 |
20160105188 | SEMICONDUCTOR DEVICE - A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader. | 2016-04-14 |
20160105189 | DELAY CIRCUIT, DELAY LOCKED LOOP CIRCUIT INCLUDING DELAY CIRCUIT AND PROCESSOR INCLUDING DELAY LOCKED LOOP CIRCUIT - A delay circuit comprises a plurality of delay buffers each including two or more serially connected delay units, each of the delay units being capable of variably controlling a delay amount; a variable control voltage generator circuit configured to supply, to a first delay unit included in each of the plurality of delay buffers, a variable control voltage provided to control the delay amount of the first delay unit; and a fixed control voltage generator circuit configured to supply, to a second delay unit included in each of the plurality of delay buffers, a fixed control voltage among a plurality of fixed control voltages for controlling the delay amount of the second delay unit. The plurality of delay buffers are connected in series and an input signal propagates through the plurality of serially connected delay buffers. | 2016-04-14 |
20160105190 | FREQUENCY SYNTHESIS DEVICE AND METHOD - A frequency synthesis device, including: a first generator configured to generate a periodical signal with a frequency f | 2016-04-14 |
20160105191 | FREQUENCY SYNTHESIZER - The output of a reference frequency generator is connected to the input of a high-order frequency multiplier, the output of which is connected to the input of an additional frequency multiplier and to a first input of a frequency converter. The output of the additional frequency multiplier is connected to the input of a frequency divider, the output of which is connected to a reference input of a frequency-phase detector. The output of the frequency converter is connected to the input of a frequency divider with a variable division ratio, the output of which is connected to another input of the frequency-phase detector. The output of the frequency-phase detector is connected to an error signal filter, the output of which is connected to the input of a controlled generator. A second input of the frequency converter is connected to the output of the controlled generator. The main technical result is an increase in the frequency resolution and spectral purity of an output signal. | 2016-04-14 |
20160105192 | DIGITAL TO ANALOG CONVERTER - A digital to analog converter includes a reference voltage generation unit that generates a reference voltage, and a plurality of unit conversion units. A number of unit conversion units to be activated are decided in response to digital codes. An activated unit conversion unit drives a control node to a voltage level corresponding to a voltage level of the reference voltage, and a deactivated unit conversion unit substantially maintains the control node to a voltage level greater than a voltage level of a ground voltage. | 2016-04-14 |
20160105193 | ANALOG-TO-DIGITAL CONVERTER PROBE FOR MEDICAL DIAGNOSIS AND MEDICAL DIAGNOSIS SYSTEM - Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal. | 2016-04-14 |
20160105194 | PASSIVE ANALOG SAMPLE AND HOLD IN ANALOG-TO-DIGITAL CONVERTERS - In an example embodiment, an analog to digital converter (ADC) facilitating passive analog sample and hold is provided and includes a pair of binary weighted conversion capacitor arrays, a pair of sampling capacitors, and a plurality of switches that configure each conversion capacitor array and the sampling capacitors for a sampling phase, a charge transfer phase, and a bit trial phase. During the sampling phase, the sampling capacitors are decoupled from the conversion capacitors and coupled to an analog input voltage. During the charge transfer phase, the sampling capacitors are coupled to the conversion capacitors and decoupled from the analog input voltage. During the bit trial phase, the sampling capacitors are decoupled from the conversion capacitors. | 2016-04-14 |
20160105195 | Parallel Sample-and-Hold Circuit for a Pipelined ADC - A parallel sample-and-hold circuit includes a sampling switch and a hold capacitor for each of the ADC and MDAC of a converter stage for a pipelined ADC. Each sampling switch couples the analog input of the first converter stage to its hold capacitor at the time a sample is desired to be taken. After the sample is placed on the hold capacitor, the sampling switch is opened and the hold capacitor stores the sample. To compensate for mismatches in the signal paths of these sample-and-hold circuits, a compensation switch is further used. The compensation switch couples the terminals of the hold capacitors together, creating a parallel sample-and-hold circuit. The compensation switch is controlled such that it is closed after the sampling switches are opened to equalize a voltage of the samples. | 2016-04-14 |
20160105196 | DIRECT SIGMA-DELTA RECEIVER - A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal. | 2016-04-14 |
20160105198 | CODING METHOD, DECODING METHOD, CODER, AND DECODER - A coding method, a decoding method, a coder, and a decoder are disclosed herein. A coding method includes: obtaining the pulse distribution, on a track, of the pulses to be encoded on the track; determining a distribution identifier for identifying the pulse distribution according to the pulse distribution; and generating a coding index that includes the distribution identifier. A decoding method includes: receiving a coding index; obtaining a distribution identifier from the coding index, wherein the distribution identifier is configured to identify the pulse distribution, on a track, of the pulses to be encoded on the track; determining the pulse distribution, on a track, of all the pulses to be encoded on the track according to the distribution identifier; and reconstructing the pulse order on the track according to the pulse distribution. | 2016-04-14 |
20160105199 | FAST MAPPING METHOD FOR LAYERED MIN-SUM DECODING OF LDPC CODES, - A method is disclosed for performing LDPC decoding, specifically layered min-sum decoding using a Tanner graph including check nodes (CN) and variable nodes (VN). Messages passed between nodes are quantized in a non-uniform manner. Values below a threshold are uniformly quantized whereas values above the threshold are non-uniformly quantized. A corresponding inverse-quantization is also defined. | 2016-04-14 |
20160105200 | APPARATUS AND METHOD FOR PROCESSING TRACE DATA STREAMS - An apparatus comprising: a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and a higher-layer decoder configured to decode the first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising: synchronisation logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronisation event; and decoding logic configured to use the synchronisation event to synchronise decoding of the received first data stream to produce the trace data. | 2016-04-14 |
20160105201 | METHOD AND INTERLEAVING APPARATUS FOR INTERLEAVING FOR ERROR DISPERSION AND COMPUTER READABLE RECORDING MEDIUM FOR PERFORMING THE SAME - An interleaving apparatus, a computer-readable recording medium, and a method for interleaving data elements comprised in data frame which are transmitted via a channel for error dispersion are provided. The interleaving apparatus includes a block division unit that divides a given page of the data frame including two-dimensional array data into a plurality of data block units, and an interleaving unit that performs interleaving at least between two of the plurality of data blocks units, which are divided by the block division unit. A first block unit in the plurality of data block units is set as a reference interleaving block unit, and first data in the first block unit and second data in a second block unit are interleaved. The first block unit and the second block unit are included in the plurality of data block units, and the first block unit is different from the second block unit. | 2016-04-14 |
20160105202 | CODING AND DECODING METHODS AND APPARATUS - According to an embodiment a decoder for decoding a received set of blocks each comprising a plurality of data symbols and a plurality of parity symbols, wherein the received set of blocks is a subset of a complete set of blocks, the complete set of blocks comprising at least one erased block not included in the received set of blocks comprises storage for a coding matrix which is the kronecker product of a totally non-singular matrix with an anti-diagonal matrix; and a processor operable to determine data symbols of the at least one erased block using the encoding matrix. | 2016-04-14 |
20160105203 | Interference Reduction for Multiple Signals - The present invention reduces the degradation in performance of one or more radio signals that are co-transmitted with a first radio signal from the same transmitting antenna in the same frequency channel and received by the same antenna due to multipath or other shared interference, where the one or more radio signals can be separated from the first radio signal. All received signals are coupled to the same adaptive array or adaptive filter to reduce multipath or other shared interference of the first radio signal, which reduces multipath and other shared interference in the other radio signals before they are separated and processed by their respective receivers, or the individual radio signals are separated before the first signal enters the adaptive array and coupled to a slave weighting network slaved to the weights of the adaptive array of the first signal to reduce interference in all the signals. | 2016-04-14 |
20160105204 | PROTECTION COVER - A protection cover is provided, which includes a first cover that is foldable, a first electronic device being attachable to or detachable from the first cover; a second cover that is connected to the first cover so as to be foldable, a second electronic device being attachable to or detachable from the second cover, and a third cover that is connected to the first cover so as to be foldable. | 2016-04-14 |
20160105205 | Hinged Sleeve for a Mobile Device - A sleeve for a mobile computing device. The sleeve includes a top surface, a bottom surface, and a friction hinge disposed between the top surface and the bottom surface. The top surface includes a plurality of first edges. The bottom surface includes a plurality of second edges. One or more of the plurality of second edges are attached to one or more of the plurality of first edges to form a pocket for the mobile computing device. The friction hinge is configured to incline a portion of the top surface when in a closed position to provide an inclined surface onto which the mobile computing device may be disposed. The friction hinge is configured to maintain its position when a mobile computing device is placed on the top surface. | 2016-04-14 |
20160105206 | Electronic Device and Method for Manufacturing Housing Thereof - An electronic device and a method for manufacturing the housing thereof are disclosed. The electronic device includes a housing made of a metal material, the housing has a bottom, a sidewall extending along a first direction from an outer edge of the bottom, and a texture extending from an outer surface of the bottom to an outer surface of the side wall; M electronic elements set in the housing fixedly, where M≧1 and is a positive integer. The texture of the surface of the housing of the electronic device provided by the disclosure is extended from the bottom to the side wall, providing the user with a favorite appearance effect. | 2016-04-14 |
20160105207 | MOBILE DEVICE CASE WITH GPS TRACKING - A mobile device case for a mobile device having a first battery to operate, said mobile device case comprising of a housing to receive said mobile device; a second battery being embedded in said housing; a pair of thermometers embedded in said housing to monitor the temperature of said first battery and ambient surrounding said housing; a GPS device to determine the location of the mobile device case; an electronic communication means to communicate with a plurality of satellites to send and receive a data related to the location of the mobile device case; and a processor to process the functionality of said second battery, said thermometers, said GPS device and said communication means and switch between said second battery and said first battery; whereby the processor switches the power source of the mobile device from said first battery to said second battery when said first battery is dead. | 2016-04-14 |
20160105208 | MOBILE PHONE COVER WITH MECHANICAL KEYBOARD - A mobile phone cover with mechanical keyboard is provided. The mobile phone cover includes a top cover, a bottom cover and a connecting assembly connecting the top cover and the bottom cover. The top cover and the bottom cover cooperatively define a receiving space for receiving a mobile phone. The top cover includes a first communication unit. The bottom cover includes a second communication unit. The top cover communicates with the bottom cover via the first communication unit and second communication unit. The mobile phone cover further includes a mechanical keyboard module. The mechanical keyboard module includes a number of first mechanical keys located on the top cover and a number of second mechanical keys located on the bottom cover. | 2016-04-14 |
20160105209 | APPARATUS AND METHOD FOR SECURING OR PROTECTING ELECTRONIC DEVICES - An apparatus for providing impact protection to a cell phone comprises a flexible elongated member configured to loop around an upper end of the phone, and a flexible elongated member configured to loop around a lower end of the phone, each elongated member sized to elastically stretch over and about opposing side edges of the phone. A plurality of different connecting pieces may join these two flexible members over a portion of the rear face of the phone. A method of use is also disclosed. | 2016-04-14 |
20160105210 | WIDE BAND ANTENNA SYSTEMS - A system that incorporates teachings of the subject disclosure may include, for example, a communication device including a matching network for impedance tuning and pairs of antennas that can be utilized as primary and diversity antennas, respectively, and can provide high radiation efficiency. An RF switch can be utilized for re-configuring the primary and diversity antennas. Other embodiments are disclosed. | 2016-04-14 |
20160105211 | METHOD AND APPARATUS FOR RECONSTRUCTING DESIRED SIGNAL IN CASE OF USING FULL DUPLEX RADIO (FDR) SCHEME - The apparatus for reconstructing a desired signal using a full duplex radio (FDR) scheme includes: a digital self-interference cancellation unit configured to output a first digital signal; a demodulator configured to demodulate the first digital signal; a modulator configured to modulate the demodulated first digital signal; an attenuator configured to attenuate the modulated first digital signal by applying an attenuation coefficient to the modulated first digital signal; and an operation unit configured to receive the attenuated first digital signal and the first digital signal, and transmit a residual signal to the digital self-interference cancellation unit, wherein the residual signal is obtained by subtracting the attenuated first digital signal from the first digital signal. | 2016-04-14 |
20160105212 | HIGH RADIATION EFFICIENCY ANTENNA SYSTEMS - A system that incorporates teachings of the subject disclosure may include, for example, a communication device including a matching network for impedance tuning and pairs of antennas that can be utilized as primary and diversity antennas, respectively, and can provide high radiation efficiency. An RF switch can be utilized for re-configuring the primary and diversity antennas. Other embodiments are disclosed. | 2016-04-14 |
20160105213 | METHODS FOR CANCELLATION OF RADIO INTERFERENCE IN WIRELESS COMMUNICATION SYSTEMS - A full duplex radio includes self-interference cancellation circuitry for reducing self-interference. The self-interference cancellation circuitry may receive analog radio frequency signals that are to be transmitted by an antenna, and downconvert and digitize the signals to provide a digital baseband signal for processing, for example by an adaptive filter. The filtered signal may be Cconverted to an analog signal and applied in an analog portion of a receive chain of a receiver of the full duplex radio. Preferably the analog signal is applied in the receive chain after low noise amplification of received signals of interest. | 2016-04-14 |
20160105214 | CROSSTALK REDUCTION METHOD AND REPEATER - A crosstalk reduction method includes providing a signal transmission unit including first to eighth main transmission paths, the first and second paths, the third and sixth paths, the fourth and fifth paths and the seventh and eighth paths being respectively paired to transmit differential signals, providing a first coupling transmission path in the signal transmission unit, the first coupling transmission path being adapted to electrically couple the third main transmission path to the fifth and seventh main transmission paths that are located adjacent to the sixth main path, and providing a second coupling transmission path in the signal transmission unit, the second coupling transmission path being adapted to electrically couple the sixth main transmission path to the second and fourth main transmission path that are located adjacent to the third main transmission path. | 2016-04-14 |
20160105215 | Crosstalk Cancellation Over Multiple Mediums - A method of cancelling crosstalk including receiving, by a vector processor, a first signal from a first medium and a second signal from a second medium, wherein the first medium is different from the second medium, determining, using the vector processor, vectoring coefficients based on the first signal and the second signal received, cancelling, using the vector processor, the crosstalk from at least one of the first medium to the second medium and the second medium to the first medium using the vectoring coefficients determined, and transmitting or demodulating corrected signals following the cancellation of the crosstalk. | 2016-04-14 |
20160105216 | LINE INITIALIZATION METHOD, DEVICE, AND SYSTEM - Embodiments of the present invention provide a line initialization method, a device, and a system. The method includes: when a new line is added, releasing at least one resource unit that is on a line at a Showtime stage, so that on the line at the Showtime stage data is transmitted on a remaining resource unit that is obtained after the at least one resource unit is released; performing basic initialization on the new line by using the at least one resource unit or a subset of the at least one resource unit, so that after the basic initialization, data can be transmitted on the new line by using the at least one resource unit or the subset of the at least one resource unit; and performing crosstalk cancellation initialization on the line at the Showtime stage and the new line by using all resource units. | 2016-04-14 |
20160105217 | METHOD FOR TRANSMITTING A SIGNAL VIA A POWER LINE NETWORK, TRANSMITTER, RECEIVER, POWER LINE COMMUNICATION MODEM AND POWER LINE COMMUNICATION SYSTEM - A method for transmitting signals over a power line network, wherein within the power line network at least one transmitter and at least one receiver communicate via at least two channels, each channel including a respective feeding port of at least one transmitter and the respective receiving port of the at least one transmitter and transmitter including at least two feeding ports. The method: determines a channel characteristic of each of the channels; applies a feeding port selection criterion based on the channel characteristic; and selects an excluded feeding port among the at least two feeding ports based on the feeding port selection criterion, wherein the excluded feeding port is not used during further communication. A corresponding power line communication modem can implement the method. | 2016-04-14 |
20160105218 | METHOD AND APPARATUS FOR TRANSMITTING OR RECEIVING SIGNALS IN A TRANSPORTATION SYSTEM - Aspects of the subject disclosure may include, for example, a system for transmitting first electromagnetic waves that propagate on a surface of a component of a transit system, and receiving second electromagnetic waves that propagate on the surface of the component of the transit system. Other embodiments are disclosed. | 2016-04-14 |
20160105219 | POSITIONING GUIDANCE FOR INCREASING RELIABILITY OF NEAR-FIELD COMMUNICATIONS - To promote ease of use, as well as a reduction in bit error rates during extended data exchange between a coupled NFC tag/reader pair, signal strength is measured from a plurality of NFC tag antennas each positioned differently with respect to a common reader field, and differences in signal strength are used to determine an optimum positioning of the tag, or tag emulator, with respect to the reader. Alternative embodiments may include signal time of flight for determining orientation of the NFC antennas within the reader field. Information is generated by the tag, or tag emulator, and output by the tag, or tag emulator, such that a user may direct the positioning of the tag, or tag emulator, for improved communication with the reader. | 2016-04-14 |
20160105220 | NFC CARD READER, SYSTEM INCLUDING NFC CARD READER, AND A METHOD OF OPERATING THE SAME - A near-field communication (NFC) card reader may include a monitor configured to measure an amplitude of a magnetic field induced by an antenna; a gain controller configured to determine an amplification gain based on the measured amplitude of the magnetic field and output a gain control signal; a signal restoration unit configured to receive a carrier signal and a data signal that overlaps with the carrier signal via the antenna, and restore the data signal from the received signals; and a variable-gain amplifier configured to amplify the data signal restored by the signal restoration unit according to the gain control signal. | 2016-04-14 |
20160105221 | METHODS AND APPARATUS FOR COORDINATED MULTIPOINT COMMUNICATION - Systems and techniques for managing helper cells in coordinated multipoint processing. Bandwidth assistance is requested from one or more cells operating in a network. In response to demand price and headroom information provided by a plurality of cells receiving the request, a set of potential helper cells is rank ordered and identified one or more helpers is identified from the ordered set and a candidate helper set is assembled based on bandwidth performance assistance criteria. A new request for bandwidth assistance is made. In response to new demand price and headroom information obtained from the candidate helper set, a determination is made whether sufficient iterations have been performed. If sufficient iterations have not been performed, the process is repeated, and if sufficient iterations have been performed, a requesting cell proceeds to operate while receiving bandwidth assistance from the assembled set. | 2016-04-14 |
20160105222 | APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS - A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for receiving broadcast signals, the apparatus comprises a receiver to receive the broadcast signals, a demodulator to demodulate the received broadcast signals by an OFDM (Orthogonal Frequency Division Multiplex) scheme, a frame parser to parse a signal frame from the demodulated broadcast signals, wherein the signal frame includes at least one service data, a time deinterleaver to time deinterleave each the service data, wherein the time deinterleaving is performed depending on a number of physical paths for each the service data, a damapper to demap the time deinterleaved data and a decoder to decode the demapped service data. | 2016-04-14 |
20160105223 | APPARATUS FOR TRANSMITTING BROADCAST SIGNALS, APPARATUS FOR RECEIVING BROADCAST SIGNALS, METHOD FOR TRANSMITTING BROADCAST SIGNALS AND METHOD FOR RECEIVING BROADCAST SIGNALS - A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for receiving broadcast signals, the apparatus comprises a receiver to receive the broadcast signals, a demodulator to demodulate the received broadcast signals by an OFDM (Orthogonal Frequency Division Multiplex) scheme, a frame parser to parse a signal frame from the demodulated broadcast signals, wherein the signal frame includes at least one service data, a time deinterleaver to time deinterleave each the service data, wherein the time deinterleaving is performed depending on a number of physical paths for each the service data, a damapper to demap the time deinterleaved data and a decoder to decode the demapped service data. | 2016-04-14 |
20160105224 | TRANSMISSION METHOD AND TRANSMISSION APPARATUS - A transmission apparatus includes a plurality of antennas and a transmission scheme determination processor that selects one of either a first transmission scheme of transmitting a plurality of signals including a first amount of data in a frame, respectively, from the plurality of antennas, and a second transmission scheme of transmitting a plurality of signals including a second greater amount of data in a frame, respectively, from the plurality of antennas. The apparatus includes a modulation scheme selection processor that selects a modulation scheme among a plurality of modulation schemes and a control processor that controls the transmission scheme determination processor and the modulation scheme selection processor to change the transmission scheme less frequently than the modulation scheme. A transmitter transmits from the plurality of antennas a signal generated based on the selected transmission scheme and the selected modulation scheme. | 2016-04-14 |
20160105225 | TRANSFORM-DOMAIN FEEDBACK SIGNALING FOR MIMO COMMUNICATION - A control method for a communication network that has a transmitter with an array of transmit antennas and that has at least one receiver communicating with the transmitter. The receiver performs a channel measurement for a receive antenna of the receiver using a signal transmitted from the transmitter to the receiver. The receiver further determines channel coefficients for each of an array of transmit antennas at the transmitter from an output of the channel measurement, and then applies a linear, reversible and orthogonal transform to the channel coefficients, thus ascertaining channel component coefficients indicative of the individual weight of respective channel components in a transform domain. The receiver then selects one or more channel components in the transform domain and communicates to the transmitter a control signal indicative of one or more preferred channel components or a magnitude of one or more channel component coefficients, or both, in quantized form. The transmitter receives the control signal and constructs a beam pattern in the transform domain using the information received from the receiver. | 2016-04-14 |
20160105226 | Methods for Opportunistic Multi-User Beamforming in Collaborative MIMO-SDMA - A system and method for opportunistically designing collaborative beamforming vectors is disclosed for a wireless multiple input, multiple output (MIMO) space division multiple access (SDMA) communication system by sequentially designing beamforming vectors for ranked channels in order to exploit the instantaneous channel conditions to improve per user average SNR performance. Each subscriber station independently transmits information to a base station that allows the base station to determine beamforming vectors for each subscriber station by ranking the subscriber stations by channel strength. Using sequential nullspace methods, the ranked channel matrices are then used to select the channel matrix H | 2016-04-14 |
20160105227 | Data Transmission Method and Apparatus - The present invention discloses a data transmission method and apparatus. A first access point determines a current working uplink receiving beam, and broadcasts an identifier of the current working uplink receiving beam of the first access point, so that when a first station associated with the first access point determines, according to the identifier of the current working uplink receiving beam of the first access point, that a first transmitting beam at which the first station is currently working is the current working uplink receiving beam of the first access point, the first station performs data transmission with the first access point by using the first transmitting beam. The current working uplink receiving beam of the first access point and a current working uplink receiving beam of a second access point do not overlap in space. | 2016-04-14 |