15th week of 2014 patent applcation highlights part 12 |
Patent application number | Title | Published |
20140097401 | SEMICONDUCTOR STRUCTURE FOR EMITTING LIGHT, AND METHOD FOR MANUFACTURING SUCH A STRUCTURE - A semiconductor structure for emitting light including a substrate made of a first semi-conductor material having a first type of conductivity, a first electrical contact, a second semiconductor material, having a second type of conductivity to form a junction, a second electrical contact contacting the second semiconductor material, a polarizer configured to polarize at least one portion of the semiconductor structure, and a plurality of micro- or nano-structures each including a first end connected to the substrate. Each micro- or nano-structure includes at least one portion made from the second semiconductor material, or each micro- or nano-structure having the first type of conductivity, a second end contacting the second semiconductor material to form the junction. | 2014-04-10 |
20140097402 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate ( | 2014-04-10 |
20140097403 | TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING GRAPHENE CHANNEL - According to example embodiments, a tunneling field-effect transistor (TFET) includes a first electrode on a substrate, a semiconductor layer on a portion of the first electrode, a graphene channel on the semiconductor layer, a second electrode on the graphene channel, a gate insulating layer on the graphene channel, and a gate electrode on the gate insulating layer. The first electrode may include a portion that is adjacent to the first area of the substrate. The semiconductor layer may be between the graphene channel and the portion of the first electrode. The graphene channel may extend beyond an edge of at least one of the semiconductor layer and the portion of the first electrode to over the first area of the substrate. | 2014-04-10 |
20140097404 | MEMORY DEVICES INCLUDING GRAPHENE SWITCHING DEVICES - A memory device includes a graphene switching device having a source electrode, a drain electrode and a gate electrode. The graphene switching device includes a Schottky barrier formed between the drain electrode and a channel in a direction from the source electrode toward the drain electrode. The memory device need not include additional storage element. | 2014-04-10 |
20140097405 | SYSTEMS AND DEVICES FOR QUANTUM PROCESSOR ARCHITECTURES - Quantum processor architectures employ unit cells tiled over an area. A unit cell may include first and second sets of qubits where each qubit in the first set crosses at least one qubit in the second set. Each unit cell is positioned proximally adjacent at least one other unit cell. Within each unit cell, at least one qubit is longitudinally shifted with respect to at least one other qubit such that the longitudinally-shifted qubit crosses at least one qubit in a proximally adjacent unit cell. Communicative coupling between qubits is realized through respective intra-cell and inter-cell coupling devices. The longitudinal shifting of qubits and resultant crossing of qubits in proximally adjacent unit cells enables quantum processor architectures that can be better suited to solve certain problems. | 2014-04-10 |
20140097406 | ARYLOXYALKYLCARBOXYLATE SOLVENT COMPOSITIONS FOR INKJET PRINTING OF ORGANIC LAYERS - A liquid composition (e.g., inkjet fluid) for forming an organic layer of an organic electronic device (e.g., an OLED). The liquid composition comprises a small molecule organic semiconductor material mixed in a solvent in which the solvent compound has the following formula: | 2014-04-10 |
20140097407 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display apparatus and a method of manufacturing the same. The organic light emitting display apparatus includes a substrate; an insulating layer formed on the substrate and including a groove; a first electrode formed on the insulating layer so as to overlap at least with the groove; a pixel defining layer covering edges of the first electrode and including an opening that overlaps at least with the groove; an intermediate layer formed on the first electrode to overlap with the opening and including an organic emission layer; and a second electrode formed on the intermediate layer. | 2014-04-10 |
20140097408 | FLEXIBLE DISPLAY APPARATUS - A flexible display apparatus includes a flexible substrate having a bending area, and a non-bending area adjacent the bending area, and having a display area for realizing a visible image, a plurality of wirings at the bending area, and a plurality of insulating patterns between the flexible substrate and the plurality of wirings, wherein respective ones of the plurality of insulating patterns are separated by separate areas. | 2014-04-10 |
20140097409 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - An organic light emitting diode display includes: a substrate, an insulating layer on the substrate; a plurality of pixel electrodes on the insulating layer; a pixel defining layer on the insulating layer overlapping with an end of at least one of the pixel electrodes and defining an emission region and a non-emission region; an organic emission layer on the pixel electrodes; and a common electrode on the organic emission layer, wherein the insulating layer has a plurality of concave portions in the non-emission region adjacent corresponding ones of the pixel electrodes, wherein each of the concave portions has a bottom portion and an inclined portion, and wherein a reflective surface is on at least one of the inclined portions. | 2014-04-10 |
20140097410 | THIN FILM TRANSISTOR SUBSTRATE, METHOD OF REPAIRING THE THIN FILM TRANSISTOR SUBSTRATE, ORGANIC LIGHT EMITTING DISPLAY APPARATUS, AND METHOD OF REPAIRING THE ORGANIC LIGHT EMITTING DISPLAY APPARATUS - A thin film transistor substrate includes a capacitor including a first capacitor electrode and a second capacitor electrode on a substrate, a first wire connected to the first capacitor electrode, a second wire connected to the second capacitor electrode, a first conductive pattern layer spaced apart from the first capacitor electrode and the second capacitor electrode, a second conductive pattern layer spaced apart from the first conductive pattern layer and formed to overlap with the first conductive pattern layer, a first conductive wire pattern connected to the first conductive pattern layer, spaced apart from the second conductive pattern layer, and overlapping with the second wire in at least one area, and a second conductive wire pattern connected to the second conductive pattern layer, spaced apart from the first conductive pattern layer and the first conductive wire pattern, and overlapping with the first wire in at least one area. | 2014-04-10 |
20140097411 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device may include a plurality of scan lines, a plurality of data lines, and a plurality of pixels located at an intersection region of the scan line and the data line, wherein the organic light-emitting display device includes a thin film transistor including a gate electrode on a different layer than a scan line, an active layer on the gate electrode, and source and drain electrodes that are in contact with source and drain regions of the active layer, and a capacitor including a first capacitor electrode on the same layer as the scan line, a second capacitor electrode on the gate electrode, and a third electrode on the same layer as the source and drain electrodes. | 2014-04-10 |
20140097412 | BRIGHTNESS ENHANCED SELF-LUMINOUS DISPLAY - A brightness enhanced self-luminous type display including a self-luminous display panel and a brightness enhancement stacked layer is provided. The self-luminous display panel includes pixels arranged in array, wherein each pixel includes light-emitting sub-pixels displaying different colors. The brightness enhancement stacked layer is disposed on the self-luminous display panel. The brightness enhancement stacked layer includes an absorptive polarizer layer, a phase retardation layer and a reflective polarizer layer. The reflective polarizer layer is between the self-luminous display panel and the phase retardation layer. The phase retardation layer is between the absorptive polarizer layer and the reflective polarizer layer. The reflective polarizer layer includes reflective polarizer blocks arranged in array. Each reflective polarizer block is disposed over one of the light-emitting sub-pixels correspondingly, and a wavelength of maximum intensity of each light-emitting sub-pixel is respectively within a wavelength band of light effectively reflected and polarized by the corresponding reflective polarizer block. | 2014-04-10 |
20140097413 | ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - Embodiments of the present invention provide an organic light emitting diode display panel and a method for manufacturing the same. The manufacturing method comprises: coating a photoresist layer on a transparent substrate with an active array formed; performing exposure on the photoresist layer from one side of the transparent substrate opposed to the photoresist layer, where the scan lines and the at least one kind of lines are used as a mask to prevent exposure of the corresponding photoresist, so that a photoresist remaining region is formed by the photoresist layer; conducting a development treatment on the photoresist layer, so that the photoresist outside the photoresist remaining region is removed and the photoresist in the photoresist remaining region is retained to form the pixel defining layer. The embodiments of the invention may simplify the fabricating flow of the display panel, reduce production costs of the display panel, and increase yield of the display panel. | 2014-04-10 |
20140097414 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device includes a substrate in which a first pixel area and a second pixel area different from each other are defined, a first electrode, a pixel defining layer, a common layer, a first surface processing layer, a second surface processing layer, a first liquid solution layer, a second liquid solution layer, and a second electrode. The first surface processing layer has a first width and is correspondingly included in the first pixel area. The second surface processing layer has a second width different from the first width and is correspondingly included in the second pixel area. The first liquid solution layer has the first width, and the second liquid solution layer has the second width. The first and second liquid solution layers have the same volume and different thicknesses. | 2014-04-10 |
20140097415 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate, an organic light emitting element positioned on the substrate, and a first thin film transistor (TFT) connected to the organic light emitting element and having a driving channel region including at least one groove. | 2014-04-10 |
20140097416 | ORGANIC PHOTOELECTRIC DEVICE AND IMAGE SENSOR - An organic photoelectric device may include a first electrode and a second electrode facing each other and an active layer between the first electrode and the second electrode, the active layer including a compound represented by Chemical Formula 1 and a compound represented by Chemical Formula 2. An image sensor may include the organic photoelectric device. | 2014-04-10 |
20140097417 | Flexible display and method for manufacturing the same - A flexible display and a method for manufacturing the same are disclosed. The flexible display comprises a carrier; an interface layer disposed on a surface of the carrier; and an organic light-emitting diode layer disposed on the interface layer, wherein the interface layer has a thickness of 0.5 μm to 10 μm. | 2014-04-10 |
20140097418 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting diode (OLED) display including a substrate, a plurality of organic light emitting diodes placed on the substrate and each configured to include a first electrode, an organic emission layer, and a second electrode, a filling film placed on the substrate and configured to include an opening corresponding to the organic light emitting diode, and a sealing member formed on the filling film. | 2014-04-10 |
20140097419 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting diode (OLED) display includes a substrate, a first signal line on the substrate, a first thin film transistor connected to the first signal line, a second thin film transistor connected to the first thin film transistor, an interlayer insulating layer on the first thin film transistor and the second thin film transistor, a second signal line on the interlayer insulating layer and connected to a source electrode of the first thin film transistor, a third signal line on the interlayer insulating layer and connected to a source electrode of the second thin film transistor, a first electrode on the interlayer insulating layer and connected to a drain electrode of the second thin film transistor, an organic emission layer on the first electrode, and a second electrode placed on the organic emission layer, wherein the third signal line and the first electrode are made of different metals. | 2014-04-10 |
20140097420 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes: a pixel region; and a peripheral region surrounding the pixel region, the peripheral region including: a gate common voltage line; an interlayer insulating film that covers the gate common voltage line and has a common voltage contact hole exposing part of the gate common voltage line; a data common voltage line that is formed on the interlayer insulating film and comes in contact with the gate common voltage line via the common voltage contact hole; barrier ribs that cover the data common voltage line and have common voltage openings exposing part of the data common voltage line; and a peripheral common electrode that is formed on the barrier ribs and comes in contact with the data common voltage line via the common voltage openings, wherein the barrier ribs are formed at positions corresponding to the boundaries with the common voltage contact hole. | 2014-04-10 |
20140097421 | ORGANIC EL DISPLAY - Disclosed is a coated type organic EL display wherein the light extraction efficiencies of all organic light-emitting elements are improved even when the organic light-emitting elements have different organic light-emitting layers for respective emission colors. Specifically disclosed is an organic EL display which comprises a substrate and a red organic light-emitting element (R), a green organic light-emitting element (G), and a blue organic light-emitting element (B) arranged on the substrate. Each organic light-emitting element has a pixel electrode that is a reflective electrode, a functional layer formed on the pixel electrode by coating, an organic light-emitting layer arranged on the functional layer, a counter electrode that is a transparent electrode arranged on the organic light-emitting layer, and a tapered bank that defines the functional layer formed by coating. A dimension of a bank-to-bank gap at a top of the bank differs among the R, G, and B elements. | 2014-04-10 |
20140097422 | LIGHTING DEVICE - For integration of light-emitting elements and for suppression of a voltage drop, plural stages of light-emitting element units provided over a substrate having an insulating surface and each including a plurality of light-emitting elements which is connected in parallel are connected in series. Further, besides a lead wiring with a large thickness, a plurality of auxiliary wirings with different widths and different thicknesses is used, and the arrangement of the wirings, electrodes of the light-emitting elements, and the like is optimized. Note that in the lighting device, light emitted from the light-emitting element passes through the substrate having an insulating surface and then is extracted. | 2014-04-10 |
20140097423 | ORGANIC LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE INCLUDING SAME - The present invention relates to an organic light-emitting element comprising a first electrode, a second electrode, and an organic layer interposed between said first electrode and said second electrode, and to a light-emitting device including the same, wherein in the organic light-emitting element, a connection electrode for electrically connecting two or more elements in serial is formed on a non-light-emitting surface of said organic light-emitting element. The invention can electrically connect a plurality of organic light-emitting elements easily, and can be implemented as a large-scale lighting or display device or the like. | 2014-04-10 |
20140097424 | PLANAR LIGHT EMITTING DEVICE HAVING STRUCTURE FOR BRIGHTNESS UNIFORMITY AND A COMPACT AREA OF NON-LIGHT EMITTING PART - Planar light emitting device includes: anode and cathode feeding parts formed on first surface side of transparent substrate and electrically connected to quadrilateral planar anode and cathode, respectively; quadrilateral frame shaped anode auxiliary electrode formed at the whole circumference of surface of the planar anode; anode feeding auxiliary electrode integrally and continuously formed to the auxiliary electrode and laminated on anode feeding part. Two distances between predetermined two parallel sides of four sides of a light emitting part and outer circumferential edges of the transparent substrate on sides adjacent to the two parallel sides, respectively are smaller than two distances between the other two parallel sides and the outer circumferential edges of the transparent substrate on sides adjacent to the other two parallel sides, respectively. | 2014-04-10 |
20140097425 | ORGANIC EL ELEMENT, ORGANIC EL PANEL HAVING ORGANIC EL ELEMENT, ORGANIC EL LIGHT-EMITTING APPARATUS, AND ORGANIC EL DISPLAY APPARATUS - An organic EL element comprises: an anode; a cathode; a buffer layer; and a hole injection layer between the anode and the buffer layer. The hole injection layer includes a nickel oxide that includes both nickel atoms with a valence of three and nickel atoms with a valence of two. At least part of the hole injection layer has a crystal structure A | 2014-04-10 |
20140097426 | TRANSISTORS - This invention comprises a field effect transistor which comprises source and drain electrodes ( | 2014-04-10 |
20140097427 | ORGANIC ELECTROLUMINESCENCE ELEMENT AND PRODUCTION METHOD THEREFOR - The organic electroluminescence element of the present invention includes: a first substrate; a second substrate facing the first substrate; an element member between the first and second substrates; first and second extension electrodes on first and second inner surfaces of the first and second substrates facing the element member; and an insulating member having an electrically insulating property. The element member includes: a functional layer including a light-emitting layer and having first and second surfaces in a thickness direction; and first and second electrode layers on the respective first and second surfaces of the functional layer. The element member is between the first and second extension electrodes such that parts of the first and second electrode layers are in contact with the first and second extension electrodes respectively. The insulating member is between the first and second inner surfaces of the respective first and second substrates. | 2014-04-10 |
20140097428 | OXIDE SEMICONDUCTOR FILM, TRANSISTOR, AND SEMICONDUCTOR DEVICE - To provide an oxide semiconductor film which has high stability and does not easily cause variation in electric characteristics of a transistor, a transistor including the oxide semiconductor film in its channel formation region, and a highly reliable semiconductor device including the transistor. The oxide semiconductor film including indium includes a crystal part whose c-axis is substantially perpendicular to a surface of the oxide semiconductor film. In the crystal part, the length of a crystal arrangement part containing indium and oxygen on a plane perpendicular to the c-axis is more than 1.5 nm. Further, the semiconductor device includes the transistor including the oxide semiconductor film in its channel formation region. | 2014-04-10 |
20140097429 | ARRAY SUBSTRATE FOR FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE ARRAY SUBSTRATE - In an aspect, an array substrate for a flexible display device and a method of manufacturing the array substrate, the method including operations of arranging at least one lower protective film on which a plurality of display units that are covered by thin-film encapsulation (TFE) units are arrayed; performing half cutting and full cutting on the at least one lower protective film; and completing the manufacture of each of the plurality of display units by removing remaining parts on the at least one lower protective film from the half cutting and full cutting is provided. | 2014-04-10 |
20140097430 | ARRAY SUBSTRATE FOR FLEXIBLE DISPLAY DEVICE - An array substrate for a flexible display device, the array substrate including a mother substrate, a plurality of display units separated on the mother substrate, in which the plurality of display units include display regions that display images and non-display regions that extend from the display regions to edges of each of the plurality of display units, respectively, encapsulation units covering the display regions of the plurality of display units, respectively, a plurality of testing wires in a wire region between adjacent display units from among the plurality of display units, in which the plurality of testing wires are electrically connected to each of the plurality of display units, and crack preventing units in the non-display regions between edges of the encapsulation units and the edges of each of the plurality of display units, respectively. | 2014-04-10 |
20140097431 | SEMICONDUCTOR DEVICES AND PROCESSING METHODS - A method for processing a semiconductor device in accordance with various embodiments may include: providing a semiconductor device having a first pad and a second pad electrically disconnected from the first pad; applying at least one electrical test potential to at least one of the first pad and the second pad; and electrically connecting the first pad and the second pad to one another after applying the at least one electrical test potential. | 2014-04-10 |
20140097432 | SHEET OF SEMICONDUCTING MATERIAL, LAMINATE, AND SYSTEM AND METHODS FOR FORMING SAME - Methods of forming a laminate comprising a sheet of semiconductor material utilize a system. The system comprises a fibrous sheet, a guide member for guiding the fibrous sheet, and a melt of a semiconductor material. The sheet of semiconductor material and a laminate comprising the fibrous sheet and the sheet of semiconductor material are also included. | 2014-04-10 |
20140097433 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE DEVICE - A semiconductor device includes a substrate; a carrier traveling layer formed on the substrate, made of first group III nitride semiconductor, and containing carriers traveling in a direction along a principal surface of the substrate; a barrier layer formed on the carrier traveling layer and made of second group III nitride semiconductor having a wider band gap than the first group III nitride semiconductor; and an electrode formed on the barrier layer. The device further includes a cap layer formed on the barrier layer at a side of the electrode, and made of third group III nitride semiconductor containing a mixture of single crystals and polycrystals. | 2014-04-10 |
20140097434 | BACK-END-OF-LINE METAL-OXIDE-SEMICONDUCTOR VARACTORS - Device structures, design structures, and fabrication methods for a varactor. The device structure includes a first electrode formed on a dielectric layer, and a semiconductor body formed on the first electrode. The semiconductor body is comprised of a silicon-containing semiconductor material in an amorphous state or a polycrystalline state. The device structure further includes an electrode insulator formed on the semiconductor body and a second electrode formed on the electrode insulator. | 2014-04-10 |
20140097435 | NAND Memory Constructions and Methods of Forming NAND Memory Constructions - Some embodiments include NAND memory constructions. The constructions may contain semiconductor material pillars extending upwardly between dielectric regions, with individual pillars having a pair of opposing vertically-extending sides along a cross-section. First conductivity type regions may be along first sides of the pillars, and second conductivity type regions may be along second sides of the individual pillars; with the second conductivity type regions contacting interconnect lines. Vertical NAND strings may be over the pillars, and select devices may selectively couple the NAND strings with the interconnect lines. The select devices may have vertical channels directly against the semiconductor material pillars and directly against upper regions of the first and second conductivity type regions. Some embodiments include methods of forming NAND memory constructions. | 2014-04-10 |
20140097436 | THIN-FILM TRANSISTOR PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF - A thin-film transistor (TFT) pixel structure and manufacturing method thereof are described. The TFT pixel structure includes a substrate, first conducting layer, gate insulation layer, channel layer, second conducting layer, contact holes, passivation layer and transparent conducting layer. The method includes: forming gate insulation layer on substrate and covering scan lines, gate electrode layer and shielding layer; forming the second conducting layer on substrate; and patterning the second conducting layer for generating data lines, drain layer, and source layer on channel layer to construct thin-film transistors, channel layer being disposed between the shielding layer and source layer, wherein when light beam illuminates on substrate, the shielding layer is correspondingly disposed to channel layer along an emitting direction of the light beam for shielding channel layer from light beam by the shielding layer to solve the problems of abnormal display quality and image sticking and maintain aperture rate. | 2014-04-10 |
20140097437 | THIN FILM TRANSISTOR, DISPLAY DEVICE AND MANUFACTURING THEREOF, DISPLAY APPARATUS - A thin-film transistor (TFT) comprises a gate electrode, a gate insulating layer, a source electrode and a drain electrode which are formed on a base substrate, the source electrode and the drain electrode are disposed on different layers and isolated from each other through a semiconductor connecting section made of an oxide semiconductor material; a position of the semiconductor connecting section corresponds to a position of the gate electrode; and at least one part of the source electrode and at least one part of the drain electrode overlap each other at a position corresponding to the semiconductor connecting section. A display device comprising the TFT and a display device comprising the display device are also disclosed. | 2014-04-10 |
20140097438 | LIGHT EMITTING DEVICE - An object of the present invention is to provide a light emitting device in which variations in an emission spectrum depending on a viewing angle with respect to a side from which luminescence is extracted are decreased. A light emitting device according to the invention has a transistor, an insulating layer covering the transistor and a light emitting element provided in an opening of the insulating layer. The transistor and the light emitting element are electronically connected through a connecting portion. Additionally, the connecting portion is connected to the transistor through a contact hole penetrating the insulating layer. Note that the insulating layer may be a single layer or a multilayer in which a plurality of layers including different substances is laminated. | 2014-04-10 |
20140097439 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME - A TFT array substrate includes: a first insulation layer over a semiconductor layer; a second insulation layer over a plurality of first gate wires formed on the first insulation layer; a third insulation layer over a plurality of second gate wires formed on the second insulation layer; a cover metal formed over the third insulation layer and contacting the semiconductor layer through a contact hole that passes through the first, second and third insulation layers; a fourth insulation layer over the cover metal; a protection layer formed over the fourth insulation layer; and an anode electrode formed over the protection layer and contacting the cover metal through a via hole that passes through the protection layer, the fourth insulation layer, and the contact hole. | 2014-04-10 |
20140097440 | FLEXIBLE DISPLAY PANEL - A flexible display panel includes a first display region that is flat, second display regions located at both sides of the first display region and curved by a predetermined angle, a plurality of pixels formed in the first display region, and a plurality of pixels formed in the second display regions, Each of the plurality of pixels formed in the first display region and the second display regions includes a light-emitting diode and a driving thin-film transistor (TFT) connected to the light-emitting diode, the driving TFT supplying a driving current to the light-emitting diode. A size of the driving TFT varies for each of the plurality of pixels formed in the second display regions so that driving currents supplied by driving TFTs in the second display regions vary in one direction with respect to boundaries between the first display region and the second display regions. | 2014-04-10 |
20140097441 | DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES - Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate. | 2014-04-10 |
20140097442 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a silicon substrate, a nucleation layer, a first buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The first buffer layer is disposed on the nucleation layer. The first buffer layer includes a dopant and Gallium, and an atomic radius of the dopant is larger than an atomic radius of Gallium. The first type nitride semiconductor layer is disposed over the first buffer layer. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer. | 2014-04-10 |
20140097443 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor stacked layer, a light-emitting layer and a second type nitride semiconductor layer. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor stacked layer is disposed on the buffer layer. The first type nitride semiconductor stacked layer being a plurality of lattice mismatch stacked layers includes a plurality of first nitride semiconductor layers and a plurality of second nitride semiconductor layers. The first nitride semiconductor layers and the second nitride semiconductor layers are stacked alternately, and the first nitride semiconductor layers and the second nitride semiconductor layers are different material. The light-emitting layer is disposed on the first type nitride semiconductor stacked layer. The second type nitride semiconductor layer is disposed on the light-emitting layer. | 2014-04-10 |
20140097444 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a silicon substrate, a nucleation layer, a buffer layer, a first type nitride semiconductor layer, a light-emitting layer and a second type nitride semiconductor layer is provided. The nucleation layer is disposed on the silicon substrate. The buffer layer is disposed on the nucleation layer. The first type nitride semiconductor layer is disposed on the buffer layer. The first type nitride semiconductor layer is doped with a first type dopant, at least one of the buffer layer and the first type nitride semiconductor layer comprises a codopant distributed therein, and an atomic radius of the codopant is larger than an atomic radius of the first type dopant. The light-emitting layer is disposed on the first type nitride semiconductor layer. The second type nitride semiconductor layer is disposed on the light-emitting layer, the second type nitride semiconductor layer comprising a second type dopant. | 2014-04-10 |
20140097445 | SEMICONDUCTOR DEVICE - A transistor SEL is formed by using a compound semiconductor layer (channel layer CNL). The channel layer CNL is formed over a buffer layer BUF. In a first direction where a drain electrode DRE, a gate electrode GE, and a source electrode SOE of the transistor SEL are arranged, at least a portion of the buried electrode BE is situated on the side opposing the source electrode SOE with reference to the gate electrode GE. The buried electrode BE is connected to the source electrode SOE of the transistor SEL. The top end of the buried electrode BE intrudes into the buffer layer BUF. | 2014-04-10 |
20140097446 | Gallium Nitride Devices with Gallium Nitride Alloy Intermediate Layer - The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications. | 2014-04-10 |
20140097447 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device and method of manufacturing the semiconductor, including an n type buffer layer disposed on a first surface of an n+ type silicon carbide substrate, an n− type epitaxial layer disposed on the n type buffer layer, a first type of trench disposed on each side of a second type of trench, wherein the trenches are disposed in the n− type epitaxial layer, an n+ region disposed on the n− type epitaxial layer, a p+ region disposed in each first type of trench, a gate insulating layer disposed in the second trench, a gate material disposed on the gate insulating layer, an oxidation layer disposed on the gate material, a source electrode disposed on the n+ region, oxidation layer, and p+ region, and a drain electrode disposed on a second surface of the n+ type silicon carbide substrate. | 2014-04-10 |
20140097448 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a drift layer including a trench formed on a semiconductor substrate. A well in the drift layer overlaps an edge of the trench, and at least one gate electrode is formed at this overlapping edge region. The drift layer and semiconductor may be doped with a first type of impurity and the well may be doped with a second type of impurity. Through this arrangement, an improved distribution of carriers may be formed in the drift layer. | 2014-04-10 |
20140097449 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress. | 2014-04-10 |
20140097450 | Diffused Junction Termination Structures for Silicon Carbide Devices - An electronic device includes a silicon carbide layer having a first conductivity type and a main junction adjacent a surface of the silicon carbide layer, and a junction termination region at the surface of the silicon carbide layer adjacent the main junction. Charge in the junction termination region decreases with lateral distance from the main junction, and a maximum charge in the junction termination region may be less than about 2×10 | 2014-04-10 |
20140097451 | PROXIMITY SENSOR AND CIRCUIT LAYOUT METHOD THEREOF - A proximity sensor and a circuit layout method thereof are disclosed. The proximity sensor includes a light sensor and a light emitting unit. The light sensor includes a semiconductor substrate and a bonding pad. The semiconductor substrate has a first circuit region. At least one semiconductor device is disposed in the first circuit region. The bonding pad is disposed above the first circuit region and a gap is existed between the bonding pad and the at least one semiconductor device. The bonding pad is connected to the semiconductor substrate out of the first circuit region. The light emitting unit is disposed on the bonding pad of the light sensor. | 2014-04-10 |
20140097452 | LUMINESCENCE DEVICE - A luminescence device used in a backlight unit for lighting or displaying may include: a substrate including at least two electrode patterns and LED chips which are provided over the substrate and include a phosphor provided thereon. A dam is provided over the substrate, and an encapsulation layer is provided over the substrate. The dam is spaced from the LED Chips, and the substrate comprises a direct copper bonding (DCB) substrate including a first copper layer, a second copper layer and a substrate body. | 2014-04-10 |
20140097453 | LIGHT EMITTING DEVICES FOR LIGHT EMITTING DIODES (LEDS) - Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a substrate, one or more LEDs disposed over the substrate, and the LEDs can include electrical connectors for connecting to an electrical element. A light emitting device can further include a retention material disposed over the substrate and the retention material can be disposed over at least a portion of the electrical connectors. The LEDs can be connected in a pattern that is non-linear. | 2014-04-10 |
20140097454 | LIGHT EMITTING DEVICES FOR LIGHT EMITTING DIODES (LEDS) - Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a submount and a light emission area disposed over the submount. The light emission area can include one or more light emitting diodes (LEDs), a fillet at least partially disposed about the one or more the LEDs, and filling material. The filling material can be disposed over a portion of the one or more LEDs and a portion of the fillet. | 2014-04-10 |
20140097455 | SEMICONDUCTOR DEVICE AND DISPLAY APPARATUS - A semiconductor device according to an aspect of the present invention includes: a semiconductor layer including a channel region and a contact region; a pattern of a first conducting layer disposed at a position which overlaps with the channel region; a gate line formed in one of a second conducting layer or a third conducting layer, and connected to the pattern of the first conducting layer; and a source line formed in the other of the second conducting layer and the third conducting layer, and connected to the contact region. | 2014-04-10 |
20140097456 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE AND METHOD FOR PRODUCING THE SAME - A method for producing a light-emitting device includes the steps of: forming a layer containing In on a substrate in a reactor in which a Mg-containing raw material has been used; and forming an active layer including a nitride semiconductor on the layer containing In. | 2014-04-10 |
20140097457 | SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate and a semiconductor unit. The substrate includes a base and at least one pattern unit. The pattern unit includes a plurality of surrounding members disposed on the base and a central member surrounded by the surrounding members. A geometrical center is collectively defined by the surrounding members, an interval between the central member and the geometrical center is larger than zero. The semiconductor unit is disposed on the substrate and is operating with a current. | 2014-04-10 |
20140097458 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE USING THE SAME - There is provided a semiconductor light emitting device, a method of manufacturing the same, and a semiconductor light emitting device package using the same. A semiconductor light emitting device having a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a second electrode layer, and insulating layer, a first electrode layer, and a conductive substrate sequentially laminated, wherein the second electrode layer has an exposed area at the interface between the second electrode layer and the second conductivity type semiconductor layer, and the first electrode layer comprises at least one contact hole electrically connected to the first conductivity type semiconductor layer, electrically insulated from the second conductivity type semiconductor layer and the active layer, and extending from one surface of the first electrode layer to at least part of the first conductivity type semiconductor layer. | 2014-04-10 |
20140097459 | OPTICAL ELEMENT MODULE, OPTICAL TRANSMISSION MODULE, AND METHOD OF MANUFACTURING OPTICAL TRANSMISSION MODULE - An optical element module includes an optical element having a light receiving unit configured to input an optical signal or a light emitting unit configured to output an optical signal, a board on which the optical element is mounted, and a guide holding member that has a through hole into which an optical fiber is configured to be inserted for inputting and outputting the optical signal to or from the light receiving unit or the light emitting unit of the optical element, and is mounted and arranged to be aligned with the optical element in a thickness direction of the board. The through hole has a cylindrical shape and has substantially the same diameter as an outer diameter of the optical fiber. A diameter of the light receiving unit or the light emitting unit is smaller than that of the optical fiber. | 2014-04-10 |
20140097460 | LED DEVICE - An LED device comprises a substrate, an LED chip and a luminescent conversion layer. The substrate comprises a first electrode, a second electrode and a reflector located on top faces of the first and the second electrodes. The LED chip is disposed on the first electrode and electrically connected to the first and the second electrodes. The luminescent conversion layer is located inside the reflector and comprises a first luminescent conversion layer and a second luminescent conversion layer with different specific gravities. | 2014-04-10 |
20140097461 | PHOSPHOR SHEET-FORMING RESIN COMPOSITION - A phosphor sheet-forming resin composition uses a low-cost resin material having high light fastness and low visible light absorption and is capable of providing a phosphor sheet at low cost with deterioration of a phosphor due to moisture being suppressed. The phosphor sheet-forming resin composition contains a film-forming resin composition and a powdery phosphor that emits fluorescence when irradiated with excitation light. The film-forming resin composition contains a hydrogenated styrene-based copolymer, and uses a sulfide-based phosphor as the phosphor. Examples of the hydrogenated styrene-based copolymer include hydrogenated products of styrene-ethylene-butylene-styrene block copolymers. CaS:Eu is used as a preferred sulfide-based phosphor. | 2014-04-10 |
20140097462 | SEMICONDUCTOR LIGHT-EMITTING APPARATUS AND METHOD OF FABRICATING THE SAME - A light-emitting apparatus has a light-emitting device and a supporting board. The light-emitting device has a pair of n-electrodes with a p-electrode therebetween, on the same plane. The supporting board includes an insulating substrate on which positive and negative electrodes are formed, opposing to the p- and n-electrodes of the light-emitting device, respectively. Bonding members bond the p- and n-electrodes with the positive and negative electrodes, respectively. The positive electrode on the supporting board is formed within the width region of the p-electrode and narrower in width than the width of the p-electrode, in a cross-section along a line extending through the pair of n-electrodes. The negative electrodes oppose to the n-electrodes, respectively, with the same widths, or with that side face of each of the negative electrodes which faces the positive electrode being retracted outwardly from that side face of each of the n-electrodes which faces the p-electrode. | 2014-04-10 |
20140097463 | ANISOTROPIC CONDUCTIVE ADHESIVE - An anisotropic conductive adhesive includes an epoxy adhesive containing an epoxy compound and a curing agent and conducive particles dispersed in the epoxy adhesive. When elastic moduluses at 35° C., 55° C., 95° C., and 150° C. of a cured product of the anisotropic conductive adhesive are denoted by EM | 2014-04-10 |
20140097464 | Electronic Device for Protection against Electrostatic Discharges, with a Concentric Structure - The component incorporates, in topological terms, a scalable number of triac structures in a concentric annular arrangement. The component can be used with an electronic device to protect against electrostatic discharges. For example, the components can be used to protect the input/output pad, the first power supply terminal, and the second power supply terminal of an integrated circuit against electrostatic discharges. | 2014-04-10 |
20140097465 | SILICON CONTROLLED RECTIFIER (SCR) DEVICE FOR BULK FINFET TECHNOLOGY - Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed. | 2014-04-10 |
20140097466 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device includes a p-type collector region, a drift region arranged on the collector region, a base region arranged on the drift region, an emitter region arranged on the base region, a gate oxide film arranged on the bottom surface and side surface of a trench which penetrates the emitter region and the base region, and a gate electrode embedded in the inside of the trench so as to be opposed to the base region while interposing the gate oxide film therebetween, wherein the position of the lower surface of the base region is shallower in the region brought into contact with the gate oxide film than in the region spaced apart from the gate oxide film. | 2014-04-10 |
20140097467 | COMPRESSIVELY STRAINED SOI SUBSTRATE - A method of forming a strained silicon-on-insulator includes forming a first wafer having a compressively strained active semiconductor layer, forming a second wafer having an insulation layer formed above a bulk semiconductor layer, and bonding the compressively strained active semiconductor layer of the first wafer to the insulation layer of the second wafer. | 2014-04-10 |
20140097468 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer ( | 2014-04-10 |
20140097469 | HYDROGEN MITIGATION SCHEMES IN THE PASSIVATION OF ADVANCED DEVICES - Embodiments of a Silicon Nitride (SiN) passivation structure for a semiconductor device and methods of fabrication thereof are disclosed. In general, a semiconductor device includes a semiconductor body and a SiN passivation structure over a surface of the semiconductor body. In one embodiment, the SiN passivation structure includes one or more Hydrogen-free SiN layers on, and preferably directly on, the surface of the semiconductor body, a Hydrogen barrier layer on, and preferably directly on, a surface of the one or more Hydrogen-free SiN layers opposite the semiconductor body, and a Chemical Vapor Deposition (CVD) SiN layer on, and preferably directly on, a surface of the Hydrogen barrier layer opposite the one or more Hydrogen-free SiN layers. The Hydrogen barrier layer preferably includes one or more oxide layers of the same or different compositions. Further, in one embodiment, the Hydrogen barrier layer is formed by Atomic Layer Deposition (ALD). | 2014-04-10 |
20140097470 | HIGH-ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - According to example embodiments, a HEMT includes a channel supply layer on a channel layer, a p-type semiconductor structure on the channel supply layer, a gate electrode on the p-type semiconductor structure, and source and drain electrodes spaced apart from two sides of the gate electrode respectively. The channel supply layer may have a higher energy bandgap than the channel layer. The p-type semiconductor structure may have an energy bandgap that is different than the channel supply layer. The p-type semiconductor structure may include a hole injection layer (HIL) on the channel supply layer and be configured to inject holes into at least one of the channel layer and the channel supply in an on state. The p-type semiconductor structure may include a depletion forming layer on part of the HIL. The depletion forming layer may have a dopant concentration that is different than the dopant concentration of the HIL. | 2014-04-10 |
20140097471 | Active Area Shaping of III-Nitride Devices Utilizing A Field Plate Defined By A Dielectric Body - In an exemplary implementation, a III-nitride semiconductor device includes a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas. The III-nitride semiconductor device further includes a gate well formed in a dielectric body, the dielectric body situated over the III-nitride heterojunction. The III-nitride semiconductor device also includes a gate arrangement situated in the gate well and including a gate electrode and a field plate. The field plate includes at least two steps, the at least two steps being defined in the dielectric body. | 2014-04-10 |
20140097472 | BIPOLAR FIELD EFFECT TRANSISTOR STRUCTURES AND METHODS OF FORMING THE SAME - Bipolar field effect transistor (BiFET) structures and methods of forming the same are provided. In one embodiment, an apparatus includes a substrate and a plurality of epitaxial layers disposed over the substrate. The plurality of epitaxial layers includes a first epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer. The first epitaxial layer includes at least a portion of a channel of a first field effect transistor (FET) and the third epitaxial layer includes at least a portion of a channel of a second FET. | 2014-04-10 |
20140097473 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an electron transit layer formed on a substrate and of a group III nitride-based compound semiconductor; an electron supply layer formed on the electron transit layer and of a group III nitride-based compound semiconductor having a higher band gap energy than the transit layer; a field plate layer formed on the supply layer, formed of a non-p-type group III nitride-based compound semiconductor, and having a lower band gap energy than the supply layer; a first electrode forming an ohmic contact with a two-dimensional electron gas layer in the transit layer at an interface thereof with the supply layer; and a second electrode forming a Schottky contact with the electron gas layer. The second electrode forms an ohmic contact, at a side wall of the field plate layer, with two-dimensional hole gas in the field plate layer at an interface thereof with the supply layer. | 2014-04-10 |
20140097474 | SPIN MOSFET AND RECONFIGURABLE LOGIC CIRCUIT - A spin MOSFET includes a first ferromagnetic layer having a fixed magnetization direction, a first tunnel barrier, a second ferromagnetic layer having a variable magnetization direction, and a nonmagnetic semiconductor layer provided in that order on a substrate. The nonmagnetic semiconductor layer has lower and upper faces and a side faces serving as a channel. A third ferromagnetic layer having a fixed magnetization direction is provided on the upper face of the nonmagnetic semiconductor layer, wherein the magnetization direction of each of the first to third ferromagnetic layers is in parallel or antiparallel to a direction from the third ferromagnetic layer to the first ferromagnetic layer. A nonmagnetic layer is provided on the third ferromagnetic layer, and a gate insulating film and gate electrode are provided in that order on the side face of the nonmagnetic semiconductor layer. | 2014-04-10 |
20140097475 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a first metal layer on a carrier; forming an insulation layer directly on the first metal layer; exposing a portion of the first metal layer for directly attaching to a die interconnect connecting to an integrated circuit; forming a second metal layer directly on the insulation layer opposite the side of the insulation layer exposed by removing the carrier; and forming a protective layer directly on the insulation layer and the second metal layer, the protective layer exposing a portion of the second metal layer for directly attaching an external interconnect. | 2014-04-10 |
20140097476 | SOLID-STATE IMAGING APPARATUS AND ELECTRONIC APPARATUS - A solid-state imaging apparatus includes a charge accumulation unit, a signal voltage detection unit, a transfer transistor, and a pinning layer. The charge accumulation unit accumulates photoelectrically converted charges, and is formed on a silicon substrate. The signal voltage detection unit detects signal voltage corresponding to the charges accumulated in the charge accumulation unit, and is formed on the silicon substrate. The transfer transistor transfers the charges accumulated in the charge accumulation unit to the signal voltage detection unit, and is formed on the silicon substrate. The pinning layer pins a surface of the silicon substrate so that the surface is filled with electron holes, and is formed directly on the silicon substrate at a gate end at which a gate electrode of the transfer transistor and the charge accumulation unit come into contact with each other on the silicon substrate. | 2014-04-10 |
20140097477 | MAGNETIC RANDOM ACCESS MEMORY AND A METHOD OF FABRICATING THE SAME - An aspect of the present embodiment, there is provided magnetic random access memory device including a semiconductor substrate, a selection transistor on the semiconductor substrate, the selection transistor including a diffusion layer, a contact plug on diffusion layer, an amorphous film on the contact plug, a lower electrode provided on the amorphous film, a first magnetic layer, a nonmagnetic layer, a second magnetic layer, an upper electrode stacked in an order and a sidewall contact film on the contact plug, the sidewall contact film being in contact with a sidewall of the upper electrode. | 2014-04-10 |
20140097478 | REDUCED CHARGE TRANSISTOR - Representative implementations of devices and techniques provide a reduced charge transistor arrangement. The capacitance and/or charge of a transistor structure may be reduced by minimizing an overlap of a top gate with respect to a drain of the transistor. | 2014-04-10 |
20140097479 | PILLARS FOR VERTICAL TRANSISTORS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon. | 2014-04-10 |
20140097480 | METHOD FOR MANUFACTURING A MEMORY CELL, A METHOD FOR MANUFACTURING A MEMORY CELL ARRANGEMENT, AND A MEMORY CELL - A method for manufacturing a memory cell in accordance with various embodiments may include: forming at least one charge storing memory cell structure over a substrate, the charge storing memory cell structure having a first sidewall and a second sidewall opposite the first sidewall; forming an electrically conductive layer over the substrate and the charge storing memory cell structure; patterning the electrically conductive layer to form a spacer at the first sidewall and a blocking structure at the second sidewall of the charge storing memory cell structure; implanting first dopant atoms to form a first doped region in the substrate proximate the spacer, wherein the first dopant atoms are blocked by the blocking structure; removing the blocking structure after implanting the first dopant atoms; implanting second dopant atoms to form a second doped region in the substrate proximate the second sidewall of the charge storing memory cell structure. | 2014-04-10 |
20140097481 | NON-VOLATILE MEMORY WITH VERTICAL SELECTION TRANSISTORS - The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors. | 2014-04-10 |
20140097482 | Full Metal Gate Replacement Process for NAND Flash Memory - A NAND flash memory chip is made by forming sacrificial control gate structures and sacrificial select structures, and subsequently replacing these sacrificial structures with metal. Filler structures are formed between sacrificial control gate structures and are subsequently removed to form air gaps between neighboring control gate lines and between floating gates. | 2014-04-10 |
20140097483 | 3-D SINGLE FLOATING GATE NON-VOLATILE MEMORY DEVICE - A 3-D Single Floating Gate Non-Volatile Memory (SFGNVM) device based on the 3-D fin Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is disclosed. The disclosed Non-Volatile Memory (NVM) device consists of a pair of semiconductor fins and one floating metal gate. The floating metal gate for storing electrical charges to alter the threshold voltage of the fin MOSFET crosses over the pair of semiconductor fins on top of coupling and tunneling dielectrics above the surfaces of the two semiconductor fins. One semiconductor fin with the same type impurity forms the control gate of the non-volatile memory device. The other semiconductor fin is doped with opposite type of impurity in the channel regions under the metal floating gate and with the same type of impurity in the source and drain regions on the sides of the crossed metal floating gate. | 2014-04-10 |
20140097484 | VERTICAL TYPE MEMORY DEVICE - A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections. | 2014-04-10 |
20140097485 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a first stacked structure body, a first semiconductor layer, a first organic film, a first semiconductor-side insulating film, and a first electrode-side insulating film. The first stacked structure body includes a plurality of first electrode films stacked along a first direction and a first inter-electrode insulating film provided between the first electrode films. The first semiconductor layer is opposed to side faces of the first electrode films. The first organic film is provided between the side faces of the first electrode films and the first semiconductor layer and containing an organic compound. The first semiconductor-side insulating film is provided between the first organic film and the first semiconductor layer. The first electrode-side insulating film provided between the first organic film and the side faces of the first electrode films. | 2014-04-10 |
20140097486 | Semiconductor Constructions, NAND Unit Cells, Methods Of Forming Semiconductor Constructions, And Methods Of Forming NAND Unit Cells - Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. | 2014-04-10 |
20140097487 | PLASMA DOPING A NON-PLANAR SEMICONDUCTOR DEVICE - In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different. | 2014-04-10 |
20140097488 | Method for Producing a Semiconductor Device and Field-Effect Semiconductor Device - A method for producing a semiconductor device is provided. The method includes providing a wafer including a main surface and a silicon layer arranged at the main surface and having a nitrogen concentration of at least about 3*10 | 2014-04-10 |
20140097489 | SEMICONDUCTOR DEVICE HAVING LOCALIZED CHARGE BALANCE STRUCTURE AND METHOD - In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region. | 2014-04-10 |
20140097490 | SEMICONDUCTOR DEVICE - A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator. | 2014-04-10 |
20140097491 | Dielectrically Terminated Superjunction FET - A dielectrically-terminated superjunction field-effect transistor (FET) architecture for use in high voltage applications. The architecture adds a dielectric termination to general features of a high voltage superjunction process. The dielectrically-terminated FET (DFET) is more compact and more manufacturable than a conventional, semiconductor-terminated superjunction FET. | 2014-04-10 |
20140097492 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a dielectric layer, a dielectric structure and an electrode structure. The dielectric layer is on an upper substrate surface of the semiconductor substrate. The dielectric structure and the semiconductor substrate have opposing first and second interfaces therebetween. The electrode structure comprises an electrode truck portion and at least one electrode branch portion. The at least one electrode branch portion is extended from the electrode truck portion down into the dielectric structure. The at least one electrode branch portion and the first interface have the smallest gap distance substantially bigger than 300 Å therebetween. | 2014-04-10 |
20140097493 | CELLS INCLUDING AT LEAST ONE FIN FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR INTEGRATED CIRCUITS INCLUDING THE SAME - A semiconductor integrated circuit (IC) may comprise at least one cell comprising at least one fin field-effect transistor (FET). The at least one cell may comprise a plurality of fins that extend in a first direction and are arranged in parallel to each other in a second direction that is perpendicular to the first direction. A size of the at least one cell in the second direction may correspond to a number and a pitch of the plurality of fins. | 2014-04-10 |
20140097494 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes forming a fin-shaped silicon layer, a first insulating film around the fin-shaped silicon layer, a pillar-shaped silicon layer on the fin-shaped silicon layer, a gate electrode and a gate insulating film around the pillar-shaped silicon layer, a gate line connected to the gate electrode, a first diffusion layer in an upper portion of the pillar-shaped silicon layer, a second diffusion layer in a lower portion of the pillar-shaped silicon layer and an upper portion of the fin-shaped silicon layer, and a first silicide and a second silicide on the first diffusion layer and the second diffusion layer; an interlayer insulating film to expose an upper portion of the pillar-shaped silicon layer; etching the interlayer insulating film to form a contact hole; depositing a metal to form the first contact on the second silicide; and performing etching to form the metal wire. | 2014-04-10 |
20140097495 | APPARATUS AND METHODS FOR IMPROVING MULTI-GATE DEVICE PERFORMANCE - Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed. | 2014-04-10 |
20140097496 | GUARD RINGS ON FIN STRUCTURES - A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric. The device further includes a plurality of semiconductor regions, each disposed between and contacting two neighboring ones of the plurality of semiconductor fins. The device further includes a plurality of contact plugs, each overlying and electrically coupled to one of the plurality of semiconductor regions. An electrical connection electrically interconnects the plurality of semiconductor regions and the gate electrodes of the plurality of gate stacks. | 2014-04-10 |
20140097497 | Spacer Design to Prevent Trapped Electrons - Charge-trapping field effect transistors may be formed into an array on a wafer suitable to be a NAND memory device. A thick oxide layer is applied over the gates to ensure that the gap between the gates is filled. The filled gap substantially prevents nitride from being trapped, which could otherwise decrease the yield of the devices. This technique, and its variations, are useful for a range of semiconductor devices. | 2014-04-10 |
20140097498 | Open Source Power Quad Flat No-Lead (PQFN) Leadframe - According to an exemplary implementation, a power quad flat no-lead (PQFN) leadframe includes U-phase, V-phase, and W-phase power switches situated on the PQFN leadframe. A drain of the U-phase power switch is connected to a U-phase output strip of the PQFN leadframe. A source of the U-phase power switch is connected to a U-phase current sense terminal. The U-phase output strip can substantially traverse across the PQFN leadframe. Another U-phase power switch is situated on the PQFN leadframe with a source of the another U-phase power switch connected to the U-phase output strip of the PQFN leadframe. The PQFN leadframe can include a leadframe island within the U-phase output strip. At least one wirebond may be connected to the U-phase output strip. | 2014-04-10 |
20140097499 | Semiconductor Structures - Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed. | 2014-04-10 |
20140097500 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer. | 2014-04-10 |