| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716114000 | Buffer or repeater insertion | 33 |
| 20110161904 | METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND COMPUTER READABLE MEDIUM - A design method of a semiconductor integrated circuit sets an area having apices of opposing corners of a position of a start point logic cell and a position of an end point logic cell to a repeater search area, adds free area information to the repeater search area, sets a drive boundary in the repeater search area based on a drive ability of the start point logic cell, searches a repeater candidate that can be arranged in an area of the drive boundary based on the free area information, calculates a delay time from the start point logic cell to the end point logic cell based on delay time information and a coordinate of the repeater candidate that is searched, and determines a repeater arranged between the start point logic cell and the end point logic cell from the repeater candidate based on the delay time that is calculated. | 06-30-2011 |
| 20110258589 | CLOCK DISTRIBUTION CIRCUIT AND LAYOUT DESIGN METHOD USING THE SAME - A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit. | 10-20-2011 |
| 20110320994 | APPARATUS FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, AND PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - A device comprises a analysis section for detecting hold errors according to data including the values of the input and output nodes of the FF circuit, and identifying the node in which a hold error has occurred, a determining section for determining insertion of the trailing edge FF or the buffer into hold error sections on the basis of the results of the analysis by the analysis section, a FF insertion section for inserting the FF into a hold error section subjected to position determination so as to insert the trailing edge FF, and connecting a clock line to the FF based on the results of the determining section, and a buffer insertion section for inserting the buffer into the hold error section subjected to the position determination so as to insert the FF based on the results of data of the determining section. | 12-29-2011 |
| 20120060136 | Design supporting method, design supporting device, computer product, and semiconductor integrated circuit - A method executed by a computer and for designing a semiconductor integrated circuit, includes detecting, from layout data of a semiconductor integrated circuit, a clock path that propagates the clock signal and of which clock buffers are single-gate inverting clock buffers; selecting sequentially data holding elements connected to the detected clock path; identifying an input clock buffer of each selected data holding element; determining whether the identified clock buffer outputs the clock signal according to non-inverting logic or inverting logic, based on the number of gates from the clock source to the clock buffer; replacing, based on a determination result, the data holding element with a first data holding element that takes in data in synchronization with a rising edge of the clock signal or with a second data holding element that takes in data in synchronization with a falling edge of the clock signal; and outputting a replacement result. | 03-08-2012 |
| 20120110532 | LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS - A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one. | 05-03-2012 |
| 20120110533 | IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES - A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions. | 05-03-2012 |
| 20120124539 | Clock Optimization with Local Clock Buffer Control Optimization - A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers. | 05-17-2012 |
| 20120167030 | METHOD AND APPARATUS FOR ADDRESSING AND IMPROVING HOLDS IN LOGIC NETWORKS - A method and apparatus for modifying a synchronous logic network so that the hold slack calculated at all pins is greater than or equal to a user-specified threshold, with the condition that the setup slack at any pin does not become negative or smaller than a user-specified margin. The result is an improved design which is less likely to fail due to a hold time violation. The method and apparatus introduce a limited number of logic cells which helps keep power consumption and design size to a minimum. | 06-28-2012 |
| 20120221993 | Integrated Circuit Chip with Repeater Flops and Methods for Automated Design of Same - An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided. | 08-30-2012 |
| 20120324412 | Reducing Leakage Power in Integrated Circuit Designs - A method for reducing leakage power of an IC during the design of the IC. A cell based IC design is received that includes a plurality of signal paths with positive slack. The positive slack is converted to negative slack by replacing cell instances in the IC design with footprint equivalent variants of the cell instances. The negative slack is converted back to positive slack via an iterative path-based analysis of the IC design. In each iteration, a path is selected that has negative slack and replacement values are computed for cell instances in the path. One or more cell instances in the path are then replaced with variants based on the replacement values. | 12-20-2012 |
| 20130007685 | AUTOMATED INTEGRATED CIRCUIT CLOCK INSERTION - A user device receives a request to perform an automatic clock insertion operation for an integrated circuit; retrieves location information regarding a group of components, of the integrated circuit, that use a clock signal; deploys a clock mesh based on the location information regarding the group of components; and inserts drop points into the clock mesh; deploys a particular buffer for a particular drop point; maps a component, of the group of components, to the particular buffer; generates a clock box for the particular buffer, where dimensions of the clock box are based on a location of the component; deploys an H-tree for the clock box, where dimensions of the H-tree are proportional to the clock box dimensions; connects the H-tree to the component; and displays or stores clock mesh information, information regarding the group of buffers, information regarding the H-tree, and the location information regarding the group of components. | 01-03-2013 |
| 20130061193 | IMPLEMENTING ENHANCED CLOCK TREE DISTRIBUTIONS TO DECOUPLE ACROSS N-LEVEL HIERARCHICAL ENTITIES - A method, system and computer program product for implementing enhanced clock tree distributions to decouple across N-level hierarchical entities of an integrated circuit chip. Local clock tree distributions are constructed. Top clock tree distributions are constructed. Then constructing and routing a top clock tree is provided. The local clock tree distributions and the top clock tree distributions are independently constructed, each using an equivalent local clock distribution of high performance buffers to balance the clock block regions. | 03-07-2013 |
| 20130326449 | INCREMENTAL ELMORE DELAY CALCULATION - Systems and techniques for incrementally updating Elmore pin-to-pin delays are described. During operation, an embodiment receives a representation of a physical topology of a routed net that electrically connects a driver pin to a set of load pins. The embodiment then computes a set of incremental Elmore delay coefficients based on the representation. Next, using the Elmore delay coefficients, the embodiment computes a set of delays based on the representation, wherein each delay in the set of delays corresponds to a delay between the driver pin and a corresponding load pin in the set of load pins. As load pin capacitances change during circuit optimization, the set of incremental Elmore delay coefficients can then be used to update the delays between the driver pin and the load pins in a very computationally efficient manner. | 12-05-2013 |
| 20130326450 | EARLY DESIGN CYCLE OPTIMZATION - Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component. | 12-05-2013 |
| 20130326451 | Structured Latch and Local-Clock-Buffer Planning - Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance. | 12-05-2013 |
| 20140040845 | SYSTEM AND METHOD FOR EMPLOYING SIDE TRANSITION TIMES FROM SIGNOFF-QUALITY TIMING ANALYSIS INFORMATION TO REDUCE LEAKAGE POWER IN AN ELECTRONIC CIRCUIT AND AN ELECTRONIC DESIGN AUTOMATION TOOL INCORPORATING THE SAME - The disclosure provides leakage power recovery that considers side transition times of multi-input cells. In one embodiment, a leakage power recovery system is disclosed that includes: (1) a power recovery module that considers side transitions when making a first conditional replacement of a cell in a path of a circuit design with a lower leakage cell and estimates delays and slack of the at least one path of the circuit design, and (2) a speed recovery module that makes a second conditional replacement of a slower lower leakage cell of the path with a higher leakage cell when there is a timing violation with respect to the path, determines if any other cells of the at least one path has a slower input transition and makes a third conditional replacement of a driver thereof to a higher leakage cell when the driver is one of the slower lower leakage cells. | 02-06-2014 |
| 20140082577 | Uniform-Footprint Programmable-Skew Multi-Stage Delay Cell - Described embodiments provide a delay cell for a complementary metal oxide semiconductor integrated circuit. The delay cell includes a delay stage to provide an output signal having a programmable delay through the delay cell. The delay cell has a selectable delay value from a plurality of delay values and a selectable output skew value from a plurality of output skew values, where the cell size and terminal layout of the delay cell are relatively uniform for the plurality of delay values and the plurality of output skew values. The delay stage includes M parallel-coupled inverter stages of stacked PMOS transistors and stacked NMOS transistors. The stacked transistors have configurable source-drain connections between a drain and a source of each transistor, wherein the selectable delay value corresponds to a configuration of the configurable source-drain connections to adjust a delay value of each of the M inverter stages and an output skew value of the delay cell. | 03-20-2014 |
| 20140143746 | DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN - A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis. | 05-22-2014 |
| 20140165019 | SEMICONDUCTOR HOLD TIME FIXING - Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete. | 06-12-2014 |
| 20140181772 | DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN - A design tool with an initial sink locator unit determines a number of clock buffers for driving clock signals to loads in a clock distribution network. The design tool determines clusters of loads in the clock distribution network, wherein the number of clusters is equal to the number of clock buffers and the loads are uniformly distributed amongst the clusters. The design tool determines centers of the clusters as initial candidate sink locations for the clock buffers. The design tool iteratively determines new clusters and determines centers of the new clusters as optimized initial candidate sink locations. | 06-26-2014 |
| 20140189627 | INCREMENTAL CLOCK TREE SYNTHESIS - Methods and apparatuses are described for optimizing local clock skew, and/or for synthesizing clock trees in an incremental fashion. For optimizing local clock skew, the circuit design can be partitioned into clock skew groups. Next, for each clock skew group, an initial clock tree can be constructed that substantially minimizes worst case clock skew in the clock skew group, and then the initial clock tree can be further optimized by substantially minimizing worst case local clock skew in the clock skew group. For performing incremental clock tree synthesis, a portion of a clock tree in the circuit design can be selected based on a set of modifications to the circuit design. Next, a new clock tree can be determined to replace the selected portion of the clock tree. The circuit design can then be modified by replacing the selected portion of the clock tree with the new clock tree. | 07-03-2014 |
| 20140258957 | ENGINEERING CHANGE ORDER HOLD TIME FIXING METHOD - An ECO hold time fixing method fulfills a short path padding in a placed and routed design by a minimum capacitance insertion. In the method, a padding value determination step receives the placed and routed design and is based on a cell library, timing constraints, and a timing analysis report to determine padding values and locations required for each gate of the placed and routed design to output. A load/buffer allocation step is based on a spare cell information, a dummy metal information, and the padding values and locations to achieve the short path padding in the placed and routed design. | 09-11-2014 |
| 20140282336 | TOOL FOR EVALUATING CLOCK TREE TIMING AND CLOCKED COMPONENT SELECTION - Techniques for generating timing constraints for an integrated circuit including a clock tree network are described. The techniques may be associated with a clock tree synthesis tool that receives a design of the integrated circuit and generates a clock tree network including a plurality of clocked components of the integrated circuit. The constraints may be generated as a function of the duration of propagation of a data signal from a transmitting clocked component coupled to a receiving clocked component. | 09-18-2014 |
| 20140298282 | DESIGN STRUCTURE FOR STACKED CMOS CIRCUITS - An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a pluraility of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output. | 10-02-2014 |
| 20140298283 | CLOCK TREE CONSTRUCTION ACROSS CLOCK DOMAINS - Disclosed is a method and system for clock tree construction across clock domains, an integrated circuit and fabrication method thereof. A method for clock tree construction includes acquiring a netlist describing an integrated circuit (IC), comprising data for describing physical locations and logic connections of clock sinks belonging to multiple clock domains on the pattern of the IC, and constructing the clock tree across clock domains based on the netlist, such that clock cells belonging to different clock domains can share more physical locations. Accordingly, clock trees can be constructed across clock domains to improve IC performance. | 10-02-2014 |
| 20150074630 | LAYOUT METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT AND RECORDING MEDIUM - A layout method of a semiconductor integrated circuit includes detecting a path having a constraint violation in a laid-out semiconductor integrated circuit, determining an insertable range of a buffer to be inserted on a route of the path so as to remove the constraint violation, evaluating, with respect to a cell already placed in the insertable range, a wiring length, and presence or absence of a constraint violation if the cell is hypothetically moved to an empty space in a vicinity of the insertable range, determining an insertion position of the buffer based on a result of the evaluation, moving the cell already placed at the insertion position of the buffer to the empty space in the vicinity of the insertable range, placing the buffer at the insertion position, and rerouting the buffer and the moved cell. | 03-12-2015 |
| 20150100936 | REGISTER CLUSTERING FOR CLOCK NETWORK TOPOLOGY GENERATION - In some embodiments, in a method, a physical netlist of a placed IC chip design is received. The physical netlist comprises a plurality of registers. Timing criticalities of register pairs in the registers are obtained. Weights to the register pairs are assigned based on the timing criticalities of the register pairs. Candidate registers that are in physical vicinity of a first cluster are identified. If a first candidate register in the candidate registers of the first cluster is in a second cluster, selecting the first candidate register as the first register to be added to the first cluster if sum of weights of other candidate registers in register pairs across the boundary of the first cluster and the first candidate register in one or more register pairs across a boundary of the second cluster is optimized. | 04-09-2015 |
| 20150310153 | Methods and Computer-Readable Media for Synthesizing a Multi-Corner Mesh-Based Clock Distribution Network for Multi-Voltage Domain and Clock Meshes and Integrated Circuits - One aspect of the invention provides a including: (a) placing N×N max size buffers at an (n−1)st level of one of the voltage domains i until a maximum slew slew | 10-29-2015 |
| 20160042117 | FIXING OF SEMICONDUCTOR HOLD TIME - Computer implemented techniques are disclosed for fixing signal hold-time violations in semiconductor chips. Analysis includes estimation of hold-time requirements using ideal clocks. Allocation of placement regions within the design and near the macro circuits allows for later placement and wiring use during layout hold-time fixing. The placement region sizes are based on estimates of the needed buffers. Nets, within the design for detail routing, are ordered such that nets with hold-time violations are wired later, thus fixing hold-time violations without scaling or adding further buffers. Hold times are re-evaluated once wiring of track routes is complete. | 02-11-2016 |
| 20160085901 | LINEAR COMPLEXITY PRIORITIZATION OF TIMING ENGINEERING CHANGE ORDER FAILURES - A system and a method are disclosed for displaying an output of a static timing analysis. A plurality of timing violations of an integrated circuit is identified. The timing violations are associated with a timing path. A reason is identified for each of the timing violations. A priority for fixing the timing violations is determined. Information describing the timing violations is sent for being presented. The information presented includes an information indicating priority associated with timing violations to assist developers in prioritizing tasks for fixing the timing violations. | 03-24-2016 |
| 20160092626 | Methods and Apparatus for Repeater Count Reduction via Concurrent Gate Sizing and Repeater Insertion - Techniques for circuit concurrent gate sizing and repeater insertion considering the issue of size conflicts are described herein. Certain of these techniques can be directed to coupled gates within levels of a levelized circuit falling within a coupling window defined by a minimum slack gate and adjacent gates coupled to the minimum slack gate with an adjacency parameter less than a predefined adjacency limit. | 03-31-2016 |
| 20160117434 | NOVEL LOW POWER MINIMAL DISRUPTIVE METHOD TO IMPLEMENT LARGE QUANTITY PUSH & PULL USEFUL-SKEW SCHEDULES WITH ENABLING CIRCUITS IN A CLOCK-MESH BASED DESIGN - According to one general aspect, a method may include receiving a digital circuit model that includes models of a clock mesh and a plurality of logic circuits, each logic circuit associated with end-points of the logic circuit. The method may also include identifying a cluster of end-points, wherein the cluster is associated with a common version of the clock signal. The method may also include identifying an associated skew-schedule for each end-point. The method may include determining a timing slack and skew schedule for each end-point within the cluster. The method may include adjusting a clock-gater cell, based upon a common push/pull schedule associated with the cluster. The method may further include inserting, for at least one end-point of the cluster, a skew-buffer, wherein a variant of the skew-buffer for a respective end-point is based upon a difference between the end-point's skew schedule and the common push/pull schedule. | 04-28-2016 |
| 20160147928 | METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT LAYOUT GENERATION - A method performed at least partially by a processor includes performing an air gap insertion process. The air gap insertion process includes sorting a plurality of nets of a layout of an integrated circuit in an order, and inserting, in accordance with the sorted order of the plurality of nets, air gap patterns adjacent to the plurality of nets. The method further includes generating a modified layout of the integrated circuit. The modified layout includes the plurality of nets and the inserted air gap patterns. | 05-26-2016 |
