| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716109000 | Power estimation | 26 |
| 20110191736 | INTEGRATED CIRCUIT WITH ON-BOARD POWER UTILIZATION INFORMATION - A system and method for storing power utilization information in an integrated circuit and utilizing such information. Various aspects of the present invention provide an integrated circuit that comprises a first module, which stores power utilization information for at least a portion of the integrated circuit. A second module of the integrated circuit may communicate the power utilization information with an electrical device external to the integrated circuit. Various aspects of the present invention provide a method for storing power utilization information in an integrated circuit. For example, a performance characteristic and/or a power supply characteristic may be monitored as the integrated circuit is utilized. Power utilization information may be determined from the monitored characteristic(s), and the power utilization information may be stored in the integrated circuit. Various aspects of the present invention also provide a system and method for utilizing an integrated circuit having on-board power utilization information. | 08-04-2011 |
| 20110239174 | METHOD AND APPARATUS FOR LAYING OUT POWER WIRING OF SEMICONDUCTOR DEVICE - A method for laying out a power wiring of a semiconductor device including an analog circuit and a digital circuit includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a maximum current node from nodes of the digital circuit when a substrate noise violation exists in a voltage value of a node of the analog circuit, the maximum current node having a maximum amount of current flowing into the node of the analog circuit; searching a path of a current flowing into the maximum current node in the digital circuit; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor. | 09-29-2011 |
| 20120011481 | Hierarchical Finite State Machine Generation For Power State Behavior in an Electronic Design - The invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine, representing the power behavior of an electronic design is extracted from the power specification for the electronic design. Subsequently, a hierarchical finite state machine representation for the power behavior is generated from the flat finite state machine, the power specification and the logical specification. | 01-12-2012 |
| 20120017188 | METHOD OF DETERMINING EVENT BASED ENERGY WEIGHTS FOR DIGITAL POWER ESTIMATION - A method for determining event based energy weights for digital power estimation includes obtaining a reference energy value corresponding to a power consumed by at least a portion of an integrated circuit (IC) device during operation. The method includes determining and selecting a subset of signals from a set of all signals within the IC that correlates to energy use within the IC. The method includes determining an activity factor of each signal in the subset by monitoring each signal while simulating execution of a particular set of instructions. The method includes determining a weight factor or at least an approximation of a weight factor for each signal in the subset by solving within a predetermined accuracy, a multivariable equation in which the reference energy value equals a weighted sum of the activity of the signals of the selected subset multiplied by their respective weight factors. | 01-19-2012 |
| 20120151426 | METHOD FOR IMPLEMENTING POWER GATING IN AN INTEGRATED CIRCUIT DESIGN LOGIC BLOCK INCLUDING N-NARY DYNAMIC LOGIC (NDL) GATES - A method for adding power gating to an integrated circuit design logic block that includes N-Nary dynamic logic (NDL) gates includes determining an initial number of power gating rows to add to the logic block. The logic block includes a number of rows of logic gates in which some of the rows include gates implemented as one of n NDL circuits, where n may be any positive integer. The method also includes determining a total power gating device width for all of the power gating rows, and determining a distribution of the power gating device width among a final number of power gating rows based upon a number of different clock phases used to clock the gates implemented as one of n NDL circuits. The method further includes placing the power gating rows within the logic block. | 06-14-2012 |
| 20120151427 | AUTOMATED IDENTIFICATION OF POWER AND GROUND NETS IN AN INTEGRATED CIRCUIT NETLIST - A computerized method of automatically identifying nets that are statistically likely to be power or ground nets in a complex integrated circuit design. The method, which does not require a-priori information, operates by determining the electrical properties of each device or device terminal that is coupled to the analyzed net, and creating an overall mathematical description of the overall electrical properties of these various devices. The method will then compare this mathematical description with at least various preset mathematical descriptions of power nets or a ground nets. If the overall mathematical description fits, the invention will at least provisionally determine that this particular analyzed net is a power net or a ground net. The invention may also determine likely voltages for these various power nets. | 06-14-2012 |
| 20120198401 | APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR DEVICE - A design supporting apparatus for a semiconductor device, includes an IR drop analyzing section configured to carry out an IR drop analysis on each of N (2 N) functional blocks, which operates independently on a semiconductor device, to generate an IR drop analysis result. An area of the semiconductor device is divided into small areas in a lattice. A mapping value generating section calculates a distribution of individual mapping values related to the small areas from the IR drop analysis result for each of the function blocks. A grouping section calculates a distribution of group mapping values from the distributions of individual mapping values for n (n≦N) simultaneously operating functional blocks of the N functional blocks, and output group data indicative of the n simultaneously operating functional blocks when each of the group mapping values falls within a permission value. | 08-02-2012 |
| 20120216160 | ESTIMATING POWER CONSUMPTION OF AN ELECTRONIC CIRCUIT - A method comprises estimating power consumption of an electronic circuit. The estimating includes assigning a first gate of the at least one gate into a priority queue based on a levelized result of the electronic circuit for a full circuit calculation and assigning a second gate of the at least one gate into the priority queue which fan-out gate is directly connected to a fan-in gate of a resized gate for an incremental circuit calculation. The estimating includes, for each gate from the priority queue, performing the following operations. Latest and earliest signal arrival times at an output net of the gate are determined by static timing analysis and calculating a glitch window as difference, and a transition metric is calculated for the output net based on the glitch window. The operations include determining an upper bound of signal transitions, and estimating the power consumption based on the upper bound. | 08-23-2012 |
| 20120266120 | GLITCH POWER REDUCTION - A method comprises reducing power consumption of an electronic circuit, wherein the electronic circuit comprises at least one logic cone with at least one gate having a single output net, wherein representations of the at least one gate are instances of elements from a standard cell library. Reducing of the power consumption comprises determining an upper bound for dynamic power consumption by calculating transition metrics and power metrics for each gate. Reducing of the power consumption comprises selecting gates with an upper bound for power consumption greater than a predetermined threshold value. For each selected gate, performing operations comprising: testing multiple configurations from the standard cell library for the selected gate by calculating respective upper bound for power consumption for each of the multiple configurations; selecting gate configuration with minimum upper bound for power consumption; and modifying the gate-level design representation according to the selected gate configuration. | 10-18-2012 |
| 20120266121 | METHOD TO DETERMINE HIGH LEVEL POWER DISTRIBUTION AND INTERFACE PROBLEMS IN COMPLEX INTEGRATED CIRCUITS - A computer software implemented method of automatically determining adequacy of an integrated circuit electrical power distribution and signal protection schemes, based on netlist data, which does not rely on other a-priori data. The method determines which nets are power supply nets, their connectivity to different types of power supplies. The method automatically traverses the nested block structure of the circuit, ascending and descending in block hierarchy as needed, and automatically determines (often based on an inspection of the power needs of the individual block devices) the type of power supply needed to power that block, power supply adequacy, and adequate protection of signal interfaces to other blocks. The method can present the analysis in a high level report, such as a graphical map, that can make root cause sources of power and power related signal interface problems immediately evident, and which suppresses most irrelevant details. | 10-18-2012 |
| 20120266122 | METHOD AND SYSTEM OF AUTOMATICALLY IDENTIFYING LEVEL SHIFTER CIRCUITS - A logical and topological based software method of detecting level shifter circuits in complex integrated circuit designs. The method, which identifies level shifters by various design rules such as suitably connected PFET and NFET pairs in various circuit contexts, rather than prior art simulation methods, can identify and mark various devices and circuits as being part of a level shifter, and also place the identified level shifters within the context of the integrated circuit chip's various power domains. In some embodiments, the method, working with little or no a-priori information other than the integrated circuit's netlist computer file, can automatically trace power and signal lines, automatically determine power domains, and automatically flag when signal lines between different power domains are not adequately protected by level shifters. | 10-18-2012 |
| 20120304137 | METHOD AND APPARATUS FOR MULTI-DIE THERMAL ANALYSIS - Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies. | 11-29-2012 |
| 20130007682 | MATCHING SYSTEMS WITH POWER AND THERMAL DOMAINS - A system, and computer program product for matching systems with power and thermal domains are provided in the illustrative embodiments. A subset of the set of systems is sorted according to size to form a sorted list of systems. The smallest remaining system in the sorted list of systems is selected. The smallest remaining system is allocated to a domain responsive to a determination that the domain can service the smallest remaining system. A system from a second subset is allocated to a plurality of domains such that the plurality of domains includes a smallest number of domains from the set of domains. | 01-03-2013 |
| 20130198704 | Estimation of Power and Thermal Profiles - Aspects of the invention relate to techniques for estimating power and thermal profiles for an integrated circuit design. With various implementations of the invention, a group of devices is identified in a netlist based on information of the group of devices. The netlist may be a schematic netlist or a layout netlist extracted from a layout design. Power consumption information for the group of devices is determined based on device parameters for the group of devices and a lookup table. The determined power consumption information is then associated with layout location information. A thermal profile may then be estimated based on the power consumption information. | 08-01-2013 |
| 20130212546 | METHOD FOR INSERTING CHARACTERISTIC EXTRACTOR - A method for inserting characteristic extractor is provided. The method includes parsing a transaction level model (TLM) of an electronic device of a target system to find out at least one target point of an operation status of the electronic device; and inserting at least one characteristic extractor into the at least one target point. | 08-15-2013 |
| 20130275933 | HIERARCHICAL POWER MAP FOR LOW POWER DESIGN - A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result. | 10-17-2013 |
| 20140082574 | Token-Based Current Control to Mitigate Current Delivery Limitations in Integrated Circuits - A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack. | 03-20-2014 |
| 20140181769 | NETLIST CELL IDENTIFICATION AND CLASSIFICATION TO REDUCE POWER CONSUMPTION - In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode. | 06-26-2014 |
| 20140223399 | CIRCUIT ANALYSIS DEVICE AND CIRCUIT ANALYSIS METHOD - A circuit analysis device includes: a processor configured to execute a procedure by: calculating, for power supply noise included in a power supply voltage supplied to a semiconductor memory device, variation characteristics of an electric potential relative to the power supply voltage in a specific memory cell included in a memory cell array; calculating power supply noise of a power supply system that occurs when a current is supplied to an equivalent circuit of the power supply system under a predetermined condition, the power supply system including a power supply line and an element for supplying a power supply voltage from a voltage source to a semiconductor device; calculating, from the variation characteristics, the electric potential obtained when the power supply noise is equal to a specific magnitude; and determining, by comparing the calculated electric potential with a threshold, whether memory latch-up will occur in the specific memory cell. | 08-07-2014 |
| 20150040087 | IDENTIFICATION OF POWER SENSITIVE SCAN CELLS - Aspects of the disclosed techniques relate to techniques for identifying power sensitive scan cells. Signal probability values for signal lines in a circuit design are first computed, wherein the signal lines comprise signal lines associated with scan cells in the circuit design. Toggling probability values are then computed based on the signal probability values, wherein the toggling probability values comprise toggling rate values for the scan cells. Toggling rate reduction values are then computed based on the toggling probability values, wherein the toggling rate reduction values comprise toggling rate reduction values for the scan cells. Finally, scan cells having high toggling rate reduction values are identified. | 02-05-2015 |
| 20150095863 | INTEGRATED CIRCUIT DESIGN USING DYNAMIC VOLTAGE SCALING - A method and an apparatus from such method for designing an integrated circuit (IC) that mitigates the effects of process, voltage, and temperature dependent characteristics on the fabrication of advanced IC's but provides high die yields, lower power usage, and faster circuits. Conventional design process takes into account power supply voltage Vdd as a variable that must be considered in a skewed corner analysis. The disclosure teaches that the IC design process can be substantially simplified by essentially factoring out voltage based variations in corner lot analysis for IC designs that include dynamic voltage scaling circuitry, because each fabricated IC die of an IC design having dynamic voltage scaling can individually adjust the applied supply voltage Vdd within a range to offset local process-induced variations in the performance of that specific IC die. | 04-02-2015 |
| 20150347666 | MICRO-BENCHMARK ANALYSIS OPTIMIZATION FOR MICROPROCESSOR DESIGNS - Embodiments include systems and methods for optimization of micro-benchmark analysis for microprocessor designs. For example, embodiments seek to generate a suite of micro-benchmarks and associated weighting factors, which can be used to effectively define a weighted aggregate workload condition for a fine-grained (e.g., RTL) simulation in a manner that is a sufficient proxy for predicted commercial workload conditions. The suite of micro-benchmarks can be appreciably more efficient to simulate than the commercial workload, so that using the suite of micro-benchmarks as a proxy for the commercial workload can provide many benefits, including more efficient iterative design. | 12-03-2015 |
| 20160063172 | Connectivity-Aware Layout Data Reduction For Design Verification - Aspects of the disclosed technology relate to techniques of connectivity-aware reduction of layout data. With various implementations of the disclosed technology, circuit elements of interest are selected in a circuit design which includes netlist information and layout data. Based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, nets of interest are determined. Cells of interest, comprising cells that are identified based at least on pins for the circuit elements of interest, the circuit elements of interest, or both, are then determined. Based on the nets of interest and the cells of interest, layout geometric elements are selected and may be analyzed for design verification. For electrostatic discharge (ESD) protection verification, the cells of interest may further comprise cells that include portions of power supply grids on top metal layers. | 03-03-2016 |
| 20160140281 | System On Chip I/O Connectivity Verification In Presence Of Low Power Design Considerations - Formal verification of connectivity of a circuit, for example, a circuit representing a system on chip I/O ring is performed with low power considerations. The formal verification determines whether the connectivity of a circuit remains valid when low power design specification is introduced. The system receives assertions representing connectivity of the circuit. The system receives low power design specification for a circuit that describes power states of power domains of the circuit. The system generates combinational constraints representing valid power states of power domains of the circuit. The system performs formal verification based on the assertions representing the connectivity of the circuit and the combinational constraints representing the power states of power domains of the circuit. The result of the formal verification is used to determine whether the connectivity of the circuit is valid in view of the low power design specification. | 05-19-2016 |
| 20160180012 | Low Power Verification Method for a Circuit Description and System for Automating a Minimization of a Circuit Description | 06-23-2016 |
| 20160188772 | METHOD OF DESIGNING AN INTEGRATED CIRCUIT AND COMPUTING SYSTEM FOR DESIGNING AN INTEGRATED CIRCUIT - In a method of and computing system for designing or modifying a design of an integrated circuit including a combinational logic and a scan chain, at least one flip-flop satisfying a predetermined condition is detected from among a plurality of flip-flops included in the scan chain by analyzing the combinational logic, and the detected flip-flop is replaced with a settable flip-flop that is set during a scan test for the integrated circuit, a resettable flip-flop that is reset during the scan test, or a settable-and-resettable flip-flop that is set or reset during the scan test. | 06-30-2016 |
