| Entries |
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| 20100313176 | DELAY LIBRARY, DELAY LIBRARY CREATION METHOD, AND DELAY CALCULATION METHOD - A timing window (TW) representing a time zone where a signal transition possibly occurs in a time axis is generated for each of input signals in input terminals in a multi-input logic cell based on a signal transition timing in each of the input terminals. An overlap between the timing windows (TW) of input signals is detected, and a circuit delay time is calculated by selectively using one of a synchronous transition time and an asynchronous transition time in accordance with the overlap between the timing windows (TW). These processing steps are sequentially repeated to eliminate an optimistic or pessimistic analysis in the calculation of delay times in the multi-input logic cell. | 12-09-2010 |
| 20100318951 | SYSTEM AND METHOD FOR DEVICE HISTORY BASED DELAY VARIATION ADJUSTMENT DURING STATIC TIMING ANALYSIS - A system and method for the adjustment of history based delay variation during static timing analysis of an integrated circuit design. The method may include obtaining information through sources of variability of history based components of delay variability, and a relationship between the sources of variability and one or more bounded device histories. Then, inputting history bounds for at least one signal of the integrated circuit design, and computing and propagating history bounds through at least one first segment of the integrated circuit design to at least one signal of the integrated circuit design. Further, the method may include evaluating from at least one of the propagated history bounds, device history bounds for at least one second segment of the integrated circuit design, and based on the evaluated device history bounds, adjusting at least one of a value of the history based delay variability and propagation of timing. | 12-16-2010 |
| 20100318952 | System and Method Incorporating An Arithmetic Logic Unit For Emulation - A system and method for verifying logic circuit designs having arithmetic operations and complex logical operations such that the operations may be evaluated at substantially full hardware speed is disclosed. According to one embodiment, a system for verifying the functionalities of an electronic circuit design comprises hardware emulation resources emulating at least a portion of an electronic circuit design; and a first hardware ALU block having an arithmetic logic unit that performs an arithmetic operation or a complex logical operation of the electronic circuit design, and a set of flag registers that contains a conditional value for enabling the arithmetic logic unit. | 12-16-2010 |
| 20100325595 | METHOD AND SYSTEM PERFORMING RC EXTRACTION - A method, system, and computer program product are disclosed for performing RC extraction. The present approach can consider multiple types of manufacturing processes, and allows location-based prediction data to be used in the context of net-based analysis. RC extraction can be more accurately performed based upon net-specific top and bottom adjustments to thickness prediction that are location-based. The net-based prediction data can be used for other purposes as well, such as to perform electrical hotspot analysis, to visually display physical properties of the nets, or allow queries for other data analysis purposes. | 12-23-2010 |
| 20100325596 | CLOCK GATING USING ABSTRACTION REFINEMENT - An initial clock gating function is introduced to an original circuit design. Using abstraction-refinement, the initial clock gating function is modified such that the gated circuit design is equivalent to the original circuit design. A model checker, such as a SAT solver, may be utilized to determine equivalency of two circuit designs. A counter-example may be determined by the model checker to negate equivalency. The counter-example may be utilized to modify the initial clock gating function to determine a modified gated circuit design that is equivalent to the original circuit design. | 12-23-2010 |
| 20100333055 | INTEGRATED CIRCUIT HAVING SECURE ACCESS TO TEST MODES - Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information. | 12-30-2010 |
| 20110016442 | Method of Performing Static Timing Analysis Considering Abstracted Cell's Interconnect Parasitics - An abstraction model supporting multiple hierarchical levels is inputted into a generalized static timing analysis of a hierarchical IC chip design to analyze and optimize the design of circuits integral to the chip containing a plurality of macro abstracts. An electrical network, synthesized for an internal abstract interconnect segment, is performed only once per macro and is applied to multiple instances of the macro abstract model in the IC chip design. The synthesized electrical network is a resistive capacitive or a resistive inductive capacitive network or a combination thereof. The synthesized electrical network is then used to match impulse response transfer functions of the network and the abstract interconnect segment's timing model. This network is stitched with the electrical parasitics of external interconnect segments connected to macro primary outputs. Various model order reductions are then performed on the electrical parasitics of external interconnects prior to network stitching. A static timing analysis is performed on the final network. | 01-20-2011 |
| 20110016443 | Dummy Pattern Performance Aware Analysis and Implementation - Embodiments of the present invention are a system, a computer program product, and a method for implementing an integrated circuit design. An embodiment is a method for implementing an integrated circuit design. The method comprises accessing an original electronic representation of an integrated circuit layout from a first user file, accessing a defined sensitivity index that characterizes an impact of the dummy pattern on the functional component, analyzing the impact of the dummy pattern on the functional component, determining whether the impact is within a limit of the sensitivity index, adjusting one of a plurality of features of the dummy pattern if the impact is not within the limit to form a generated electronic representation of a modified integrated circuit layout, and outputting the generated electronic representation to a second user file. The integrated circuit layout comprises a dummy pattern and a functional component. | 01-20-2011 |
| 20110022998 | METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD - Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, a method includes: (1) partitioning a design implementation flow for an IC into a late design flow portion and an early design flow portion employing a processor, (2) dividing components of the late design flow portion and the early design flow portion into a functional block implementation section and a top level implementation section employing the processor, (3) aligning dependencies between the functional block implementation sections and the top level implementation sections in both of the early design flow portion and the late design flow portion employing the processor and (4) implementing a layout for the IC based on the early and the late design flow portions employing the processor. | 01-27-2011 |
| 20110035714 | SYSTEM AND METHOD FOR COMMON HISTORY PESSIMISM RELIEF DURING STATIC TIMING ANALYSIS - A system and method for adjustment of modeled timing data variation as a function of past state and/or switching history during static timing analysis. One illustrative embodiment may include inputting and asserting at least one of initial signal history bound and explicit device history bound constraints for at least one signal of a circuit design and evaluating for a segment processed during a forward propagation of block based static timing analysis whether any input signal to a current segment has a bounded history, at least one of propagated and asserted. The method may further include evaluating for the segment whether history bounds are downstream from a gating restriction, and processing a next segment until there are no further segments. | 02-10-2011 |
| 20110035715 | SYSTEM AND METHOD FOR ON-CHIP-VARIATION ANALYSIS - Apparatus is provided for performing timing analysis on a circuit. A first storage device portion stores a state dependent stage weight for each of a rising time arc and a falling time arc of each of a plurality of cells in a cell library. An adder is provided for calculating a sum of the state dependent stage weights for each of the cells that are included in a circuit path. A second storage device portion stores a table containing on chip variation (OCV) derating factors. The table is indexed by values of the sum. A total path delay is calculated for the circuit path, based on the OCV derating factor corresponding to the sum of the state dependent stage weights for the cells in the circuit path. | 02-10-2011 |
| 20110041108 | MOMENT-BASED CHARACTERIZATION WAVEFORM FOR STATIC TIMING ANALYSIS - In one embodiment, the invention is a moment-based characterization waveform for static timing analysis. One embodiment of a method for mapping a timing waveform associated with a gate of an integrated circuit to a characterization waveform includes using a processor to perform steps including: computing one or more moments of the timing waveform and defining the characterization waveform in accordance with the moments. | 02-17-2011 |
| 20110041109 | MEMORY BUILDING BLOCKS AND MEMORY DESIGN USING AUTOMATIC DESIGN TOOLS - The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis. | 02-17-2011 |
| 20110055781 | NON-INVASIVE TIMING CHARACTERIZATION OF INTEGRATED CIRCUITS USING SENSITIZABLE SIGNAL PATHS AND SPARSE EQUATIONS - Techniques for non-invasive, post-silicon characterization of signal propagation delay/timing of devices in an integrated circuit (IC) are generally disclosed. A system of equations may be developed based on a plurality of sensitizable signal paths (SSPs) of the IC for characterizing signal propagation delay or timing of devices within the SSPs. Input Vectors (IVs) may be selected and consecutively applied at one or more input sequential element devices of the IC associated with the SSPs with to produce corresponding output values at one or more output sequential element devices of the IC associated with the SSPs. Various pre-processing and post-processing techniques may be practiced to further improve accuracy of solution of the equations to enable efficient determination of solutions. Example techniques may include variable splitting, device clustering, IV and equation selection, and boosting, among others. Other aspects may also be disclosed and claimed. | 03-03-2011 |
| 20110061036 | TIMING LIBRARY TEST APPARATUS, METHOD FOR TESTING TIMING LIBRARY, AND COMPUTER READABLE MEDIUM COMPRISING TIMING LIBRARY TEST PROGRAM - A timing library test apparatus includes a difference calculator looks into a look-up table in a timing library, the look-up table having timing constraint values registered in association with combinations between reference transient times of a signal at a reference terminal and constraint transient times of a signal at a constraint terminal, and groups neighboring two timing constraint values in the look-up table as one pair, respectively, to calculate differences between neighboring two timing constraint values of pairs, a determination part determines whether the differences calculated by the difference calculator has a characteristic feature of increase inclination or decrease inclination, and a decision part decides that the timing library has a singular point when the determination part determines that the differences doesn't have the characteristic feature, and to decide that the timing library doesn't have the singular point when the determination part determines that the differences has the characteristic feature. | 03-10-2011 |
| 20110066989 | METHOD AND SYSTEM TO AT LEAST PARTIALLY ISOLATE NETS - A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated. | 03-17-2011 |
| 20110066990 | INFORMATION PROCESSING APPARATUS - An information processing apparatus which includes a storage unit having stored a design data denoting layout and connection of a circuit, and a timing constraint data including a clock skew value denoting a delay difference allowed for a clock inputted to a pair of elements; a data read-out unit for reading out the design data and the timing constraint data; a clock skew value acquisition unit for acquiring the clock skew value set in correspondence with the pair of elements in layout in the circuit denoted by the design data from the timing constraint data; and a slack calculation unit for calculating a delay time between the pair of elements on the basis of the design data, and calculating a slack value indicating whether or not the pair of elements meets a predetermined design requirement by utilizing the acquired clock skew value and the calculated delay time with respect to the pair of elements. | 03-17-2011 |
| 20110072404 | Parallel Timing Analysis For Place-And-Route Operations - Signal paths in a circuit design are identified, and each node in each path to be processed by an electronic design automation operation is assigned a value. More particularly, each node in a signal path to be processed is sequentially assigned an incrementing value. If a node occurring in multiple signal paths already has been assigned a value, and the new value to be assigned to the node is higher than its previously-assigned value, then the node is assigned the higher value. Two or more portions of the circuit design having the same assigned node values are then processed in parallel by the electronic design automation operation. | 03-24-2011 |
| 20110078644 | ASYCHRONOUS SYSTEM ANALYSIS - Methods, systems, and circuits that implement timing analyses of an asynchronous system are described. A method may include converting a synchronous circuit design into an asynchronous representation, wherein a critical path may be identified. The critical path may be converted to a corresponding path in the synchronous circuit design. Additional methods, systems, and circuits are disclosed. | 03-31-2011 |
| 20110093825 | TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC - A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information. | 04-21-2011 |
| 20110126163 | METHOD TO REDUCE DELAY VARIATION BY SENSITIVITY CANCELLATION - A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design. | 05-26-2011 |
| 20110131540 | Path Preserving Design Partitioning With Redundancy - Partitioning of a design allows STA to be performed in parallel on multiple, less demanding, and more available hardware resources. Therefore, runtime of STA can be significantly shortened. Notably, the partitioning can include redundancy. That is, partitions are allowed to share objects in order to preserve the timing path completeness and design structural integrity. Due to this redundancy, these partitions can account for many constraints specifically imposed by STA. Once these partitions are populated, analysis can be performed on those partitions in parallel to generate the same timing results as if the design had been analyzed flat as a single unit. Therefore, the performance of STA can be optimized without compromising the accuracy and quality of results. | 06-02-2011 |
| 20110145771 | Modeling for Soft Error Specification - Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A logical simulation model is created based on the SEU specification and the design information. A logical verification is performed based on the logical simulation model to produce a first result. The logical verification comprises selecting a first node for injection, injecting an SEU into the first node to produce a first result, and responsive to the first result not agreeing with the SEU specification, providing the first result to the design entry. A netlist based on the SEU specification and the design information is created. The netlist comprises a specification-based-logic-derating derived from the SEU specification. A physical design verification based on the netlist, a logic derating, and clock information is performed. It comprises calculating node failure-in-time based on the specification-based-logic-derating. | 06-16-2011 |
| 20110161901 | SYSTEM AND PROCESS FOR AUTOMATIC CLOCK ROUTING IN AN APPLICATION SPECIFIC INTEGRATED CIRCUIT - Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well. | 06-30-2011 |
| 20110161902 | Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification - A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, mulitple trace status tables are received, and each of the trace status tables contains a trace error identified by a formal verification engine that was utilized to perform a relative timing (RT) verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations. | 06-30-2011 |
| 20110161903 | VERIFICATION SUPPORT COMPUTER PRODUCT AND APPARATUS - A computer-readable, non-transitory medium stores therein a verification support program that causes a computer to execute first detecting a state change in a circuit and occurring when input data is given to the circuit; second detecting a state change in the circuit and occurring when the input data partially altered is given to the circuit; determining whether a difference exists between a series of state changes detected at the first detecting and a series of state changes detected at the second detecting; and outputting a determination result obtained at the determining. | 06-30-2011 |
| 20110167395 | Timing Point Selection For A Static Timing Analysis In The Presence Of Interconnect Electrical Elements - A method and a system for selecting timing points in an electrical interconnect network to be used in electrical simulations for a static timing analysis for improved accuracy. The present method includes discovering choke points in an electrical model of the interconnect for which all the paths from drivers to receivers must pass through on certain types of nets. The method then uses the choke point electrical nodes, where they exist, as an output timing point of the logic gate driving the net. The method solves the problem of inaccuracies due to resistances between different driver pins on the same interconnect net, though it can also be applied to solving analogous inaccuracies due to resistances between different receiver pins associated with the same receiver timing point. It further also applies to interconnect with other two-port parasitic elements, to cases where only a subset of receiver pins on the net require accurate timing, and to cases where a set of electrical nodes, rather than a single node, partition all paths from drivers to receivers on a net. | 07-07-2011 |
| 20110167396 | DESIGN PLACEMENT METHOD AND DEVICE THEREFOR - An instantiation of a standard cell is placed at a location of a device design. The standard cell includes a designation identifying a sensitive feature of the standard cell. An instantiation of a filler cell is placed at a selective location of the device design based on the designation. | 07-07-2011 |
| 20110173584 | REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION - A method for reducing logic and delay within a logic structure that includes searching logic structures to be analyzed, finding a plurality of latches within a logic structure to be analyzed, determining if any respective latches of the plurality of latches have sufficiently positive slack within an input and output path thereof and optionally excluding the respective latches from being analyzed, determining if there is at least one remaining latch to be analyzed, and determining whether inverters are disposed within an input path and an output path of the at least one remaining latch. The method further includes obtaining logic functions of the input path and output path of the at least one remaining latch when inverters are found, modifying the logic functions using DeMorgan's Theorems, determining whether timing violations exist with the modified logic functions, and annotating hardware description language based on the modified logic functions when no timing violations exist. | 07-14-2011 |
| 20110191730 | ORDERING OF STATISTICAL CORRELATED QUANTITIES - Solutions for ordering of statistical correlated quantities are disclosed. In one aspect, a method includes timing a plurality of paths in an integrated circuit to determine a set of timing quantities associated with each of the plurality of paths; determining a most critical timing quantity in the set of timing quantities; forming a tiered timing quantity arrangement for ordering a plurality of timing quantities in the set of timing quantities; removing the most critical timing quantity from the set of timing quantities and placing the most critical timing quantity in an uppermost available tier of the tiered timing quantity arrangement; and repeating the determining, forming and removing for the set of timing quantities excluding the removed most critical timing quantity. | 08-04-2011 |
| 20110191731 | ZONE-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on the selected cell. Next, the system may determine a zone around the selected cell. Next, the system may propagate arrival times within the zone to obtain updated slack values at endpoints of the zone. The system may compute one or more timing metrics at the endpoints. If the updated slack values do not degrade the timing metric(s) at the endpoints, the system may accept the area-recovery operation of the selected cell. | 08-04-2011 |
| 20110191732 | METHOD AND APPARATUS FOR DETERMINING A ROBUSTNESS METRIC FOR A CIRCUIT DESIGN - Some embodiments provide techniques and systems for determining a change indicator for an endpoint, a pathgroup, a design, and/or a flow. The system can determine base critical path delays and base slacks for the endpoints in a base implementation of the circuit design. The system can then determine the new critical path delays and new slacks for the endpoints in a new implementation of the circuit design. Next, the system determines slack differences for the endpoints using the new slacks and the base slacks. Finally, for each endpoint, the system can determine an endpoint change indicator using the associated slack difference, the base critical path delay, and the new critical path delay. A pathgroup change indicator can be determined using endpoint change indicators. A design change indicator can be determined using pathgroup change indicators or scenario change indicators. A design flow change indicator can be determined using design change indicators. | 08-04-2011 |
| 20110191733 | Segment and Bipartite Graph Based Apparatus and Method to Address Hold Violations in Static Timing - A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking. | 08-04-2011 |
| 20110191734 | DESIGNING APPARATUS, DESIGNING METHOD, AND COMPUTER READABLE MEDIUM - In general, according to one embodiment, a designing apparatus includes a clock tree generator, a logic modifier, a layout modifier, and an outputting module. The clock tree generator is configured to generate a clock tree. The logic modifier is configured to logically insert a delay element in such a manner that a hold violation is modified without considering a setup timing with respect to circuit data corresponding to the clock tree generated by the clock tree generator. The layout modifier is configured to modify a layout of a semiconductor integrated circuit based on a processing result of the logic modifier. The outputting module is configured to output the layout of the semiconductor integrated circuit. The layout is modified by the layout modifier. | 08-04-2011 |
| 20110191735 | SEMICONDUCTOR VERIFICATION APPARATUS, METHOD AND PROGRAM - A semiconductor device which can only load a logical value of an arbitrary memory element is rendered possible to allow a logical value of an arbitrary signal to be loaded at a high speed. A circuit diagram of the semiconductor device is input and a memory element required for calculating a desired signal is detected. The logical value of the memory element is loaded from the semiconductor device, and the logical value of the desired signal is determined in accordance with the logical value of the memory element and the circuit configuration. | 08-04-2011 |
| 20110202894 | Method and Apparatus for Versatile Controllability and Observability in Prototype System - Methods and systems for testing a prototype, the method including receiving, at a first interface component, a configuration parameter associated with a configured image representative of at least a portion of a user design and an associated verification module. The method further includes, sending, using the first interface component, the configured image to a device. A second interface component may be configured to send timing and control information to the verification module based on at least one of the configuration image and runtime control information received from the first interface component. In response to receiving the timing and control information from the second interface component, the verification module may control the device and/or monitor the device state of at least a portion of the user design. | 08-18-2011 |
| 20110214098 | SEMICONDUCTOR DESIGN SUPPORT APPARATUS - A disclosed semiconductor design support apparatus reads circuit description information and generates information required for delay adjustment. The semiconductor design support apparatus includes a logic simulation unit configured to perform logic simulation based on the circuit description information and output logic simulation result information; a latency information acquiring unit configured to acquire, from the logic simulation result information, latency information relating to signals at a signal junction, the signals being output from multiple blocks; an adjustment latency calculating unit configured to calculate, from the latency information, adjustment latency information required for the delay adjustment; and an adjustment delay information generating unit configured to generate, from the adjustment latency information, adjustment delay information required for the delay adjustment. | 09-01-2011 |
| 20110239173 | Common Clock Path Pessimism Analysis for Circuit Designs Using Clock Tree Networks - Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results. | 09-29-2011 |
| 20110252388 | COMPARING TIMING CONSTRAINTS OF CIRCUITS - Timing behaviors associated with constraints of circuits are compared to identify mismatches between circuit configurations. Aggregate sets of timing constraints associated with timing nodes are determined for timing paths between start points and end points. Precedence rules are applied to aggregate sets of timing constraints by applying precedence rules to interacting timing constraints. Aggregate sets of constraints for corresponding timing nodes are matched to determine if timing constraint mismatches exist between circuits. If aggregate timing constraints associated with start point, end point pairs are found to match, reconvergent points between the start point and end points are analyzed to see if aggregate constraints of timing nodes connected to reconvergent/divergent points match if timing exception matches are involved. Graph traversal algorithms allow efficient computation of aggregate timing constraints for timing nodes. | 10-13-2011 |
| 20110252389 | REDUCING CRITICAL CYCLE DELAY IN AN INTEGRATED CIRCUIT DESIGN THROUGH USE OF SEQUENTIAL SLACK - A method is provided that includes: determining a minimum clock cycle that can be used to propagate a signal about the critical cycle in a circuit design; wherein the critical cycle is a cycle in the design that has a highest proportionality of delay to number of registers; determining for a circuit element in the circuit design, sequential slack associated with the circuit element; wherein the sequential slack represents a minimum delay from among respective maximum delays that can be added to respective structural cycles of which the circuit element is a constituent, based upon the determined limit upon clock cycle duration; using the sequential slack to as certain sequential optimization based design flexibility throughout multiple stages of a design flow. | 10-13-2011 |
| 20110258588 | INTEGRATED CIRCUIT DEVICE WITH REDUCED LEAKAGE AND METHOD THEREFOR - A method implemented at a computer aided design tool includes preferentially placing fill regions adjacent to transistors of a first conductivity type for a plurality of standard cell instances of a device design to reduce leakage of the plurality of standard cell instances. Preferentially placing the fill regions includes preferentially placing the fill regions adjacent to transistors of a first conductivity type as compared to placing the fill regions adjacent to transistors of a second conductivity type that is opposite the first conductivity type. | 10-20-2011 |
| 20110265052 | EFFICIENTLY APPLYING A SINGLE TIMING ASSERTION TO MULTIPLE TIMING POINTS IN A CIRCUIT - A computer implemented method, system and/or computer program product efficiently manage timing parameters in a circuit. Multiple instances of a definition are implemented onto a circuit. A set of related pins from the multiple instances are defined, and a common assertion value is asserted against all pins in the set of related pins. | 10-27-2011 |
| 20110271245 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 11-03-2011 |
| 20110276933 | Method for Supporting Multiple Libraries Characterized at Different Process, Voltage, and Temperature Points - A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances. | 11-10-2011 |
| 20110276934 | FORMAL EQUIVALENCE CHECKING BETWEEN TWO MODELS OF A CIRCUIT DESIGN USING CHECKPOINTS - Some embodiments of the present invention provide techniques and systems for determining whether a high-level model (HLM) for a circuit design is equivalent to a register-transfer-level (RTL) model for the circuit design. During operation, a system can identify a set of checkpoints. Each checkpoint can be associated with a characteristic function defined over the states of a finite-state-machine (FSM) representation of the HLM, a characteristic function defined over the states of an FSM representation of the RTL model, and an invariant defined over a set of variables in the HLM and a set of registers in the RTL model. Next, the system can generate a set of invariant proof problems, wherein each invariant proof problem corresponds to a transition between two checkpoints in the set of checkpoints. The system can then determine whether the HLM is equivalent to the RTL model by solving the set of invariant proof problems. | 11-10-2011 |
| 20110289464 | GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT - Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate. | 11-24-2011 |
| 20110296361 | CIRCUIT ANALYSIS METHOD - A maximum delay of a combinational circuit is accurately reduced in consideration of a correlation between variations in delays of devices (transistors etc.) and interconnects. Circuit modification candidate information about a circuit modification candidate for improving a delay of a circuit to be designed is generated based on circuit information about the circuit to be designed, technology information about a distribution of a characteristic of a device and/or an interconnect based on a process to be designed, delay distribution information about a distribution of the delay in the circuit to be designed, and delay correlation information about a correlation between variations in the delay in the circuit to be designed. | 12-01-2011 |
| 20110307850 | RECURSIVE HIERARCHICAL STATIC TIMING ANALYSIS - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 12-15-2011 |
| 20110307851 | STATIC VERIFICATION PROGRAM, STATIC VERIFICATION DEVICE, AND STATIC VERIFICATION METHOD - A static verification program according to the present invention reads a circuit description and property. In a static verification step, static verification of the circuit description is performed on the basis of the property and the number of states that can be reached and the number of states that is reached are calculated. In a search coverage value calculation step, a search coverage value is calculated on the basis of the number of states that can be reached and the number of states that is reached. In a display step, the search coverage value is displayed in a state in which the search coverage value can be visually checked. | 12-15-2011 |
| 20120005641 | SEMICONDUCTOR DESIGNING APPARATUS - The present invention provides a semiconductor designing apparatus realizing dispersed power consumption timings without causing a setup violation and a hold violation. An STA unit calculates a setup slack as a margin of setup time of a flip-flop on the basis of a present design value of a clock latency of the flip-flop. Based on the calculated setup slack, an HSLD unit adjusts the clock latency of the flip-flop so as to be advanced more than a present design value without causing a timing violation. When a peak equal to or larger than a threshold value remains in the number of synchs in a clock latency distribution as a result of the latency control of the HSLD unit, a PAS unit smoothes the clock latency of the flip-flop without causing a timing violation on the basis of the timing information recalculated by the HSLD unit. | 01-05-2012 |
| 20120023466 | IMPLEMENTING FORWARD TRACING TO REDUCE PESSIMISM IN STATIC TIMING OF LOGIC BLOCKS LAID OUT IN PARALLEL STRUCTURES ON AN INTEGRATED CIRCUIT CHIP - A method, system and computer program product are provided for implementing forward tracing to reduce pessimism in static timing of logic blocks laid out in parallel structures on an integrated circuit chip. A common path pessimism removal algorithm is enhanced by a forward tracing parallel clock tree proximity credit algorithm that uses forward tracing, and computes a proximity credit that is applied to reduce pessimism in the static timing. | 01-26-2012 |
| 20120042294 | APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN - Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them. | 02-16-2012 |
| 20120047477 | Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis - Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof. | 02-23-2012 |
| 20120047478 | Method For Estimating The Latency Time Of A Clock Tree In An Asic Design - Estimating the latency time of the clock tree of an ASIC including: providing a netlist and a placement related to the clock tree of the ASIC; extracting a number of the load timing devices connected by the clock tree according to the netlist related to the clock tree; extracting a physical distribution area of the load timing devices connected by the clock tree according to the placement related to the clock tree; estimating a latency time of the clock tree according to the relationship between the number of the load timing devices, the physical distribution area of the load timing devices and latency time of the clock tree in design data related to the ASIC design. | 02-23-2012 |
| 20120060133 | Annotation of RTL to Simplify Timing Analysis - A method for simulating operation of a design model for a digital system is provided. A library of functional cells is maintained in a storage unit that includes an attribute template with one or more of the functional cells in the library. The attribute template provides fields for specifying design constraint data for a functional cell each time it is instantiated in a design model. A design model is created and stored that includes one or more instantiations of a functional cell and its associated design constraint data. A set of test cases may be pruned to remove test cases that are not needed based on the design constraint data associated with the instantiated functional cells of the design model. | 03-08-2012 |
| 20120066656 | Parallel Parasitic Processing In Static Timing Analysis - A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect parasitics can be processed and stored on disk. Information on attaching to the stored parasitic data can be generated and provided to the main process during the step of performing the timing update. The parallel process can run concurrently and asynchronously with the main process. | 03-15-2012 |
| 20120079441 | Nonlinear Approach to Scaling Circuit Behaviors for Electronic Design Automation - Circuit behaviors are scaled to different operating conditions by using a generalized nonlinear model. Nonlinear transforms are applied to the operating conditions and/or to the circuit behaviors contained in a library set. The transformed quantities have a more linear relationship between them. Parameters for the linear relationship are estimated based on the data and operating conditions in the library set. These parameters and nonlinear transforms can then be used to scale circuit behaviors to operating points not contained in the library set. | 03-29-2012 |
| 20120124534 | System and Method for Performing Static Timing Analysis in the Presence of Correlations Between Asserted Arrival Times - A method of applying common path credit in a static timing analysis in the presence of correlations between asserted arrival times, comprising the steps of using a computer, identifying one or more pairs of asserted arrival times for which one or more correlations exist; propagating to each of the one or more pairs of asserted arrival times a timing value dependent on the one or more correlations; and performing a subsequent common path pessimism removal analysis for at least one test during which a timing value dependent on the one or more correlations between asserted arrival times is used to compute an adjusted test slack. | 05-17-2012 |
| 20120131525 | METHOD AND APPARATUS FOR FIXING DESIGN REQUIREMENT VIOLATIONS IN MULTIPLE MULTI-CORNER MULTI-MODE SCENARIOS - Systems and techniques for fixing design requirement violations in a circuit design in multiple scenarios are described. During operation, a system can receive a scenario image and a multi-scenario ECO database. The scenario image can store parameter values for circuit objects in a scenario, and the multi-scenario ECO database can store a subset of parameter values for a subset of circuit objects in multiple scenarios. Next, the system can determine an engineering change order to fix one or more design requirement violations, which can involve estimating parameter values for circuit objects in multiple scenarios using parameter values stored in the scenario image and the multi-scenario ECO database. | 05-24-2012 |
| 20120144353 | Method for Implementing Timing Point Engineering Change Orders in an Integrated Circuit Design Flow - A method and system for automatically implementing engineering change order (ECO) corrections in an integrated circuit (IC) include a design tool performing a timing analysis on a netlist of the IC. The method may also include annotating each of the device cells with a worst timing slack through a respective timing point associated with the device cell. In addition, the method may include generating an ECO list of device cells needing ECO correction and prioritizing the ECO correction order of the device cells in the ECO list based upon cell attributes. The method may further include excluding device cells in the ECO list based upon the fan-in or fan-out connection path of other device cells in the ECO list that will be corrected, and the design tool selecting and replacing device cells in the ECO list with different device cells from a design library. | 06-07-2012 |
| 20120151425 | System and Method for Automatically Managing Clock Relationships in Integrated Circuit Designs - Systems and methods for identifying and managing the relationships between clock domains in an integrated circuit design are disclosed. A computer-implemented method analyzes the behavioral structure of the clock-to-clock logical relationships in a proposed integrated circuit design. In one embodiment, the method comprises receiving as inputs a description of the design (in a synthesizable format or a synthesized gate-level netlist and definitions of the clock waveforms and timing constraints used in the design, and automatically identifying the relationships between the clocks specified in the description and categorizing the relationships into a plurality of behavioral categories. A list of timing exceptions may optionally also be provided as an input. The identified relationships between clocks and the behavioral categories may be used to verify any existing timing exceptions between clock pairs, and/or to create any missing exceptions between the clock pairs. | 06-14-2012 |
| 20120159410 | Method for Identifying Redundant Signal Paths for Self-gating Signals - A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic. | 06-21-2012 |
| 20120174048 | METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING A PARTITIONED HIERARCHICAL DESIGN FLOW AND AN APPARATUS EMPLOYING THE METHOD - Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies. | 07-05-2012 |
| 20120185810 | Method for Improving Static Timing Analysis and Optimizing Circuits Using Reverse Merge - Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs. | 07-19-2012 |
| 20120185811 | Method and Apparatus for Automated Circuit Design - Methods and apparatuses to automatically modify a circuit design (e.g., a synthesis solution) according to the sensitivity in design parameters with respect to the possible deviation in the subsequent implementation (e.g., placement and routing) of the circuit. In one aspect of the present invention, a method to design a circuit includes: determining likelihood of a design constraint being violated in an implementation of a first circuit design (e.g., a technology specific netlist with or without a placement solution); and, modifying the first circuit design to reduce the likelihood of the design constraint being violated. In one example, the implementation of the first circuit design includes a routing solution for implementing the first circuit design; and, the first circuit is modified through sizing an instance of a logic element, buffering a signal, load shielding for a signal, or other operations. | 07-19-2012 |
| 20120192133 | LOGIC DESIGN VERIFICATION TECHNIQUES FOR LIVENESS CHECKING WITH RETIMING - A technique for verification of a retimed logic design using liveness checking includes assigning a liveness gate to a liveness property for an original netlist and assigning a fairness gate to a fairness constraint for the original netlist. In this case, the fairness gate is associated with the liveness gate and is asserted for at least one time-step during any valid behavioral loop associated with the liveness gate. The original netlist is retimed, using a retiming engine, to provide a retimed netlist. The liveness and fairness gates of the retimed netlist are retimed such that a lag of the fairness gate is no greater than a lag of the liveness gate. Verification analysis is then performed on the retimed netlist. Finally, when the verification analysis yields a valid counter-example trace for the retimed netlist, a liveness violation for the original netlist is returned. | 07-26-2012 |
| 20120210282 | VERIFICATION SUPPORT APPARATUS, VERIFYING APPARATUS, COMPUTER PRODUCT, VERIFICATION SUPPORT METHOD, AND VERIFYING METHOD - A verification support apparatus includes a detecting unit that detects an inconsistency between a simulation result at an observation point in a circuit-under-test and an expected value; a setting unit that sets a portion of output values to logic values different from those of the simulation result when the detecting unit detects the inconsistency, wherein the output values are random values output from elements that receive a signal in a second clock domain that receives the signal from a first clock domain asynchronously; a comparing unit that compares the expected value and a simulation result at the observation point after the setting by the setting unit; and an identifying unit that identifies whether the portion of the output values are a cause of the inconsistency, based on a result of comparison by the comparing unit. | 08-16-2012 |
| 20120254815 | Method and System for Synthesizing Relative Timing Constraints on an Integrated Circuit Design to Facilitate Timing Verification - A method for synthesizing relative timing (RT) constraints on an integrated circuit design is disclosed. Initially, multiple trace status tables are received, each containing a trace error identified by a formal verification engine that was utilized to perform a RT verification on an integrated circuit design. An error causing signal is then recognized for each of the trace errors. For each of error causing signals, two associating signals are identified, and the two associating signals are then utilized to locate a common point of convergence (POC). The POC is further utilized to locate a common point of divergence (POD), and an RT constraint can be generated based on the identified POC and POD. All the generated RT constraints are applied to constrain the integrated circuit design such that the integrated circuit design is able to pass RT verifications in the future without any timing violations. | 10-04-2012 |
| 20120266119 | Delay Model Construction In The Presence Of Multiple Input Switching Events - A method for constructing delay rules which include the effects of MIS simulations for static timing analysis with reduced cost. The present method includes constructing skew windows for applying MIS penalties purely from SIS data, and scales the MIS penalties during rule use based upon how closely the skews in the use case approach the edge of the skew window. The method applies both to timing rule construction for a library of circuits and to timing rule construction for macros where only part of the circuits in the macro may be sensitive to skew between macro inputs. | 10-18-2012 |
| 20120278775 | Method and Apparatus for Generating Memory Models and Timing Database - A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads. | 11-01-2012 |
| 20120284677 | SLACK-BASED TIMING BUDGET APPORTIONMENT - A slack-based timing budget apportionment methodology relies not only upon timing analysis-based determinations of slack in the units in an integrated circuit design, but also potential performance optimization opportunities in the logic used to implement such circuits. Logic in various units of an integrated circuit design that is amenable to being replaced with comparatively faster logic may be identified during timing budget apportionment, such that the magnitude of the slack reported for those units can be adjusted to account for such potential performance improvements. Then, when timing budgets are reapportioned using the slack calculated for each unit, additional slack is available to be reapportioned to those units needing larger timing budgets. | 11-08-2012 |
| 20120290994 | TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT - A method of reducing total power dissipation for logic cells includes selecting a distribution of logic cells corresponding to at least one path, computing a dynamic to static power ratio for each logic cell in the distribution of logic cells and ranking the dynamic to static power ratio for each logic cell into a lower group, a middle group and an upper group of logic cells. Additionally, the method includes swapping the lower group of logic cells and the upper group of logic cells for a reconfigured middle group of logic cells and verifying path timing for the reconfigured middle group of logic cells. Methods of reducing total power dissipation using Boolean equations and for logic cell sets are also provided. | 11-15-2012 |
| 20120304136 | Clock Tree Planning for an ASIC - The present invention discloses a method and system for clock tree planning for an ASIC, the method comprising: determining a netlist and a timing constraint file of the ASIC; creating a sequential device undirected graph for sequential devices in the netlist according to connection relationships of the sequential devices in the netlist and timing constraint relationships of the sequential devices in the timing constraint file; grouping the sequential devices in the netlist according to the sequential device undirected graph, such that the sequential devices in one group do not have a timing constraint relationship with the sequential devices in another group. The ASIC design method improved by using this method will reduce the design cycle from weeks to days, and enable designer to quickly plan the clock tree, thus reducing the design time and improving the design efficiency. | 11-29-2012 |
| 20120311514 | Decentralized Dynamically Scheduled Parallel Static Timing Analysis - A method for performing a parallel static timing analysis in which multiple processes independently update a timing graph without requiring communication through a central coordinator module. Local processing queues are used to reduce locking overhead without causing excessive load imbalance. A parallel analysis is conducted on a circuit design represented by a timing graph formed by a plurality of interconnected nodes, the method including: using a computer for creating a shared work queue of ready to process independent nodes; assigning the independent nodes from the work queue to at least two parallel computation processes, simultaneously performing node analysis computations thereof; and modifying the circuit design by updating values of the processed independent nodes obtained from the node analysis, the at least two parallel computation processes independently updating the shared work queue to process a new plurality of independent nodes. | 12-06-2012 |
| 20120311515 | Method For Performing A Parallel Static Timing Analysis Using Thread-Specific Sub-Graphs - A method for efficient multithreaded analysis of a timing graph is described. The method is applicable to multithreaded common path pessimism removal, critical path traversing for timing report generation, and other types of analysis requiring traversal of sub-graphs of timing graph. In order to achieve high efficiency and scalability for parallel multithreaded execution, the number of access locks is minimized. One parent computation thread and multiple child threads are employed. The parent computational thread identifies the tasks for analysis and distributes them among child threads. Each child thread identifies a sub-graph to be analyzed, creates a thread-specific replica of the identified sub-graph, and performs the analysis required. After completing the analysis, the child thread transfers the results back to the main timing graph and waits for next task. As all data structures of each child thread are accessed only by the child thread owing them, no access locks are required for construction and processing of thread specific graph replica of the timing sub-graph. The construction of each thread specific graph replica is performed by the child thread without locking the main timing graph data structures. Access locks are used only for transferring results of the analysis back to the main timing graph where the results computed by all child threads are combined together. | 12-06-2012 |
| 20120317527 | PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION - A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions. | 12-13-2012 |
| 20130007681 | YIELD BASED FLOP HOLD TIME AND SETUP TIME DEFINITION - Systems and method for defining a timing parameter for a circuit element based on process variation, including, determining a point of failure parameter associated with the timing parameter, the point of failure parameter correlated with a specific value of the process variation. A standard deviation associated with the point of failure parameter is determined. The process variation per the standard deviation is calculated and the timing parameter for the circuit element is defined as a function of the failure parameter, the standard deviation, and the process variation per the standard deviation. A margin factor, which varies with the standard deviation, is optionally applied to the timing parameter. The timing parameter may be one of a setup time or hold time. | 01-03-2013 |
| 20130036393 | NOVEL MODELING APPROACH FOR TIMING CLOSURE IN HIERARCHICAL DESIGNS LEVERAGING THE SEPARATION OF HORIZONTAL AND VERTICAL ASPECTS OF THE DESIGN FLOW - A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block. | 02-07-2013 |
| 20130055182 | COMPUTER PRODUCT, VERIFICATION SUPPORT METHOD, AND VERIFICATION SUPPORT APPARATUS - A computer-readable medium stores a verification support program that causes a computer to execute a process that includes executing a first simulation of applying a given input pattern to circuit information of a circuit under test having a first clock domain and a second clock domain that receives asynchronously a signal from the first clock domain; detecting during execution of the first simulation, an output value that is a random value output by an element in the second clock domain; copying the execution state of the first simulation at the time of detection of the output value; setting in the copied execution state of the first simulation, output of the element in the second clock domain, to a logic value that is different from the detected output value; and executing, exclusive of the first simulation, a second simulation that is based on the set execution state. | 02-28-2013 |
| 20130061190 | IDENTIFYING SPEED BINNING TEST VECTORS DURING SIMULATION OF AN INTEGRATED CIRCUIT DESIGN - A method for automated functional coverage includes creating event monitors that monitor signals and events within an IC design based upon timing information in a timing report generated by a timing analysis tool. In particular, speed paths that have a higher timing criticality may be selected for monitoring during simulations of the IC design. In addition, if an event is detected on a speed path, the endpoint of that speed path may be forced to a failing value, and the simulation may be resumed. At some point later in the simulation, the simulation results may be checked to determine if a failure that corresponds to the failing value was observed at a structure that would be visible on a manufactured version of the IC design. If the failure is visible, the test vectors that were used may be identified and captured for use in production testing. | 03-07-2013 |
| 20130074020 | METHOD FOR IDENTIFYING REDUNDANT SIGNAL PATHS FOR SELF-GATING SIGNALS - A method for identifying and removing redundant signal paths includes determining whether a given input to a logic circuit is coupled to both an input of a cone of logic of a data input of a clocked state element and a clock gate circuit that is coupled to disable a clock input to the clocked state element. The method may include removing the given input from the cone of logic such that the given input is no longer coupled to the input of the cone of logic responsive to determining that the given input is coupled to both the input of the cone of logic and the clock gate circuit. The method may include preserving the given input to the clock gate circuit such that the given input continues to be coupled to the clock gate circuit after being removed from the input of the cone of logic. | 03-21-2013 |
| 20130074021 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 03-21-2013 |
| 20130074022 | CLOCK ALIAS FOR TIMING ANALYSIS OF AN INTEGRATED CIRCUIT DESIGN - A timing analysis mechanism allows defining a clock alias that correlates a clock that is not present in an integrated circuit design to a real clock in the integrated circuit design. In a first implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a new user assertion that references the real clock specified in the clock alias. The new user assertion is then used in the timing analysis and the existing user assertion is not. In a second implementation, when an existing user assertion references a clock alias, the timing analysis mechanism generates a duplicate clock in the timing database, preserving all its attributes, and then passes the assertion using the alias name as well as any assertions using the corresponding real clock name to the timing engine to be used in the timing analysis. | 03-21-2013 |
| 20130097567 | CYCLE CUTTING WITH TIMING PATH ANALYSIS - The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow. | 04-18-2013 |
| 20130125073 | TEST PATH SELECTION AND TEST PROGRAM GENERATION FOR PERFORMANCE TESTING INTEGRATED CIRCUIT CHIPS - A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths | 05-16-2013 |
| 20130145331 | SEQUENTIAL SIZING IN PHYSICAL SYNTHESIS - Techniques and systems for optimizing a circuit design are described. In some embodiments, a sequential cell is selected for optimization. Next, the system iterates through a set of candidate sequential cells that are functionally equivalent to the sequential cell that is being optimized. The system evaluates the global timing impact of each candidate sequential cell in a highly efficient manner. For each candidate sequential cell that is evaluated, a non-timing metric and a timing metric for a candidate sequential cell are compared with the corresponding non-timing metric and timing metric for the current best sequential cell. If a candidate sequential cell improves the timing metric, or maintains the timing metric and has better non-timing metric(s), then the candidate sequential cell is stored as the current best sequential cell. Once the process completes, the current best sequential cell is the optimized cell size for the sequential cell. | 06-06-2013 |
| 20130167096 | LOCATION AND TIMING WINDOW BASED DECOUPLING CAPACITOR EVAULATION TOOL AND METHOD - A method of designing an integrated circuit includes receiving a placement database of logic devices of an electronic device design that includes first and second logic devices. The method further includes determining a first timing window associated with a first state transition of the first logic device, and a second timing window associated with a second state transition of the second logic device. In the event that the first and second timing windows overlap, the placement database is modified, thereby reducing interaction of the first and second logic devices. | 06-27-2013 |
| 20130179851 | STATISTICAL CORNER EVALUATION FOR COMPLEX ON CHIP VARIATION MODEL - The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). | 07-11-2013 |
| 20130185685 | TIMING ANALYSIS OF AN ARRAY CIRCUIT CROSS SECTION - A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity. | 07-18-2013 |
| 20130185686 | SEMICONDUCTOR CIRCUIT DESIGN SUPPORTING APPARATUS AND METHOD, AND NON-TRANSITORY COMPUTER-READABLE MEDIUM - A semiconductor circuit design supporting method includes: reading Register Transfer Level (RTL) description circuit data; generating an equivalent circuit corresponding to the RTL description circuit data; extracting a plurality of arithmetic components included in the generated equivalent circuit; clustering some of the extracted arithmetic components as a single arithmetic component, wherein no storage element exists between said some of the extracted arithmetic components; reading a timing constraint on the RTL description circuit data; tracing an exception path of the RTL description circuit data when the timing constraint includes a timing exception; determining whether or not the timing exception is set for input pins of said some of the arithmetic components which are clustered as the single arithmetic component, based on the traced exception path of the RTL description circuit data; and separating a arithmetic component for which the timing exception is set, from said some of the arithmetic components which are clustered as the single arithmetic component. | 07-18-2013 |
| 20130219352 | LSI DESIGN METHOD - Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs. | 08-22-2013 |
| 20130227506 | TIMING VERIFICATION METHOD FOR DETERMINISTIC AND STOCHASTIC NETWORKS AND CIRCUITS - The timing verification method for deterministic and stochastic networks and circuits is a computerized method that includes a non-enumerative path length analysis algorithm for deterministic and stochastic directed acyclic graphs (DAGs) with applications to timing verification of circuits, the algorithm computing statistical measures of path lengths without storing and/or manipulating the paths in such networks. The timing verification method is able to compute deterministic or probabilistic costs assigned to edges, vertices, or both. | 08-29-2013 |
| 20130227507 | Recursive Hierarchical Static Timing Analysis - A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block. | 08-29-2013 |
| 20130246989 | SYSTEM AND METHOD FOR METASTABILITY VERIFICATION OF CIRCUITS OF AN INTEGRATED CIRCUIT - A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system. | 09-19-2013 |
| 20130254728 | COMPUTER PRODUCT, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT APPARATUS - A computer-readable recording medium stores a design support program that causes a computer to execute a process that includes generating based on a control flow graph conversion result for operation description information concerning a circuit-under-design, a first synthesis result according to which a time length of 1 clock cycle of the circuit-under-design is greater than or equal to a clock period in which the circuit-under-design operates; calculating based on the generated first synthesis result, first circuit scale information indicating a circuit scale of the circuit-under-design; acquiring a second synthesis result that is for the circuit-under-design and conforms to a timing constraint that is based on the control flow graph conversion result; calculating second circuit scale information indicating the circuit scale of the circuit-under-design, based on the generated second synthesis result; and outputting the calculated first circuit scale information and the calculated second circuit information. | 09-26-2013 |
| 20130268907 | BEST CLOCK FREQUENCY SEARCH FOR FPGA-BASED DESIGN - Searching for desired clock frequency for integrated circuit-based design may receive timing result of a hardware synthesis job executed based on a code specifying hardware design. One or more different timing constraints specifying respective one or more different clock frequencies than used in the hardware synthesis job may be automatically generated without modifying the code. One or more instances of the hardware synthesis job to run with the respective one or more different timing constraints may be automatically spawned. The automatic generation and spawning may repeat until a termination criterion is met, and/or a desired successful timing constraint is identified for the hardware design from the different timing constraints based on whether the one or more instances of the hardware synthesis job met their respective timing constraints. | 10-10-2013 |
| 20130275932 | TIMING ANALYSIS PROGRAM, TIMING ANALYSIS APPARATUS, AND TIMING ANALYSIS METHOD - A timing analysis program for performing analysis condition generation processing which generates a first analysis condition in which the variation width of a first delay value of a first circuit cell is shifted on the basis of a first variation coefficient and a second analysis condition in which the variation width of a second delay value of a second circuit cell is shifted on the basis of a second variation coefficient. | 10-17-2013 |
| 20130290920 | DESIGN AND ANALYSIS OF DIGITAL CIRCUITS WITH TIME DIVISION MULTIPLEXING - Methods and apparatuses to design and analyze digital circuits with time division multiplexing. In one embodiment, the method for designing a digital circuit comprises determining signal timing for a portion of the digital circuit, and automatically replacing nets for a plurality of connections in the digital circuit with a Time Division Multiplexing (TDM) channel in response to a determining of routing congestion. | 10-31-2013 |
| 20130305201 | INTEGRATED CIRCUIT SIMULATION USING FUNDAMENTAL AND DERIVATIVE CIRCUIT RUNS - A system that simulates an integrated circuit is formed of a plurality of devices. The system initially performs a fundamental circuit simulation run using original parameters for the plurality of devices and an initial time step. The system generates one or more fundamental time steps from the fundamental circuit simulation run. The fundamental time steps are generated when changes that indicate state time derivatives during two or more successive integration steps are within a predetermined range. The system stores the one or more fundamental time steps as fundamental circuit events in an events queue, and updates the parameters for the plurality of devices based on the fundamental circuit events to generate one or more derivative circuits. The system then performs one or more derivative circuit simulation runs using the derivative circuits. | 11-14-2013 |
| 20130318488 | EXCLUDING LIBRARY CELLS FOR DELAY OPTIMIZATION IN NUMERICAL SYNTHESIS - Methods and systems for excluding library cells are described. Some embodiments receive a generic logical effort value and optionally a generic parasitic delay value for a timing arc of a library cell type. Next, library cells of the library cell type are excluded whose specific logical effort values for the timing arc are greater than the generic logical effort value by more than a first threshold and/or optionally whose specific parasitic delay values for the timing arc are greater than the generic parasitic delay value by more than a second threshold. A new generic logical effort value and optionally a new generic parasitic delay value can be determined based on at least some of the remaining library cells. The process of excluding library cells and determining new generic logical effort values and optionally new generic parasitic delay values can be performed iteratively. | 11-28-2013 |
| 20130346931 | TIMING ERROR REMOVING METHOD AND DESIGN SUPPORT APPARATUS - A timing error removing method includes selecting a logic-level correction location and a first buffer to be inserted at the correction location, the logic-level correction location and the first buffer being able to remove a timing error in a semiconductor integrated circuit to be designed; and searching for a vacant area in the semiconductor integrated circuit where the first buffer can be placed for the correction location, and if the vacant area is not found, further searching for a combination of a plurality of buffers smaller than the first buffer, the combination of the plurality of buffers being to be placed in the semiconductor integrated circuit and being able to replace the first buffer in terms of a delay obtained as if the first buffer is inserted. | 12-26-2013 |
| 20130346932 | INTELLIGENT TIMING ANALYSIS AND CONSTRAINT GENERATION GUI - A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results. | 12-26-2013 |
| 20140040841 | APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN - Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them. | 02-06-2014 |
| 20140040842 | TOTAL POWER OPTIMIZATION FOR A LOGIC INTEGRATED CIRCUIT - A method of reducing total power dissipation for logic cells using Boolean equations includes selecting a path, identifying at least one group of logic cells for analysis in the path, and deriving Boolean equations for the at least one group of logic cells. Additionally, the method includes listing possible logic cell implementations for each Boolean equation while maintaining original transistor values, verifying path timing for the possible logic cell implementations to provide retained logic cells that achieve a path timing requirement, computing a total power dissipation for the retained logic cells, and choosing a logic cell set from the retained logic cells corresponding to a minimum total power dissipation for the path. A method for reducing total power dissipation for logic cell sets and a processor configured to reduce total power dissipation for groups of logic cells are also provided. | 02-06-2014 |
| 20140047402 | LSI DESIGN METHOD AND LSI DESIGN DEVICE - In an LSI design method of designing a clock tree that supplies a clock signal to a plurality of leaves from a clock supply point, when a high level clock tree is constituted by H-tree and a low level clock tree is formed by CTS, the number of stages of a high level clock tree is optimized without giving any constraint on the placement of a low level clock tree. The leaves are divided into a plurality of groups to form a low level local tree. A clock-supplied region including all leaves to be supplied with a clock is uniformly divided and for each divided region, a skew when a clock signal is supplied from an end of an H-tree to start points of a plurality of local trees included in that region is estimated. The clock-supplied region is more finely equally-divided to increase the number of stages of H-tree. | 02-13-2014 |
| 20140047403 | Statistical Corner Evaluation For Complex On-Chip Variation Model - The invention provides a method for performing statistical static timing analysis using a novel on-chip variation model, referred to as Sensitivity-based Complex Statistical On-Chip Variation (SCS-OCV). | 02-13-2014 |
| 20140059505 | METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CORRECT-BY-CONSTRUCTION PROGRESSIVE MODELING AND AN APPARATUS EMPLOYING THE METHOD - Methods of designing an integrated circuit and an apparatus for designing an integrated circuit are disclosed herein. In one embodiment, a method includes: (1) generating a block model of the integrated circuit according to a first timing budget, (2) developing a top level implementation of the integrated circuit according to the first timing budget, (3) determining a second timing budget for the integrated circuit based on the block model and (4) modifying the block model and the top level implementation employing the second timing budget to provide a progressive block model and a modified top level implementation. | 02-27-2014 |
| 20140068533 | INFORMATION THEORETIC SUBGRAPH CACHING - Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach. | 03-06-2014 |
| 20140082573 | CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND COMPUTER PRODUCT - A circuit design support apparatus includes a processor configured to calculate a time period necessary for a transition of a logical state, based on circuit configuration information indicating connection relations of elements of an integrated circuit and input information indicating a logical value input into an input terminal of the integrated circuit; calculate capacitance between power source wires in each logical state based on the circuit configuration information and the input information; and calculate temporal variation of the capacitance based on the capacitance and the time period. | 03-20-2014 |
| 20140101629 | EARLY DESIGN CYCLE OPTIMZATION - Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component. | 04-10-2014 |
| 20140123089 | MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING - Systems and methods for modeling multi-patterning variability with statistical timing analysis during IC fabrication are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to define at least one source of variation in an integrated circuit design. The programming instructions further operable to model the at least one source of variation for at least two patterns in at least one level of the integrated circuit design as at least two sources of variability respectively. | 05-01-2014 |
| 20140130000 | STRUCTURAL RULE ANALYSIS WITH TCL SCRIPTS IN SYNTHESIS OR STA TOOLS AND INTEGRATED CIRCUIT DESIGN TOOLS - A method of designing a circuit, an apparatus and a structural analysis tool are disclosed. In one embodiment, the structural analysis tool includes: (1) a structural analyzer configured to apply a structural rule to the circuit design in a design environment of said design process having valid timing data and (2) a structural assessor configured to generate structural data of the circuit design based on application of the structural rule by the structural analyzer. | 05-08-2014 |
| 20140189624 | ABSTRACT CREATION - Systems and techniques for creating a circuit abstraction are described. During operation, an embodiment can identify a set of side loads based on a set of timing paths. According to one definition, a side load of a timing path is a circuit element that is not on the timing path (i.e., the timing path does not pass through the circuit element), but whose input is electrically connected to an output of at least one circuit element that is on the timing path. Next, the embodiment can creating the circuit abstraction by retaining circuit elements and nets on each timing path in the set of timing paths, and retaining an identifier for each side load in the set of side loads. The circuit abstraction can then be used to update timing information during one or more stages of an electronic design automation flow. | 07-03-2014 |
| 20140223398 | METHOD FOR DETERMINING INTERFACE TIMING OF INTEGRATED CIRCUIT AUTOMATICALLY AND RELATED MACHINE READABLE MEDIUM THEREOF - A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file. | 08-07-2014 |
| 20140245244 | SETTING SWITCH SIZE AND TRANSITION PATTERN IN A RESONANT CLOCK DISTRIBUTION SYSTEM - Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit. | 08-28-2014 |
| 20140282317 | ARRIVAL EDGE USAGE IN TIMING ANALYSIS - A logic design is analyzed using static timing analysis and timing edge tracking for various nets within the logic design. Crosstalk analysis is performed on the logic design to evaluate timing impacts. To reduce pessimism of crosstalk analysis for a victim net, arrival edges are tracked for the victim net. The switching times of the aggressor net are compared to the edges of the victim net during crosstalk analysis. | 09-18-2014 |
| 20140282318 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 09-18-2014 |
| 20140282319 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted. | 09-18-2014 |
| 20140282320 | ANALYZING TIMING REQUIREMENTS OF A HIERARCHICAL INTEGRATED CIRCUIT DESIGN - Logic gates in a child unit of a hierarchical integrated circuit design that are visible in an abstract model of the child unit of the hierarchical integrated circuit design are marked. A hide bit is set for the marked logic gates and a modification on the child unit is performed. The marked logic gates in the child unit are preserved during modification of the child unit. The hide bit is cleared from each marked logic gate and the logic gates are unmarked when modification of the child unit is complete. | 09-18-2014 |
| 20140282321 | SYSTEM AND METHOD FOR A HYBRID CLOCK DOMAIN CROSSING VERIFICATION - A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage. Results are then reiterated through the system back to the static CDC verification. | 09-18-2014 |
| 20140282322 | SYSTEM AND METHOD FOR FILTRATION OF ERROR REPORTS RESPECTIVE OF STATIC AND QUASI-STATIC SIGNALS WITHIN AN INTEGRATED CIRCUIT DESIGN - A system and method identify potentially static and/or quasi-static signals within an integrated circuit (IC), or portion thereof. Static and quasi-static signals may be identified in a design description of the IC by any one or more of: (1) a fan-out size exceeding some threshold, (2) a toggle frequency in a simulation trace that is below some threshold, and (3) a signal name that appears in a list accessed from the memory. Identification of static and quasi-static signals is performed, typically, as part of a verification process in order to flag cases where the verification system would otherwise indicate an error (e.g., at a clock domain crossing). Identifying a signal of the IC as being static or quasi-static improves the quality of results of verification and makes it easier for a prospective user to concentrate on actual rather than spurious issues reported during verification. | 09-18-2014 |
| 20140289686 | Single Event Upset Mitigation for Electronic Design Synthesis - Technology is disclosed herein that provides for modifying a circuit design to reduce the potential occurrence of single event upset errors during operation of a device manufactured from the synthesized design. After a circuit design has been synthesized to a particular abstraction level, a static timing analysis procedure is run on the design. The slack values for paths within the design are determined based upon the static timing analysis procedure. Subsequently, delays are added to selected paths within the design based upon the slack values. | 09-25-2014 |
| 20140325463 | Integrated Circuit Design Verification Through Forced Clock Glitches - A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions. | 10-30-2014 |
| 20150026653 | RELATIVE TIMING CHARACTERIZATION - Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point of convergence (poc) events, wherein the two poc events include a first poc event (poc | 01-22-2015 |
| 20150026654 | Hierarchical Verification Of Clock Domain Crossings - The invention provides for the hierarchical verification of clock domain crossings. In various implementations of the invention, a device design is partitioned into blocks. Subsequently, a block level clock domain crossing verification process is performed on selected ones of the blocks. Verification interface files are generated by the block level clock domain crossing process. After which, a top level clock domain crossing verification process is performed over the entire design. In various implementations, the top level clock domain crossing verification process utilizes the verification interface files to verify clock domain crossing signals between blocks. Additionally, in some implementations, blocks not verified during block level verification are verified during top level verification. With some implementations of the invention, the device design is partitioned based input from a user of the implementation. Furthermore, in various implementations, the specific clock domain crossing verification checks employed during block level verification and top level verification are specified by a user of the implementation. | 01-22-2015 |
| 20150033196 | Clustering For Processing Of Circuit Design Data - Nodes in microdevice design data are selected to form initial clusters. Typically the nodes are selected based upon the type of process to be performed on the design data. The initial clusters are then be grown, merged with other nodes, or come combination of both until the processing costs of the final clusters are compatible with the amount of resources that will be used to process the design data. | 01-29-2015 |
| 20150067623 | TIMING ANALYSIS METHOD FOR NON-STANDARD CELL CIRCUIT AND ASSOCIATED MACHINE READABLE MEDIUM - A timing analysis method applied for a non-standard cell circuit, includes: identifying at least a first register and a second register from the circuit; calculating at least one path delay of at least one path between the first register and the second register; calculating a first register clock delay from a first clock source to a first register clock input terminal of the first register; calculating a second register clock delay from a second clock source to a second register clock input terminal of the second register; and determining whether timing violation takes place in respect of the second register according to the path delay, the first register clock delay, the second register clock delay, and a first register delay of the first register. | 03-05-2015 |
| 20150082264 | MINIMIZING THE USE OF CHIP ROUTING RESOURCES WHEN USING TIMESTAMPED INSTRUMENTATION DATA - A timestamp generator generates a timestamp value having a predetermined number of most significant bits and a predetermined number of least significant bits. The least significant bits are transmitted to a client via a parallel data bus. The most significant bits are transmitted to the client sequentially via a series data bus. Each client receives the parallel least significant bits and the series most significant bits and assembles a complete time stamp value. | 03-19-2015 |
| 20150113488 | CONGESTION ESTIMATION TECHNIQUES AT PRE-SYNTHESIS STAGE - A method analyzes RTL code to determine congestion of a logic design without completing a synthesis phase of a chip design process. The method can include receiving RTL code, and identifying a statement in the RTL code. The method can include determining that the statement in the RTL code corresponds to a structured device group in a component library, wherein the structured device group includes logic devices configured to occupy an area in a predefined spatial arrangement and with predetermined connectivity between the logic devices. The method can include determining congestion associated with the structured device group by performing operations including determining a congestion figure. The method can also include providing, based on the congestion figure, an indication of the congestion associated with the structured device group. | 04-23-2015 |
| 20150121326 | Functional Verification of a Circuit Description - A method for functional verification of a circuit description comprises generating a first set of crossover paths based on the circuit description, generating a low power information based on a power design description associated with the circuit description, the low power information determining a set of power state combinations, and generating a second set of crossover paths based on the first set of crossover paths and the low power information, the second set of crossover paths being a subset of the first set of crossover paths. Each of the second set of crossover paths is evaluated to identify circuit description errors, in particular functional circuit description errors. | 04-30-2015 |
| 20150128100 | CYCLE-ACCURATE REPLAY AND DEBUGGING OF RUNNING FPGA SYSTEMS - As described herein, a tool records a log (or trace) of all sources of non-determinism in the system. In most of the cases, it's enough to log all transitions and the exact timestamps at all the entry and exit points of the system. By using this information it is possible to recreate a cycle accurate execution of the hardware system in simulation. Unlike CHIPSCOPE and SIGNALTAP which let you monitor a small number of signals in the design, the tool provides visibility into the whole system. | 05-07-2015 |
| 20150310151 | System and Method for Efficient Statistical Timing Analysis of Cycle Time Independent Tests - A method and a system performing selected timing comparisons in a digital electronic design includes propagating from signal sources to timing comparisons of one or multiple signal labels. The signal label includes signal source identifiers and signal path cycle adjust information. Timing comparisons are determined in which signal label values at each input of the timing comparison are required to compute the selected timing comparisons. The propagation back from the timing comparisons are needed signal labels, followed by the propagation and computing timing data from the signal source applied to the propagated signal labels corresponding to the required signal labels. | 10-29-2015 |
| 20150370940 | CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS - A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of numerous waveforms without simulating the individual waveforms. The design tool can determine an input sequence of signal transition representations associated with an input net of a component in RTL circuit design, where each signal transition representation represents a nondeterministic transition from a previous signal state to possible signal state(s). Determining the input sequence of signal transition representations includes determining that the input sequence of signal transition representations indicates an input gated clock waveform. The design tool also can determine, based on the indicated component and on the input gated clock waveform, an output sequence of signal transition representations derived from the input sequence of signal transition. Determining the output sequence includes determining whether signal transition representation(s) of the output sequence indicate an output gated clock waveform. | 12-24-2015 |
| 20160012166 | INCREMENTAL SLACK MARGIN PROPAGATION | 01-14-2016 |
| 20160048626 | Clock-Tree Transformation in High-Speed ASIC Implementation - A method includes providing a first clock tree including a root clock and a plurality of levels of integrated clock gates (ICGs) under the root clock. The plurality of levels of ICGs in the first clock tree is flattened to generate a second clock tree including a plurality of ICGs in a same level under the root clock. A fake module is formed to reserve a region between the root clock and the plurality of ICGs. The fake module includes the root clock as a first input, and a first plurality of outputs coupled to clock-inputs of the plurality of ICGs. A skew balancing is performed on the second clock tree using a clock tree synthesis (CTS) tool to generate a third clock tree, wherein no buffers are inserted into the fake module, and wherein buffers are inserted by the CTS tool under the plurality of ICGs. | 02-18-2016 |
| 20160070835 | CYCLE-ACCURATE REPLAY AND DEBUGGING OF RUNNING FPGA SYSTEMS - As described herein, a tool records a log (or trace) of all sources of non-determinism in the system. In most of the cases, it's enough to log all transitions and the exact timestamps at all the entry and exit points of the system. By using this information it is possible to recreate a cycle accurate execution of the hardware system in simulation. Unlike CHIPSCOPE and SIGNALTAP which let you monitor a small number of signals in the design, the tool provides visibility into the whole system. | 03-10-2016 |
| 20160098507 | INTEGRATED CIRCUIT DEVICE CONFIGURATION METHODS ADAPTED TO ACCOUNT FOR RETIMING - A method of configuring an integrated circuit device with a user logic design includes analyzing the user logic design to identify timing requirements of paths within the user logic design, determining latency requirements along those paths, routing the user logic design based on availability of storage elements for incorporation into those paths to satisfy the latency requirements, and retiming the user logic design following that routing by incorporating at least some of the storage elements. | 04-07-2016 |
| 20160103943 | UNIFIED TOOL FOR AUTOMATIC DESIGN CONSTRAINTS GENERATION AND VERIFICATION - Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information. | 04-14-2016 |
| 20160110485 | Simplifying Modes of an Electronic Circuit by Reducing Constraints - A mode of a circuit design is simplified by eliminating clocks and corresponding exceptions and timing constraints from the mode. A system receives a description of a mode of a circuit. The system identifies sets of clock pairs and corresponding exceptions associated with timing nodes of the mode, each clock pair comprising a launch clock and a capture clock and corresponding exceptions for a timing path. The system compares time intervals between an edge of the launch clock and a corresponding edge of the capture clock for the clock pairs subject to timing exceptions associated with the timing path. The system identifies certain clock pairs as critical based on the comparison of the time interval associated with each clock pair. The system simplifies the mode by eliminating non-critical clocks and corresponding exceptions and timing constraints. The modified mode is used for performing timing analysis. | 04-21-2016 |
| 20160117429 | SYSTEM FOR REDUCING POWER CONSUMPTION OF INTEGRATED CIRCUIT - A method for reducing dynamic power consumption of an integrated circuit design having flip-flops with an EDA tool that initiates clock gating by gating a clock signal received by the flip-flops. A first set of positive-edge triggered flip-flops and a second set of negative-edge triggered flip-flops, and a first set of OR-type clock gating cells and a second set of AND-type clock gating cells are selected from a technology library. The OR-type clock gating cells are connected to clock input terminals of the first set of positive-edge triggered flip-flops and the AND-type clock gating cells to clock terminals of the second set of negative-edge triggered flip-flops. | 04-28-2016 |
| 20160140272 | METHOD TO MEASURE EDGE-RATE TIMING PENALTY OF DIGITAL INTEGRATED CIRCUITS - Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit. | 05-19-2016 |
| 20160140280 | REDUCING DYNAMIC CLOCK SKEW AND/OR SLEW IN AN ELECTRONIC CIRCUIT - Reducing dynamic clock skew and/or slew in an electronic circuit is provided by: referencing a layout database and/or netlist of a design for the electronic circuit; identifying a set of neighboring buffer pairs with active buffers and adjacent sub-meshes, which are connected by a shorting bar; for each neighboring buffer pair of the set: placing a dummy buffer for each of their active buffers in the adjacent sub-meshes close to the active buffers; routing an input of a first dummy buffer located in a first sub-mesh to an output of an active buffer in a second sub-mesh; routing an input of a second dummy buffer located in the second sub-mesh to an output of an active buffer in the first sub-mesh; and connecting inputs of the first and second dummy buffers to the shorting bar. | 05-19-2016 |
| 20160154915 | STATIC TIMING ANALYSIS IN CIRCUIT DESIGN | 06-02-2016 |
| 20160188758 | STANDARD CELL DESIGN WITH REDUCED CELL DELAY - The disclosure provides a standard cell. The standard cell includes a first PMOS transistor and a second PMOS transistor whose gate terminal respectively receives a first input and a second input. A drain terminal of each of the first PMOS transistor and the second PMOS transistor is coupled to a first node. The standard cell further includes a first NMOS transistor and a third NMOS transistor whose gate terminal respectively receive the first input and the second input. A drain terminal of each of the first NMOS transistor and the third NMOS transistor is coupled to the first node. The first NMOS transistor is coupled to a second NMOS transistor, and the third NMOS transistor is coupled to a fourth NMOS transistor. A gate terminal of the second NMOS transistor and the fourth NMOS transistor respectively receives the second input and the first input. | 06-30-2016 |
| 20160188774 | Circuit Design and Optimization - A method implemented on a data processing system for circuit design is described. The method comprises identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via nets, and determining whether timing of an element of a particular first portion is sensitive to degradation of a signal from a net associated with the particular first portion. In one embodiment, the method further comprises reporting the determination. | 06-30-2016 |
| 20160188782 | COMPUTER PROGRAM PRODUCT FOR TIMING ANALYSIS OF INTEGRATED CIRCUIT - A computer program product stored in a non-transitory storage device of an integrated circuit (IC) timing analysis device includes: a netlist reading module for reading a netlist of an integrated circuit; a signal path analysis module for analyzing signal paths of a clock signal to generate a simplified netlist of the integrated circuit; a clock delay calculating module for calculating clock delays of the clock signal respectively corresponding to the signal paths. | 06-30-2016 |
| 20170235864 | METHODS AND SYSTEMS FOR FUNCTIONAL ANALYSIS OF AN INTEGRATED CIRCUIT | 08-17-2017 |
| 20170235868 | Static Timing Analysis with Improved Accuracy and Efficiency | 08-17-2017 |
