| Entries |
| Document | Title | Date |
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| 20100313173 | Dual Metric OPC - A technique for creating mask layout data to print a desired pattern of features via a photolithographic process includes defining one or more subresolution assist features (SRAFs) and performing OPC on printing features and the added SRAF features. | 12-09-2010 |
| 20100333048 | METHOD AND APPARATUS FOR DESIGNING AN INTEGRATED CIRCUIT - Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design. | 12-30-2010 |
| 20110004855 | METHOD FOR VERIFYING OPTICAL PROXIMITY CORRECTION - A method for verifying an optical proximity correction includes: performing an optical proximity correction on a target pattern layout; performing a primary verification on the target pattern layout which has undergone the optical proximity correction; performing a secondary verification on defect weak points detected in the primary verification; and performing an additional optical proximity correction on hot spot points which are detected in the secondary verification and which may be generated as defects when transferred to a real wafer. | 01-06-2011 |
| 20110029938 | PATTERN CREATING METHOD, COMPUTER PROGRAM PRODUCT, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a pattern creating method includes: calculating, from pattern data on which a circuit pattern formed on a substrate and an auxiliary pattern not formed on the substrate are arranged, a first feature value of a first pattern edge of a circuit pattern affected by the auxiliary pattern and a second feature value of a second pattern edge connected to the first pattern edge; and arranging, when a relation between the feature values does not have a desired relation corresponding to the circuit pattern, the auxiliary pattern such that the relation between the feature values has the relation corresponding to a shape of the circuit pattern. | 02-03-2011 |
| 20110072402 | PHOTOMASK DESIGNING METHOD AND PHOTOMASK DESIGNING PROGRAM - In one embodiment, a photomask designing method for creating a pattern layout having an assist pattern placed around a design pattern is disclosed. The method can place a plurality of evaluation points around the design pattern and set an evaluation index for imaging properties of the design pattern on an imaging surface. The method can combine a light intensity distribution of the design pattern with light intensity distributions of the evaluation points to obtain a light intensity distribution on the imaging surface and evaluate the light intensity distribution on the imaging surface using the evaluation index to determine a region having an effective evaluation point placed. In addition, the method can determine a placement condition for the assist pattern based on the region where the effective evaluation point is placed and place the assist pattern around the design pattern based on the placement condition to create the pattern layout. | 03-24-2011 |
| 20110083113 | System and Method for Lithography Simulation - There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques. In this regard, in one embodiment, the present invention employs a lithography simulation system architecture, including application-specific hardware accelerators, and a processing technique to accelerate and facilitate verification, characterization and/or inspection of a mask design, for example, RET design, including detailed simulation and characterization of the entire lithography process to verify that the design achieves and/or provides the desired results on final wafer pattern. The system includes: (1) general purpose-type computing device(s) to perform the case-based logic having branches and inter-dependency in the data handling and (2) accelerator subsystems to perform a majority of the computation intensive tasks. | 04-07-2011 |
| 20110107280 | Selection of Optimum Patterns in a Design Layout Based on Diffraction Signature Analysis - The present invention relates generally to selecting optimum patterns based on diffraction signature analysis, and more particularly to, using the optimum patterns for mask-optimization for lithographic imaging. A respective diffraction map is generated for each of a plurality of target patterns from an initial larger set of target patterns from the design layout. Diffraction signatures are identified from the various diffraction maps. The plurality of target patterns is grouped into various diffraction-signature groups, the target patterns in a specific diffraction-signature group having similar diffraction signature. A subset of target patterns is selected to cover all possible diffraction-signature groups, such that the subset of target patterns represents at least a part of the design layout for the lithographic process. The grouping of the plurality of target patterns may be governed by predefined rules based on similarity of diffraction signature. The predefined rules comprise coverage relationships existing between the various diffraction-signature groups. | 05-05-2011 |
| 20110113389 | MULTIPLE TECHNOLOGY NODE MASK - A method of fabricating a mask set is provided. The method includes providing mask data associated with a plurality of mask layers. The mask data includes a first pattern associated with a first technology node and a second pattern associated with a second technology node. The method continues with determining to form a multi-technology node mask (MTM) for a first mask layer of the plurality of mask layers. The MTM for the first mask layer is formed, which includes features associated with the first pattern and features associated with the second pattern. | 05-12-2011 |
| 20110161894 | FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES - A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon. | 06-30-2011 |
| 20110161895 | Retargeting Based On Process Window Simulation - Aspects of the invention relate to retargeting based on process window simulation to fix hotspots. The process window simulation is performed to generate process window information. Edge fragments are selected for retargeting. Based on the process window information, the selected edge fragments are retargeted in a balanced way. | 06-30-2011 |
| 20110167394 | OPC CONFLICT IDENTIFICATION AND EDGE PRIORITY SYSTEM - An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edge segments are in conflict so that a user may remove the conflict to achieve a better OPC result. In another embodiment of the invention, edge segments are assigned a priority such that the correction of a lower priority edge does not hinder a desired OPC correction of a higher priority edge. | 07-07-2011 |
| 20110173577 | Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields - Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained. | 07-14-2011 |
| 20110191727 | Method and System for Design of a Reticle to be Manufactured Using Variable Shaped Beam Lithography - A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots. | 08-04-2011 |
| 20110191728 | INTEGRATED CIRCUIT HAVING LINE END CREATED THROUGH USE OF MASK THAT CONTROLS LINE END SHORTENING AND CORNER ROUNDING ARISING FROM PROXIMITY EFFECTS - An integrated circuit that includes a line end created through use of a mask that controls line end shortening and corner rounding arising from proximity effects is provided. The mask includes a main feature having opaque and transmissive areas arranged to reflect a patterned feature of the line end, at least one of an opaque edge or a transmissive edge located at each end of the main feature, wherein the opaque edge has a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge has a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature. | 08-04-2011 |
| 20110197169 | Methods of Optical Proximity Correction - Systems and methods of optical proximity correction are disclosed. A preferred embodiment comprises a method of determining optical proximity correction, which includes providing a design for a lithography mask. The design comprises a layout for a material layer of a semiconductor device. A predicted wafer image producible by the design for the lithography mask is calculated, and an amount of error between a target image and the calculated predicted wafer image is measured over a plurality of pixels of the predicted wafer image. The plurality of pixels comprises a plurality of different sizes. | 08-11-2011 |
| 20110202892 | RETARGET PROCESS MODELING METHOD, METHOD OF FABRICATING MASK USING THE RETARGET PROCESS MODELING METHOD, COMPUTER READABLE STORAGE MEDIUM, AND IMAGING SYSTEM - In a retarget process modeling method, an effect according to density of patterns, and shapes or distances with respect to neighboring patterns may be sufficiently reflected while a relatively small amount of time and few costs are consumed. The retarget process modeling method involves obtaining prediction data, by a modelling calculating unit, on a test layout using a first process model, obtaining bias data based on measurement data of the test layout and the prediction data, using the bias data to check and detect corresponding features of a representative pattern affected by a photoresist (PR) flow rate, generating kernels including a PR flow kernel in consideration of a sub resolution assist feature (SRAF) pattern of the representative pattern to determine an uncalibrated model including the kernels and obtaining a second process model by fitting the uncalibrated model to the measurement data to obtain a second process model. | 08-18-2011 |
| 20110202893 | Contour Self-Alignment For Optical Proximity Correction Model Calibration - Techniques for model calibration and alignment of measurement contours of printed layout features with simulation contours obtained with a model are disclosed. With various implementations of the invention, contour point errors are determined. Based on the contour point errors and a cost function, values of alignment parameters may be determined. The values of alignment parameters may be used to realign the measurement contours for model calibration. The alignment may be conducted concurrently with model calibration. | 08-18-2011 |
| 20110209105 | Photolithographic mask correction - An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with a corresponding modified cell of the modified library to obtain a modified integrated circuit device layout. The modified library includes modified cells corresponding to cells in the library and candidate areas of each modified cell indicating portions of the cell for further processing. At least some of the modified cells have been modified to at least partially compensate for a manufacturing effect. | 08-25-2011 |
| 20110246953 | SELECTIVE SHIELDING FOR MULTIPLE EXPOSURE MASKS - A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system. | 10-06-2011 |
| 20110252385 | SELECTIVE SHIELDING FOR MULTIPLE EXPOSURE MASKS - A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system. | 10-13-2011 |
| 20110252386 | Method for Optical Proximity Correction of a Reticle to be Manufactured Using Variable Shaped Beam Lithography - A method for optical proximity correction (OPC) of a desired pattern for a substrate is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form on a surface an OPC-corrected version of the desired substrate pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the OPC-corrected version of the desired pattern for the substrate. In some embodiments, optimization may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots, that is, glyphs. A method for creating glyphs is also disclosed, in which patterns that would result on a surface from one or a group of VSB shots are pre-calculated. | 10-13-2011 |
| 20110265048 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING UNIFORM OPTICAL PROXIMITY CORRECTION - A method of manufacturing a semiconductor device includes dividing a design pattern layout into a repetitive pattern part and a non-repetitive pattern part, obtaining an optical proximity correction (OPC) bias from an extracted portion, the extracted portion being a partial portion of the repetitive pattern part, applying the OPC bias obtained from the extracted portion equally to the extracted portion and other portions of the repetitive pattern part so as to form a first corrected layout in which corrected layouts of the other portions are the same as that of the extracted portion, and forming a photomask in all portions of the repetitive pattern part according to the first corrected layout. | 10-27-2011 |
| 20110265049 | METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING - Various embodiments of the present invention relate to particle beam writing to fabricate an integrated circuit on a wafer. In various embodiments, cell projection (CP) cell library information is stored in the form of a data structure. Subsequently, the CP cell library information is referenced by a writing system. The patterns are written on the wafer depending on the referenced CP cell library. | 10-27-2011 |
| 20110276928 | METHOD FOR CONTROLLING PATTERN UNIFORMITY OF SEMICONDUCTOR DEVICE - A method for controlling uniformity of patterns formed in a semiconductor device includes obtaining simulation contours with respect to respective cases while controlling a size of an outermost pattern and determining a size of the outermost pattern in which uniform distribution values (3σ) value of patterns included in the simulation contours satisfying specific conditions as a size of target outermost pattern. | 11-10-2011 |
| 20110314431 | METHOD OF ETCH PROXIMITY CORRECTION AND METHOD OF CREATING PHOTOMASK LAYOUT USING THE SAME - Provided is an etch proximity correction method in which an accurate etch bias value is calculated. The etch proximity correction method includes creating an etch bias value from a project area corresponding to an area blocked by a pattern region within a linear distance projected from a target position selected in a target layout to an outermost portion of the proximity region and a non-project area corresponding to an area projected into an edge linear distance from an edge of the pattern region blocked in the linear distance to the outermost portion of the proximity region and correcting the target position in the layout using the etch bias value. Since an etch bias model includes the project area and the non-project area, the accurate etch bias value may be calculated. | 12-22-2011 |
| 20110320987 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, DATA GENERATING APPARATUS, DATA GENERATING METHOD AND RECORDING MEDIUM READABLE BY COMPUTER RECORDED WITH DATA GENERATING PROGRAM - A semiconductor manufacturing method comprising, a data generating process including, acquiring a simulation light pattern that simulates a shape of a light exposure pattern formed on a substrate on the basis of design data of a semiconductor device, acquiring a simulation electron beam exposure pattern that simulates a shape of an electron beam exposure pattern formed by an electron beam exposure on the substrate on the basis of the design data, extracting difference information representing a shape difference portion between the simulation light pattern and the simulation electron beam exposure pattern, acquiring changed design data for modifying shape by changing the design data in accordance with the difference information, conducting the electron beam exposure on the substrate by use of the changed design data for modifying the shape. | 12-29-2011 |
| 20120005634 | Control of Critical Dimensions in Optical Imaging Processes for Semiconductor Production by Extracting Imaging Imperfections on the Basis of Imaging Tool Specific Intensity Measurements and Simulations - Variations in critical dimensions of circuit features of sophisticated semiconductor devices may be reduced by efficiently extracting mask and/or imaging tool specific non-uniformities with high spatial resolution by using measured intensity values and simulated intensity values. For example, a tool internal radiation sensor may be used for measuring the intensity of an image of a lithography mask, while a simulated intensity enables eliminating the mask pattern specific intensity contributions. In this manner, high spatial resolution of the corresponding correction map may be obtained without undue effort in terms of man power and measurement tool resources. | 01-05-2012 |
| 20120005635 | METHOD OF FORMING PHOTOMASK, COMPUTER-READABLE RECORDING MEDIUM STORING PROGRAMMED INSTRUCTIONS FOR EXECUTING THE METHOD, AND MASK IMAGING SYSTEM - A method of forming a photomask includes providing a layout of design patterns, setting an optical proximity correction (OPC) with respect to the layout of design patterns, and forming a layout of correction patterns with respect to the layout of design patterns by using the set OPC. The method also includes collecting verification data about the layout of correction patterns by using a layout of contour patterns based on the layout of correction patterns, and verifying whether the layout of design patterns and the layout of correction patterns are substantially identical to each other by using the verification data. | 01-05-2012 |
| 20120005636 | METHOD FOR MANUFACTURING A PHOTOMASK - A method for manufacturing a photomask based on design data includes the steps of forming a figure element group including a figure element in a layout pattern on the photomask and a figure element affecting the figure element due to the optical proximity effect, adding identical identification data to a data group indicating an identical figure element group, estimating an influence of the optical proximity effect on the figure element group, generating correction data indicating a corrected figure element in which the influence of the optical proximity effect is compensated for at the time of exposure, creating figure data by associating data having the identical identification data with correction data having the identical identification data, and forming a mask pattern on the photomask using figure data. Thus, the computation time for correction of the layout can be reduced, thereby reducing the production time of the photomask. | 01-05-2012 |
| 20120011478 | MERGING SUB-RESOLUTION ASSIST FEATURES OF A PHOTOLITHOGRAPHIC MASK - Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is established. A distance between the first sub-resolution assist feature and the second sub-resolution assist feature is determined. A merging technique is determined in accordance with the distance and the merge bar width. The first sub-resolution assist feature and the second sub-resolution assist feature are merged according to the identified merging technique. | 01-12-2012 |
| 20120030638 | METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME - Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of a rectangular target geometry may comprise predicting a contour of an image to be produced in an optical proximity correction simulation of a target geometry. The target geometry may comprise a plurality of line segments, each line segment of the plurality having one evaluation point defined thereon. The method may further comprise shifting at least one evaluation point to an associated point on the predicted contour of the image. | 02-02-2012 |
| 20120047473 | Layout Decomposition Based on Partial Intensity Distribution - Layout design data are decomposed for double dipole lithography based on partial intensity distribution information. The partial intensity distribution information is generated by performing optical simulations on the layout design data. The layout decomposition may further be adjusted during an optical proximity correction process. The adjustment may utilize the partial intensity distribution information. | 02-23-2012 |
| 20120047474 | Method for Manufacturing Semiconductor Devices - A method of manufacturing semiconductor devices is disclosed. The method includes determining fractured shots that do not overlap each other based on a final pattern; determining overlapping shots that are shots that overlap each other based on the final pattern; generating area difference data by comparing the areas of the overlapping shots and the fractured shots with each other; calculating a radiation influenced pattern based on the area difference data; and correcting the overlapping shots based on the radiation influenced pattern. | 02-23-2012 |
| 20120084740 | METHOD AND SYSTEM FOR DESIGN OF A RETICLE TO BE MANUFACTURED USING VARIABLE SHAPED BEAM LITHOGRAPHY - A method for fracturing or mask data preparation or proximity effect correction of a desired pattern to be formed on a reticle is disclosed in which a plurality of variable shaped beam (VSB) shots are determined which can form the desired pattern. Shots within the plurality of VSB shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary with respect to each other. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots. | 04-05-2012 |
| 20120096412 | Method and System for Forming High Accuracy Patterns Using Charged Particle Beam Lithography - A method and system for fracturing or mask data preparation for charged particle beam lithography are disclosed in which accuracy and/or edge slope of a pattern formed on a surface by a set of charged particle beam shots is enhanced by use of partially-overlapping shots. In some embodiments, dosages of the shots may vary with respect to each other before proximity effect correction. Particle beam simulation may be used to calculate the pattern and the edge slope. Enhanced edge slope can improve critical dimension (CD) variation and line-edge roughness (LER) of the pattern produced on the surface. | 04-19-2012 |
| 20120096413 | PROGRAM STORAGE MEDIUM AND METHOD FOR DETERMINING EXPOSURE CONDITION AND MASK PATTERN - A method of determining an exposure condition and a mask pattern includes: setting the exposure condition and the mask pattern; temporarily determining the mask pattern using a first evaluation function describing indices of quality of an image of the mask pattern, using the set exposure condition; calculating a value of a second evaluation function describing indices of quality of the image of the mask pattern, using the temporarily determined mask pattern and the set exposure condition; changing the exposure condition and the mask pattern based on the value of the calculated second evaluation function; and judging whether to execute a process of repeating the temporarily determining step and the calculating step. In the judging step, the mask pattern temporarily determined in the latest second step, and the exposure condition changed in the latest fourth step are determined as the mask pattern and the exposure condition, respectively. | 04-19-2012 |
| 20120096414 | METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES - Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems. | 04-19-2012 |
| 20120102440 | METHOD AND SYSTEM FOR IMPLEMENTING CONTROLLED BREAKS BETWEEN FEATURES USING SUB-RESOLUTION ASSIST FEATURES - Disclosed is a method, system, and computer program product for implementing controlled breaks using sub-resolution assist features. Sub-resolution bridging features are added to implement controlled breaks between features on the layout. The bridging features may also be used to facilitate or optimize multiple mask/exposure techniques that split a layout or features on a layout to address pitch problems. | 04-26-2012 |
| 20120110522 | Pattern Recognition with Edge Correction for Design Based Metrology - Exemplary embodiments include a method for edge correction in pattern recognition, the method including receiving a design layout, receiving a sample plan based on the design layout, receiving user-generated edge input and generating a recipe output from the design layout, the sample plan and the user-generated edge input. The incorporation of the edge input results in SEM recipes that are much more successful in recognizing patterns that have tendency to deviate in appearance from design by, for example, moderate to severe sidewall angle. | 05-03-2012 |
| 20120110523 | PATTERN RECOGNITION WITH EDGE CORRECTION FOR DESIGN BASED METROLOGY - A method for edge correction in pattern recognition includes generating a pattern recognition output for a pattern recognition process, including receiving, in the processor, a design layout, receiving a sample plan based on the design layout, receiving a first user-generated edge input, generating a pattern recognition recipe output from the design layout, the sample plan and the user-generated edge input, wherein the pattern recognition recipe output is configured to drive the pattern recognition process, generating a measurement model from the pattern recognition process, generating a measurement model pattern recognition output for an measurement model pattern recognition process, including receiving a second user-generated input and generating a measurement model pattern recognition recipe output from the measurement model and the second user-generated edge input, wherein the measurement model pattern recognition recipe output configured to drive the measurement model pattern recognition process. | 05-03-2012 |
| 20120117519 | METHOD OF TRANSISTOR MATCHING - A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to forming a photomask. A method to reduce transistor-to-transistor Ids variation in an integrated circuit by adjusting transistor gate lengths and optionally transistor widths in the design data base prior to the application of OPC and prior to printing a gate pattern and optionally printing an active pattern on a wafer. | 05-10-2012 |
| 20120117520 | Systems And Methods For Inspecting And Controlling Integrated Circuit Fabrication Using A Calibrated Lithography Simulator - A system and method for precise control of fine-line photolithography is disclosed. The system includes a wafer inspector that detects and measures edges and contours of patterns as produced on a wafer and a lithography simulator. The method calibrates the lithography simulator using multiple measurements and/or edges of patterns on the wafer. The calibrated lithography simulator is used to simulate processing to permit optimization of processing conditions by iterative adjustment and re-simulation. In embodiments, the process conditions optimized include one or more of dose, placement of edges on masks, and placement, shape, and locations of SRAF/OPC structures on the masks. In embodiments, the method includes using the calibrated lithography simulator to match results of production process equipment to those achieved with standard equipment. In embodiments, process data from multiple process simulations is stored in a single image file. The method concludes with fabrication of wafers using the optimized conditions and masks. | 05-10-2012 |
| 20120131521 | LAYOUT PATTERN - A layout pattern is disclosed. The layout pattern includes: a polygon pattern having at least one segment; and at least one notch formed in the polygon pattern, wherein at least one side of the notch is less than the length of the segment. | 05-24-2012 |
| 20120167020 | Pre-OPC Layout Editing For Improved Image Fidelity - An optical proximity correction operation is performed on a layout design, and faults created by the design are identified. If the faults occur where the optical proximity correction was constrained by a mask rule, then the layout design data is edited so that violation of the mask rule is avoided. Once the original layout design has been edited, another optical proximity correction operation is then performed on the edited layout design data. In this subsequent optical proximity correction operation, a simulated image is generated using the edited layout design data, but this simulated image is compared with the target image of the original layout design data rather than the edited layout design data. | 06-28-2012 |
| 20120174046 | METHOD FOR COMPENSATING FOR VARIATIONS IN STRUCTURES OF AN INTEGRATED CIRCUIT - A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying a rules-based optical proximity correction to the selected region of the mask design shape. | 07-05-2012 |
| 20120192123 | METHOD TO COMPENSATE OPTICAL PROXIMITY CORRECTION - A method to compensate optical proximity correction adapted for a photolithography process includes providing an integrated circuit (IC) layout. The IC layout includes active regions, a shallow trench isolation (STI) region and ion implant regions overlapped with a part of the STI region and at least a part of the active regions. Subsequently, at least a photoresist line width compensation region disposed in the STI region is acquired in a photoresist covering region outside the ion implant regions according to the IC layout. Afterwards, the IC layout is corrected according to a width of the photoresist line width compensation region, a length of a side of the active region facing a side of the photoresist line width compensation region and a distance from the side of the photoresist line width compensation region to the active region facing the side. Then, the corrected IC layout is transferred to a photomask. | 07-26-2012 |
| 20120198394 | Method For Improving Circuit Design Robustness - Improving circuit design robustness is based on identifying process sensitive and design critical devices. Design critical devices are identified using circuit design information. Various model-based simulations may be performed on the layout areas associated with the identified design critical devices to extract process sensitive and design critical devices. To make the circuit design more robust, various techniques may be employed to treat the extracted process sensitive and design critical devices. | 08-02-2012 |
| 20120198395 | FLARE VALUE CALCULATION METHOD, FLARE CORRECTION METHOD, AND COMPUTER PROGRAM PRODUCT - In a flare value calculation method according to an embodiment, an average optical intensity is calculated for each of mask patterns in a case where an exposure process is performed on a substrate using the mask patterns. Then, pattern correction amounts for the mask patterns corresponding to the average optical intensity and information about the dimensions of the mask patterns are calculated for each mask pattern. Then, post-correction mask patterns are prepared by performing pattern correction on each of the mask patterns using the pattern correction amount. Then, a flare value of an optical system of an exposure apparatus is calculated using a pattern average density of the post-correction mask patterns. | 08-02-2012 |
| 20120204135 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE USING A MODELING ALGORITHM TO MODEL THE PROXIMITY EFFECT FROM THE SUB-LAYER - A method for forming a circuit layout comprises performing process proximity effect modeling based on process proximity effects caused by a sub-layer, wherein the sub-layer comprises an active layer positioned under a gate poly, and wherein performing the process proximity effect modeling includes calculating a pattern density of the sub-layer, incorporating results of the process proximity effect modeling into a modeling algorithm, and performing proximity correction using the results to manipulate a layout of a mask to be used when forming the circuit layout by photolithography. | 08-09-2012 |
| 20120210279 | DECOMPOSITION AND MARKING OF SEMICONDUCTOR DEVICE DESIGN LAYOUT IN DOUBLE PATTERNING LITHOGRAPHY - Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features. | 08-16-2012 |
| 20120210280 | Method and System for Lithography Hotspot Correction of a Post-Route Layout - Disclosed herein are correcting methods and devices for lithography hotspots of the post-routing layout, used for correcting lithography hotspots detected in the post-routing layout. At least one two-dimensional pattern of changeable size or position of the number of hotspots in the local area is selected and adjusted, so that the simulation value of the aerial image intensity of various local areas is optimized. The simulation value of the aerial image intensity is derived through calculation with respect to a set of optical simulation model cells that can be determined by the numerical value of distribution of the aerial image intensity of a number of basic two-dimensional patterns. After adjustment, the aerial image intensity of the local area can be calculated with respect to a set of optical simulation model cells, and a number of cells in the simulation model cells are selected to synthesize the two-dimensional pattern after the change. | 08-16-2012 |
| 20120221980 | METHOD AND SYSTEM FOR DESIGN OF ENHANCED ACCURACY PATTERNS FOR CHARGED PARTICLE BEAM LITHOGRAPHY - A method and system for fracturing or mask data preparation are presented in which overlapping shots are generated to increase dosage in selected portions of a pattern, thus improving the fidelity and/or the critical dimension variation of the transferred pattern. In various embodiments, the improvements may affect the ends of paths or lines, or square or nearly-square patterns. Simulation is used to determine the pattern that will be produced on the surface. | 08-30-2012 |
| 20120221981 | METHOD AND SYSTEM FOR DESIGN OF ENHANCED EDGE SLOPE PATTERNS FOR CHARGED PARTICLE BEAM LITHOGRAPHY - A method and system for fracturing or mask data preparation are presented in which overlapping shots are generated to increase dosage in selected portions of a pattern, thus improving the fidelity and/or the critical dimension variation of the transferred pattern. In various embodiments, the improvements may affect the ends of paths or lines, or square or nearly-square patterns. Simulation is used to determine the pattern that will be produced on the surface. | 08-30-2012 |
| 20120221982 | METHOD OF FORMING LAYOUT OF PHOTOMASK - A method of forming a layout of a photomask using optical proximity correction (OPC) includes: receiving a layout of a mask pattern; obtaining image parameters of a two-dimensional (2D) layout mask from a simulation; obtaining image parameters of a three-dimensional (3D) layout mask from a simulation; obtaining differences between the image parameters of the 2D and 3D masks; and performing optical proximity correction (OPC) on the 2D mask to compensate for the differences between the image parameters of the 2D and 3D masks by using a visible kernel with respect to the 2D mask. | 08-30-2012 |
| 20120221983 | METHOD FOR COMPENSATING PROXIMITY EFFECTS OF PARTICLE BEAM LITHOGRAPHY PROCESSES - A method for compensating proximity effects of particle beam lithography processes is provided. The method includes the following steps. A control pattern is provided. A dissection process is provided. A set of control points are provided. The control pattern is defined as an input pattern of a lithography process. A target pattern is provided. A set of target points are produced. A set of target measurement values are provided. An actual pattern is defined. A set of actual measurement values are provided. A set of comparison values are calculated. An adjusting strategy is provided. A corrected pattern is produced. The corrected pattern is defined as an updated input of the lithography process. | 08-30-2012 |
| 20120227017 | MULTIFEATURE TEST PATTERN FOR OPTICAL PROXIMITY CORRECTION MODEL VERIFICATION - A method for optical proximity correction (OPC) model accuracy verification for a semiconductor product includes generating a multifeature test pattern, the multifeature test pattern comprising a plurality of features selected from the semiconductor product; exposing and printing the multifeature test pattern on a test wafer under a process condition; generating an OPC model of the semiconductor product for the process condition; and comparing the test wafer to the OPC model to verify the accuracy of the OPC model. | 09-06-2012 |
| 20120240086 | MODELING EUV LITHOGRAPHY SHADOWING EFFECT - Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model. | 09-20-2012 |
| 20120246602 | METHOD OF PREPARING PATTERN, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT - An embodiment provides a method of preparing a pattern. In the pattern preparing method, when mask patterns corresponding to on-substrate patterns are prepared to form the on-substrate patterns corresponding to design patterns, the mask patterns are prepared based on a correlation which needs to be satisfied between the design patterns so that a relation which same the correlation can be satisfied between the mask patterns corresponding to the design patterns. | 09-27-2012 |
| 20120272195 | SYSTEM AND METHOD FOR OPTICAL PROXIMITY CORRECTION OF A MODIFIED INTEGRATED CIRCUIT LAYOUT - A system and method for modifying an integrated circuit (IC) layout includes performing a correction process, such as an optical proximity correction (OPC) process, only on regions within designated blocks that are defined around respective modified structures. An IC layout can be compared to a modified version of the IC layout to detect modified structures. One or more large blocks can then be defined around respective modified structures. A correction process can then be performed on only the one or more large blocks. Small blocks within respective large blocks can then be extracted from the modified IC layout and merged with the original IC layout to generate a final modified and corrected IC layout. | 10-25-2012 |
| 20120272196 | Local Multivariable Solver for Optical Proximity Correction in Lithographic Processing Method, and Device Manufactured Thereby - A multivariable solver for proximity correction uses a Jacobian matrix to approximate effects of perturbations of segment locations in successive iterations of a design loop. The problem is formulated as a constrained minimization problem with box, linear equality, and linear inequality constraints. To improve computational efficiency, non-local interactions are ignored, which results in a sparse Jacobian matrix. | 10-25-2012 |
| 20120278770 | METHOD AND SYSTEM FOR FORMING NON-MANHATTAN PATTERNS USING VARIABLE SHAPED BEAM LITHOGRAPHY - A method and system for fracturing or mask data preparation or proximity effect correction is disclosed in which a series of charged particle beam shots is determined, where the series of shots is capable of forming a continuous non-manhattan track on a surface, such that the non-manhattan track has a line width roughness (LWR) which nearly equals a target LWR. A method and system for fracturing or mask data preparation or proximity effect correction is also disclosed in which at least two series of shots are determined, where each series of shots is capable of forming a continuous non-manhattan track on a surface, and where the space between tracks has space width roughness (SWR) which nearly equals a target SWR. | 11-01-2012 |
| 20120284675 | EUV LITHOGRAPHY FLARE CALCULATION AND COMPENSATION - Extreme ultraviolet (EUV) lithography flare calculation and compensation is disclosed herein. A method of calculating flare for a mask for use in EUV lithography includes decomposing the flare power spectrum density (PSD) into a low frequency component and a high frequency component. Further, the method includes receiving a plurality of layouts in a flare map generator. Each of the plurality of layouts corresponds to a chip pattern location on the mask. Moreover, the method includes generating, using the flare map generator, a low frequency flare map for the mask from the low frequency component by using fast Fourier transform (FFT). | 11-08-2012 |
| 20120317524 | MASK DATA VERIFICATION APPARATUS, DESIGN LAYOUT VERIFICATION APPARATUS, METHOD THEREOF, AND COMPUTER PROGRAM THEREOF - A mask data verification apparatus compares a design layout with design layout patterns stored in an existing-type library and extracts a design layout pattern found to be neither equal nor similar as a new-type design layout pattern. The mask data verification apparatus generates mask data using OPC/RET with reference to a new design layout pattern stored in a new-type library and performs post-verification. The mask data verification apparatus can previously verify a new design layout pattern, shorten a semiconductor device manufacturing period, ensure efficient development, and improve a manufacturing yield. | 12-13-2012 |
| 20120324405 | Performing OPC on Hardware or Software Platforms with GPU - Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps. | 12-20-2012 |
| 20130007675 | METHOD AND SYSTEM FOR STENCIL DESIGN FOR PARTICLE BEAM WRITING - Various embodiments of the present invention relate to particle beam writing to fabricate an integrated circuit on a wafer. In various embodiments, cell projection (CP) cell library information is stored in the form of a data structure. Subsequently, the CP cell library information is referenced by a writing system. The patterns are written on the wafer depending on the referenced CP cell library. | 01-03-2013 |
| 20130024824 | Optical Proximity Correction Method - An optical proximity correction method is provided. A target pattern is provided, and then the target pattern is decomposed to a first pattern and a second pattern. The first pattern and the second pattern are alternately arranged in a dense region. Then, a compensation pattern is provided and it is determined whether the compensation pattern is added into the first pattern to become a first revised pattern, or into the second pattern to become a second revised pattern. Finally, the first revised pattern is output onto a first mask and the second revised pattern is output onto a second mask. | 01-24-2013 |
| 20130042210 | CYCLE TIME REDUCTION IN DATA PREPARATION - The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout. | 02-14-2013 |
| 20130042211 | Lithography Model for 3D Topographic Wafers - Described herein is a method for simulating an image formed within a resist layer on a substrate resulting from an incident radiation, the method comprising: calculating a forward propagating electric field or forward propagating magnetic field resultant from the incident radiation at a depth in the resist layer; calculating a backward propagating electric field or backward propagating magnetic field resultant from the incident radiation at the depth in the resist layer; calculating a radiation field at the depth in the resist layer from the forward propagating electric field or forward propagating magnetic field and from the backward propagating electric field or backward propagating magnetic field while ignoring an interference between the forward propagating electric field or forward propagating magnetic field and the backward propagating electric field or backward propagating magnetic field. | 02-14-2013 |
| 20130055173 | GEOMETRIC PATTERN DATA QUALITY VERIFICATION FOR MASKLESS LITHOGRAPHY - The present disclosure involves a method of performing a maskless lithography process. The method includes providing a proximity correction pattern. The method includes generating a deformed pattern based on the proximity correction pattern. The method includes performing a first convolution process to the proximity correction pattern to generate a first proximity correction pattern contour. The method includes processing the first proximity correction pattern contour to generate a second proximity correction pattern contour. The method includes performing a second convolution process to the deformed pattern to generate a first deformed pattern contour. The method includes processing the first deformed pattern contour to generate a second deformed pattern contour. The method includes identifying mismatches between the second proximity correction pattern contour and the second deformed pattern contour. The method includes determining whether the deformed pattern is lithography-ready in response to the identifying. | 02-28-2013 |
| 20130067423 | METHOD OF MAKING OPTICAL PROXIMITY CORRECTION TO ORIGINAL GATE PHOTOMASK PATTERN BASED ON DIFFERENT SUBSTRATE AREAS - The present invention relates to the field of semiconductor manufacturing, and particularly to a method of making Optical Proximity Correction to an original gate photomask pattern based on different substrate areas. The present invention discloses a method of making OPC to an original gate photomask pattern based on different substrate areas, which makes correction to gate photomask pattern dimension on the AA and to gate photomask pattern dimension on the STI respectively by creating two different optical proximity effect models of the gate, so as to control the finally imaged gate photomask pattern dimensions more accurately; moreover, the error of the correction result of the gate spacing dimension on the STI can be reduced by 4% by separating the patterns and using the gate model based on the STI, so as to avoid the spacing dimension error when the photolithography exposure conditions vary. | 03-14-2013 |
| 20130080981 | METHOD FOR IMPROVING OPTICAL PROXIMITY SIMULATION FROM EXPOSURE RESULT - A method for improving an optical proximity simulation is disclosed. First, multiple exposure data are determined. An original simulation result corresponding to the exposure result and generated from multiple original simulation parameters is provided. Then, an original deviation value from the original simulation result and the exposure result is verified to determine whether it is within a predetermined range. Next, the original simulation parameters are adjusted to obtain adjusted simulation parameters. The adjusted simulation parameters whose adjusted deviation value is within the predetermined range are collected to obtain an optical proximity correction model for outputting a pattern on a reticle. | 03-28-2013 |
| 20130080982 | Simulation And Correction Of Mask Shadowing Effect - Disclosed are techniques for simulating and correcting the mask shadowing effect using the domain decomposition method (DDM). According to various implementations of the invention, DDM signals for an extreme ultraviolet (EUV) lithography mask are determined for a plurality of azimuthal angles of illumination. Base on the DDM signals, one or more layout designs for making the mask may be analyzed and/or modified. | 03-28-2013 |
| 20130104091 | Tolerable Flare Difference Determination - Aspects of the invention relate to techniques for compensating flare effects in a lithographic process for an array of identical circuits to be fabricated on a wafer. According to various implementations of the invention, a reference circuit is selected from the array of identical circuits and intolerable flare difference regions are determined based on flare difference layers and tolerable flare difference layers. The lithographic process result for the array of identical circuit may be derived from that for the reference circuit and the intolerable flare difference regions. | 04-25-2013 |
| 20130111419 | METHOD AND SYSTEM FOR MODIFYING DOPED REGION DESIGN LAYOUT DURING MASK PREPARATION TO TUNE DEVICE PERFORMANCE | 05-02-2013 |
| 20130111420 | MASK DATA PRODUCING METHOD AND MASK DATA PRODUCING PROGRAM | 05-02-2013 |
| 20130139118 | THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHYSIMULATION - A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image. | 05-30-2013 |
| 20130191794 | SCANNER BASED OPTICAL PROXIMITY CORRECTION SYSTEM AND METHOD OF USE - A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether δ | 07-25-2013 |
| 20130191795 | Layout Design Defect Repair Using Inverse Lithography - Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, transition and visible portions. An inverse lithography process is then performed on the core and transition portions of the re-correction region while taking into account effects from the visible portion to generate a modified re-correction region. The transition portion is processed based on distance from boundary between the transition portion and the core portion such that layout features near the boundary between the transition portion and the core portion are adjusted more than layout features farther away from the boundary. | 07-25-2013 |
| 20130198698 | EDGE FRAGMENT CORRELATION DETERMINATION FOR OPTICAL PROXIMITY CORRECTION - Aspects of the invention relate to techniques for determining edge fragment correlation information. With various implementations of the invention, image intensity slope information for edge fragments in a layout design is determined. The image intensity slope information comprises information describing how image intensity for each of the edge fragments changes with its position. Image amplitude sensitivity information for the edge fragments is also determined. The image amplitude sensitivity information comprises information describing how image amplitude for each of the edge fragments changes with positions of neighboring edge fragments. Based on the image intensity slope information and the image amplitude sensitivity information, edge fragment correlation information for the edge fragments is determined. Using the edge fragment correlation information, the layout design may be processed by using, for example, OPC techniques. This OPC process may be performed on the whole layout design or problematic layout regions identified by a conventional OPC process. | 08-01-2013 |
| 20130198699 | Pattern Matching Optical Proximity Correction - Aspects of the invention relate to techniques for improving speed and consistency of OPC processes based on pattern matching. Pattern matching may be performed on a layout design to determine one or more arrays in the layout design that comprise arrays of identical layout patterns of which each matches a reference pattern. The one or more arrays may then be partitioned into core portions and boundary portions. The OPC process information for the reference pattern may be applied to the core portions, while a conventional OPC process may be performed on the boundary portions and layout regions outside of the one or more arrays. | 08-01-2013 |
| 20130198700 | Layout Design Defect Repair Based On Inverse Lithography And Traditional Optical Proximity Correction - Aspects of the invention relate to techniques for repairing layout design defects after layout data have been processed by resolution enhancement techniques. The repair process first determines a re-correction region that includes three portions: core, context and visible portions. An inverse lithography process is then performed on the core portion of the re-correction region while taking into account effects from the context portion of the re-correction region to generate a first modified re-correction region. A traditional OPC process is then performed on the core and context portions of the first modified re-correction region while taking into account effects from the visible portion of the first modified re-correction region to generate a second modified re-correction region. | 08-01-2013 |
| 20130205264 | METHOD AND SYSTEM FOR FORMING HIGH PRECISION PATTERNS USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for fracturing or mask data preparation or proximity effect correction or optical proximity correction or mask process correction is disclosed in which a set of charged particle beam shots is determined that is capable of forming a pattern on a surface, wherein critical dimension (CD) split is reduced through the use of overlapping shots. | 08-08-2013 |
| 20130205265 | OPTICAL PROXIMITY CORRECTION CONVERGENCE CONTROL - A method of optical proximity correction (OPC) convergence control that includes providing a lithography system having a photomask and an illuminator. The method further includes performing an exposure by the illuminator on the photomask. Also, the method includes optimizing an optical illuminator setting for the lithography system with a defined gate pitch in a first direction in a first template. Additionally, the method includes determining OPC correctors to converge the OPC results with a target edge placement error (EPE) to produce a first OPC setting for the first template. The first OPC setting targets a relatively small EPE and mask error enhancement factor (MEEF)of the defined gate pitch in the first template. In addition, the method includes checking the first OPC setting for a relatively small EPE, MEEF and DOM consistency with the first template of the defined gate pitch in a second, adjacent template. | 08-08-2013 |
| 20130219349 | METHOD FOR PROCESS PROXIMITY CORRECTION - A method for process proximity correction may include obtaining a point spread function (PSF) from test patterns, the test patterns including an etching process performed thereon, generating a target layout with polygonal patterns, dividing the target layout into grid cells, generating a density map including long-range layout densities, each of the long-range layout densities being obtained from the polygonal patterns located within a corresponding one of the grid cells, performing a convolution of the long-range layout densities with the PSF to obtain long-range etch skews for the grid cells, and generating an etch bias model including short-range etch skews and the long-range etch skews, each of the short-range etch skews being obtained from a neighboring region of a target pattern selected from the polygonal patterns in each of the grid cells. | 08-22-2013 |
| 20130232454 | OPTICAL PROXIMITY CORRECTION FOR MASK REPAIR - Integrated circuit (IC) methods for optical proximity correction (OPC) modeling and mask repair are described. The methods include use of an optical model that generates a simulated aerial image from an actual aerial image obtained in an optical microscope system. In the OPC modeling methods, OPC according to stage modeling is simulated, and OPC features may be added to a design layout according to the simulating OPC. In the mask repair methods, inverse image rendering is performed on the actual aerial image and diffraction image by applying an optical model that divides an incoherent exposure source into a plurality of coherent sources. | 09-05-2013 |
| 20130232455 | ERROR DIFFUSION AND GRID SHIFT IN LITHOGRAPHY - The present disclosure involves a method of data preparation in lithography processes. The method of data preparation includes providing an integrated circuit (IC) layout design in a graphic database system (GDS) grid, and converting the IC layout design GDS grid to a second exposure grid by applying an error diffusion and a grid shift technique to a sub-pixel exposure grid. | 09-05-2013 |
| 20130232456 | OPTICAL PROXIMITY CORRECTION METHODS FOR MASKS TO BE USED IN MULTIPLE PATTERNING PROCESSES - Disclosed herein are various OPC methods as it relates to the formation of masks to be used in multiple patterning processes, such as double patterning processes, and to the use of such masks during the manufacture of semiconductor devices. One illustrative method disclosed herein includes the steps of decomposing an initial overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein each of the first and second sub-target patterns comprise at least one feature, and performing a first optical proximity correction process on the first sub-target pattern, wherein a position of at least one feature of the second sub-target pattern in the initial overall target pattern is considered when performing the first optical proximity correction process. | 09-05-2013 |
| 20130232457 | METHODS AND SYSTEMS FOR LITHOGRAPHY CALIBRATION - A method of efficient optical and resist parameters calibration based on simulating imaging performance of a lithographic process utilized to image a target design having a plurality of features. The method includes the steps of determining a function for generating a simulated image, where the function accounts for process variations associated with the lithographic process; and generating the simulated image utilizing the function, where the simulated image represents the imaging result of the target design for the lithographic process. Systems and methods for calibration of lithographic processes whereby a polynomial fit is calculated for a nominal configuration of the optical system and which can be used to estimate critical dimensions for other configurations. | 09-05-2013 |
| 20130239071 | METHOD AND APPARATUS FOR ENHANCED OPTICAL PROXIMITY CORRECTION - Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction. | 09-12-2013 |
| 20130239072 | MASK MAKING WITH ERROR RECOGNITION - A method of making a mask includes receiving an IC design layout from a designer, applying an logic operation (LOP) correction, performing an OPC correction, fracturing the modified data into a plurality of main features in an electron beam format, and sending the electron beam format data to a mask writer for a mask fabrication. An XOR operation is implemented into the method to check and verify if a pattern is lost during OPC modification and/or data fracture. A BACKBONE XOR operation is also implemented into the method for a plurality of main features with a critical dimension (CD) size smaller than the max OPC correction to check and verify if a small pattern feature is lost during OPC modification and/or data fracture for 45 nm and beyond semiconductor technologies. | 09-12-2013 |
| 20130246981 | DISSECTION SPLITTING WITH OPTICAL PROXIMITY CORRECTION TO REDUCE CORNER ROUNDING - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having an main feature, the main feature including two corners and an edge spanning between the two corners; performing a feature adjustment to the edge; performing a dissection to the edge such that the edge is divided to include two corner segments and one center segment between the two corner segments; performing a first optical proximity correction (OPC) to the main feature for a center target associated with the center segment; thereafter, performing a second OPC to the main feature for two corner targets associated with the corner segments; and thereafter, performing a third OPC to main feature for the center target, resulting in a modified design layout. | 09-19-2013 |
| 20130246982 | GENERATION METHOD, STORAGE MEDIUM, AND INFORMATION PROCESSING APPARATUS - The present invention provides a generation method of generating data for a mask pattern to be used for an exposure apparatus including a projection optical system for projecting a mask pattern including a main pattern and auxiliary pattern onto a substrate, including a step of setting a generation condition under which the auxiliary pattern is generated, and a step of determining whether a value of an evaluation function describing an index which indicates a quality of an image of the mask pattern calculated, wherein if it is determined that the value of the evaluation function falls outside a tolerance range, the generation condition is changed to set a new generation condition. | 09-19-2013 |
| 20130254723 | COMPUTATIONAL LITHOGRAPHY WITH FEATURE UPSIZING - A method of computational lithography includes providing through-focus critical dimension (CD) curves at a range of different focus values (Bossung curves) for a plurality of feature types that include different ratios of line width to space width. Using software run on a computing device, it is determined if there is at least one marginal feature type from the plurality of feature types based an image tool capability and a predetermined process specification affected by at least one of the plurality of feature types. Provided a marginal feature type is determined to be present, at least the marginal feature type(s) is upsized. A degree of upsizing increases as a curvature of the Bossung curves increases. A computational lithography model is compiled including the upsizing. | 09-26-2013 |
| 20130254724 | EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USING A DATA WEIGHTING ALGORITHM - A method of computational lithography includes collecting a critical dimension (CD) data set including CD data from printing a test structure including a set of gratings which provide a plurality of feature types including different ratios of line width to space width, where the printing includes a range of different focus values. The CD data is weighted to form a weighted CD data set using a weighting algorithm (WA) that assigns cost weights to the CD data based its feature type and its magnitude of CD variation with respect to a CD value for its feature type at a nominal focus (nominal CD). The WA algorithm reduces a value of the cost weight as the magnitude of variation increases. At least one imaging parameter is extracted from the weighted CD data set. A computational lithography model is automatically calibrated using the imaging parameter(s). | 09-26-2013 |
| 20130254725 | EXTRACTION OF IMAGING PARAMETERS FOR COMPUTATIONAL LITHOGRAPHY USING A DATA WEIGHTING ALGORITHM - A method of computational lithography includes collecting inline post-develop resist critical dimension (CD) data obtained from printing a test structure having resist on a substrate having a layer thereon using a mask including a set of gratings having main features and resolution assist features (RAFs) in proximity to the main features. The RAFs include a size range so that a lithography system used for the printing prints some of the RAFs, while some of the RAFs do not print. A plurality of resist kernels are determined from the post-develop resist CD data including a non-Gaussian developer etching kernel which represents a developer used for the printing and a Gaussian kernel. A resist model is generated which provides a resist image contour from an aerial image contour and the plurality of resist kernels. | 09-26-2013 |
| 20130254726 | MULTI-PATTERNING METHOD - A method includes receiving data representing a layout of a DPT-layer of an integrated circuit generated by a place and route tool. The layout includes a plurality of polygons to be formed in the DPT-layer by a multi-patterning process. First and second ones of the plurality of polygons to be formed using first and second photomasks, respectively are identified. Any intervening polygons along a first path connecting the first polygon to the second polygon, and separator regions between adjacent polygons along the first path are identified. The separator regions have sizes less than a minimum threshold distance between polygons formed on the first photomask. The separator regions are counted. A multi-patterning conflict is identified, if the count of separator regions is even, prior to assigning all remaining ones of the plurality of polygons to the first or second masks. | 09-26-2013 |
| 20130263062 | METHOD OF DESIGNING PATTERN LAYOUTS - A method of designing a pattern layout includes defining one shot area including a plurality of chip areas, generating an initial common layout in the plurality of chip areas, primarily correcting the initial layout to form a primary corrected layout, and secondarily correcting the primary corrected layout independently to form a plurality of secondary corrected layouts. | 10-03-2013 |
| 20130268902 | DECISION METHOD, STORAGE MEDIUM AND INFORMATION PROCESSING APPARATUS - The present invention provides a decision method which decides a mask pattern used in an exposure apparatus comprising a projection optical system that projects a mask pattern including a main pattern and an auxiliary pattern onto a substrate, and an exposure condition in the exposure apparatus, the method including a step of calculating an image of a mask pattern formed on the substrate by the projection optical system while changing settings of the mask pattern and the exposure condition, and deciding the mask pattern and the exposure condition based on the image of the mask pattern, wherein the step includes determining whether or not to generate a new auxiliary pattern after the settings are changed. | 10-10-2013 |
| 20130275925 | Pattern Correction With Location Effect - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a plurality of IC regions each including an IC pattern; performing a dissection process to the IC design layout; and performing a correction process to the IC design layout using a correction model that includes proximity effect and location effect. The correction process includes performing a first correction step to a first IC region of the IC regions, resulting in a first corrected IC pattern in the first IC region; and performing a second correction step to a second IC region of the IC regions, starting with the first corrected IC pattern, resulting in a second corrected IC pattern. | 10-17-2013 |
| 20130275926 | NOVEL METHODOLOGY OF OPTICAL PROXIMITY CORRECTION OPTIMIZATION - A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database. | 10-17-2013 |
| 20130275927 | RC Corner Solutions for Double Patterning Technology - A method includes determining model parameters for forming an integrated circuit, and generating a techfile using the model parameters. The techfile includes at least two of a C_worst table, a C_best table, and a C_nominal table. The C_worst table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks comprising the layout patterns shift relative to each other. The C_best table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The C_nominal table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other. The techfile is embodied on a tangible non-transitory storage medium. | 10-17-2013 |
| 20130275928 | METHOD FOR CORRECTING LAYOUT PATTERN AND MASK THEREOF - A method for correcting layout pattern and a mask having the corrected layout pattern thereon are provided. In an exemplary method, a first layout pattern including a plurality of first hole patterns can be provided to form an auxiliary pattern in each first hole pattern and to obtain a second layout pattern. The auxiliary pattern can have a dimension smaller than an exposure resolution in a photolithography process. The second layout pattern can then be processed by an optical proximity correction (OPC) to obtain a first modified layout pattern. The first modified layout pattern can include a plurality of modified first hole patterns modified by the OPC. The first modified layout pattern can be simulated to obtain an actual layout pattern such that the actual layout pattern and the first layout pattern have an edge placement error (EPE) within a predetermined range. | 10-17-2013 |
| 20130283217 | METHOD AND SYSTEM FOR FORMING PATTERNS USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask data preparation (MDP) is disclosed, in which a set of shots is determined that will form a pattern on a reticle, where the determination includes calculating the pattern that will be formed on a substrate using an optical lithographic process with a reticle formed using the set of shots. A method for optical proximity correction (OPC) or MDP is also disclosed, in which a preliminary set of charged particle beam shots is generated using a preliminary mask model, and then the shots are modified by calculating both a reticle pattern using a final mask model, and a resulting substrate pattern. A method for OPC is also disclosed, in which an ideal pattern for a photomask is calculated from a desired substrate pattern, where the model used in the calculation includes only optical lithography effects and/or substrate processing effects. | 10-24-2013 |
| 20130283218 | METHOD AND SYSTEM FOR FORMING PATTERNS USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask data preparation (MDP) is disclosed, in which a set of shots is determined that will form a pattern on a reticle, where the determination includes calculating the pattern that will be formed on a substrate using an optical lithographic process with a reticle formed using the set of shots. A method for optical proximity correction (OPC) or MDP is also disclosed, in which a preliminary set of charged particle beam shots is generated using a preliminary mask model, and then the shots are modified by calculating both a reticle pattern using a final mask model, and a resulting substrate pattern. A method for OPC is also disclosed, in which an ideal pattern for a photomask is calculated from a desired substrate pattern, where the model used in the calculation includes only optical lithography effects and/or substrate processing effects. | 10-24-2013 |
| 20130283219 | METHOD AND SYSTEM FOR FORMING PATTERNS USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask data preparation (MDP) is disclosed, in which a set of shots is determined that will form a pattern on a reticle, where the determination includes calculating the pattern that will be formed on a substrate using an optical lithographic process with a reticle formed using the set of shots. A method for optical proximity correction (OPC) or MDP is also disclosed, in which a preliminary set of charged particle beam shots is generated using a preliminary mask model, and then the shots are modified by calculating both a reticle pattern using a final mask model, and a resulting substrate pattern. A method for OPC is also disclosed, in which an ideal pattern for a photomask is calculated from a desired substrate pattern, where the model used in the calculation includes only optical lithography effects and/or substrate processing effects. | 10-24-2013 |
| 20130290913 | METHOD FOR OPTICAL PROXIMITY CORRECTION OF A RETICLE TO BE MANUFACTURED USING SHAPED BEAM LITHOGRAPHY - In the field of semiconductor production using shaped charged particle beam lithography, a method and system for fracturing or mask data preparation or proximity effect correction is disclosed, wherein a series of curvilinear character projection shots are determined for a charged particle beam writer system, such that the set of shots can form a continuous track, possibly of varying width, on a surface. A method for forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. Methods for manufacturing a reticle and for manufacturing a substrate such as a silicon wafer by forming a continuous track on a surface using a series of curvilinear character projection shots is also disclosed. | 10-31-2013 |
| 20130311958 | PATTERN SELECTION FOR FULL-CHIP SOURCE AND MASK OPTIMIZATION - The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result. | 11-21-2013 |
| 20130311959 | MULTIVARIABLE SOLVER FOR OPTICAL PROXIMITY CORRECTION - The method of the invention tracks how the collective movement of edge segments in a mask layout alters the resist image values at control points in the layout and simultaneously determines a correction amount for each edge segment in the layout. A multisolver matrix that represents the collective effect of movements of each edge segment in the mask layout is used to simultaneously determine the correction amount for each edge segment in the mask layout. | 11-21-2013 |
| 20140007025 | METHOD AND SYSTEM FOR CREATION OF BINARY SPATIAL FILTERS | 01-02-2014 |
| 20140013287 | FRACTURE AWARE OPC - The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits. | 01-09-2014 |
| 20140019919 | FLARE EFFECT INDUCED ERROR CORRECTION - A target pattern is provided including a first pattern in a first region. A sensor pattern is inserted in the target pattern in the first region. A flare intensity of the sensor pattern in the first region is determined. A pattern bias is determined based on the flare intensity. | 01-16-2014 |
| 20140019920 | METHOD FOR CREATING A PHOTOLITHOGRAPHY MASK - A method may be for creating a photolithography mask from a set of initial mask cells arranged to form an initial mask. The set may include first and second initial mask cells having a mask element in common within an initial region of the initial mask. The method may include a creation of a first modified mask cell and of a second modified mask cell including OPC processing operations, a comparison of the position of the mask element in common between the first modified mask cell and the second modified mask cell, and if the result of the comparison is greater than a threshold, a creation of a new mask region including an optical proximity correction processing operation on the initial region, and a creation of the photolithography mask from the new mask region. | 01-16-2014 |
| 20140033143 | MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing a semiconductor device is provided which includes forming a target layout; producing a skewed layout that includes retargeting the target layout; detecting an envelope of the skewed layout; generating a jog-free layout according to the detected envelope; fragmenting the jog-free layout; acquiring a layout that converges towards the skewed layout by performing an optical proximity correction on the fragmented jog-free layout; and patterning a material for forming the semiconductor device using the acquired layout. | 01-30-2014 |
| 20140033144 | PROVIDING ELECRON BEAM PROXIMITY EFFECT CORRECTION BY SIMULATING WRITE OPERATIONS OF POLYGONAL SHAPES - A method for writing a design to a material using an electron beam includes assigning a first dosage to a first polygonal shape. The first polygonal shape occupies a first virtual layer and includes a first set of pixels. The method also includes simulating a first write operation using the first polygonal shape to create the design, discerning an error in the simulated first write operation, and assigning a second dosage to a second polygonal shape to reduce the error. The second polygonal shape occupies a second virtual layer. The method further includes creating a data structure that includes the first and second polygonal shapes and saving the data structure to a non-transitory computer-readable medium. | 01-30-2014 |
| 20140040838 | Methods For Making A Mask For An Integrated Circuit Design - A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask. | 02-06-2014 |
| 20140047397 | LENS HEATING COMPENSATION SYSTEMS AND METHODS - Methods for calibrating a photolithographic system are disclosed. A cold lens contour for a reticle design and at least one hot lens contour for the reticle design are generated from which a process window is defined. Aberrations induced by a lens manipulator are characterized in a manipulator model and the process window is optimized using the manipulator model. Aberrations are characterized by identifying variations in critical dimensions caused by lens manipulation for a plurality of manipulator settings and by modeling behavior of the manipulator as a relationship between manipulator settings and aberrations. The process window may be optimized by minimizing a cost function for a set of critical locations. | 02-13-2014 |
| 20140075398 | Method and Apparatus for Process Window Modeling - A photolithographic modeling process is disclosed. Optical and non-optical parts of a model of the photolithographic process are calibrated. With the non-optical part of the model one or more model corrections are determined between (i) modeled critical dimension data from an aerial image generated by the optical part of the model, and (ii) empirical critical dimension data from tangible structures made at only a first process combination of a first dose and a first defocus in the photolithographic process. Critical dimension data of the photolithographic process are predicted at a second process combination of a second dose and a second defocus in the photolithographic process. | 03-13-2014 |
| 20140075399 | METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY - A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error. | 03-13-2014 |
| 20140101624 | CONTOUR ALIGNMENT SYSTEM - The present disclosure describes a method of calibrating a contour. The method includes designing an anchor pattern, printing the anchor pattern on a substrate, collecting scanning electron microscope (SEM) data of the printed anchor pattern on the substrate, wherein the SEM data includes a SEM image of the printed anchor pattern on the substrate, converting the SEM image of the printed anchor pattern on the substrate into a SEM contour of the printed anchor pattern, analyzing the SEM contour of the printed anchor pattern, and aligning the SEM contour of the anchor pattern to form the calibrated SEM contour. | 04-10-2014 |
| 20140109026 | Novel Methodology of Optical Proximity Correction Optimization - A method for performing optical proximity correction (OPC) and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first OPC modification to a mask feature of the design database is made by performing a first OPC process. The OPC process includes: dividing the mask feature into child shapes and adjusting an attribute of a child shape based on an edge placement error (EPE) factor. A first lithography simulation is performed utilizing a first set of performance indexes after making the first OPC modification, and a second OPC modification to the mask feature is made based on a result of the first lithography simulation. A second lithography simulation of the mask feature is performed utilizing a second set of performance indexes to verify the first and second OPC modifications, and the design database is provided for manufacturing. | 04-17-2014 |
| 20140123083 | AUTOMATIC WAFER DATA SAMPLE PLANNING AND REVIEW - A method of constructing a mask for use in semiconductor device manufacturing is disclosed. A first shape that is related to mask construction is selected from a set of shapes. A second shape related to the mask construction is selected from the set of shapes. The first shape and the second shape are represented using a first shape vector and a second shape vector, respectively. A cluster is formed that includes the first shape and the second shape when the first shape vector and the second shape vector are within a selected criterion. | 05-01-2014 |
| 20140123084 | System and Method for Improving a Lithography Simulation Model - A method of performing initial optical proximity correction (OPC) with a calibrated lithography simulation model. The method includes providing a photomask having an integrated circuit (IC) pattern formed thereon, acquiring an aerial image of the IC pattern formed on the photomask using an optical microscope, and calibrating an optical component of the lithography simulation model based on the aerial image. The method also includes exposing and developing a photoresist layer on a semiconductor wafer using the photomask to form a post-development pattern on the photoresist layer, acquiring a post-development image of the post-development pattern on the photoresist layer, and calibrating the photoresist component of the lithography simulation model based on the post-development image. Further, the method includes performing initial optical proximity correction (OPC) on an IC design layout based on a simulation of the IC design layout by the lithography simulation model including the calibrated optical and photoresist components. | 05-01-2014 |
| 20140143741 | FRAGMENTATION POINT AND SIMULATION SITE ADJUSTMENT FOR RESOLUTION ENHANCEMENT TECHNIQUES - A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon. | 05-22-2014 |
| 20140189614 | METHOD AND SYSTEM OF MASK DATA PREPARATION FOR CURVILINEAR MASK PATTERNS FOR A DEVICE - A method comprises: (a) transforming a layout of a layer of an integrated circuit (IC) or micro electro-mechanical system (MEMS) to a curvilinear mask layout; (b) replacing at least one pattern of the curvilinear mask layout with a previously stored fracturing template having approximately the same shape as the pattern, to form a fractured IC or MEMS layout; and (c) storing, in a non-transitory storage medium, an e-beam generation file including a representation of the fractured IC or MEMS layout, to be used for fabricating a photomask. | 07-03-2014 |
| 20140208278 | PATTERN SELECTION FOR LITHOGRAPHIC MODEL CALIBRATION - The present invention relates generally to methods and apparatuses for test pattern selection for computational lithography model calibration. According to some aspects, the pattern selection algorithms of the present invention can be applied to any existing pool of candidate test patterns. According to some aspects, the present invention automatically selects those test patterns that are most effective in determining the optimal model parameter values from an existing pool of candidate test patterns, as opposed to designing optimal patterns. According to additional aspects, the selected set of test patterns according to the invention is able to excite all the known physics and chemistry in the model formulation, making sure that the wafer data for the test patterns can drive the model calibration to the optimal parameter values that realize the upper bound of prediction accuracy imposed by the model formulation. | 07-24-2014 |
| 20140215416 | Integration of Optical Proximity Correction and Mask Data Preparation - Aspects of the invention relate to techniques for integrating optical proximity correction and mask data preparation. First mask writer instructions for a layout design are simulated to generate a mask contour. Based on the generated mask contour, first layout data for the layout design are adjusted for optical proximity correction to generate second layout data. Using the generated second layout data as mask target, the first mask writer instructions are adjusted to generate second mask writer instructions. The above process may be iterated until an end condition is met. | 07-31-2014 |
| 20140215417 | NEAR-NEIGHBOR TRIMMING OF DUMMY FILL SHAPES WITH BUILT-IN OPTICAL PROXIMITY CORRECTIONS FOR SEMICONDUCTOR APPLICATIONS - Near-neighbor trimming of dummy fill shapes with built-in optical proximity corrections (OPCs) for semiconductor applications is provided. A method for the near-neighbor trimming includes adding one or more hole shapes onto a semiconductor design layout comprising a plurality of design shapes. The method further includes trimming adjacent ones of the plurality of which are covered by the one or more hole shapes. | 07-31-2014 |
| 20140223392 | OPTIMIZED OPTICAL PROXIMITY CORRECTION HANDLING FOR LITHOGRAPHIC FILLS - An approach for providing a fragmentation scheme for lithographic fills is provided. In a typical embodiment, a plurality of shapes in a lithographic (e.g., dummy) fill will be grouped/classified into a first set of shapes (e.g., a representative set of shapes) and a second set of shapes (e.g., a similar set of shapes). A set of points will be identified along the edges of the first set of shapes (e.g., at corners of the edges and at positions along the edges that are in alignment with corners of adjacent shapes) to yield an initial mask output. This initial mask output will be copied to the second set of shapes to yield a final mask output which may then be outputted using such an optimized fragmentation scheme. | 08-07-2014 |
| 20140223393 | Method and System for Forming High Accuracy Patterns Using Charged Particle Beam Lithography - A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed. | 08-07-2014 |
| 20140245240 | Free Form Fracturing Method for Electronic or Optical Lithography - The invention discloses a computer implemented method of fracturing a surface into elementary features wherein the desired pattern has a rectilinear or curvilinear form. Depending upon the desired pattern, a first fracturing will be performed of a non-overlapping or an overlapping type. If the desired pattern is resolution critical, it will be advantageous to perform a second fracturing step using eRIFs. These eRIFs will be positioned either on the edges or on the medial axis or skeleton of the desired pattern. The invention further discloses method steps to define the position and shape of the elementary features used for the first and second fracturing steps. | 08-28-2014 |
| 20140282295 | Method for Forming Photo-masks and OPC Method - The present invention provides a method for forming at least a photo mask. A first photo-mask pattern relating to a first structure is provides. A second photo-mask pattern relating to a second structure is provides. A third photo-mask pattern relating to a third structure is provides. The first structure, the second structure and the third structure are disposed in a semiconductor structure in sequence. An optical proximity process including a comparison step is provided, wherein the comparison step includes comparing the first photo-mask pattern and the third photo-mask pattern. Last, the first photo-mask pattern is import to form a first mask, the second photo-mask pattern is import to form a second mask, and the third photo-mask pattern is import to form a third mask. The present invention further provides an OPC method. | 09-18-2014 |
| 20140282296 | HYBRID METHOD FOR PERFORMING FULL FIELD OPTICAL PROXIMITY CORRECTION FOR FINFET MANDREL LAYER - A hybrid OPC process and a resulting reticle are disclosed. Embodiments include generating a finfet fin reticle including a first portion having regular pitches and a second portion having irregular pitches, performing rule based OPC on at least the first portion, and performing OPC repair locally at the second portion. | 09-18-2014 |
| 20140282297 | METHOD FOR GENERATING POST-OPC LAYOUT IN CONSIDERATION OF TOP LOSS OF ETCH MASK LAYER - A method of forming a semiconductor circuit includes receiving target layout. An optical proximity correction process is performed on the target layout data to generate a post-OPC layout. A patterning process is performed using the post-OPC layout. The post-OPC layout may be adjusted to compensate for a top loss of an etch mask layer. | 09-18-2014 |
| 20140282298 | PERFORMING IMAGE CALCULATION BASED ON SPATIAL COHERENCE - Computer-implemented techniques for pixel source optics calculations using spatial coherence are disclosed. Pixelated sources are used for source-mask co-optimization to enhance semiconductor lithography. Calculation of a partially coherent imaging system is used for optical-lithography simulation. The spatial coherence property of neighboring source points is used to reduce imaging calculation complexity. Two or more neighboring points are treated as one pseudo-spatially coherent area element. | 09-18-2014 |
| 20140282299 | METHOD AND APPARATUS FOR PERFORMING OPTICAL PROXIMITY AND PHOTOMASK CORRECTION - An approach is provided for enabling simulation of photomask contour shapes, performing verification on the simulated photomask shapes, and correcting errors in OPC correction or bad fracturing methods to perform photomask proximity correction in real time before physically writing of the photomask. Embodiments include performing optical proximity correction of a photomask of a semiconductor layout to generate a corrected photomask, simulating the corrected photomask to generate one or more simulated contour shapes within a simulated photomask, verifying the simulated contour shapes to determine errors associated with the simulated photomask, and correcting the errors in the simulated contour shapes of the simulated photomask to generate a final photomask. | 09-18-2014 |
| 20140282300 | TOPOGRAPHY DRIVEN OPC AND LITHOGRAPHY FLOW - Enhancements in lithography for forming an integrated circuit are disclosed. The enhancements include a topography analysis of a design data file to obtain accumulative topography information for different mask levels. The topography information facilitates topography driven optical proximity correction and topography driven lithography. | 09-18-2014 |
| 20140304666 | METHOD OF OPTICAL PROXIMITY CORRECTION FOR MODIFYING LINE PATTERNS AND INTEGRATED CIRCUTS WITH LINE PATTERNS MODIFIED BY THE SAME - A method of optical proximity correction executed by a computer system and integrated circuit layout formed by the same, the step of optical proximity correction comprises: providing an integrated circuit layout with a plurality of parallel line patterns, wherein one side of at least one line pattern is provided with a convex portion; and modifying the integrated circuit layout by forming a concave portion corresponding to the convex portion at the other side of the line pattern. | 10-09-2014 |
| 20140310663 | Performing OPC on Hardware or Software Platforms with GPU - Optical proximity correction techniques performed on one or more graphics processors improve the masks used for the printing of microelectronic circuit designs. Execution of OPC techniques on hardware or software platforms utilizing graphics processing units. GPUs may share the computation load with the system CPUs to efficiently and effectively execute the OPC method steps. | 10-16-2014 |
| 20140317580 | METHODS FOR PERFORMING MODEL-BASED LITHOGRAPHY GUIDED LAYOUT DESIGN - Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine-tune already-placed SRAFs. The SRAF guidance map can be used directly to place SRAFs in a mask layout. Mask layout data including SRAFs may be generated, wherein the SRAFs are placed according to the SRAF guidance map. The SRAF guidance map can comprise an image in which each pixel value indicates whether the pixel would contribute positively to edge behavior of features in the mask layout if the pixel is included as part of a sub-resolution assist feature. | 10-23-2014 |
| 20140317581 | REVISING LAYOUT DESIGN THROUGH OPC TO REDUCE CORNER ROUNDING EFFECT - The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner that is disposed adjacent to at least one of the gate lines. The first layout design for the semiconductor device is revised via an optical proximity correction (OPC) process, thereby generating a second layout design that includes a revised active region with a revised corner that protrudes outward. Thereafter, the semiconductor device is fabricated based on the second layout design. | 10-23-2014 |
| 20140331191 | METHOD OF CORRECTING ASSIST FEATURE - A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern. | 11-06-2014 |
| 20140351773 | MODEL-BASED PROCESS SIMULATION SYSTEMS AND METHODS - Systems and methods for process simulation are described. The methods may use a reference model identifying sensitivity of a reference scanner to a set of tunable parameters. Chip fabrication from a chip design may be simulated using the reference model, wherein the chip design is expressed as one or more masks. An iterative retuning and simulation process may be used to optimize critical dimension in the simulated chip and to obtain convergence of the simulated chip with an expected chip. Additionally, a designer may be provided with a set of results from which an updated chip design is created. | 11-27-2014 |
| 20140359542 | METHOD AND SYSTEM FOR DIMENSIONAL UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY - A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern. | 12-04-2014 |
| 20140359543 | METHOD AND APPARATUS FOR COST FUNCTION BASED SIMULTANEOUS OPC AND SBAR OPTIMIZATION - Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features. | 12-04-2014 |
| 20140365982 | Method for Making a Mask With a Phase Bar in An Integrated Circuit Design Layout - A method for making a mask includes receiving an integrated circuit (IC) design layout and identifying at least one targeted-feature-surrounding-location (TFSL) in the IC design layout, wherein TFSL is identified by a model-based approach. The method further includes inserting at least one phase bar (PB) in the IC design layout and performing an optical proximity correction (OPC) to the IC design layout having the at least one PB to form a modified IC design layout. A mask is then fabricated based on the modified IC design layout. | 12-11-2014 |
| 20140365983 | INTEGRATION OF LITHOGRAPHY APPARATUS AND MASK OPTIMIZATION PROCESS WITH MULTIPLE PATTERNING PROCESS - The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. A method of splitting a pattern to be imaged onto a substrate via a lithographic process into a plurality of sub-patterns is disclosed, wherein the method comprises a splitting step being configured to be aware of requirements of a co-optimization between at least one of the sub-patterns and an optical setting of the lithography apparatus used for the lithographic process. Device characteristic optimization techniques, including intelligent pattern selection based on diffraction signature analysis, may be integrated into the multiple patterning process flow. | 12-11-2014 |
| 20150040078 | METHODS AND SYSTEMS FOR DESIGNING AND MANUFACTURING OPTICAL LITHOGRAPHY MASKS - A method of designing an optical photomask includes providing a target pattern, correcting the target pattern with an OPC model, adjusting the target pattern and/or the OPC model, and correcting a first corrected pattern. The target pattern indicates a target shape of a pre-pattern opening in a photoresist layer on a semiconductor substrate. Correcting the target pattern includes using an optical proximity correction (OPC) model to generate OPC output information that includes edge placement error (EPE) information, a first corrected pattern, and/or a simulated contour of the pre-pattern opening. Adjusting the target pattern and/or the OPC model includes adjusting with OPC based adjustments that are based on the OPC output information. Correcting the first corrected pattern includes using the OPC model in response to the OPC based adjustments to generate a second corrected pattern. | 02-05-2015 |
| 20150040079 | Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons. | 02-05-2015 |
| 20150040080 | METHODS FOR MODIFYING AN INTEGRATED CIRCUIT LAYOUT DESIGN - Methods for modifying a layout design of an integrated circuit using model-based retargeting are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial integrated circuit layout design, correcting the initial layout design for etch-induced lithography errors to generate an etch-corrected layout design, and fragmenting the etch-corrected layout design to generate a fragmented layout design comprising a plurality of fragments. The method further includes performing a bridging condition simulation and a pinching condition simulation on the fragmented layout design and calculating a required movement for at least one fragment of the fragmented layout design based on the bridging condition simulation and the pinching condition simulation. Still further, the method includes modifying the fragmented layout design by moving the at least one fragment in accordance with the required movement to generate a modified layout design and performing optical proximity correction on the modified layout design. | 02-05-2015 |
| 20150040081 | Method and Apparatus for Integrated Circuit Mask Patterning - Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process. | 02-05-2015 |
| 20150052491 | METHOD FOR GENERATING LAYOUT PATTERN - A method for generating a layout pattern is provided. First, a layout pattern is provided to a computer system and is classified into two sub-patterns and a blank pattern. Each of the sub-patterns has pitches in simple integer ratios and the blank pattern is between the two sub-patterns. Then, a plurality of first stripe patterns and at least two second stripe patterns are generated. The edges of the first stripe patterns are aligned with the edges of the sub-patterns and the first stripe patterns have equal spacings and widths. The spacings or widths of the second stripe patterns are different from that of the first stripe patterns. | 02-19-2015 |
| 20150058814 | METHOD AND SYSTEM FOR OBTAINING OPTICAL PROXIMITY CORRECTION MODEL CALIBRATION DATA - A method may be implemented for obtaining calibration data for use in calibrating an optical proximity correction model. The method may include capturing an image for each portion of a plurality of portions of a wafer to obtain captured images. The method may further include assembling at least portions of the captured images to form an assembled image. The method may further include mapping layout data of the wafer with the assembled image. The method may further include selecting portions of the assembled image based on the layout data of the wafer. The method may further include obtaining data associated with the portions of the assembled image as the calibration data. | 02-26-2015 |
| 20150058815 | CORRECTION FOR FLARE EFFECTS IN LITHOGRAPHY SYSTEM - A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. | 02-26-2015 |
| 20150067619 | ADVANCED CORRECTION METHOD - An advanced correction method is provided. A target layout pattern is provided, and is corrected by a correction model to obtain a corrected pattern. A simulation is performed on the corrected pattern to obtain a simulation contour. A plurality of off-target evaluation points are established on the simulation contour, the simulation contour is compared with a target layout pattern, and a plurality of risk weighting values of each of the off-target evaluation points are obtained. A risk sum value obtained by summing up the risk weighting values of each of the off-target evaluation points is sorted into a processing sequence in descending manner. The target layout pattern is identified, classified and grouped into a plurality of pattern blocks. The corrected pattern is modified according to the processing sequence, so as to converge the simulation contour of the corrected pattern being modified to be close to the target layout pattern. | 03-05-2015 |
| 20150067620 | METHOD AND SYSTEM OF GENERATING LAYOUT - A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern. | 03-05-2015 |
| 20150074620 | METHOD OF MAKING PHOTOMASK LAYOUT AND METHOD OF FORMING PHOTOMASK INCLUDING THE PHOTOMASK LAYOUT - A method of making a photomask layout is provided. A graphic data of a photomask is provided. The graphic data includes at least one rectangular pattern. A correction step is performed to the graphic data by using a computer. The correction step includes adding a substantially ring-shaped pattern inside the rectangular pattern. A method of forming a photomask by using the photomask layout obtained by the said method is also provided. In an embodiment, the photomask is suitable for defining micro-lenses of a solid-state image sensor. | 03-12-2015 |
| 20150089459 | DESIGN RULE AND LITHOGRAPHIC PROCESS CO-OPTIMIZATION - A computer-implemented method for obtaining values of one or more design variables of one or more design rules for a pattern transfer process comprising a lithographic projection apparatus, the method comprising. simultaneously optimizing one or more design variables of the pattern transfer process and the one or more design variables of the one or more design rules. The optimizing comprises evaluating a cost function that measures a metric characteristic of the pattern transfer process, the cost function being a function of one or more design variables of the pattern transfer process and one or more design variables of the one or more design rules. | 03-26-2015 |
| 20150089460 | METHOD OF PERFORMING OPTICAL PROXIMITY CORRECTION FOR PREPARING MASK PROJECTED ONTO WAFER BY PHOTOLITHOGRAPHY - A method of performing optical proximity correction for preparing a mask projected onto a wafer by photolithography includes the following steps. An integrated circuit layout design including a first feature and a second feature is obtained, wherein the first feature overlaps a first boundary of two structures in the wafer. An edge of the first feature close to the second feature pertaining to a specific trend section of an experimental chart having trend sections is recognized. An optical proximity correction value is evaluated for the edge through a computer system according to a rule corresponding to the specific trend section. The layout design is compensated with the optical proximity correction value. | 03-26-2015 |
| 20150106773 | METHODOLOGY FOR PATTERN CORRECTION - The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time. | 04-16-2015 |
| 20150113486 | ENHANCED OPTICAL PROXIMITY CORRECTION (OPC) METHOD AND SYSTEM - An enhanced optical proximity correction method is provided. The method includes providing a mask substrate and a substrate and obtaining a customer target pattern. The method also includes obtaining a production layout by performing an optical proximity correction process onto the customer target pattern using the pattern and a pattern formed on the substrate. Further, the method includes obtaining the light intensity information instead of dimension of the production layout. Further, the method includes storing the light intensity information of the production layout, the production layout and surrounding coherence radius in an optical proximity correction model database if the light intensity information of the production layout does not coincide with light intensity information of original modeling patterns already stored in the optical proximity correction model database. Further, the method also includes generating actual patterns using the stored optical proximity correction model corresponding to the stored light intensity information. | 04-23-2015 |
| 20150135146 | THREE-DIMENSIONAL MASK MODEL FOR PHOTOLITHOGRAPHY SIMULATION - A three-dimensional mask model of the invention provides a more realistic approximation of the three-dimensional effects of a photolithography mask with sub-wavelength features than a thin-mask model. In one embodiment, the three-dimensional mask model includes a set of filtering kernels in the spatial domain that are configured to be convolved with thin-mask transmission functions to produce a near-field image. In another embodiment, the three-dimensional mask model includes a set of correction factors in the frequency domain that are configured to be multiplied by the Fourier transform of thin-mask transmission functions to produce a near-field image. | 05-14-2015 |
| 20150143304 | Target Point Generation for Optical Proximity Correction - A method performed by a computer processing system includes receiving a design pattern for an integrated circuit, applying a function to the design pattern to generate a model contour, generating a plurality of Optical Proximity Correction (OPC) target points along the model contour, adjusting the design pattern to create an adjusted pattern, and performing a simulation on the adjusted pattern to create a simulated contour. | 05-21-2015 |
| 20150294053 | Pattern Optical Similarity Determination - Aspects of the invention relate to techniques for determining pattern optical similarity in lithography. Optical kernel strength values for a first set of layout features and a second set of layout features are computed first. Based on the optical kernel strength values, optical similarity values between the first set of layout features and the second set of layout features are then determined. Subsequently, calibration weight values for the first set of layout features may be determined based on the optical similarity values, which, along with the first set of layout features, may be employed to calibrate lithography process model parameters. | 10-15-2015 |
| 20150302132 | MASK3D MODEL ACCURACY ENHANCEMENT FOR SMALL FEATURE COUPLING EFFECT - A method and apparatus of a novel full chip edge-based mask three-dimensional (3D) model for performing photolithography simulation with consideration for edge coupling effect is described. The method receives a mask design layout in order to perform mask topography effect modeling. The method generates scaling parameters for edge coupling effects. Each scaling parameter has an associated combination of feature width and space. The sum of feature width and space associated with at least one scaling parameter is less than a minimum pitch. The method applies a thick mask model that includes several edge-based kernels to the mask design layout to create a mask 3D residual. To apply the thick mask model to the mask design layout, the method updates the edge-based kernels with the scaling parameters. | 10-22-2015 |
| 20150310155 | NET-VOLTAGE-AWARE OPTICAL PROXIMITY CORRECTION (OPC) - Various embodiments include computer-implemented methods, computer program products and systems for verifying an integrated circuit (IC) layout. In some cases, approaches include a computer-implemented method of verifying an IC layout, the method including: obtaining data about a process variation band for at least one physical feature in the IC layout; determining voltage-based process variation band thresholds for the at least one physical feature in the IC layout; determining whether the process variation band for the at least one physical feature in the IC layout meets design specifications for the IC layout based upon the voltage-based process variation band thresholds for the at least one physical feature in the IC layout; and modifying the IC layout in response to a determination that the process variation band for the at least one physical feature does not meet the design specifications. | 10-29-2015 |
| 20150310156 | METHOD AND APPARATUS FOR OPTICAL PROXIMITY CORRECTION - Some embodiments of the present disclosure provide an integrated circuit (IC) design method. The method includes (1) receiving a first layout comprising stripe patterns with a first separation and a first width; (2) receiving a second layout comprising stripe patterns with a second width narrower than the first separation, each stripe on the second layout is configured to situate between two adjacent stripes on the first layout when overlaying the first layout and the second layout; (3) performing a separation check by identifying a spacing between a stripe on the second layout and one of the two adjacent stripes on the first layout; and (4) adjusting the spacing between the stripe on the second layout and one of the two adjacent stripes on the first layout when the separation check determining the spacing is greater than a predetermined value. | 10-29-2015 |
| 20150310157 | MASK ERROR COMPENSATION BY OPTICAL MODELING CALIBRATION - Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio. | 10-29-2015 |
| 20150310158 | Method for Integrated Circuit Manufacturing - Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage. | 10-29-2015 |
| 20150317424 | SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE - In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter. | 11-05-2015 |
| 20150338737 | Method and System for Design of Enhanced Edge Slope Patterns for Charged Particle Beam Lithography - A method and system for fracturing or mask data preparation are presented in which overlapping shots are generated to increase dosage in selected portions of a pattern, thus improving the fidelity and/or the critical dimension variation of the transferred pattern. In various embodiments, the improvements may affect the ends of paths or lines, or square or nearly-square patterns. Simulation is used to determine the pattern that will be produced on the surface. | 11-26-2015 |
| 20150347657 | METHOD FOR GENERATING LAYOUT PATTERN - A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask. | 12-03-2015 |
| 20150356230 | OPTICAL PROXIMITY CORRECTION (OPC) ACCOUNTING FOR CRITICAL DIMENSION (CD) VARIATION FROM INTER-LEVEL EFFECTS - Various embodiments include computer-implemented methods, computer program products and systems for modeling at least one feature in an integrated circuit (IC) layout for an inter-layer effect. In some cases, approaches include a computer-implemented method of modeling at least one feature in an IC layout for an inter-level effect, the method including: building a set of shape measurement regions each connected with an edge of the at least one feature; determining a set of shape parameters for each shape measurement region in the set of shape measurement regions; and creating a column vector representing each shape measurement region using the set of shape parameters, the column vector representing the inter-layer effect of the at least one feature, wherein the inter-layer effect includes a physical relationship between the at least one feature and another feature on a distinct level of the IC layout. | 12-10-2015 |
| 20150356231 | PLANAR DESIGN TO NON-PLANAR DESIGN CONVERSION METHOD - A planar design to non-planar design conversion method includes following steps. At least a diffusion region pattern including a first side and a second side perpendicular to each other is received. A look-up table is queried to obtain a first positive integer according to the first side of the diffusion region pattern and a second positive integer according to the second side of the diffusion region pattern. Then, a plurality of fin patterns is formed. An amount of the fin patterns is equal to the second positive integer. The fin patterns respectively include a first fin length, and the first fin length is a product of the first positive integer and a predetermined value. The forming is performed by at least a computer-aided design (CAD) tool. | 12-10-2015 |
| 20150362834 | EXPOSURE METHODS USING E-BEAMS AND METHODS OF MANUFACTURING MASKS AND SEMICONDUCTOR DEVICES THEREFROM - Disclosed are an exposure method and a method of manufacturing a mask and a semiconductor device using the same, which minimize time taken by mask data preparation (MDP) to optimize a total exposure process and enhance a quality of a pattern by using an inverse solution concept, based on a multi-beam mask writer. The exposure method includes receiving mask tape output (MTO) design data obtained through optical proximity correction (OPC), preparing mask data, including a job deck, for the MTO design data without a data format conversion, performing complex correction, including proximity effect correction (PEC) of an error caused by an e-beam proximity effect and mask process correction (MPC) of an error caused by an exposure process, on the mask data, generating pixel data, based on data for which the complex correction is performed, and performing e-beam writing on a substrate for a mask, based on the pixel data. | 12-17-2015 |
| 20150363536 | CORRECTING FOR STRESS INDUCED PATTERN SHIFTS IN SEMICONDUCTOR MANUFACTURING - Apparatus, method and computer program product for reducing overlay errors during a semiconductor photolithographic mask design process flow. The method obtains data representing density characteristics of a photo mask layout design; predicts stress induced displacements based on said obtained density characteristics data; and corrects the mask layout design data by specifying shift movement of individual photo mask design shapes to pre-compensate for predicted displacements. To obtain data representing density characteristics, the method merges pieces of data that are combined to make a photo mask to obtain a full reticle field data set. The merge includes a merge of data representing density characteristic driven stress effects. The density characteristics data for the merged reticle data are then computed. To predict stress-induced displacements, the method inputs said density characteristics data into a programmed model that predicts displacements as a function of density, and outputs the predicted shift data. | 12-17-2015 |
| 20150379185 | MASK DATA GENERATION METHOD, MASK DATA GENERATION SYSTEM, AND RECORDING MEDIUM - According to one embodiment, there is provided a mask data generation method. The mask data generation method includes obtaining depth information about a pattern depth of a hole included in design information about a semiconductor device. The mask data generation method includes obtaining a first correction rule used to correct, in terms of the pattern depth, a process conversion difference between a resist pattern and a processed pattern. The mask data generation method includes determining temporary mask data including a lithography target pattern by applying a first process conversion difference correction processing to a dimension of hole pattern arranged in design layout data based on the depth information and the first correction rule. | 12-31-2015 |
| 20150379188 | IC LAYOUT ADJUSTMENT METHOD AND TOOL FOR IMPROVING DIELECTRIC RELIABILITY AT INTERCONNECTS - Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias. | 12-31-2015 |
| 20160026079 | MASK PATTERN CORRECTING METHOD - A mask pattern correcting method according to an embodiment is a correcting method of a mask pattern to be used in a semiconductor device manufacturing process. In the correcting method, a plurality of kernels calculated based on an optical system of an exposure tool is prepared. Weight coefficients for weighting the kernels, respectively, to be used when the kernels are synthesized, are calculated. The kernels are synthesized using the calculated weight coefficients. The mask pattern is corrected using the synthesized kernels. | 01-28-2016 |
| 20160034632 | POSITION MEASURING METHOD, MISPLACEMENT MAP GENERATING METHOD, AND INSPECTION SYSTEM - In a position measuring method, a mask including first patterns to be transferred and second patterns not to be transferred is prepared. The position coordinates of the second patterns are measured with a position measuring apparatus and an inspection system. First position correction data is generated based on the position coordinates of the second patterns. A difference is obtained between the measured position coordinates of the second patterns and the first position correction data is corrected using the obtained difference. Second position correction data is generated from the corrected first position correction data. An optical image including the position coordinates of the first and second patterns is acquired. The position coordinates of the first patterns of the optical image are corrected using a difference between the position coordinates of the second patterns of the optical image and of the second patterns based on the second position correction data. | 02-04-2016 |
| 20160055281 | MODEL-BASED GENERATION OF DUMMY FEATURES - Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features. | 02-25-2016 |
| 20160070843 | APPARATUS AND METHOD FOR E-BEAM WRITING - A method of preparing mask data, the method begins with performing a logic operation to a design layout, and an optical proximity correction (OPC) is performed to the design layout to form an OPC feature. The OPC feature has a first jog and a second jog on a line, and the first jog is larger than the second jog in width. The OPC feature is resized to form a resized first jog and a resized second jog on the line if a width ratio of the first jog to the second jog being smaller than a predetermined value. | 03-10-2016 |
| 20160070847 | PATTERN DIMENSION CALCULATION METHOD, SIMULATION APPARATUS, COMPUTER-READABLE RECORDING MEDIUM AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - According to an embodiment, a pattern dimension calculation method includes setting a reference point on a first circuit pattern, calculating, as a size of area of an opposing pattern, a size of area of a range corresponding to the reference point of a second circuit pattern opposite to the reference point, and calculating a dimension of the first circuit pattern in accordance with the size of area of the opposing pattern. | 03-10-2016 |
| 20160085906 | Method and Apparatus for Integrated Circuit Mask Patterning - Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process. | 03-24-2016 |
| 20160098511 | MATRIX REDUCTION FOR LITHOGRAPHY SIMULATION - A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector. | 04-07-2016 |
| 20160103389 | METHOD AND PROGRAM PRODUCT FOR DESIGNING SOURCE AND MASK FOR LITHOGRAPHY - A system and method for optimizing (designing) a mask pattern, in which SMO and OPC are collaboratively used to exert a sufficient collaborative effect or are appropriately used in different manners. The method for designing a source and a mask for lithography includes a step (S | 04-14-2016 |
| 20160109795 | SOURCE, TARGET AND MASK OPTIMIZATION BY INCORPORATING CONTOUR BASED ASSESSMENTS AND INTEGRATION OVER PROCESS VARIATIONS - Methods and systems for determining a source shape, a mask shape and a target shape for a lithography process are disclosed. One such method includes receiving source, mask and target constraints and formulating an optimization problem that is based on the source, mask and target constraints and incorporates contour-based assessments for the target shape that are based on physical design quality of a circuit. Further, the optimization problem is solved by integrating over process condition variations to simultaneously determine the source shape, the mask shape and the target shape. In addition, the determined source shape and mask shape are output | 04-21-2016 |
| 20160132627 | METHOD AND SYSTEM TO PREPARE, MANUFACTURE AND INSPECT MASK PATTERNS FOR A SEMICONDUCTOR DEVICE - A system and method that includes receiving a layout of an integrated circuit (IC) device. A template library is provided having a plurality of parameterized shape elements. A curvilinear feature of layout is classified by selecting at least one of the parameterized shape elements that defines the curvilinear feature. A template index is associated with the layout is formed that includes the selected parameterized shape element. The template index and the layout can be delivered to a mask writer, which uses the template index and the layout to fabricate a pattern on a photomask. | 05-12-2016 |
| 20160154922 | OPTICAL PROXIMITY CORRECTION TAKING INTO ACCOUNT WAFER TOPOGRAPHY | 06-02-2016 |
| 20160154925 | Method for Integrated Circuit Mask Patterning | 06-02-2016 |
| 20160161841 | SAMPLING FOR OPC MODEL BUILDING - Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy. | 06-09-2016 |
| 20160161842 | SCANNER BASED OPTICAL PROXIMITY CORRECTION SYSTEM AND METHOD OF USE - A modeling technique is provided. The modeling technique includes inputting tool parameters into a model and inputting basic model parameters into the model. The technique further includes generating a simulated, corrected reticle design using the tool parameters and the basic model parameters. An image of test patterns is compared against the simulated, corrected reticle design. A determination is made as to whether δ | 06-09-2016 |
| 20160162627 | Method for Integrated Circuit Manufacturing - Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern. | 06-09-2016 |
| 20160188781 | METHODS FOR RETARGETING CIRCUIT DESIGN LAYOUTS AND FOR FABRICATING SEMICONDUCTOR DEVICES USING RETARGETED LAYOUTS - Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict. | 06-30-2016 |
| 20160196381 | METROLOGY PATTERN LAYOUT AND METHOD OF USE THEREOF | 07-07-2016 |
| 20190146355 | Optical Proximity Correction and Photomasks | 05-16-2019 |
