Entries |
Document | Title | Date |
20100315112 | SOCKET ADAPTER FOR TESTING SINGULATED ICS WITH WAFER LEVEL PROBE CARD - An integrated probe card and socket adapter includes probe needles for probing a wafer including a plurality of CSP IC each having a plurality of bumps. A socket adapter includes a socket body having an elevated portion and a recessed base portion. The recessed base portion has a base portion thickness and includes a plurality of base portion through-holes that align with and receive the bumps on at least one of said plurality of CSP IC after singulation (singulated CSP IC) for securing the singulated CSP IC thereto. The elevated portion includes a plurality of elevated portion through-holes for fastening to the probe card when the probe card is underlying. The base portion thickness is sized so that the probe needles extend into the base portion through-holes a sufficient distance to contact the bumps of the singulated CSP IC for testing using the probe card. | 12-16-2010 |
20110001505 | TEST SOCKETS FABRICATED BY MEMS TECHNOLOGY FOR TESTING OF SEMICONDUCTOR DEVICES - The present invention dicloses test sockets fabricated by MEMS technology for testing of semiconductor devices. Semiconductor device test sockets fabricated by MEMS technology in accordance with one or more embodiments of the invention offer many unique advantages over conventional test sockets (e.g. sockets utilizing pogo-pins). In one embodiment of the invention, a novel test socket includes a substrate with multiple cavities of certain depths in middle region of one side, electrical contacts (electrodes) of cantilever type directly above the cavities making individual contact with each contactor of semiconductor device, and multiple signal paths electrically connecting the cantilever type contacts on one side of the substrate and the loadboard PCB(printed circuit board) or motherboard PCB placed on the other side of the substrate. | 01-06-2011 |
20110050264 | SUBSTRATE INSPECTION APPARATUS - According to one embodiment, a substrate inspection apparatus includes a probe socket, a probe pin, and an adaptor. The probe socket is fixed to an inspection jig on which a substrate is provided, one end of the probe socket being connected to a processor. The probe pin is attached to the other end portion of the probe socket, includes a tip shape conforming to an inspection point of the substrate with which the probe pin is in contact, and including at least one of a projection and a groove designed to specify the tip shape on a side on which the probe pin is attached to the probe socket. The adaptor is attached to the other end portion of the probe socket, and including a through hole formed in conformity with the shape of the side on which the probe pin is attached to the probe socket. | 03-03-2011 |
20110074457 | System For Testing Electronic Components - An improved efficiency system for testing electronic components in a motherboard/daughterboard assembly in which the daughterboard is mounted in spaced parallel relationship the to motherboard includes one or more device-under-test socket sub-assemblies having a test socket thereon for receiving a device-under-test and a connector component for disengagable connection to a complementary connector component on the daughterboard with the socket sub-assembly effecting interengagement of the complementary connector component on the daughterboard via an opening in the motherboard to allow ready access to the test socket for temporary installation, testing, and removal of a device-under-test. | 03-31-2011 |
20110080187 | Device Interface Board with Cavity Back for Very High Frequency Applications - In one embodiment, a device interface board is provided which includes a printed circuit board with a DUT interface structure, such as socket, associated with a DUT side of the printed circuit board. A high frequency connector and electronic component are mounted in a cavity formed in a back side of the printed circuit board. A signal via through the printed circuit board couples the high frequency connector and electronic component with the DUT interface structure. An encapsulating structure may be provided, which covers the cavity while allowing a cable to connect to the high frequency connector. | 04-07-2011 |
20110084720 | TEST APPARATUS FOR ELECTRONIC DEVICE PACKAGE AND METHOD FOR TESTING ELECTRONIC DEVICE PACKAGE - A test apparatus for an electronic device package is provided, which includes a test socket having a first portion with a recess for receiving an electronic device package having external terminals arranged in a terminal configuration and a second portion. An interchangeable insert board is disposed between the first portion and the second portion and extended on the recess, which includes first contact pads arranged in a first pad configuration compatible with the terminal configuration and facing the recess and second contact pads arranged in a second pad configuration and disposed between the first and the second portions. Trace layers each electrically connects one of the first contact pads to one of the second contact pads. The contact pins each penetrates through the second portion and electrically connects to one of the second pads, wherein the contact pins are arranged in a pin configuration compatible with the second pad configuration. | 04-14-2011 |
20110084721 | MANUFACTURING METHOD AND WAFER UNIT FOR TESTING - A manufacturing method of manufacturing a wafer unit for testing includes forming a plurality of test circuits on a circuit wafer, forming a plurality of circuit pads on a predetermined surface of a connecting wafer, forming a plurality of wafer pads on a rear surface of the connection wafer opposing the predetermined surface, forming a plurality of long via holes to electrically connect the plurality of circuit pads and the plurality of wafer pads, and forming the wafer unit for testing, by overlapping the circuit wafer and the connection wafer to electrically connect the plurality of test circuits and the plurality of circuit pads. | 04-14-2011 |
20110102008 | Socket For Testing Semiconductor Chip - A socket for testing a semiconductor chip includes a base cover, a conductive sheet, upper plungers, a housing, lower plungers and a support plate. The base cover has a coupling opening in the central portion thereof, and the conductive sheet is fitted into the coupling opening of the base cover and includes conductive parts and an insulation part. The upper plungers are seated onto upper ends of the conductive parts and come into contact with corresponding terminals of the semiconductor chip. The housing has insert holes at positions corresponding to the upper plungers and fastens the upper plungers to the corresponding conductive parts. The lower plungers are provided under lower ends of the conductive parts and come into contact with corresponding terminals of a PCB to electrically connect the conductive parts to the PCB. The support plate has holes at positions corresponding to the lower plungers and fastens the lower plungers to the lower ends of the corresponding conductive parts such that lower ends of the lower plungers protrude outside through the holes of the support plate. | 05-05-2011 |
20110102009 | TEST SOCKET ELECTRICAL CONNECTOR, AND METHOD FOR MANUFACTURING THE TEST SOCKET - A test socket, an electrical connector, and a method for manufacturing the test socket. In detail, the test socket for electrically connecting terminals of a semiconductor device to pads of a test apparatus includes: a housing having through-holes vertically extending to correspond in position to the terminals of the semiconductor device; contact pins disposed to correspond in position to the through-holes of the housing and contacting the terminals of the semiconductor device; and elastic members connected to the contact pins in the through-holes of the housing to contract and expand, wherein the elastic members are adhered to the contact pins by using an adhesive material. | 05-05-2011 |
20110121850 | SPRING STRUCTURE AND TEST SOCKET USING THEREOF - Spring assemblies and a test socket using the spring assemblies. The spring assemblies are used in a test socket electrically connecting lead terminals of a semiconductor chip to test terminals of a test device by contacting the lead terminals and the test terminals, and include: first springs in which a first steel wire having elasticity and conductivity is coiled in a spiral in one direction; and second springs in which a second steel wire having elasticity and conductivity is coiled in a spiral in an opposite direction to the direction in which the first springs are coiled, which have outer diameters narrower than inner diameters of the first springs, and are inserted into the first springs. Accordingly, electric resistances and inductances of two spring assemblies coiled in a spiral are reduced to improve electricity transmission characteristic. A height of a test socket is easily adjusted using spring assemblies having desired lengths. Also, since only plating is performed on the springs to form the spring assemblies, the spring assemblies are formed at a very low cost and have a wide range of applications. | 05-26-2011 |
20110156739 | TEST KIT FOR TESTING A CHIP SUBASSEMBLY AND A TESTING METHOD BY USING THE SAME - A test kit for testing a chip subassembly and a testing method by using the same is provided. The chip subassembly includes at least two stacked chips each having a number of electric contacts is provided. The test kit includes a test socket and a test plate. The test socket is configured to electrically engage the electric contacts on a first side of the chip subassembly. The test plate has at least a number of first probes configured for electrically engaging the electric contacts on a second side of the chip subassembly. At least one of the test socket and the test plate has a number of second probes for electrically connecting the test socket and the test plate. | 06-30-2011 |
20110187400 | SEMICONDUCTOR TEST APPARATUS AND TEST METHOD - In a semiconductor test apparatus, a first device is tested as a device under test in a state where the first device provided with a transmitter transmitting a signal and a second device provided with a receiver receiving the signal transmitted by the transmitter, are connected together. The transmitter includes an equalizer circuit that shapes the waveform of the differential signal to be transmitted. The receiver includes a latch circuit that latches data corresponding to the differential signal thus received with the use of a clock, the timing of which is variable. A control unit varies, in a matrix, a parameter of the equalizer circuit and an edge timing of the clock CLK supplied to the latch circuit. | 08-04-2011 |
20110193584 | UNIVERSAL MULTIPLEXING INTERFACE SYSTEM AND METHOD - A system for communicatively connecting devices for testing to respective test pins of a test head of an automatic test equipment (ATE). The system includes a tester interface device for communicative connection to the test pins of the ATE. The tester interface device includes a first connector and a second connector. The first connector is communicatively connected by the tester interface device to a first group of the test pins and the second connector is communicatively connected by the tester interface device to a second group of the test pins. The first group and the second group can be different test pins, same test pins, or combinations of some same and some different test pins. A first pogo pin block device of the system is communicatively connected to the first connector, and a second pogo pin block device communicatively connected to the second connector. A first device interface board (DIB) with test sockets for devices is communicatively connected to the first pogo pin block device, and a second device interface board with test sockets for same or other devices is communicatively connected to the second pogo pin block device. During testing, devices (DUTs) for testing are transferrable (by one or more handlers) to the respective test sockets of the first DIB and the second DIB for respective tests by the ATE, in accordance with test resources of the ATE provided via the first group of test pins or the second group of test pins, respectively. More than one handler can be multiplexed via the system, or more than one manipulator of a single handler can be multiplexed via the system. Conventional or unmodified DIBs can be employed for testing if the first pogo pin block and the second pogo pin block include conventional or applicable DIB connections. | 08-11-2011 |
20110193585 | CONVEYOR-BASED MEMORY-MODULE TESTER WITH ELEVATORS DISTRIBUTING MOVING TEST MOTHERBOARDS AMONG PARALLEL CONVEYORS FOR TESTING - A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns. | 08-11-2011 |
20110204914 | MUXING INTERFACE PLATFORM FOR MULTIPLEXED HANDLERS TO REDUCE INDEX TIME SYSTEM AND METHOD - A system for connecting a test pin of automatic test equipment (ATE) to devices for testing includes a first handler for manipulating a first portion and a second handler for manipulating a second portion of devices. A first wire connected to first socket(s) and a second wire connected to second socket(s) are connected to a relay connected to the test pin. The first handler connects first portion devices to the first socket. The second handler connects second portion devices to the second socket. A controller connects the first handler, second handler, and relay, for switching the relay to the first wire for testing in first socket if the first handler has connected any first portion device, and to the second wire for testing in second socket if the second handler has connected any second portion device. The controller multiplexes two handlers, or dual manipulators, asynchronously for immediate switch of testing. | 08-25-2011 |
20110227595 | INTERFACE MEMBER, TEST SECTION UNIT AND ELECTRONIC DEVICE HANDLING APPARATUS - An interface member | 09-22-2011 |
20110248737 | TEST APPARATUS AND CONNECTION DEVICE - It is an object to use an additional circuit to increase speed and functioning of an existing test apparatus at a low cost. Provided is a test apparatus that is connected to a socket board corresponding to a type of device under test and tests the device under test. The test apparatus comprises a test head including therein a test module that tests the device under test; a function board that is connected to the test module in the test head via a cable and also connected to the socket board; and an additional circuit that is loaded on the function board and connected to the test module and the device under test. | 10-13-2011 |
20110298486 | Parking Structure Memory-Module Tester that Moves Test Motherboards Along a Highway for Remote Loading/Unloading - A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors. | 12-08-2011 |
20110304349 | LATERAL COUPLING ENABLED TOPSIDE ONLY DUAL-SIDE TESTING OF TSV DIE ATTACHED TO PACKAGE SUBSTRATE - A method of topside only dual-side testing of an electronic assembly includes providing a singulated through substrate via (TSV) die flip chip attached to a die support including a package substrate. The TSVs on the TSV die extend from its frontside to contactable TSV tips on its bottomside. The TSVs on the frontside of the TSV die are coupled to embedded topside substrate pads on a top surface of the ML substrate. The die support includes lateral coupling paths between at least a portion of the embedded topside substrate pads and lateral topside pads on a topside surface of the die support lateral to the die area. The contactable TSV tips are contacted with probes to provide a first topside connection to the TSVs, and the lateral topside pads are contacted with probes to provide a second topside connection. Dual-side testing across the electronic assembly is performed using the first and second topside connections. | 12-15-2011 |
20120025860 | Burn-in socket and testing fixture using the same - A burn-in socket for carrying an electronic device to let the electronic device electrically connect to a circuit board via the burn-in socket is provided. The electronic device has a body and at least a lead. The burn-in socket comprises a frame and a carrier, the frame has an opening and a plurality of first aligning portions, wherein the opening fits onto the contour of the body, and the first aligning portions surrounds the opening. The carrier has a plurality of second aligning portions. The frame is assembled to the carrier with the conjunction of the first aligning portions and the second aligning portions. The body is capable of fitting into the opening to let the lead electrically connect to the circuit board via the carrier. | 02-02-2012 |
20120025861 | TEST SOCKET AND TEST DEVICE HAVING THE SAME - A test device is provided. The test device includes a first via which transmits a supply voltage, a second via which transmits a ground voltage, a test board including a plurality of test signal vias for transmitting a plurality of test signals, a capacitor disposed on an upper part of the test board and connected between the first via and the second via, and a test socket which electrically connects a device under test (DUT) with the test board. The test socket includes a first region including a flat lower surface bordering the test board, a second region including an uneven lower surface, a plurality of first contactors which are disposed in the first region and which are connected to the plurality of vias, and two second contactors which are disposed in the second region and which are connected to two terminals of the capacitor. | 02-02-2012 |
20120112780 | OPEN TOP BURN IN SOCKET - A test socket for an integrated circuit device includes a base for receiving the circuit device and a frame movable linearly toward and away from the base. Springs bias the frame away from the base. Device holders are movable substantially linearly on the frame between a closed position where the device holders are in proximity to one another and an open position where the device holders are remote from one another. Cams move the device holders between the open and closed positions in response to movement of the frame toward and away from the base. | 05-10-2012 |
20120146678 | TESTING IN TRAYS - Embodiments of the system and methods disclosed herein reduce the amount of handling necessary to organize the IC packages and thus may be utilized to increase the throughput of a test handler. To organize the IC packages, the IC packages may be initially placed on a first IC tray by the test handler. All of the IC packages are tested from the first IC tray so as to generate operational state data items for the IC packages. After all of the IC packages on the first IC tray are tested, the IC packages are sorted based on the operational state data items. In this manner, the operational state data items of the IC packages are known before sorting and thus not every IC package needs to be picked and placed in order to organize the IC packages. | 06-14-2012 |
20120182037 | IC DEVICE TESTING SOCKET - To provide an IC device testing socket, capable of improving signal transmission efficiency during testing an IC device, without deteriorating the replacement workability of contact pins. A substrate | 07-19-2012 |
20120229158 | APPARATUS FOR TESTING A SEMICONDUCTOR DEVICE AND METHOD OF TESTING A SEMICONDUCTOR DEVICE - An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals. | 09-13-2012 |
20120235700 | Device Retention for Test Socket - Structures and techniques for restraining devices for testing. Test sockets may retain devices under test using one or more retention members protruding from sidewalls of the test sockets. Retained devices may be oriented such that contact arms may traverse horizontally to access the devices to, for example, provide desired testing environments. Devices may be retained by forces applied by the retention members to the retained devices in response to displacement, such as compression or deformation, of the retention members caused by the retained devices. Retention of the devices may be achieved without the need for additional fasteners, claims, or adjustment. | 09-20-2012 |
20120242363 | Non-Linear Vertical Leaf Spring - An electrically conductive contact element can include a first base and a second base with elongate, spaced apart leaves between the bases. A first end of each leaf can be coupled to the first base and an opposite second end of the leaf can be coupled to the second base. A body of the leaf between the first end and the second end can be sufficiently elongate to respond to a force through said contact element substantially parallel with the first axis and the second axis by first compressing axially while said force is less than a buckling force and then bending while said force is greater than the buckling force. | 09-27-2012 |
20120249176 | TEST STRUCTURE AND MEASUREMENT METHOD THEREOF - A test structure including a substrate, at least one conductive plug, a first conductive trace and a second conductive trace is provided. The substrate has a first area and a second area. The at lest one conductive plug is disposed in the substrate in the first area, wherein the conductive plug does not penetrate through the substrate. | 10-04-2012 |
20120249177 | HANDLER TRAY, SYSTEM AND METHOD OF TESTING AN OBJECT INCLUDING THE SAME - A handler tray may include a tray body and a socket. The tray body may be configured to receive an object. The tray body with the object may be transferred to a test board. The tray body may be selectively interposed between the object and the test board to supply a test current from the test board to external terminals of the object. The socket may be formed on the tray body. The socket may electrically make contact with the external terminals of the object. Thus, a pick-up robot and an insert may be unnecessary, so that a test system and method of testing the object may have an optimally available space. | 10-04-2012 |
20120268155 | COMPLIANT PRINTED CIRCUIT SOCKET DIAGNOSTIC TOOL - Diagnostic tools for testing integrated circuit (IC) devices, and a method of making the same. The first diagnostic tool includes a first compliant printed circuit with a plurality of contact pads configured to form an electrical interconnect at a first interface between proximal ends of contact members in the socket and contact pads on a printed circuit board (PCB). A plurality of printed conductive traces electrically couple to a plurality of the contact pads on the first compliant printed circuit. A plurality of electrical devices are printed on the first compliant printed circuit at a location external to the first interface. The electrical devices are electrically coupled to the conductive traces and programmed to provide one or more of continuity testing at the first interface or functionality of the IC devices. A second diagnostic tool includes a second compliant printed circuit electrically coupled to a surrogate IC device. | 10-25-2012 |
20120280705 | TEST HEAD, TEST BOARD AND TEST APPARATUS - A test board can be inserted to a test head and removed from the test head while the connecting section for mounting thereon devices under test is mounted on the upper portion of the test head. A test head for retaining therein at least one test board for testing devices under test, includes: a casing provided with, on one side surface thereof, an opening through which the at least one test board is inserted and removed, the casing retaining therein the at least one test board with an upper side thereof oriented towards an upper surface of the casing; and a mounting member that guides a lower side of the at least one test board through the opening to a pre-set position, imposes an upward force to the lower side of the at least one test board, thereby mounting the at least one test board to the casing. | 11-08-2012 |
20120286818 | ASSEMBLY FOR OPTICAL BACKSIDE FAILURE ANALYSIS OF WIRE-BONDED DEVICE DURING ELECTRICAL TESTING - Systems, methods, devices, and computer program products are described for allowing optical backside failure analysis of a wire-bonded semiconductor device concurrent with electrical testing of the device. For example, a semiconductor device is prepared and mounted in the optical testing subsystem, such that a circuit region of the device is exposed to an optical testing environment, and an analog to the original array of the device is presented via the optical testing subsystem as a derived array. The electrical testing subsystem converts the derived array to a test array, and presents the test array in a way that is physically and electrically compatible with a test socket of an electrical testing environment. By coupling the electrical testing subsystem with the optical testing subsystem, a pin-to-pin coupling may be effectuated between the test array of the test socket and bonding locations on the device corresponding to the device's original array. | 11-15-2012 |
20120299614 | Test socket with a rapidly detachable electrical connection module - A test socket includes a test base and at least one electrical connection module. The at least one electrical connection module is detachably mounted in the test base and each one of the at least one electrical connection module has a frame and an electrically conducting element. The frame has a receiving hole for receiving and testing an IC. The electrically conducting element is detachably mounted on a bottom of the frame. After long time of use, the ineffective electrical connection module or electrically conducting element thereof can be rapidly and easily replaced with a new or an effective one by directly detaching the electrical connection module from the test base. Therefore, idle time or dead time of test apparatuses is shortened and test efficiency is enhanced. | 11-29-2012 |
20130009659 | PROBE CARD AND METHOD FOR TESTING MAGNETIC SENSORS - A probe card and method are provided for testing magnetic sensors at the wafer level. The probe card has one or more probe tips having a first pair of solenoid coils in parallel configuration on first opposed sides of each probe tip to supply a magnetic field in a first (X) direction, a second pair of solenoid coils in parallel configuration on second opposed sides of each probe tip to supply a magnetic field in a second (Y) direction orthogonal to the first direction, and an optional third solenoid coil enclosing or inscribing the first and second pair to supply a magnetic field in a third direction (Z) orthogonal to both the first and second directions. The first pair, second pair, and third coil are each symmetrical with a point on the probe tip array, the point being aligned with and positioned close to a magnetic sensor during test. | 01-10-2013 |
20130015874 | MUT FOR TESTING MEMORY MODULESAANM Yang; Yung-ChingAACI Taoyuan CountyAACO TWAAGP Yang; Yung-Ching Taoyuan County TW - An MUT unit for testing memory modules includes a first circuit board; a second circuit board coupled to the first circuit board in a vertical orientation; a socket on a top surface of the first circuit board; and a resilient member electrically connecting the first and second circuit boards at an joint there between, wherein the resilient member comprises a horizontal segment that is welded to a bottom surface of the first circuit board, a vertical segment that is welded to a surface of the second circuit board, and a curved buffer segment connecting the horizontal segment and the vertical segment. | 01-17-2013 |
20130021052 | Wafer prober integrated with full-wafer contacter - Methods and apparatus for testing unsingulated integrated circuits on a wafer include adapting a wafer prober for use with full-wafer-contacter disposed on the wafer. Some embodiments include placing wafer on a chuck of the prober, aligning the wafer to a full-wafer contacter incorporated in the wafer prober, removably attaching the wafer to the full wafer contacter, separating the wafer from the chuck, and making electrical contact to one or more integrated circuits of the wafer by making physical contact with a surface of the full-wafer contacter that faces away from the wafer. | 01-24-2013 |
20130069685 | INTEGRATED CIRCUIT TEST SOCKET HAVING TEST PROBE INSERTS - A test socket having a lid and a base with a cavity for receipt of an integrated circuit and removable test probe inserts having test probes positioned around a perimeter of the cavity. | 03-21-2013 |
20130106458 | HOLDER FOR MEASUREMENT AND MEASUREMENT APPARATUS | 05-02-2013 |
20130113513 | TEST APPARATUS OF SEMICONDUCTOR PACKAGE AND METHODS OF TESTING THE SEMICONDUCTOR PACKAGE USING THE SAME - A semiconductor package testing apparatus and testing a semiconductor package, the apparatus including a test circuit substrate that electrically tests a semiconductor package having connection terminals; a socket electrically connecting the test circuit substrate with the semiconductor package; a socket guide having an open region delimiting the socket; an insert that fixes the semiconductor package and positions the semiconductor package in the open region of the socket guide; a pusher that presses the semiconductor package to make contact between the socket and the semiconductor package; and an alignment part that aligns the semiconductor package with the open region, wherein the alignment part is configured to selectively apply a magnetic force to align keys of the semiconductor package, the align keys being formed of a magnetic material. | 05-09-2013 |
20130120013 | TEST CARRIER AND METHOD OF ASSEMBLY OF TEST CARRIER - A test carrier which enables a reduction of cost to be achieved. The test carrier | 05-16-2013 |
20130120014 | TEST CARRIER - A test carrier which can suppress the occurrence of contact defects and secure positional precision of the terminals is provided. | 05-16-2013 |
20130120015 | TEST CARRIER - A test carrier which can suppress the occurrence of contact defects and secure positional precision of the terminals is provided. | 05-16-2013 |
20130135002 | TEST ELECTRONICS TO DEVICE UNDER TEST INTERFACES, AND METHODS AND APPARATUS USING SAME - In one embodiment, an interface includes a plurality of test electronics to DUT interfaces. Each test electronics to DUT interface has at least one test electronics interface, at least one DUT interface, and an electrical coupling between the at least one test electronics interface and the at least one DUT interface. First and second subsets of the DUT interfaces are respectively positioned along the perimeters of first and second concentric shapes. | 05-30-2013 |
20130162279 | UNIVERSAL TEST SYSTEM FOR TESTING ELECTRICAL AND OPTICAL HOSTS - According to an example implementation, a universal tester includes a host interface slot connected to a first pluggable host card during an electrical test mode of operation to provide a stressed electrical signal to a host under test. The host interface slot is connected to a second pluggable host card during an optical test mode of operation, the second pluggable host card including an electrical-optical conversion block to convert a stressed electrical signal to a stressed optical signal that is provided to a host under test. A stressor generator may operation in pass-through mode or a loop-back mode. | 06-27-2013 |
20130200913 | Testing System with Test Trays - A test system may be provided in which devices under test are loaded into test trays and tested at a plurality of test stations. To test a device under test at a given test station, the test tray may be installed into a test fixture at the test station. Test equipment at each test station may communicate with the device under test via the test fixture and the test tray. Each test tray may have a spring-loaded corner portion that may be used to secure the device under test to the test tray. The test tray may have contacts that mate with corresponding contacts at each test fixture and may have a built in cable that connects to the device under test. The test fixture may have a detector that can detect whether or not a test tray is present on the test fixture. | 08-08-2013 |
20130214809 | SOCKET AND ELECTRONIC DEVICE TEST APPARATUS - A socket which enables occurrence of contact defects to be suppressed is provided. A socket | 08-22-2013 |
20130234748 | TRANSFERRING ELECTRONIC PROBE ASSEMBLIES TO SPACE TRANSFORMERS - Transferring electronic probe assemblies to space transformers. In accordance with a first method embodiment, a plurality of probes is formed in a sacrificial material on a sacrificial substrate via microelectromechanical systems (MEMS) processes. The tips of the plurality of probes are formed adjacent to the sacrificial substrate and the remaining structure of the plurality of probes extends outward from the sacrificial substrate. The sacrificial material comprising the plurality of probes is attached to a space transformer. The space transformer includes a plurality of contacts on one surface for contacting the plurality of probes at a probe pitch and a corresponding second plurality of contacts on another surface at a second pitch, larger than the probe pitch, wherein each of the second plurality of contacts is electrically coupled to a corresponding one of the plurality of probes. The sacrificial substrate is removed, and the sacrificial material is removed, leaving the plurality of probes intact. | 09-12-2013 |
20130257470 | SEMICONDUCTOR TESTING APPARATUS - A semiconductor testing apparatus is provided wherein components that must be arranged most closely are arranged most closely to terminals of a test object. The present apparatus is semiconductor testing apparatus comprising a printed circuit board, and a test socket mounted on an upper surface of the printed circuit board and forming a signal connection path between a test object and the printing circuit board, wherein a chip shaped capacitor is mounted on the upper surface of the printed circuit board, an interference avoidance space avoiding contact with the capacitor is formed in the test socket, the interference avoidance space being formed at a location facing the location where the capacitor is mounted, and the capacitor and the test socket being non-contacted from each other by the interference avoidance space. | 10-03-2013 |
20130285692 | TEST SOCKET INCLUDING ELECTRODE SUPPORTING PORTION AND METHOD OF MANUFACTURING TEST SOCKET - The test socket includes: an elastic conductive sheet including a conductive portion and an insulating supporting portion; a sheet type connector including an electrode portion that is disposed on the conductive portion and is formed of a metal, and a sheet member that supports the electrode portion, wherein the sheet member comprises a cut portion formed by cutting at least a portion of the sheet member between adjacent electrode portions; and an electrode supporting portion including an upper supporting portion that contacts an upper edge of the electrode portion to support the electrode portion and exposes an upper center portion of the electrode portion to be open and an electrode supporting portion including a connection supporting portion that connects the upper supporting portion and the insulating supporting portion. | 10-31-2013 |
20130293254 | TEST DEVICE FOR TESTING A POP STACKED-CHIP - A test device is provided for testing a bottom chip of a package-on-package (PoP) stacked-chip. An upper surface of the bottom chip has a plurality of soldering points for electrically connecting a plurality of corresponding soldering points of a top chip of the PoP stacked-chip. The test device includes a test head and a plurality of test contacts. The test head has the top chip installed inside. The plurality of test contacts is installed on a lower surface of the test head and electrically connected to the plurality of corresponding soldering points of the top chip inside the test head. When the lower surface of the test head contacts the upper surface of the bottom chip, the plurality of test contacts is electrically connected to the plurality of soldering points for testing the bottom chip. | 11-07-2013 |
20130307573 | TEST SYSTEM - A test system having a manipulation device and a test unit. The manipulation device has a receiving unit with a socket that accommodates a packaged integrated circuit, which has a top side and a bottom side. A plurality of electrical terminal contacts are formed on the bottom side. In a first state, the manipulation device provides the integrated circuit to the test unit, and during the first state the test unit is disposed above the top side of the integrated circuit and forms a connection with the manipulation device, and the test unit carries out a function test on the integrated circuit. A sensor device is formed on the top side, and the top side of the integrated circuit is oriented in a direction of the test unit and the electrical terminal contacts are electrically connected to the receiving unit of the manipulation device. | 11-21-2013 |
20140002123 | INSPECTION APPARATUS FOR SEMICONDUCTOR DEVICE | 01-02-2014 |
20140015559 | SOCKET FOR TESTING A SEMICONDUCTOR DEVICE AND TEST EQUIPMENT INCLUDING THE SAME - A test socket has a housing with an inlet configured to receive a substrate. A plurality of terminals are coupled to the housing, and a plurality of sliding pins are coupled to the terminals. The pins are configured to make contact with respective pads or terminals of the substrate to be tested. The pins have different lengths or positions to send and receive test signals. | 01-16-2014 |
20140035610 | SYSTEM AND METHOD TO TEST A SEMICONDUCTOR POWER SWITCH - Testing assembly for testing a singulated semiconductor die comprising a power component. The assembly comprises an current input connectable to a current source, for providing a current greater than 50 Amps to the power component; a signal output connectable to a signal analyzer, for receiving signals representing a sensed parameter of the power component sensed when the current is provided; a first contact unit, adapted to support the semiconductor die; a second contact unit, movably mounted relative to the first contact unit; and at least an electrically-conductive resilient sheath, adapted to be sandwiched between the semiconductor die and the second contact unit when the second contact unit is brought toward the semiconductor die during a test, the sheath forming part of an electrical path from the current input through at least a part of the die when thus sandwiched. | 02-06-2014 |
20140049281 | Diagnosis Framework to Shorten Yield Learning Cycles of Advanced Processes - The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA). | 02-20-2014 |
20140084954 | TESTING DEVICE FOR VALIDATING STACKED SEMICONDUCTOR DEVICES - Embodiments of the invention describe apparatuses, systems and method for utilizing testing instruments having electrical interconnects formed from High Density Interconnect (HDI) multi-layer substrates. Electrical signals may be routed between devices mounted on HDI substrates by way of conductive interconnects formed within their multiple layers. The conductive interconnects are generally comprised of metal interconnects and vias, where each via penetrates between layers to couple a metal interconnect from one layer to a metal interconnect from another layer. | 03-27-2014 |
20140111239 | LOCALIZED PRINTED CIRCUIT BOARD LAYER EXTENDER APPARATUS FOR RELIEVING LAYER CONGESTION NEAR HIGH PIN-COUNT DEVICES - A method and apparatus for a localized printed circuit board layer extender (LLX) is provided. The apparatus relieves layer routing congestion in and around high pin count integrated circuits. The method begins when a localized layer extender is provided that is compatible with the bottom-side pin-field of a device under test (DUT). The LLX is affixed to the bottom-side pin-field of the DUT. Test signals are then routed through the LLX as part of a test procedure. The apparatus includes: a LLX that substantially matches the pin-field of a bottom side of a DUT; a LLX base; and a LLX debug interface. | 04-24-2014 |
20140159761 | TEST DEVICE FOR COMPUTER INTERFACES - A test device includes a circuit board with a connector, a test socket, a contact arm, and a number of signal lines. A first end of the contact arm is rotatably mounted on the circuit board and electrically connected to the test socket. A first end of the signal line is electrically connected to the connector. A second end of the signal line is fixed on the circuit board. The contact arm can be rotated to make a second end of the contact arm contact the second end of one of the signal lines. | 06-12-2014 |
20140167804 | ASSEMBLY FOR OPTICAL BACKSIDE FAILURE ANALYSIS OF FLIP-CHIPS DURING ELECTRICAL TESTING - A method and apparatus for testing a digital device. An apparatus for facilitating testing a digital device comprises a flat-top socket and a flat-top carrier board. The flat-top socket has a recess for accepting a carrier board, the recess having electrical contacts disposed in a pattern matching a pattern on a digital device. The flat-top carrier board also has a pattern of electrical contacts that match those on a digital device. A further embodiment provides an apparatus for facilitating testing of a digital device. The apparatus includes a digital device electrically and mechanically attached to a flip-chip carrier and also includes a flip-chip socket having an interface for connecting with the flip-chip carrier and an existing socket. | 06-19-2014 |
20140167805 | REDUCED FOOTPRINT TEST SOCKET SYSTEM - A test socket system has a housing with a screw that extends through central openings in the housing and a pusher block. Positioned below the pusher block is an integrated circuit and positioned below the integrated circuit is a contact set. The contact set is slidably received within slots on the inner surface of side walls of the housing. Positioned below the contact set is a PC adapter which is connected to a motherboard. The PC adapter has holes that receive dowels that extend downwardly from the bottom edge of the side walls of the housing. This system allows for easy and quick attachment of integrated circuits to a motherboard for testing purposes. | 06-19-2014 |
20140167806 | SEMICONDUCTOR DEVICE TESTING APPARATUS - Provided is a semiconductor device testing apparatus including a first socket configured to load a package, on which a semiconductor device to be tested may be mounted, and a second socket coupled to the first socket. The first socket may include an upper part including a hole configured to accommodate the package and a terminal pad provided at both side edges of the hole to hold input and output terminals of the package, and a lower part including a heating room, in which a heater and a temperature sensing part may be provided, the heater being configured to heat the semiconductor device and the temperature sensing part being configured to measure temperature of the semiconductor device. The second socket may include a probe card with a pattern that may be configured to receive test signals from an external power source. | 06-19-2014 |
20140203833 | CONNECTOR / CABLE ASSEMBLY - A high voltage connector assembly includes a plurality of pin assemblies, each of the plurality of pin assemblies having a first end and a second end. The first end of each of the plurality of pin assemblies is configured to releasably electrically engage a load board. A plurality of pin pads, wherein the second end of each of the plurality of pin assemblies is configured to electrically engage a pin pad included within the plurality of pin pads. A plurality of connector pads are electrically coupled to the plurality of pin pads, wherein each of the plurality of connector pads is configured to be electrically coupled to a wire-based conductor included within a plurality of wire-based conductors. A potting compound is configured to encapsulate the plurality of connector pads. | 07-24-2014 |
20140218063 | PARALLEL CONCURRENT TEST SYSTEM AND METHOD - A parallel concurrent test (PCT) system is provided for performing the parallel concurrent testing of semiconductor devices. The PCT system includes a pick and place (PnP) handler for engaging and transporting the semiconductor devices along a testing plane, the PnP handler including at least one manipulator. The PCT system also includes a device under test interface board (DIB), the DIB including a broadside test socket for broadside (BS) testing of the semiconductor devices, the broadside testing using at least half of a total number of a semiconductor device pins, and a plurality of design-for-test (DFT) test sockets for DFT testing, the DFT testing using less than half of the total number of the semiconductor device pins, and a tester in electrical contact with the DIB for testing the semiconductor devices in accordance with a stepping pattern test protocol. | 08-07-2014 |
20140266281 | TESTING HOLDERS FOR CHIP UNIT AND DIE PACKAGE - A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body. | 09-18-2014 |
20140285228 | TESTING APPARATUS FOR PROVIDING PER PIN LEVEL SETTING - A testing apparatus for providing per pin level setting is disclosed, and the testing apparatus includes a control unit and a filter circuit, where the control unit is electrically connected to the filter circuit. The control unit includes a field programmable gate array (FPGA) for providing a PWM signal. The filter circuit receives the PWM signal and outputs at least one DC voltage. | 09-25-2014 |
20140327462 | TEST SOCKET PROVIDING MECHANICAL STABILIZATION FOR POGO PIN CONNECTIONS - A test socket for electrically connecting a device under test (DUT) to an electrical signal source comprises a plurality of pogo pins spaced apart from each other, a stabilizing plate supporting the plurality of pogo pins, a plurality of conductive lines passing through the stabilizing plate and configured to electrically connect the electrical signal source to the pogo pins, and at least one inner stabilizer disposed in the stabilizing plate between the conductive lines and configured to apply an elastic force toward the DUT where the DUT is brought into contact with the pogo pins. | 11-06-2014 |
20140333339 | BOARD, INTEGRATED CIRCUIT TESTING ARRANGEMENT, AND METHOD FOR OPERATING AN INTEGRATED CIRCUIT - A board may include a first set of board contact pads arranged on a first side of the board, the pads configured to connect to circuit pads of a circuit under test, the positions of the pads matching to the positions of the circuit pads; a fan-out region on the first side of the board including fan-out contact pads configured to at least one of receive a test signal and provide a measurement signal; at least one contact pad connecting to at least one pad of the first set of board pads; and a second set of board contact pads on a second side of the board, the second set of board pads configured to connect to test board pads of a test board; positions of the pads matching to the positions of the test board pads; a pad connecting to a pad of the first set of board pads. | 11-13-2014 |
20140340107 | BGA TEST SOCKET - For testing a high density BGA package, a central pressure block is designed to press against the chip of the package during test in a test socket. High density socket probe causes high pressure against the package, especially the area under the chip. With the central pressure block of the present invention, the high density BGA package is prevented from deformation because the central pressure block pressing downward against the chip, which balances the pressure coming upward from the high density socket probes under the circuit board in the area under the chip. | 11-20-2014 |
20140354321 | AUTOMATED TEST MANAGEMENT SYSTEM FOR ELECTRONIC CONTROL MODULE - An automatable management system for testing one or more electronic control modules (ECMs), in one or more machines, is disclosed. The one or more ECMs are switchably connected to a testing unit (TU). The system includes at least one ECM connector, connectable to the one or more ECMs. The at least one ECM connector is one of a male connector or a female connector. Similarly, the system includes at least one TU connector connectable with the TU. Further, at least one actuator is operably connectable to at least one of the at least one ECM connector and the at least one TU connector. The actuator is configured to facilitate an electrical connection between the ECM and the testing unit in response to a relay signal generated by the testing unit. | 12-04-2014 |
20150015293 | On-Center Electrically Conductive Pins For Integrated Testing - A structure and method for providing a contact pin between a device under test (DUT) and a load board which provides upper and lower contact point which are axial aligned is disclosed. The pin has an upper ( | 01-15-2015 |
20150015294 | Test Socket With Hook-Like Pin Contact Edge - The present invention provides a test socket adaptable for testing different Integrated Circuit (IC) pad size during an IC testing. The test socket comprising a molded socket having an inner space and a plurality of through-apertures disposed on its surface; and a plurality of contact elements disposed within the inner space of the molded socket, each contact element has a pin contact edge and a pin-end; wherein each pin contact edge extends through the through-apertures of the molded socket; wherein each pin contact edge provides a linear surface area for contact with the DUT's lead; and wherein each pin contact edge provides a large contact area for various DUT's lead size. | 01-15-2015 |
20150061717 | TEST CARRIER, DEFECT DETERMINATION APPARATUS, AND DEFECT DETERMINATION METHOD - A test carrier that temporarily accommodates a die includes: a first wiring pattern that electrically connects an external terminal of the test carrier and a TSV of the die; and a second wiring pattern that electrically connects the TSVs. | 03-05-2015 |
20150070041 | TEST INTERFACE BOARD AND TEST SYSTEM INCLUDING THE SAME - A test interface board includes a substrate including a power plane electrically connected to at least one power terminal of a semiconductor device under test, and a ground plane electrically connected to at least one ground terminal of the semiconductor device under test, and a voltage regulator arranged on the substrate and configured to supply, via the power plane and the ground plane, to the semiconductor device under test, a driving voltage. | 03-12-2015 |
20150091600 | PERFORMANCE ENHANCED SEMICONDUCTOR SOCKET - A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer. | 04-02-2015 |
20150097591 | DEVICE FOR MEASURING ELECTRONIC COMPONENTS - A device for measuring electronic components having a plurality of conductors applied to a dielectric cable carrier, which conductors are each connected both to a contact finger and to a connection contact, such that a switch is integrated in at least one of the conductors, via which the conductor can be additionally connected to a ground connection. | 04-09-2015 |
20150130493 | ELECTRONIC DEVICE TESTING APPARATUS, ELECTRONIC DEVICE HOUSING APPARATUS, ELECTRONIC DEVICE RETRIEVING APPARATUS, AND ELECTRONIC DEVICE TESTING METHOD - An electronic device testing apparatus includes a housing unit which disassembles an empty test carrier and assembles the test carrier while housing an untested die in the test carrier, a test unit which tests the die housed in the test carrier, and a retrieving unit which disassembles the test carrier, retrieves the tested die from the test carrier, and reassembles the empty test carrier. | 05-14-2015 |
20150130494 | TEST CARRIER - A test carrier includes a base member and a cover member. The base member includes a multi-layer board including a wiring line that is electrically connected to a die and a base film that supports the multi-layer board. The cover member includes a frame-shaped cover frame having an opening formed therein. The size of the multi-layer board is larger than the size of the die and is smaller than the size of the opening in a direction along a surface that is opposite to the die. | 05-14-2015 |
20150130495 | Assembly For Testing Semiconductor Devices - A testing assembly for testing a plurality of semiconductor devices comprising a carrier assembly adapted to hold the plurality of semiconductor devices at predetermined locations therein that is operably connectable with a plurality of different socket assemblies. A universal socket assembly is also described. | 05-14-2015 |
20150130496 | Method For Testing Semiconductor Devices - A method of testing semiconductor devices includes placing a plurality of semiconductor devices in a carrier assembly and performing at least one testing operation on the plurality of semiconductor devices while they remain inside the carrier assembly. | 05-14-2015 |
20150130497 | Electrical Test Socket - Provided is an electrical test socket that is arranged between a terminal of a test target device and a pad of test equipment in order to electrically connect the terminal and the pad, the electrical test socket including: a socket body including a central hole at a center thereof in order to house the test target device inside; a pin connection member comprising a plurality of conductive pins that are arranged on locations corresponding to the terminal of the test target device housed in the central hole of the socket body, and whose upper end contacts the terminal of the test target device, and a housing having penetration holes into which the conductive pins are inserted to support the conductive pins; and a sheet-type connection member in which a plurality of conductive parts are arranged on locations corresponding to the conductive pins, wherein the plurality of conductive parts are arranged on a bottom portion of the pin connection member, exhibit conductivity only in a thickness direction, and are elastically deformed in the thickness direction, wherein the conductive pins have a rectangular pillar shape. | 05-14-2015 |
20150137847 | TEST PLATFORM - A test platform includes a base, a supporting member rotatably supported on the base, a laser emitter mounted on the base, and a laser receiver mounted to the supporting member and aligning with the laser emitter. The supporting member includes a network socket electrically connected to the laser receiver. The laser emitter is electrically connected to a network communication device. | 05-21-2015 |
20150145547 | PROBE APPARATUS AND WAFER MOUNTING TABLE FOR PROBE APPARATUS - A probe apparatus includes a card clamp unit detachably supporting a probe card; and a wafer mounting table adsorbing the semiconductor wafer and bringing electrodes on the semiconductor wafer into contact with the probes. In order to mount the semiconductor wafer including an annular portion protruding from a rear surface of an outer peripheral portion and a thin portion having a thickness smaller than the annular portion, the wafer mounting table includes a planar portion on which the thin portion is mounted; and a step-shaped portion which is formed at an edge of the planar portion and mounts the annular portion thereon. Multiple circular vacuum chuck grooves are concentrically formed in the planar portion, and at least some of the vacuum chuck grooves are connected to multiple vacuum paths through which vacuum evacuation is performed at multiple positions separated from each other by 90° or more along a circumferential direction. | 05-28-2015 |
20150293147 | TEST SOCKET HAVING HIGH-DENSITY CONDUCTIVE UNIT, AND METHOD FOR MANUFACTURING SAME - The present invention relates to a test socket having a high-density conductive unit, and to a method for manufacturing same, whereby an elastic conductive sheet is arranged at a position corresponding to the terminal of the device, and includes a first conductive unit arranged in the thickness direction of an elastic material and an insulating support unit for supporting the first conductive unit. A support sheet is attached to the elastic conductive sheet and has through-holes corresponding to the terminal of the device. A second conductive unit is arranged in the through-holes of the support sheet in the thickness direction in an elastic material. | 10-15-2015 |
20150331012 | SEMICONDUCTOR PACKAGE TESTING APPARATUS - A semiconductor package testing apparatus comprises a package holder for holding a semiconductor package and which is positionable together with the semiconductor package at a test contactor station. There are probe pins located at the test contactor station for contacting a bottom surface of the semiconductor package and which are configured to apply an upwards force on the semiconductor package during testing of the semiconductor package. A restraining mechanism that is movable from a first position remote from the package holder and a second position over the package holder is configured to restrict lifting of the semiconductor package by the probe pins during testing of the semiconductor package when the restraining mechanism is at its second position. | 11-19-2015 |
20150331013 | Multi-Channel Probe Plate for Semiconductor Package Test Systems - A test apparatus includes a multi-channel probe plate having an electrically insulating body with opposing first and second main surfaces, and a plurality of spaced apart electrically conductive coupling regions embedded in or attached to the body at the first main surface. Each of the electrically conductive coupling regions is configured to cover a different zone of a semiconductor package when the semiconductor package is positioned in close proximity to the first main surface of the plate. The test apparatus further includes circuitry electrically connected to each of the coupling regions of the probe plate via a different channel. The circuitry is operable to measure a parameter indicative of the degree of capacitive coupling between each electrically conductive coupling region of the probe plate and the zone of the semiconductor package covered by the corresponding electrically conductive coupling region. | 11-19-2015 |
20150355229 | UNIVERSAL TEST FLOOR SYSTEM - In an embodiment, a universal test floor system includes a first robot that is configured to pack a plurality of universal test containers each including similar dimensions into a universal bin. Each universal test container is configured to enclose each of a plurality of different devices to test. The universal test floor system includes a universal conveyor configured to transport the universal bin. The first robot is configured to put the universal bin onto the universal conveyor and a second robot is configured to remove it. A universal test cell system is configured to receive the universal bin. The universal test cell system includes a plurality of test slots configured to receive a plurality of universal test containers. The universal test cell system is configured to test the plurality of different devices while each is located within one of the plurality of universal test containers. | 12-10-2015 |
20150355233 | TEST SOCKET AND SOCKET BODY - The present invention relates to a test socket, and more specifically, to a test socket for electrically connecting a terminal of a test target device with a pad of a test device, comprising: a socket guide provided with a center hole at the center thereof so as to enable the terminal of the test target device to pass through and a guide protrusion provided to the lower surface thereof; and a socket body arranged between the socket guide and the test device, wherein the socket body comprises: a conductive region provided with a connection part arranged at a location corresponding to the terminal of the test target device so as to electrically connect the terminal of the test target device with the pad of the test device; and a supporting region for extending from a circumference of the conductive region and supporting the conductive region, and the supporting region comprises: a guide hole for receiving the guide protrusion so as to determine the location of the socket body with respect to the test device, and an elastic pressing part for elastically pressing the guide protrusion stored in the guide hole to one inner side surface of the guide hole. | 12-10-2015 |
20150355234 | PACKAGED DEVICE ADAPTER WITH PARAMETER INDICATION - An adapter apparatus and method includes using an adapter body defining a socket cavity configured to receive a packaged device and a socket lid assembly configured to apply a force upon a packaged device received in the socket cavity of the adapter body. A measurement apparatus associated with the socket lid assembly may include a measurement element (e.g., temperature sensing element, compressible element, etc.) that is configured to contact a packaged device received in the socket cavity when the socket lid assembly closes the socket cavity and applies a force upon the packaged device (e.g., a measurement signal is generated with use of the measurement element that is configured to contact the packaged device). An indicator may be configured to display a parameter based on the measurement signal (e.g., a count, a temperature, etc.). | 12-10-2015 |
20150377923 | TEST SOCKET WITH HIGH DENSITY CONDUCTION SECTION - Provided is a test socket having high-density conduction sections. The test socket is configured to be disposed between a device to be tested and a test apparatus for electrically connecting terminals of the device and pads of the test apparatus. The test socket includes: an elastic conductive sheet including first conduction sections and an insulative support section, the first conduction sections being disposed at positions corresponding to the terminals of the device and formed by arranging a plurality of first conductive particles in an elastic material in a thickness direction of the first conduction sections, the insulative support section supporting the first conduction sections and insulating the first conduction sections from each other; a support sheet attached to a top surface of the elastic conductive sheet and including penetration holes at positions corresponding to the terminals of the device; and second conduction sections disposed in the penetration holes of the support sheet and formed by arranging a plurality of second conductive particles in an elastic material in a thickness direction of the second conduction sections. The second conductive particles are arranged more densely than the first conductive particles, and the penetration holes have an upper diameter that is greater than a lower diameter thereof. | 12-31-2015 |
20150377924 | SOCKET DEVICE FOR TESTING SEMICONDUCTOR DEVICE - The present invention relates to a socket device for testing a semiconductor device. More particularly, the present invention relates to a socket device that is capable of testing ball grid array (BGA) and land grid array (LGA) type semiconductor devices, or BGA/LGA hybrid semiconductor devices according to the shapes of leads of the semiconductor devices. A latch structure for pressing and holding a semiconductor device is improved such that a roller is provided at the front end of a latch so as to minimize wear caused by friction with a sandpaper-like surface on an upper surface of the semiconductor device, even in the case of approximately one hundred thousand or more rounds of testing, thereby remarkably extending the life of the socket device, increasing testing efficiency, and reducing costs. | 12-31-2015 |
20160003869 | TEST CARRIER - A test carrier includes a base member on which a first electronic device under test is able to be temporarily mounted, and a second electronic device which is configured to be used to test the first electronic device. The second electronic device is mounted on the base member, and the second electronic device is able to be electrically connected to the first electronic device. | 01-07-2016 |
20160025775 | ELECTRICAL CONNECTOR AND CONTACTS THEREOF - An electric contact used to electrically connecting an IC socket to a PCB, comprises an upper contact, a lower contact and an elastic member between them. The upper contact comprises a first connecting portion to be connected to the IC socket and a first contacting portion with less length than the first connecting portion. The lower contact comprises a second connecting portion and a second contacting portion connecting with the second connecting portion. The second connecting portion includes an expanding portion adjacent to the second contacting portion. The second contacting portion forms a receiving space for the first contacting portion. The first connecting portion also defines a protruding portion projecting along a thickness direction. | 01-28-2016 |
20160061861 | TEST SOCKET FOR SEMICONDUCTOR DEVICE AND TEST DEVICE INCLUDING THE SAME - Provided are a test socket for a semiconductor device and a test device including the test socket. The test device includes a test socket including terminals arranged in a two-dimensional array and corresponding to terminals of the semiconductor device and a ground line extending along at least one row of two-dimensional array; and a substrate electrically connected to the test socket so as to transmit and receive a test signal. The test socket includes a ground line extending along at least one row of the two-dimensional array. | 03-03-2016 |
20160084880 | INTEGRATED STRIKE PLATE SOCKET - An apparatus and method for facilitating testing of an electronic device is provided. The apparatus includes a strike plate with an integrated socket. Alignment dowels are located on an outside rim of the integrated strike plate and socket. Shims are located in a recess in the outside rim of the integrated strike plate and socket and may be used to adjust the height of the assembly to facilitate handling by an automated test handler. The apparatus further includes a memory nest assembly having a receptacle for retaining an electronic device to be tested. In addition, the memory nest assembly is formed to mate with the socket on the integrated strike plate. | 03-24-2016 |
20160103152 | TESTING APPARATUS - A test apparatus for testing a first flash memory chip is provided. The testing apparatus includes: an interface printed circuit board (PCB), a separate PCB, and a socket device. The separate PCB is disposed over the interface PCB, and a second flash chip is placed between the interface PCB and the separate PCB. The second flash memory chip includes a first embedded flash chip and a dynamic random access memory (DRAM), and the second flash memory chip is connected to the interface PCB through corresponding first pins of the DRAM. The socket device is disposed over the separate PCB and is configured to install the first flash memory chip. The first flash memory chip is connected to the interface PCB through corresponding second pins. | 04-14-2016 |
20160109480 | TEST SOCKET FOR TESTING SEMICONDUCTOR CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A test socket is provided that includes a base material including an insulating elastic material and a conductive portion extending through the base material in a thickness direction of the base material, wherein the conductive portion includes a plurality of conductive particle structures arranged in the thickness direction of the base material, and each of the plurality of conductive particle structures includes a plurality of conductive particles having at least one insulating wire and/or at least one conductive wire extending from a surface of the conductive particle, bonded with a material having a functional group. | 04-21-2016 |
20160124042 | ADAPTOR STRUCTURE AND APPARATUS FOR TESTING A SEMICONDUCTOR PACKAGE INCLUDING THE SAME - An adaptor structure includes a main adaptor, a first sub-adaptor, a second sub-adaptor and a first driving mechanism. The main adaptor is over a socket. The main adaptor has an opening. The first sub-adaptor is movably received in the opening of the main adaptor in a first direction. The first sub-adaptor is configured to support a first side surface of the semiconductor package. The second sub-adaptor is movably received in the opening of the main adaptor in the first direction and a second direction. The second sub-adaptor faces the first sub-adaptor to support a second side surface of the semiconductor package. The first driving mechanism is configured to move the second sub-adaptor in the second direction. Thus, the adaptor structure can guide the semiconductor packages having different sizes to the socket. | 05-05-2016 |
20160163631 | CHIP CARRIER WITH DUAL-SIDED CHIP ACCESS AND A METHOD FOR TESTING A CHIP USING THE CHIP CARRIER - Disclosed are chip carriers and methods of using them. The chip carriers each comprise a base with a first surface, a second surface opposite the first surface, and wire bond pads on the first and second surfaces. The first surface also has a chip attach area with opening(s) that extends from the first surface to the second surface. A chip can be attached to the chip attach area and, because of the opening(s), wire bond pads on opposite sides (e.g., on the top and bottom) of the chip are accessible for testing. That is, wire bond pads on the first surface can be electrically connected to one side of the chip (e.g., to the top of the chip) and/or wire bond pads on the second surface can be electrically connected through the opening(s) to the opposite side of the chip (e.g., to the bottom of the chip). | 06-09-2016 |
20160377652 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method which enables high quality semiconductor device testing. The method includes the following steps : providing a test board in which a plurality of IC sockets mounted on the front surface and a plurality of surface mount relay sockets to be electrically coupled to the IC sockets are mounted on the back surface; and placing semiconductor devices in the IC sockets and performing a test on the semiconductor devices with relays attached to the relay sockets. The IC socket and the test board are electrically coupled by a plurality of coupling terminals provided in an area for the IC socket in a plan view, and some of the electronic component sockets are mounted in a manner to overlap some of the IC sockets in a plan view. | 12-29-2016 |