| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 324755030 | Rigid | 8 |
| 20110043233 | WAFER LEVEL CONTACTOR - A probe card assembly can include a plurality of probes disposed on a substrate and arranged to contact terminals of a semiconductor wafer. Switches can be disposed on the probe card assembly and provide for selective connection and disconnection of the probes from electrical interconnections on the probe card assembly. | 02-24-2011 |
| 20120081140 | PROBE CARD - Provided is a probe card which has a space transformer which may be effectively changed to correspond to a change in wafer chip structure and is capable of maximizing acceptable channels of the space transformer. The probe card for testing a semiconductor chip on a wafer includes: a space transformer body in which a plurality of unit probe modules are arranged at intervals; a main circuit board to which an electrical signal is applied from an external test device; a reinforcement plate for supporting the main circuit board such that the unit probe modules become stable against an external effect; a standing conductive medium which is inserted into a penetration portion provided in the space transformer body; a lower surface circuit board in which the standing conductive medium is electrically connected to the unit probe module as a flexible conductive medium and the standing conductive media are mounted; and a mutual connection member for electrically connecting the lower surface circuit board to the main circuit board. | 04-05-2012 |
| 20130069683 | TEST PROBE CARD - A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining | 03-21-2013 |
| 20140347085 | TEST PROBE CARD - A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining. | 11-27-2014 |
| 20150331014 | SOLDER BUMP ARRAY PROBE TIP STRUCTURE FOR LASER CLEANING - A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package. | 11-19-2015 |
| 20150377954 | Method for Testing Semiconductor Dies and a Test Apparatus - A method includes: providing a test apparatus; providing an electrically conductive carrier; providing a semiconductor substrate having a first main face, a second main face opposite to the first main face, and a plurality of semiconductor dies, the semiconductor dies including a first contact element on the first main face and a second contact element on the second main face; placing the semiconductor substrate on the carrier with the second main face facing the carrier; electrically connecting the carrier to a contact location disposed on the first main face; and testing a semiconductor die by electrically connecting the test apparatus with the first contact element of the semiconductor die and the contact location. | 12-31-2015 |
| 20160084876 | TEST PROBE SUBSTRATE - A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques. | 03-24-2016 |
| 20160252547 | PROBE PIN AND METHOD FOR PRODUCING A PROBE PIN | 09-01-2016 |
