| Entries |
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| 20080244367 | NON-VOLATILE MEMORY WITH GUIDED SIMULATED ANNEALING ERROR CORRECTION CONTROL - Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility during the iterative decoding that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable. | 10-02-2008 |
| 20080244368 | Guided Simulated Annealing in Non-Volatile Memory Error Correction Control - Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage elements. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Simulated annealing using an adjustable temperature parameter based on a level of error in the data read from the system can be performed to assist the iterative decoding process. The simulated annealing can introduce randomness, as noise for example, into the metric based decoding process. Moreover, knowledge of the device characteristics can be used to guide the simulated annealing process rather than introducing absolute randomness. The introduction of a degree of randomness adds flexibility during the iterative decoding that permits possible faster convergence times and convergence in situations where data may otherwise be uncorrectable. | 10-02-2008 |
| 20080244369 | REGISTER READ MECHANISM - Integrated circuits have expanded a set of custom registers and a read mechanism for control registers. One embodiment includes a circuit having a first set of registers; a second set of registers to be written via one or more write operations addressed to one or more registers of the first set; and a read controller coupled with the first and second sets of registers, the read controller to selectively output a portion of data stored in the first and second sets of registers based on data stored in one or more registers of the second set. In one embodiment, the circuit further includes a logic block; and a multiplexer to select from an output of the logic block and an output of the read controller as an output of the circuit based on the data stored in the one or more registers of the second set. | 10-02-2008 |
| 20080270876 | Decoding Apparatus, Decoding Method, and Decoding Program - A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory. | 10-30-2008 |
| 20080276155 | METHOD OF DETECTING AND ISOLATING FAULT IN REDUNDANT SENSORS, AND METHOD OF ACCOMMODATING FAULT IN REDUNDANT SENSORS USING THE SAME - Provided are a method of detecting and isolating fault in sensors and a method of accommodating fault in sensors using the same. In the method of detecting and isolating fault in sensors, a one reduced-order parity vector is obtained by excluding the output of one sensor selected from n sensors, a two reduced-order parity vector is obtained by excluding output of two sensors selected from the n sensors, and when there are a plurality of parity vectors obtained at plural points of time, one reduced-order parity vectors are averaged to obtain an averaged one reduced-order parity vector and likewise, two reduced-order parity vectors are averaged to obtain an averaged two reduced-order parity vector. Therefore, a decrease in fault detection and isolation (FDI) performance can be hindered, and even when double faults occur, sensors to be excluded can be selected. Thus, a system including sensors has high reliability and high accuracy. | 11-06-2008 |
| 20080294967 | Incremental Redundancy Coding System - In packet digital communications using a two way communications medium such as wireless each received packet is subject to noise and/or interference which causes errors in some of the received symbols. A common method known as Incremental Redundancy (IR), Hybrid Automatic Repeat Request (HARQ) for corrects these transmission errors by using error detection in conjunction with transmission of additional redundant symbols forming a sequence of forward error correcting codes. Any residual errors are detected by means of a Cyclic Redundancy Check (CRC). The CRC symbols represent transmission overhead and degrade the throughput regardless of the quality of the transmission channel. This invention is concerned with providing error detection without the need for a CRC thereby improving the throughput. In a further embodiment of the invention for those systems that employ a CRC increased reliability of detection is provided which also leads to an improvement in throughput. It is shown that by adjustment of a simple threshold value, the overall packet error rate may be traded off against throughput in a flexible manner. A method of construction of a sequence of codes from a nested block code is described and an example is provided based on a nested block code of length 128. The associated performance graphs of the invention, both using and not using a CRC, for this sequence of codes are given showing the performance improvements of the invention compared to the standard arrangement using a CRC for the same sequence of error correcting codes. | 11-27-2008 |
| 20080307294 | Efficient implementation to perform iterative decoding with large iteration counts - Systems and methods are presented to improve the performance of a constant bit rate iterative decoder by providing elastic buffering, while utilizing a relatively simple decoder architecture capable of maintaining a fixed number of iterations of a lower value. An LDPC decoder can be designed, for example, to support less than the maximum possible number of iterations, and can, for example, be mated to elastic input and output buffers. If a given code block, or succession of code blocks, requires the maximum number of iterations for decoding, the decoder can, for example, run at such maximum number of iterations and the elastic input buffer can, for example, hold code blocks waiting to be processed so as to maintain a constant input rate. Alternatively, if one or more code blocks requires less than the nominal number of iterations, the output buffer can store those code blocks so as to preserve a constant output rate. It is emphasized that this abstract is provided to comply with the rules requiring an abstract, and is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims. | 12-11-2008 |
| 20090024909 | TURBO CODING HAVING COMBINED TURBO DE-PADDING AND RATE MATCHING DE-PADDING - Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding. One or more of the 3 outputs from the turbo encoding module (e.g., systematic bits, parity 1 bits, and parity 2 bits) may then undergo dummy bit padding as well. Thereafter, these 3 streams (some or all of which may have undergone dummy bit padding) undergo sub-block interleaving. After all of these operations have taken place, a singular combined de-padding module that can be employed to perform de-padding any zero padded bits and any dummy padded bits from each of the three streams that have undergone the sub-block interleaving. | 01-22-2009 |
| 20090031199 | FILE DOWNLOAD AND STREAMING SYSTEM - A method of encoding data operates on an ordered set of input symbols and includes generating redundant symbols from the input symbols, and includes generating output symbols from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols. The redundant symbols are generated from an ordered set of input symbols in a deterministic process such that a first set of static symbols calculated using a first input symbol has a low common membership with a second set of static symbols calculated using a second input symbol distinct from the first input symbol. | 01-29-2009 |
| 20090037799 | OPERATING METHOD APPLIED TO LOW DENSITY PARITY CHECK (LDPC) DECODER AND CIRCUIT THEREOF - An operating method applied to low density parity check (LDPC) decoders and the circuit thereof are proposed, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the different between the newly generated check messages and the previously check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. In the other way, the required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced. | 02-05-2009 |
| 20090044087 | Data Slicer Having An Error Correction Device - A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes. | 02-12-2009 |
| 20090063941 | METHOD AND SYSTEM FOR USING REDUNDANCY TO EXCHANGE DATA IN A MULTICAST OR ONE WAY ENVIRONMENT - A system for use in one-way communications takes data from a source and parses it into work units. The work units may have a fixed size. The data of the work units is given to a redundant array of independent disks (RAID) library. The RAID library applies parity to the data and produces a number of output streams. Each stream includes data from the work units and redundant data from the parity application. The streams are combined and sent over a network. The inverse parity is applied on the receiving side to recreate the data. The redundant data is used in place of any data having an error condition, such as being lost or corrupted. The data is reconstructed on the receiving end without the need to resend data. | 03-05-2009 |
| 20090089650 | CACHE FUNCTION OVERLOADING - A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit, corresponding to the sub-portion, in the cache line with a second parameter that indicates an action to perform when the first parameter indicates that parity generation and checking is disabled, passing the at least one set parity bit with the sub-portion to a processor for processing, and performing the action when the sub-portion is processed by the processor, wherein the processor performs the action. | 04-02-2009 |
| 20090313532 | METHOD AND SYSTEM FOR DATA REPLICATION - A method for writing data to a storage pool includes receiving a write operation to write a logical block of data to the storage pool, determining a number (n−1) of physical blocks required to store the logical block of data, generating a parity block using the logical block of data, allocating n physical blocks in the storage pool, writing the parity block in the first of n allocated physical block, and writing the logical block of data across the remaining n−1 allocated physical blocks, where n is less than a number of disks in the storage pool, and where each of the n allocated physical blocks is located on a different disk in the storage pool. | 12-17-2009 |
| 20100005374 | Ensuring Data Consistency - Mechanisms for ensuring data consistency in a data store are provided. The mechanisms access a parity scrub factor f and perform a check on a data group of the data store. The check on the data group includes performing a parity check on a portion of the data group, the portion being equal to 1/ | 01-07-2010 |
| 20100037125 | SYSTEM FOR PROVIDING RUNNING DIGITAL SUM CONTROL IN A PRECODED BIT STREAM - A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity sub-blocks between selected multiple-bit data sub-blocks. The system also modifies one or more of the bits in predetermined positions in respective data sub-blocks based on the bits of the parity sub-blocks that precede them, such that the precoding does not sign invert the data sub-blocks. | 02-11-2010 |
| 20100064205 | SELECTIVE CACHE WAY MIRRORING - A data processing system has cache circuitry having a plurality of ways. Mirroring control logic indicates a mirrored way pair and a non-mirrored way of the plurality of ways. The mirrored way pair has first and second ways wherein the second way is configured to store cache data fields redundant to cache data fields of the first way. In one form, comparison logic, in response to an address hitting in the first way or the second way within the mirrored way pair, performs a bit comparison between cache data from the first way addressed by an index portion of the address with cache data from the second way addressed by the index portion of the address to provide a bit parity error signal. In another form, allocation logic uses a portion of the address and line locking information to determine whether a mirrored or non-mirrored way is selected for allocation. | 03-11-2010 |
| 20100064206 | ERROR DETECTION SCHEMES FOR A CACHE IN A DATA PROCESSING SYSTEM - A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines. | 03-11-2010 |
| 20100162088 | XOR CIRCUIT, RAID DEVICE CAPABLE OF RECOVERING A PLURALITY OF FAILURES AND METHOD THEREOF - An XOR circuit, a RAID device which can recover several failures and method thereof are provided. A Galois field data recovery circuit having two or more sets of Galois Field engine circuits which are used in the XOR circuit, is one which can generate high efficient parity engine and high efficient flow data route and which at the same time correct the three or more failures during operation of the RAID device. | 06-24-2010 |
| 20100174971 | ERROR ADDITION APPARATUS - An error addition apparatus receives a data signal D having a frame format having a specific signal inserted into its front, adds errors to the data signal D, and outputs a resulting signal. The apparatus has an error addition regulation unit for receiving a frame synchronization signal F, indicative of a timing at which the front of the frame of the data signal has been inputted, and regulating the errors such that the errors are added to positions other than a region of the specific signal. Accordingly, errors are not added to a specific signal. | 07-08-2010 |
| 20100199157 | WIRELESS COMMUNICATION DEVICE AND CIRCULAR BUFFER CONTROL METHOD - There is provided a wireless communication device capable of improving a decoding performance by using an optimal selection criterion for a start address and a read direction in a circular buffer. An interlacer ( | 08-05-2010 |
| 20100205515 | SIGNAL PROCESSING APPARATUS FOR SETTING ERROR INDICATION INFORMATION ACCORDING ERROR DETECTION RESULT OF OUTER-CODE DECODER OUTPUT AND RELATED METHOD THEREOF - A signal processing apparatus is provided. The signal processing apparatus includes an inner-code decoder, an outer-code decoder, and an error detection unit. The inner-code decoder decodes an input data stream to generate a first output data stream, wherein the input data stream is coded using a concatenated coding scheme including an outer coding and an inner coding. The outer-code decoder decodes the first output data stream to generate a second output data stream. The error detection unit performs an error detection upon the second output data stream to generate an error detection result. The decision logic sets error indication information of the second output data stream according to at least the error detection result. | 08-12-2010 |
| 20100306631 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block. | 12-02-2010 |
| 20110041045 | TRANSMITTING APPARATUS AND TRANSMITTING METHOD - A transmitting apparatus and a transmitting method wherein the systematic bit reception quality can be improved and the throughput performance can be improved. An IR parameter control part ( | 02-17-2011 |
| 20110055671 | ADVANCED MEMORY DEVICE HAVING IMPROVED PERFORMANCE, REDUCED POWER AND INCREASED RELIABILITY - An advanced memory having improved performance, reduced power and increased reliability. A memory device includes a memory array, a receiver for receiving a command and associated data, error control coding circuitry for performing error control checking on the received command, and data masking circuitry for preventing the associated data from being written to the memory array in response to the error control coding circuitry detecting an error in the received command. Another memory device includes a programmable preamble. Another memory device includes a fast exit self-refresh mode. Another memory device includes auto refresh function that is controlled by the characteristic device. Another memory device includes an auto refresh function that is controlled by a characteristic of the memory device. | 03-03-2011 |
| 20110060974 | METHODS AND DEVICES FOR TRANSMITTING A DATA STREAM AND CORRESPONDING COMPUTER READABLE MEDIA - A data stream is transmitted from a transmitting device to a receiving device via a communication network. Data of the data stream is transmitted to the receiving device by using a transport protocol without data acknowledgement. In a transmission method, parity-encoding parameters for parity encoding a data set of the data stream is determined via the transmitting device. The transmitting device also generates parity data from the data set by using the determined parity-encoding parameters. The transmitting device further transmits the generated parity data to the receiving device via the communication network by using a transport protocol with data acknowledgement. | 03-10-2011 |
| 20110072336 | LDPC (Low Density Parity Check) coded modulation symbol decoding - LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics. | 03-24-2011 |
| 20110138261 | METHOD AND SYSTEM FOR ERROR MANAGEMENT IN A MEMORY DEVICE - A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors and cyclic redundancy check errors. In one embodiment of the invention, the memory can detect whether a received command has any parity errors by determining whether the command bits or the address bits of the received command has any parity errors. If a parity error or cyclic redundancy check error in the received command is detected, an error handling mechanism is triggered to recover from the errant command. | 06-09-2011 |
| 20110154167 | OPTIMIZING RAID MIGRATION PERFORMANCE - A method of RAID migration comprising reading first and second blocks from a first RAID array. Said first blocks are written to a second RAID array within a first write cycle. Said second blocks are read simultaneously with a portion of said first write cycle in a pipelined fashion. In a first embodiment, pipelining increases the speed of RAID migration from a one-disk stripe array to a two-disk mirror array. In a second embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a two-disk mirror array to a three-disk RAID 5 array. In a third embodiment, pipelining and the use of duplicate blocks increases the speed of RAID migration from a three-disk RAID 5 array to a four-disk RAID 5 array. | 06-23-2011 |
| 20110264989 | DISPERSED STORAGE NETWORK SLICE NAME VERIFICATION - A method begins by a processing module dispersed storage error encoding data to produce a plurality of sets of encoded data slices in accordance with dispersed storage error coding parameters. The method continues with the processing module determining a plurality of sets of slice names corresponding to the plurality of sets of encoded data slices. The method continues with the processing module determining integrity information for the plurality of sets of slice names and sending the plurality of sets of encoded data slices, the plurality of sets of slice names, and the integrity information to a dispersed storage network memory for storage therein. | 10-27-2011 |
| 20110296284 | Transmission apparatus and parity calculation method - In a transmission apparatus, a first parity calculation controller calculates parity by the frame and inserts a calculation result into a next frame to a first frame sequence. A second parity calculation controller calculates the parity by the frame and inserts a calculation result into a next frame to a second frame sequence. The second parity calculation controller receives from the first parity calculation controller first parity data which is a parity calculation result by the first parity calculation controller and which has the same value as that of a parity calculation result to be inserted into a target frame of a parity calculation in the second frame sequence. Then, the controller calculates the parity of the target frame including the first parity data and second parity data which is a parity calculation result of a previous frame in the second frame sequence before one frame of the target frame. | 12-01-2011 |
| 20110296285 | WIRELESS COMMUNICATION APPARATUS - Disclosed is a wireless communication apparatus in which reception precision characteristics are improved, by specially adapting the modulating processing in respect of the code words for each encoding system. A wireless communication apparatus ( | 12-01-2011 |
| 20110302480 | METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING CONTROL INFORMATION OF MIMO SYSTEM - The present invention relates to a method and a system for transmitting and receiving control information of an Multi-Input Multi-Output (MIMO) system, wherein the control information consists of information bits and parity bits. A base station transmits the control information including the location information for where the control information of the other terminal is transmitted. A terminal receives the control information of the other terminal based on the location information for where the control information of the other terminal is received. Therefore, the precoding matrix of the other terminal can be obtained from the received control information. The invention enables the removal of interference through the obtained precoding matrix when receiving a data symbol in an environment where a channel is not in a good state. | 12-08-2011 |
| 20120036417 | Method for detecting an error in an A/D converter by parity predictions - For detecting an error of an A/D converter, which is designed to generate at least one digital output signal, which includes a quantity of output data bits, based on at least one analog input signal, and during a conversion, to generate a thermometer code which includes a quantity T of output data values, the detection method includes: ascertaining a first parity directly for the output data bits of the output signal; making a prediction for the output data bits on the basis of the T output data values of the thermometer code; ascertaining a second parity, which is a reverse of the first parity, for the predicted output data bits; and detecting an error for the A/D converter when both the first and second parities are identical. | 02-09-2012 |
| 20120047419 | TRANSMISSION SYSTEM - A transmission system carrying out sending and receiving of OTU frames has a first transmission device carrying out the sending of an OTU frame, and a second transmission device carrying out the receiving of the OTU frame. The first transmission device calculates BIP-8 for an objective calculation range preset in the OTU frame, inserts the calculation result into the OTU frame, and sends the same. The second transmission device calculates BIP-8 from the received OTU frame for the same objective calculation range as the first transmission device, compares the calculation result with the BIP-8 sent from the first transmission device, and detects any presence of transmission error. The calculation range is set in terms of one of an area including OPU only and an area at least including an arbitrary byte of OTU/ODU overhead. | 02-23-2012 |
| 20120072811 | CONTROLLER, STORAGE APPARATUS, AND COMPUTER PROGRAM PRODUCT - According to one embodiment, a controller controls writing into and reading from a storage apparatus that includes a first data-storage unit and a second data-storage unit. The second data-storage unit stores user data and parity data of the user data. The first data-storage unit stores the parity data. The controller includes a parity updating unit and a parity writing unit. When parity data is updated, the parity updating unit writes the updated parity data into the first data-storage unit. When a certain requirement is satisfied, the parity writing unit reads the parity data written in the first data-storage unit, and writes the parity data thus read into the second data-storage unit. | 03-22-2012 |
| 20120079358 | METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS - A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory. | 03-29-2012 |
| 20120144275 | CODE GENERATING DEVICE AND CODE GENERATING METHOD, CODE CHECKING DEVICE AND CODE CHECKING METHOD, COMPUTER PROGRAM, AND COMMUNICATION DEVICE - A code generating device includes a code word generating section which generates a code word with a predetermined code word length by applying a second matrix Gq of a second error detection method with regard to an information word A′ which has been input, and a code word conversion section which converts the code word generated by the code word generating section based on an added fixed value (Qa+Pa) which is formed from respective code words Qa and Pa which are obtained by the second matrix Gq and a first matrix Gp of a first error detection method being respectively applied to an information word A which is formed from a specific data string. | 06-07-2012 |
| 20120144276 | MEMORY SYSTEM AND METHOD USING A MEMORY DEVICE DIE STACKED WITH A LOGIC DIE USING DATA ENCODING, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits. | 06-07-2012 |
| 20120151306 | MULTI-ANTENNA CONFIGURATION SIGNALING IN WIRELESS COMMUNICATION SYSTEM - A wireless communication infrastructure entity including a transceiver coupled to a controller configured to generate parity bits based on an information word. The controller is also configured to encode the parity bits based on a communication configuration, e.g., symbol information, wherein the encoded parity bits are combined with the information word for transmission by the transceiver. A user terminal in receipt of the information word includes a controller configured to determine the communication configuration based on a set of configuration indicator bits used to encode the parity bits. | 06-14-2012 |
| 20120204082 | DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD - The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme. | 08-09-2012 |
| 20120216099 | METHOD AND APPARATUS FOR TRANSMITTING SIGNALING INFORMATION IN DIGITAL BROADCASTING SYSTEM - A method and an apparatus for are provided. In a method for transmitting signaling information in a digital broadcasting system, a transmitter transmits signaling information, and an information bit stream is received. The received information bit stream is encoded and a parity bit is added. The parity bit is punctured such that parity bits of different patterns are formed between adjacent frames. | 08-23-2012 |
| 20120290905 | SYSTEM AND METHOD FOR OPTIMIZING READ-MODIFY-WRITE OPERATIONS IN A RAID 6 VOLUME - A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed. | 11-15-2012 |
| 20130007572 | System And Method For Look-Aside Parity Based Raid - Redundant storage of information is provided by distributing storage functions between a RAID controller and switching device. The switching device multi-casts writes to storage devices and to the RAID controller. The RAID controller generates parity for the information and writes the parity to the storage devices in space reserved for parity by the switching device. Information is read from the storage devices through the switching device without action by the RAID controller. | 01-03-2013 |
| 20130013985 | METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS - A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory. | 01-10-2013 |
| 20130132806 | Convolutional Turbo Code Decoding in Receiver With Iteration Termination Based on Predicted Non-Convergence - This disclosure introduces the concept of a strategy for a Convolutional Turbo Code decoder to make a prediction with regards to the likelihood of convergence. If a failure of convergence appears likely, the decoding process is aborted, The predictions regarding failure of convergence are made at the end of each half-iteration in a decoding process, leading to more efficient use of decoders in a system. | 05-23-2013 |
| 20130185617 | WIRELESS BACKHAUL COMMUNICATION - A method for wireless backhaul communication comprising receiving, by a wireless backhaul transmitter, a data stream in a bit format and generating, by the wireless backhaul transmitter using a single-carrier block transmission scheme, a radio frame to include a plurality of physical data channel (PDCH) blocks, a pilot signal (PS) block and a physical control channel (PCCH) block with each block type pre-appended with a cyclic prefix (CP). A length of the PS block in symbols, a length of the PCCH block in symbols and a length of the PDCH block in symbols is determined by a frequency band, a bandwidth, and a channel condition. The wireless backhaul transmitter then transmits the radio frame. | 07-18-2013 |
| 20130238963 | Digital Architectures For Serial Data Stream Operations - Systems and techniques for serial data stream operations are described. A described system includes a serial bus communicatively coupled with a memory structure to handle a serial data stream from or to the memory structure; generators configured to generate enablement signals that are associated with different bit-groups of the serial data stream, each of the enablement signals including pulses that are aligned with time-slots that are associated with a respective bit-group; logic elements configured to store internal states and produce output signals that are based on the serial data stream, the enablement signals, and the internal states, and circuitry configured to capture values. Each of the enablement signals enables a respective logic element to selectively change a respective internal state responsive to bit-values of a respective bit-group. Each of the captured values represents an output of a respective logic element that is responsive to all bit-values of a respective bit-group. | 09-12-2013 |
| 20130254639 | PARALLEL ENCODING FOR NON-BINARY LINEAR BLOCK CODE - An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed. | 09-26-2013 |
| 20130283135 | PARITY ERROR RECOVERY METHOD FOR STRING SEARCH CAM - Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element. | 10-24-2013 |
| 20130305128 | METHOD AND APPARATUS FOR DETECTING COMMUNICATION ERRORS ON A BUS - A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The embodiments may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory. | 11-14-2013 |
| 20130326316 | Systems and Methods for Improved Data Detection Processing - The present invention is related to systems and methods for enhancing data detection in a data processing system. | 12-05-2013 |
| 20130326317 | METHODS AND APPARATUS FOR TEMPORARILY STORING PARITY INFORMATION FOR DATA STORED IN A STORAGE DEVICE - Methods and apparatus for temporarily storing parity information for data stored in a storage device are provided. A first data block and parity information associated with the first data block are received. The first data block is stored in a first region of the storage device. The parity information is stored until a second data block is successfully stored in a second region of the storage device. The first region of the storage device is associated with the second region of the storage device. | 12-05-2013 |
| 20130346835 | Detecting Data Transmission Errors In An Inter-Integrated Circuit ('I2C') System - Detecting data transmission errors in an I | 12-26-2013 |
| 20130346836 | MEMORY DEVICE - A memory device includes a parity circuit configured to detect presence or absence of an error using a plurality of command signals and a plurality of address signals, a command shift circuit configured to shift the plurality of command signals by a preset delay value in synchronization with a control clock, a clock control circuit configured to deactivate the control clock when there is no valid command signal in command signals being shifted in the command shift circuit, and a decoder circuit configured to decode a plurality of command signals output from the command shift circuit. | 12-26-2013 |
| 20140068397 | PARTIAL PARITY MANAGEMENT - A partial outer parity management system generates a product code based on a partial data block write to a data block and partial outer parity generated by a previous partial data block write to the data block. In one implementation, a storage device includes cache storage circuit accessible by the parity generator, the cache storage circuit being configured to cache the partial outer parity generated by the previous partial data block write to the data block in a partial outer parity cache designated for association with the product code. | 03-06-2014 |
| 20140164885 | TIME INFORMATION OBTAINING DEVICE AND RADIO-CONTROLLED TIMEPIECE - A time information obtaining device and a radio-controlled timepiece are shown. According to one implementation, the time information obtaining device includes the following. A code identifying section identifies each code of a code string in a radio wave. A first portion parity calculating section calculates a portion parity where a parity bit of a variable code is subtracted from a parity code showing a parity bit for a code string portion. A first portion parity deciding section decides a portion parity based on a calculated number of portion parities. A second portion parity deciding section obtains a portion parity from an invariable code other than the variable code. A parity confirming section confirms a match between the portion parities decided by the first portion parity deciding section and the second portion parity deciding section. | 06-12-2014 |
| 20140201606 | ERROR PROTECTION FOR A DATA BUS - A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells. | 07-17-2014 |
| 20140250353 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM CONDUCTING PARITY CHECK AND OPERATING METHOD OF SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprising of a parity check unit configured to receive a command signal and a parity signal to perform error checking in the command signal and output a parity indication signal; a delay unit including a plurality of registers configured to time delay by n clock cycles the parity indication signal and output a delayed parity indication signal; a command register configured to time delay by n clock cycles the command signal and output a delayed command; and a decoder configured to pass or block the delayed command signal based on the delayed parity indicator signal. | 09-04-2014 |
| 20150058705 | STORAGE DEVICE AND DATA LATCH TIMING ADJUSTMENT METHOD - According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit. | 02-26-2015 |
| 20150381311 | PHYSICAL LAYER FRAME FORMAT FOR WLAN - In a method for generating a data unit conforming to a first communication protocol, a first field and a second field to be included in a preamble of the data unit are generated. The first field includes a first set of one or more information bits that indicate a duration of the data unit and is formatted such that the first field allows a receiver device that conforms to a second communication protocol to determine the duration of the data unit. The second field includes a second set of one or more information bits that indicate to a receiver device that conforms to the first communication protocol that the data unit conforms to the first communication protocol. The first field and the second field are modulated using a modulation scheme specified for a field corresponding to the first field and the second field, respectively, by the second communication protocol. | 12-31-2015 |
| 20160170829 | NON-LOCAL ERROR DETECTION IN PROCESSOR SYSTEMS | 06-16-2016 |
| 20160173232 | MITIGATION OF BURSTY INTERFERENCE | 06-16-2016 |
| 20170235523 | STORAGE DEVICE, LIQUID CONTAINER, AND HOST DEVICE | 08-17-2017 |
| 20190149172 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD | 05-16-2019 |
