Class / Patent application number | Description | Number of patent applications / Date published |
714777000 | Hamming code | 38 |
20080222496 | Secure Protection of Biometric Templates - This invention relates to methods and devices for verifying the identity of a person based on a sequence of feature components extracted from a biometric sample. Thereafter, the feature components are quantized and assigned a data bit sequence in such a way that adjacent quantization intervals have a Hamming distance of 1. The data bit sequences are concatenated into a bit string, and said bit string is combined with a helper data set by using an exclusive disjunction (XOR) operation into a codeword. Finally, the codeword is decoded into a secret V and a secret S is matched with the secret V. | 09-11-2008 |
20080320370 | CRC generator polynomial select method, CRC coding method and CRC coding circuit - Disclosed herein is a CRC generator polynomial select method for selecting a generator polynomial to be used in CRC coding processing and/or CRC processing of inspecting a CRC processing result, the CRC generator polynomial select method may include a first process of finding largest minimum Hamming distances Max.d | 12-25-2008 |
20090193319 | DATA BUS SYSTEM, ITS ENCODER/DECODER AND ENCODING/DECODING METHOD - The present application relates to a data bus system, its encoder/decoder and encoding/decoding method. The data bus encoder comprises: a bus-invert encoder for generating encoded data and invert-indication information by performing bus-invert encoding on data according to a predetermined bus-invert encoding scheme; a virtual bit-group generator for converting the invert-indication information into a virtual bit-group according to a predetermined code mapping; and an error-checking-and-correction encoder for generating an error-checking-and-correction code for a virtual word according to a predetermined error-checking-and-correction encoding scheme, wherein the number of error-checking bits is more than the number of error-correction bits at least by one in the predetermined error-checking-and-correction encoding scheme, the mapping is such that the Hamming distance between any possible value of the virtual bit-group and a reference virtual bit-group which cannot be converted into under the mapping is a fixed value, and not greater than the number of error-correction bits of the error-checking-and-correction encoding scheme, and the virtual word includes the data to be output, the virtual bit-group corresponding to the data, and at least one padding bit of a fixed value, which is configured as required by the error-checking-and-correction encoding scheme. | 07-30-2009 |
20090241013 | EFFICIENT DECOUPLING SCHEMES FOR QUANTUM SYSTEMS USING SOFT PULSES - A system and method for dynamical decoupling of a quantum system includes forming a graph including elements to account for decoupling sequence effects represented as nodes in the graph and soft pulses applied being represented as edges in the graph. Sequences which visit edges and nodes in the graph are provided. Binary strings corresponding to the nodes in a coordinate system are mapped using a fixed linear error correcting code. A decoupling method is provided based upon a matrix formed using the error correcting code to determine features of the soft pulses to decouple environmental effects from the quantum system. | 09-24-2009 |
20090276687 | METHOD OF ENCODING AND DECODING MULTI-BIT LEVEL DATA - A method of encoding multi-bit level data includes: determining a range of an error pattern generated according to a transmission symbol, encoding an M-bit level of a P-bit level corresponding to the transmission symbol based on the range of the error pattern, and excluding encoding of a P-M bit level of the P-bit level. The variable P is a natural number of a value at least two, and the variable M is a natural number less than P. | 11-05-2009 |
20090313529 | METHOD AND APPARATUS FOR ERROR MANAGEMENT - To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected. | 12-17-2009 |
20090319873 | SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD THAT DECODE ENCODED INFORMATION - According to an embodiment of the present invention provides the signal processing system. In the signal processing device that estimates information data from a reception signal by performing iterative processing between a demodulator that demodulates data of n(>m) bits obtained by modulating data of m bits into m bits and an ECC decoder and carrying out maximum a posteriori probability decoding, the device has a module that calculates an a posteriori value after demodulation by performing calculation of modulation data having a pattern estimated to have a high probability alone as modulation data to be decoded from all patterns of the modulation data to be decoded when effecting calculation of the a posteriori value after demodulation based on an a priori value fed back from the ECC decoder at the time of effecting modulation for a second or subsequent time. | 12-24-2009 |
20090327845 | System and Method For Mitigating Burst Noise In A Communications System - A system, method and computer program product is provided for mitigating the effects of burst noise on packets transmitted in a communications system. A transmitting device applies an outer code, which may include, for example, a block code, an exclusive OR (XOR) code, or a repetition code, to one or more packets prior to adaptation of the packets for transmission over the physical (PHY) layer of the communications system, wherein the PHY layer adaptation may include FEC encoding of individual packets. The outer coded packets are then separately transmitted over a channel of the communications system. A receiving device receives the outer coded packets, performs PHY level demodulation and optional FEC decoding of the packets, and then applies outer code decoding to the outer coded packets in order to restore packets that were erased during transmission due to burst noise or other impairments on the channel. | 12-31-2009 |
20100031124 | Transmission apparatus and method, reception apparatus and method, and program - A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing. | 02-04-2010 |
20100083074 | Block Code Decoding Method And Device Thereof - A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision. | 04-01-2010 |
20100095188 | APPARATUS AND METHOD FOR DETECTING AND CORRECTING ERRORS IN CONTROL CHARACTERS OF A MULTIMEDIA INTERFACE - An apparatus and method for detecting and correcting errors in control characters of a multimedia interface. The apparatus comprises a hamming distance filter for detecting and correcting bits errors in a first subset of bits of an input control character including M bits; a glitch filter for detecting and correcting a second subset of bits being a complementary subset of bits of the control character; and an character alignment unit for detecting and correcting misalignment errors between the corrected first subset of bits and the corrected second subset of bits. | 04-15-2010 |
20100100796 | ERROR DETECTING CODE FOR MULTI-CHARACTER, MULTI-LANE, MULTI-LEVEL PHYSICAL TRANSMISSION - A system (e.g., Fibre Channel Error Detecting Code (FC-EDC)) that maps the “standard” Hamming codes onto the bits of a 33-bit control block is provided. The system employs a “rotation” of the check positions in a two-dimensional parity-check matrix for the FC-EDC. The specification discloses a computer-implemented program to test further modifications and permutations of the “standard” distance-4 parity-check matrix to yield an FC-EDC with enhanced error-detecting properties, designed to detect the most likely errors in the known physical environment. By using a parity-check matrix with the “rotation” property, certain error-detecting properties of the parity-check matrix are ensured, and the computation time for searching for a matrix with enhanced error-detecting properties becomes much shorter. | 04-22-2010 |
20100153823 | CODING METHOD AND CODING DEVICE - The present invention relates to coding method and coding device that allow Rate-Compatible LDPC (low-density parity-check) codes to have favorable BER performance both with a low code rate and with a high code rate. In coding of LDPC codes that have plural code rates and whose all parity check matrices are composed of plural cyclic matrices, a coder | 06-17-2010 |
20100185922 | HAMMING RADIUS SEPARATED DEDUPLICATION LINKS - A method of de-duplicating duplicate data in a data storage system that includes identifying a plurality of portions of data, comparing each portion of the data to identify duplicate data and identifying a link associated with each duplicate data, determining whether a Hamming link-separation-distance between the identified link and all other existing links is greater than twice the Hamming radius of an error correction code in the data storage system, and then replacing the duplicate data with the identified link. | 07-22-2010 |
20100211856 | SYSTEMS AND METHODS FOR ERROR CORRECTION AND DECODING ON MULTI-LEVEL PHYSICAL MEDIA - Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes. | 08-19-2010 |
20100262893 | ROBUST CONTROL/DELINEATION IN SERIAL STREAMS - Control symbols taking the form {k1-k2-k2-k1} are inserted in a serial stream including m bit data words. k1 and k2 are each predefined m bit control words differing from the m bit data words. The Hamming distance between k1 and k2 is at least 2. Such control symbols may be robustly detected in the presence of a one bit error in the symbol, or a data word immediately preceding or following the symbol. The m bit words may be 8B/10B encoded data, or defined control words. The control symbols may be used for data delineation, stream synchronizaiton, transmitter/receiver synchronization or for other control signalling. | 10-14-2010 |
20100269024 | METHOD AND APPARATUS FOR MULTISET MEMBERSHIP TESTING USING COMBINATORIAL BLOOM FILTERS - A method and apparatus providing improved set membership determination and group membership identification of candidate data elements using a single Bloom filter programmed to provide a plurality of non-zero f-bit binary vectors, where each of the f-bit binary vectors is associated with a respective group. The Bloom filter is programmed using one or more (but not all) of a plurality of hash filter sets. | 10-21-2010 |
20100306626 | METHODS OF DATA HANDLING - Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the data in differing data states. Such methods further include comparing the generated one or more error correction codes to the previously-generated error correction code, and if a particular one of the generated one or more error correction codes matches the previously-generated error correction code, transmitting the data having its one or more particular bits in the data states corresponding to that particular one of the generated one or more error correction codes. Methods of data handling may further include prioritizing the error correction in response to at least locations of known bad or questionable bits of the data. | 12-02-2010 |
20100318883 | Method for Enhancing Reliability of Information Transmission - The present invention provides a method for enhancing reliability of information transmission, comprising the steps of: (a) establishing a matrix based on the length of bits of valid information in frame time slots; and creating a new matrix by presetting Error Correction Coding (ECC) for rows and columns of said matrix; (b) adopting the 1st Interleaving method to re-allocate bits which have been processed twice by using said ECC in said new matrix, to both ends of said frame time slots; and (c) adopting the 2nd Interleaving method to re-allocate the remaining bits in said new matrix to the middle of said frame time slots. After processed like this, the anti-interfering ability of the bits at both ends of TDMA frame time slot can be significantly enhanced, and the bit-error rate is decreased most, and all redundancy bits of Hamming codes can be arrayed at both ends of TDMA frame time slot. | 12-16-2010 |
20110004809 | Method and Apparatus for Detecting Frame Delimiters in Ethernet Passive Optical Networks with Forward Error Correction - Embodiments of the present invention provide a system that identifies an even delimiter in a forward error correction (FEC)-coded Ethernet frame. The system receives an FEC-coded Ethernet frame that includes the even delimiter, which is a predetermined sequence that separates a conventional Ethernet frame and FEC parity bits in the FEC-coded Ethernet frame. Next, the system scans a bit stream of the FEC-coded Ethernet frame. Then, the system determines a first Hamming distance between a first consecutive set of frame bits in the bit stream and the even delimiter. The system also determines a second Hamming distance between a second consecutive set of frame bits in the bit stream and the even delimiter. Both the first and second Hamming distances are shorter than a predefined value. The system subsequently selects one of the first and second sets of frame bits having the shorter Hamming distance as the even delimiter. | 01-06-2011 |
20110138255 | Probabilistic Learning-Based Decoding of Communication Signals - Methods and apparatus for recovering source data from noisy encoded signals apply population-based probabilistic learning algorithms. Non-converging data elements may be resolved by selective local searches. Initial populations are constructed from the data contents of the message bit positions of the received sequence, which resulted from encoding by a systematic code and channel distortion and noise. | 06-09-2011 |
20110138256 | Distributed Block Coding (DBC) - Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement. | 06-09-2011 |
20110138257 | METHOD FOR TRANSMITTING AND RECEIVING A DATA BLOCK - The invention relates to a method for transmitting a data block ( | 06-09-2011 |
20110209033 | CIRCUIT AND TECHNIQUE FOR REDUCING PARITY BIT-WIDTHS FOR CHECK BIT AND SYNDROME GENERATION FOR DATA BLOCKS THROUGH THE USE OF ADDITIONAL CHECK BITS TO INCREASE THE NUMBER OF MINIMUM WEIGHTED CODES IN THE HAMMING CODE H-MATRIX - A circuit and technique for reducing parity bit-widths for check bit and syndrome generation is implemented through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The circuit and technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry. | 08-25-2011 |
20110214037 | CODING DEVICE, DECODING DEVICE, CODING METHOD, DECODING METHOD, AND COMMUNICATION SYSTEM - Positions holding different bit values between a first code word, which is obtained by coding an information bit sequence based on a coding method utilizing quasi-cyclic codes, and a second code word, which has the close Hamming distance from the first code word and satisfies a parity check of the coding method, are identified. Thereafter, a code word is generated by inserting bit values known to the transmitter and receiver into the identified positions of the information bit sequence and coding the information bit sequence. Upon reception of a signal based on the generated code word, the receiver judges whether known bit values held by corresponding positions in a code word obtained by decoding the received signal are the same as preset bit values. If the judgment result is negative, the code word based on the received signal is judges as erroneous even when it satisfies the parity check. | 09-01-2011 |
20110289390 | VEHICLE COMMUNICATION SYSTEM DIAGNOSTIC USING HAMMING CODE - A control system includes an error calculation module that receives a data bit pattern having a predetermined quantity of data bits and that calculates a binary vector based on a predetermined binary matrix and the data bit pattern. The error calculation module further determines the data bit pattern contains a corrupted data bit when the binary vector is not a predetermined value. The control system further includes a bit position module that receives the binary vector, that locates the corrupted data bit based on the binary vector and that corrects the data bit pattern. The bit position module receives the data bit pattern when the binary number is the predetermined value. The data bits are pre-assigned a base-10 value that corresponds to a data bit position. | 11-24-2011 |
20110302478 | POWER AND PIN EFFICIENT CHIP-TO-CHIP COMMUNICATIONS WITH COMMON-MODE REJECTION AND SSO RESILIENCE - In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form. | 12-08-2011 |
20120017140 | NON-MDS ERASURE CODES FOR STORAGE SYSTEMS - Erasure-encoded data is stored across a plurality of storage devices in a data storage system. The erasure-encoded data includes k data elements to store on k data storage devices and m parity elements to store on m parity storage devices, wherein for a given minimum Hamming distance d of the data storage system and m≧(d−1), data elements are assigned only to corresponding unique combinations of parity elements of size (d−1). | 01-19-2012 |
20120036414 | RENDERING DATA WRITE ERRORS DETECTABLE - An embodiment of a data write path includes encoder and write circuits. The encoder circuit is operable to code data so as to render detectable a write error that occurs during a writing of the coded data to a storage medium, and the write circuit is operable to write the coded data to the storage medium. For example, such an embodiment may allow rendering detectable a write error that occurs while writing data to a bit-patterned storage medium. | 02-09-2012 |
20120117447 | Data transmission - If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted. | 05-10-2012 |
20120137195 | PRESERVING DATA INTEGRITY IN A MEMORY SYSTEM - A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device. | 05-31-2012 |
20120297275 | CIRCUIT AND TECHNIQUE FOR REDUCING PARITY BIT-WIDTHS FOR CHECK BIT AND SYNDROME GENERATION FOR DATA BLOCKS THROUGH THE USE OF ADDITIONAL CHECK BITS TO INCREASE THE NUMBER OF MINIMUM WEIGHTED CODES IN THE HAMMING CODE H-MATRIX - A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry. | 11-22-2012 |
20130262962 | MEMORY ERROR CORRECTION - In a method, by a first circuit, a plurality of bits is converted in a first format to a second format. By a second circuit, the plurality of bits in the second format is used to program a plurality of memory cells corresponding to the plurality of bits. The first circuit and the second circuit are electrically coupled together in a first chip. The plurality of bits is selected from the group consisting of 1) address information, cell data information, and program information of a memory cell that has an error; and 2) word data information of a first word and error code and correction information corresponding to the word data information of the first word. | 10-03-2013 |
20140053045 | EXTENDED SINGLE-BIT ERROR CORRECTION AND MULTIPLE-BIT ERROR DETECTION - Some embodiments include apparatus and methods to prevent at least one of misidentifying and ignoring multiple-bit errors if the multiple-bit errors include a plurality of erroneous data bits that belong to only one specific group of a plurality of groups of data bits and if none of the other groups of the plurality of groups have errors. | 02-20-2014 |
20140189472 | EFFICIENT CACHE SEARCH AND ERROR DETECTION - A first codeword may be constructed from a cache tag in a cache and an error correction code corresponding to the cache tag. A second codeword may be constructed from a search tag and an error correction code corresponding to the search tag. A hamming distance may be calculated between the first codeword and the second codeword. If the hamming distance is less than or equal to a threshold, a cache hit may be signaled. If the hamming distance is above the threshold, a cache miss may be signaled. | 07-03-2014 |
20140365847 | SYSTEMS AND METHODS FOR ERROR CORRECTION AND DECODING ON MULTI-LEVEL PHYSICAL MEDIA - Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes. | 12-11-2014 |
20160004591 | METHOD AND DEVICE FOR PROCESSING DATA - A method for processing data includes coding a data item to obtain a coded data item that includes a predefinable number of bits, influencing maximally k many bits of the coded data item to obtain a changed data item, decoding the changed data item by using a fault-correcting code to obtain a decoded data item, and processing the decoded data item. | 01-07-2016 |
20160173134 | Enhanced Data Bus Invert Encoding for OR Chained Buses | 06-16-2016 |