| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714775000 | Synchronization | 16 |
| 20090106629 | RDS COMPATIBLE RECEIVER AND RDS DATA RECEIVING METHOD - An RDS compatible receiver has a demodulator which demodulates RDS data, a register which converts the demodulated RDS data to block data and outputs the block data, an offset generating unit which predicts and outputs an offset word of the block data based on values of a pattern match flag signal and a synchronization flag signal, an error correction processing unit which performs error correction of the block data using the predicted offset word, compares the number of error corrections with a predetermined correction threshold, determines whether the predicted offset word is right or not based on the comparison result, and outputs the pattern match flag signal based on the determination result, and a synchronization determining unit which detects whether or not the predicted offset word determined to be right matches a predetermined offset sequence pattern, determines whether RDS block synchronization is established or not, and outputs the synchronization flag signal based on the determination result. | 04-23-2009 |
| 20090327841 | PROBABILISTIC ERROR CORRECTION IN MULTI-BIT-PER-CELL FLASH MEMORY - Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal. | 12-31-2009 |
| 20100275102 | SIGNAL DEMODULATING DEVICE, SIGNAL DEMODULATING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, AND RECEIVING APPARATUS - There is provided a signal demodulating device, including: a time frequency converting unit ( | 10-28-2010 |
| 20100287449 | FEC FRAME STRUCTURING DEVICE AND FEC FRAME STRUCTURING METHOD - An FEC frame structuring device includes a multi-lane distributing unit that distributes a data frame to be transmitted to n lanes, FEC coding units each performs FEC coding of the distributed data frame independently for each of the n lanes to generate an FEC frame, a multiplexing unit that multiplexes the FEC frame from the FEC coding units by relating to m channels of an optical signal, a demultiplexing unit that demultiplexes the m channels of the received optical signal by relating to the n lanes, FEC decoding units each performs FEC decoding of the demultiplexed FEC frame independently for each of the n lanes, and a multi-lane synchronizing unit that synchronizes the n lanes with each other after the FEC decoding performed by the FEC decoding units to reconstruct the original data frame. | 11-11-2010 |
| 20110078545 | Frame Boundary Detection and Synchronization System for Data Stream Received by Ethernet Forward Error Correction Layer - The present invention discloses a frame boundary detection system and a synchronization system for a data stream received by an Ethernet Forward Error Correction layer. The frame boundary detection system includes a shifter, two descramblers, a syndrome generator and trapper. The error trapper includes a big-little endian mode controller for controlling the big-little endian conversion of the error trapper. If the error trapper operates in the big endian mode, the error trapper implements the function of the syndrome generator, operates at the same time with the syndrome generator, and performs a second FEC check, wherein when the shifter performs the FEC check by intercepting data with a length of one frame plus A bits, two start positions of the frame can be verified, where A is a positive integer less than a length of one frame. The invention can improve the frame boundary detection speed and the frame synchronization speed, and increase only a few hardware overheads. | 03-31-2011 |
| 20110173516 | METHOD AND DEVICE FOR INFORMATION BLOCK CODING AND SYNCHRONIZATION DETECTING - A method and a device for information block coding and synchronization detecting are provided. Information block coding and synchronization detecting are preformed according to a synchronization character sequence satisfying certain conditions. Thus, the probability of incorrect synchronization is effectively reduced without increasing the complexity. Optimal synchronization character sequences in different lengths are provided to further reduce the probability of incorrect synchronization. | 07-14-2011 |
| 20110214035 | Data Decoding Method and Apparatus and Receiver and Communication System Applying the Same - A receiver including a switch for switching output of a memory to one of paths according to content of the output. The memory stores information bits, first check bits and second check bits. The first check bits and second check bits are switched to one of the paths via a rate dematch apparatus to a decoder. The information bits are switched directly to the decoder. | 09-01-2011 |
| 20110252291 | RECEIVING APPARATUS - A receiving apparatus that can prevent beforehand that a portable recording medium is erroneously ejected during examination, and can prevent body cavity image data from being lost and the portable recording medium from being damaged is provided. When an ejection operation of the portable recording medium is detected (step S | 10-13-2011 |
| 20110314357 | Phase synchronization apparatus, phase synchronization method and phase synchronization program - A phase synchronization apparatus includes: a sampling section; a phase-error detection section; a first computation section; a second computation section; and an interpolation section. | 12-22-2011 |
| 20120011417 | PLI N-BIT CORRECTION CIRCUIT, GFP LAYER 2 SYNCHRONIZATION CIRCUIT AND GFP FRAME TRANSFER DEVICE USING IT - A PLI n-bit correction circuit extracts a core header (PLI) from a GFP frame with a fixed payload length; compares it with a predetermined expectation value for each bit; calculates the number of inconsistent bits therebetween; and outputs the predetermined expectation value, instead of the core header, when the number of inconsistent bits is equal to or less than n (n is a natural number); or directly outputs the core header when the number of inconsistent bits is greater than n. A decision on establishment of GFP Layer 2 synchronization is made based on the output of the PLI n-bit correction circuit, wherein predetermined processing is executed on a payload of a GFP frame dropping its core header when GFP Layer 2 synchronization is established, whilst the payload is not subjected to predetermined processing and discarded in the event of GFP Layer 2 desynchronization. | 01-12-2012 |
| 20140201602 | METHOD AND SYSTEM FOR PROVIDING SCRAMBLED CODED MULTIPLE ACCESS (SCMA) - A multiple access scheme is described. A first bit stream is scrambled from a first terminal according to a first scrambling signature. A second bit stream is scrambled from a second terminal according to a second scrambling signature, wherein the first bit stream and the second bit stream are encoded using a low rate code. The first scrambling signature and the second scrambling signature are assigned, respectively, to the first terminal and the second terminal to provide a multiple access scheme. | 07-17-2014 |
| 20140281830 | DATA ENCODING AND DECODING - A data encoding method includes receiving a sequence of N scrambled blocks produced by scrambling a sequence of N preliminary blocks comprising one of a data block and a control block, the control block being one of K types and including a block-type field, each scrambled block having a block header indicating a scrambled data block or a scrambled control block; encoding the sequence of N scrambled blocks into an encoded block by deleting the block headers, and in the event the sequence contains any scrambled control blocks, deleting a set of scrambled bits corresponding to respective block-type field bits of at least one control block in the sequence of preliminary blocks such that the other block-type field bits are sufficient to indicate the type of control block, and adding position indicator bits indicating position of each scrambled control block in the received sequence of scrambled blocks. | 09-18-2014 |
| 20150039972 | APPARATUS, SYSTEM AND METHOD FOR MERGING CODE LAYERS FOR AUDIO ENCODING AND DECODING AND ERROR CORRECTION THEREOF - Apparatus, system and method for encoding and decoding ancillary code for digital audio, where multiple encoding layers are merged. The merging allows a greater number of ancillary codes to be embedded into the encoding space, and further introduces efficiencies in the encoding process. Utilizing certain error correction techniques, the decoding of ancillary code may be improved and made more reliable. | 02-05-2015 |
| 20150082129 | CONFIGURATIONS OF A FORWARD ERROR CORRECTION DECODER - One embodiment provides a PHY having a Media Access Control (MAC) and a Forward Error Correction (FEC) decoder, capable of error detection and error correction for FEC encoded packets based on FEC parity data included in the FEC encoded packets. The FEC decoder is capable of being enabled into different configurations of different operations to perform on FEC parity data included in the FEC encoded packets. The different configurations having different respective associated latencies. | 03-19-2015 |
| 20150381346 | METHODS AND SYSTEMS FOR SELECTION OF UNIONS OF VECTOR SIGNALING CODES FOR POWER AND PIN EFFICIENT CHIP-TO-CHIP COMMUNICATION - Methods and systems are described for communication of data over a communications bus at high speed and high pin efficiency, with good resilience to common mode and other noise. Pin efficiencies of 100% may be achieved even for bus widths of four or fewer wires. Information to be transmitted is encoded as words of a vector signaling code, each word comprising multiple values transmitted as a group over the communications bus. Subsets of the vector signaling code have distinct group characteristics, which are discernable on transmission and are used to facilitate decoding on reception. | 12-31-2015 |
| 20160105200 | APPARATUS AND METHOD FOR PROCESSING TRACE DATA STREAMS - An apparatus comprising: a lower-layer decoder configured to decode a data stream formatted according to a lower-layer protocol that interleaves portions of a first data stream and one or more additional data streams to produce separated data streams comprising the first data stream and separately the one or more additional data streams; and a higher-layer decoder configured to decode the first data stream formatted according to a higher-layer protocol to produce trace data, the higher-layer decoder comprising: synchronisation logic configured to process the first data stream to detect a data pattern within the first data stream as a synchronisation event; and decoding logic configured to use the synchronisation event to synchronise decoding of the received first data stream to produce the trace data. | 04-14-2016 |
