Entries |
Document | Title | Date |
20080294965 | Data Writing Method For Flash Memory and Error Correction Encoding/Decoding Method Thereof - A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (2 | 11-27-2008 |
20080301532 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits. | 12-04-2008 |
20090024904 | Refresh of non-volatile memory cells based on fatigue conditions - In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block. | 01-22-2009 |
20090024905 | COMBINED DISTORTION ESTIMATION AND ERROR CORRECTION CODING FOR MEMORY DEVICES - A method for operating a memory device ( | 01-22-2009 |
20090044078 | ECC FUNCTIONAL BLOCK PLACEMENT IN A MULTI-CHANNEL MASS STORAGE DEVICE - A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels. | 02-12-2009 |
20090070657 | METHOD OF ERROR CORRECTION IN MBC FLASH MEMORY - A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods. | 03-12-2009 |
20090125790 | Method and Apparatus of Automatically Selecting Error Correction Algorithms by a NAND Flash Controller - A method and apparatus of automatically selecting an optimal ECC algorithm by NAND Flash controller to detect and correct errors to read or write data from or to a flash memory device is described. In one embodiment, the method includes selecting the optimal algorithm by identifying the characteristics of the target flash memory device such as but not limited to redundant data size. The method also includes determining the optimal algorithm based on the application stored in the target flash memory device. | 05-14-2009 |
20090158126 | EFFICIENT INTERFERENCE CANCELLATION IN ANALOG MEMORY CELL ARRAYS - A method includes storing data in a group of analog memory cells by writing first storage values to the cells. After storing the data, second storage values are read from the cells using one or more first read thresholds. Third storage values that potentially cause cross-coupling interference in the second storage values are identified, and the third storage values are processed, to identify a subset of the second storage values as severely-interfered values. Fourth storage values are selectively re-read from the cells holding the severely-interfered values using one or more second read thresholds, different from the first read thresholds. The cross-coupling interference in the severely-interfered storage values is canceled using the re-read fourth storage values. The second storage values, including the severely-interfered values in which the cross-coupling interference has been canceled, are processed so as to reconstruct the data stored in the cell group. | 06-18-2009 |
20090172499 | Patrol function used in flash storage controller to detect data errors - A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors. | 07-02-2009 |
20090204872 | Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules - A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands. | 08-13-2009 |
20090217136 | STORAGE APPARATUS, CONTROLLER AND DATA ACCESSING METHOD THEREOF - A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet. | 08-27-2009 |
20090222708 | ERROR CORRECTING DEVICE AND ERROR CORRECTING METHOD - An error correcting device for correcting erroneous data included in data read out from a nonvolatile memory includes a determining unit that determines whether the data read out from the nonvolatile memory include an error beyond an error correcting capability of the error correcting device. When the determining unit has determined that an error beyond the error correcting capability exists, the error correcting device does not perform the correction of the error. | 09-03-2009 |
20090241012 | MEMORY CONTROLLER - A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line. | 09-24-2009 |
20090259919 | FLASH MANAGEMENT USING SEPARATE MEDTADATA STORAGE - Disclosed are techniques for flash memory management, including storing metadata and/or error correcting information separately from payload data. In various embodiments, metadata and/or error correcting information are stored in a random access memory within a solid state drive. | 10-15-2009 |
20090282318 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device according to an aspect of the present invention includes a memory cell array that includes a ferroelectric capacitor and a selection transistor that selects a column of the memory cell array and connects the selected column to a bit line. A plate line applies a potential for reading or writing data to the ferroelectric capacitor. A sense amplifier circuit compares and amplifies a signal read from the ferroelectric capacitor to the bit line. A plate line control circuit controls a potential of the plate line synchronously with a clock signal. | 11-12-2009 |
20090300467 | Using a Phase Change Memory as a High Volume Memory - A phase change memory may be utilized in place of more conventional, higher volume memories such as static random access memory, flash memory, or dynamic random access memory. To account for the fact that the phase change memory is not yet a high volume technology, an error correcting code may be incorporated. The error correcting code may be utilized in ways which do not severely negatively impact read access times, in some embodiments. | 12-03-2009 |
20090319871 | MEMORY SYSTEM WITH SEMICONDUCTOR MEMORY AND ITS DATA TRANSFER METHOD - A data transfer method includes reading data from a NAND flash memory in pages into a first buffer, transferring a parity in the data read into the first buffer to a second buffer, after transferring the parity to the second buffer, transferring a main data in the data read into the first buffer to the second buffer, on the basis of the parity, correcting an error in the main data transferred to the second buffer, and transferring an error-corrected main data to a third buffer. | 12-24-2009 |
20090319872 | FAST, LOW-POWER READING OF DATA IN A FLASH MEMORY - A memory includes cells at intersections of word lines and bit lines, word and bit line selection mechanisms and a programming mechanism. The cells on each bit line are connected in series. Cells of a word line are programmed simultaneously. For low-power reading, only some of the bit lines that intersect the word line at the programmed cells are selected and only the cells at those intersections are sensed. Another type of memory includes a physical page of cells, a sensing mechanism and a selection mechanism. Hard bits are sensed from all the cells of the physical page. Only some of those cells are selected for sensing soft bits. Another memory includes a plurality of cells, a sensing mechanism, an export mechanism and a selection mechanism. Hard and soft bits are sensed from all the cells of the plurality. Only some of the soft bits are selected for export. | 12-24-2009 |
20090327839 | FLASH MEMORY DEVICE USING ECC ALGORITHM AND METHOD OF OPERATING THE SAME - A flash memory device using an error correction code (ECC) algorithm and a method of operating the same. The device includes a memory cell array including a error correction code (ECC) block including data memory cells configured to store data and a parity cell configured to store a first parity code, a parity controller configured to generate a second parity code based on a the current operating mode of the flash memory device, and an error correction unit configured to receive one of the first and second parity codes and to perform an ECC algorithm on the data stored in the data memory cells using the received parity code. A control logic restarts an erase operation on an erroneously unerased data memory cell or prevents the erase operation from being restarted based on the number of erroneous bits per ECC block. | 12-31-2009 |
20090327840 | REDUNDANT DATA DISTRIBUTION IN A FLASH STORAGE DEVICE - A flash storage device comprises a plurality of channels of flash storage, a system memory, and a controller. The controller is configured to cache, in the system memory, data to be written, to partition the data into a plurality of data portions, to generate error correction information based on the plurality of data portions, to write the error correction information to a first one or more of the plurality of channels of flash storage, and to write each of the plurality of data portions to a different one of the plurality of channels of flash storage other than the first one or more thereof. | 12-31-2009 |
20100017684 | DATA RECOVERY IN SOLID STATE MEMORY DEVICES - Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed. | 01-21-2010 |
20100042901 | SUPPORTING VARIABLE SECTOR SIZES IN FLASH STORAGE DEVICES - A flash storage device comprises a plurality of data blocks, each data block comprising a plurality of data segments, a system memory, and a controller. The controller is configured to cache in the system memory a plurality of data sectors to be written, to write to a first one of the plurality of data segments a first one of the plurality of data sectors, to write to the first one of the plurality of data segments a first portion of a second one of the plurality of data sectors, and to write to a second one of the plurality of data segments a second portion of the second one of the plurality of data sectors. | 02-18-2010 |
20100050053 | ERROR CONTROL IN A FLASH MEMORY DEVICE - Flash memory devices and associated methods are described for controlling data errors in the devices through various forms of decoding, error correction, and wear concentration. To this end, a flash memory device may be partitioned into a plurality of sectors. Data may then be received from, for example, a host processor for storage within the flash memory device. Storage durations of the data are then estimated and the data is stored in the data sectors based on those estimated storage durations. | 02-25-2010 |
20100058146 | CHIEN-SEARCH SYSTEM EMPLOYING A CLOCK-GATING SCHEME TO SAVE POWER FOR ERROR CORRECTION DECODER AND OTHER APPLICATIONS - Chien search apparatus operative to evaluate an error locator polynomial having a known rank and including a sequence of terms for each element in a finite field whose elements correspond respectively to bits in each of a stream of data blocks to be decoded, the apparatus comprising a sequence of functional units each operative to compute a corresponding term in the sequence of terms included in the error locator polynomial, each term having a degree; and a power saving unit operative to de-activate at least one individual functional unit from among the sequence of functional units, the individual functional unit being operative, when active, to compute a term whose degree exceeds the rank. | 03-04-2010 |
20100064200 | MEMORY SYSTEM AND DATA PROCESSING METHOD THEREOF - A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data. | 03-11-2010 |
20100122148 | APPARATUS, SYSTEM, AND METHOD FOR PREDICTING FAILURES IN SOLID-STATE STORAGE - An apparatus, system, and method are disclosed for predicting failures in solid-state storage and include a determination module a threshold module, a storage region error module, and a retirement module. The determination module determines that data stored in an ECC chunk contains Error Correcting Code (“ECC”) correctable errors and further determines a bit error count for the ECC chunk. The ECC chunk originates from non-volatile solid-state storage media. The threshold module determines that the bit error count satisfies an ECC chunk error threshold. The storage region error module determines that a storage region that contained contains at least a portion of the ECC chunk satisfies a region retirement criteria. The retirement module retires the storage region that contains at least a portion of the ECC chunk where the storage region satisfies the region retirement criteria. | 05-13-2010 |
20100146369 | Soft Error Protection in Individual Memory Devices - Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprises the step of maximizing a distance of the error correction code by maximizing a physical distance between memory bits associated with a memory line within the column protected by the error correction code. Other soft error protection techniques may include use of a feed forward error correction code or use of a memory operation (e.g., read or write operation) suppress and retry approach. | 06-10-2010 |
20100153821 | Solid-state memory with error correction coding - In a particular embodiment, a storage device is disclosed that includes a solid-state storage media. The storage device further includes a read/write circuit including an error correction coding (ECC) encoder/decoder adapted to write data and associated ECC information to the solid-state storage media without performing a read-verify operation. | 06-17-2010 |
20100162084 | Data error recovery in non-volatile memory - When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors. | 06-24-2010 |
20100162085 | Solid-state storage device including a high resolution analog-to-digital converter - A storage device includes a solid-state storage medium having a plurality of cells adapted to store data and an analog-to-digital converter (ADC) coupled to at least one cell of the plurality of cells. The ADC includes a first operating mode having a first number of quantization levels to determine a value stored in the at least one cell based on a number of possible values represented by the at least one cell. The ADC further includes a second operating mode having a second number of quantization levels to determine the value stored in the at least one cell, where the second number of quantization levels is greater than the first number of quantization levels. The ADC selectively enables the first or the second operating mode as a selected operating mode and determines a signal representative of the value stored in the at least one cell using the selected operating mode. | 06-24-2010 |
20100169743 | Error correction in a solid state disk - In some embodiments, a solid state disk includes a non-volatile memory and a controller. The controller performs ECC on data stored on the non-volatile memory, and performs a parity operation on the data if the ECC cannot correct the data. Other embodiments are described and claimed. | 07-01-2010 |
20100169744 | Progressively Programming Flash Memory While Maintaining Constant Error Correction Codes - In an embodiment, the invention provides a method for programming flash memory while maintaining a constant error correction term. A data field and forcing bits are arranged in a packing order. Next, all the forcing bits are set to a logical zero value. A first error correction term is generated using the data field and forcing bits as an input to an ECC encoding algorithm. An exclusive OR function is performed on the constant error correction term and the first error correction term creating a difference term. A forcing function is applied to the difference term creating a new value for the forcing bits. The data field and the forcing bits are written to the flash memory. | 07-01-2010 |
20100199149 | FLASH MEMORY APPARATUS AND METHODS USING A PLURALITY OF DECODING STAGES INCLUDING OPTIONAL USE OF CONCATENATED BCH CODES AND/OR DESIGNATION OF "FIRST BELOW" CELLS - A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful. | 08-05-2010 |
20100199150 | Data Storage In Analog Memory Cell Arrays Having Erase Failures - A method for data storage includes performing an erasure operation on a group of analog memory cells ( | 08-05-2010 |
20100205509 | SYSTEMS AND METHODS FOR EFFICIENT UNCORRECTABLE ERROR DETECTION IN FLASH MEMORY - A system and method for efficient uncorrectable error detection in flash memory is described. A microcontroller including a non-volatile flash memory utilizes an Error Correction Code (ECC) having a certain error detection and correction bit strength. The user data is first processed by a hash function and hash data is stored with the user data. Then, the user data and hash data are processed by the ECC system. In detection, the hash ensures that a relatively low bit-strength ECC system did not incorrectly manipulate the user data. Such a hash integrity check provides an efficient, robust detection of incorrectly corrected user data resulting from errors beyond the correction but strength of the ECC system utilized. | 08-12-2010 |
20100211852 | METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE - In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information. | 08-19-2010 |
20100211853 | High Reliability and Low Power Redundancy for Memory - An integrated circuit containing a memory array, a redundancy circuit and a redundancy error correction circuit coupled to said redundancy circuit. A method for constructing a redundancy word which corresponds to each memory segment and a method for error checking the redundancy word during a memory access request. | 08-19-2010 |
20100223532 | SYSTEMS, DEVICES AND METHODS USING REDUNDANT ERROR CORRECTION CODE BIT STORAGE - A device, e.g., a semiconductor memory device, includes a plurality of memory cells, each configured to store at least one data bit and a plurality of error correction code (ECC) cells configured to redundantly store ECC bits for the memory cells. According to some embodiments, the plurality of ECC cells includes a plurality of pairs of ECC cells configured to store an ECC bit and a complement thereof. According to further embodiments, the plurality of ECC cells includes a plurality of groups of at least three ECC cells configured to store identical copies of an ECC bit. | 09-02-2010 |
20100251074 | DECODING/ENCODING METHOD FOR BOOTING FROM A NAND FLASH AND SYSTEM THEREOF - A decoding method for booting from a NAND Flash including a booting page storing a plurality of copies of NAND booting information and a plurality of corresponding parities, each parity generated by an predetermined error correction code (ECC) bit number. The decoding method includes reading the booting page, for obtaining a plurality of configuration data and a plurality of ECC data, and performing a voting scheme and an ECC decoding process on the plurality of configuration data and the plurality of ECC data, for obtaining the NAND booting information. Besides, an encoding method for encoding such booting information is disclosed the same. | 09-30-2010 |
20100251075 | MEMORY CONTROLLER AND SEMICONDUCTOR MEMORY APPARATUS - A memory controller that has an error correction number correspondence table that stores an error threshold level in correspondence with an error correction number; an error threshold level storage section that stores an error threshold level for each block; an uncorrected number measurement section that measures an uncorrected number of an error correction for each block; an error threshold level modification section that, each time an uncorrected number of a certain block exceeds a predetermined number, modifies the error threshold level of the block; an encoder that performs encoding processing of data stored in memory cells belonging to each block with an error correction number that is based on an error threshold level and the error correction number correspondence table; and a decoder that performs decoding processing of data. | 09-30-2010 |
20100251076 | STORAGE CONTROLLER HAVING SOFT DECODER INCLUDED THEREIN, RELATED STORAGE CONTROL METHOD THEREOF AND SYSTEM USING THE SAME - An exemplary storage controller for controlling data access of a storage device includes a control circuit and a soft decoder. The control circuit is utilized for reading data from the storage device to obtain readout data. The soft decoder is coupled to the control circuit, and utilized for performing a soft decoding operation upon the readout data to generate decoded data. The soft decoder may be a low density parity check (LDPC) decoder, a block turbo code (BTC) decoder, or a convolutional turbo code (CTC) decoder. The storage device may be a flash memory device. | 09-30-2010 |
20100251077 | STORAGE DEVICE AND DATA STORAGE SYSTEM INCLUDING OF THE SAME - A storage device includes a controller unit and a memory cell array. The controller unit is for outputting data through a first data path or a second data path according to a property of externally supplied input data. The memory cell array includes a first memory and a second memory, and receives and stores the data from the controller unit output through the first and second data paths. The first memory has a different memory cell structure than the second memory. | 09-30-2010 |
20100262891 | METHOD FOR IDENTIFYING A FLASH MEMORY DEVICE AND RELATED HOSTING DEVICE - A method is for identifying a flash memory device coupled to a host device. The flash memory device may have a page size from possible page sizes, bootstrap code stored on a first sector thereof, and a data bus for accessing data stored in the flash memory device and with a data bus size from possible data bus sizes. The method may include reading data stored in a first page of the first sector as if the flash memory device had an assumed page size and an assumed data bus size, and reading content from memory locations where error correction code (ECC) bytes of the first page are stored if the flash memory device has the assumed page size and checking whether the ECC bytes include more than a number of errors associated with the assumed page size. The method may also include if the ECC bytes do not include more than the number of errors, generating a flag signal that the flash memory device has the assumed page size and the assumed data bus size. | 10-14-2010 |
20100262892 | DATA ACCESS METHOD FOR FLASH MEORY AND STORAGE SYSTEM AND CONTROLLER THEREOF - A data access method for accessing data in a flash memory is provided, wherein the data has a plurality of sub-data. The data access method includes generating an error correction code (ECC) for the data and writing the data and the ECC into the flash memory. The data access method also includes generating a corresponding bit checking code for each of the sub-data and writing the bit checking codes into the flash memory. When the sub-data subsequently is read from the flash memory, whether the sub-data contains any error is determined only according to the bit checking code corresponding to the sub-data. Thereby, the data access efficiency is improved. | 10-14-2010 |
20100281342 | MEMORY CONTROLLER AND MEMORY SYSTEM - A memory system is provided. The memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a memory cell array and a read/write circuit configured to perform a read/write operation in the memory cell array during a read operation. The controller is configured to receive the read data from the nonvolatile memory, perform an error detection and correction operation on the read data. Upon detecting an error in a received portion of the read data, the controller is further configured to halt further transmission of the read data from the nonvolatile memory, perform the error detection and correction operation on the received portion of the read data to correct the detected error. After correcting the detected error in the received portion of the read data, the controller is configured to resume transmission of the read data from the nonvolatile memory. | 11-04-2010 |
20100287448 | FLASH MEMORY DEVICE WITH RECTIFIABLE REDUNDANCY BIT AND METHOD OF CONTROLLING THE SAME - A flash memory device connected to a host includes: a flash memory; and a control circuit comprising a first error correcting code unit and a second error correcting code unit. The data length of a redundancy bit generated by the second error correcting code unit is longer than the data length of a redundancy bit generated by the first error correcting code unit. The first error correcting code unit is adopted to process with a data transmitted to the flash memory from the host when a damage risk of the flash memory is lower than a specific value; and the second error correcting code unit is adopted to process with the data transmitted to the flash memory from the host when the damage risk of the flash memory is higher than the specific value. | 11-11-2010 |
20100299577 | INTERSYMBOL INTERFERENCE ENCODING IN A SOLID STATE DRIVE - Methods and devices are provided for intersymbol interference encoding in a solid state drive. In an illustrative embodiment, an nth data signal is received as input to a processing component. An intersymbol interference signal applicable to the nth data signal is provided, based on a set of prior-written data in a data storage array and a set of intersymbol interference behavior of the set of prior-written data in the data storage array, the data storage array being communicatively connected to the processing component. The nth data signal and the intersymbol interference signal applicable to the nth data signal are combined into an intersymbol-interference-corrected encoding of the nth data signal. The intersymbol-interference-corrected encoding of the nth data signal is provided as output from the processing component. | 11-25-2010 |
20100325523 | FAULT-TOLERANT METHOD AND APPARATUS FOR UPDATING COMPRESSED READ-ONLY FILE SYSTEMS - A fault-tolerant approach for updating a compressed read-only file system in embedded devices using a two-step approach. In the first phase an update package creates an intermediate memory image where the data blocks are independently compressed so that, if needed, the data therein can be decompressed and read without access to any other surrounding data blocks. Then in the second phase the intermediate memory image is decompressed in a buffer so that it can be reimaged into its final form and order before being recompressed and written back to non-volatile memory over-writing the intermediate memory image. | 12-23-2010 |
20100325524 | CONTROL CIRCUIT CAPABLE OF IDENTIFYING ERROR DATA IN FLASH MEMORY AND STORAGE SYSTEM AND METHOD THEREOF - A flash memory control circuit including a microprocessor unit, a first interface unit for connecting a flash memory, a second interface unit for connecting a computer host, an error correcting unit, a memory management unit, and a marking unit is provided. The memory management unit divides each page in the flash memory into a plurality of data bit areas, and a plurality of redundancy bit areas and a plurality of error correcting bit areas corresponding to the data bit areas, wherein each of the data bit areas has a plurality of sectors for respectively storing a sector data. The marking unit stores a data accuracy mark corresponding to each sector data in the corresponding redundancy bit area to record the status of the sector data. Thereby, the flash memory controller can effectively identify error data in the flash memory by using the error correcting codes and the data accuracy marks. | 12-23-2010 |
20100332951 | METHOD FOR PERFORMING COPY BACK OPERATIONS AND FLASH STORAGE DEVICE - The invention provides a method for performing copy back operations. First, a copy back command is sent to a flash memory for reading a first error correction code (ECC) data from a first address. The first ECC data is then received from the flash memory. The first ECC data is then decoded without performing error correction to calculate a fail count of the first ECC data. The fail count is then compared with a first threshold value. When the fail count is less than the first threshold value, a first program command is sent to the flash memory for storing the first ECC data to a second address of the flash memory. When the fail count is less than the first threshold value, the first ECC data is not sent back to the flash memory. | 12-30-2010 |
20100332952 | Flash Memory Controller and the Method Thereof - An embodiment discloses a flash memory controller comprising a flash memory interface controller, a host interface controller, a random-access memory (RAM) interface controller, an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The flash memory interface controller is configured to store information data, ECC segments, and linked-lists to a flash memory and read information data, ECC segments, and the linked-lists from the flash memory. The host interface controller is configured to forward information data to a host and to receive information data from the host. The RAM interface controller is configured to store the linked-lists to a RAM device and read the linked-lists from the RAM device. The ECC encoder is configured to receive a write information datum from the host interface controller and generate an ECC datum, of which the length is variable, in response to the write information datum to be stored in the flash memory when operated in a write mode. The ECC divider is configured to divide the generated ECC datum into a plurality of ECC segments according to the length of the generated ECC datum and forward the divided ECC segments to the flash memory interface controller when operated in a write mode. The ECC constructor is configured to receive a plurality of ECC segments from the flash memory interface controller and construct an ECC datum by combining the received ECC segments for a read information datum received from the flash memory when operated in a read mode. The ECC decoder is configured to correct errors of the read information datum based on the read information datum and the constructed ECC datum and forward the corrected read information datum to the host interface controller when operated in a read mode. In addition, the link relation of the ECC segments in the flash memory is indicated by the linked-lists. | 12-30-2010 |
20110010606 | MEMORY SYSTEM - A memory system that can efficiently relieve a large number of defective bits with a small number of redundant bits is provided in a Flash-EEPROM nonvolatile memory. A memory system according to an embodiment of the present invention comprises a Flash-EEPROM memory in which a plurality of memory | 01-13-2011 |
20110016372 | Prediction and cancellation of systematic noise sources in non-volatile memory - Various embodiments of the invention pertain to a technique of recovering data from a portion of a non-volatile memory which was not reliably read because the number of read errors exceeded the ability of the ECC process to correct those errors. For each cell in that portion of memory, a quantized estimate is made of the amount of offset in the read reference voltage that is predicted to correct for any systematic noise that may have affected the reading of that cell. For each quantized offset, the read reference voltage is adjusted by that amount and data from the relevant cells is read. The combined results for all the cells are then processed through the ECC again. | 01-20-2011 |
20110041039 | Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device - The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of bad blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 02-17-2011 |
20110041040 | Error Correction Method for a Memory Device - An error correction method for a memory device is disclosed. A base reading of a memory device is performed, and an error correction code (ECC) decoding is performed on the data read out of the memory device. The memory device is further read when the result of the ECC decoding is not strongly determined, wherein extra information acquired in the further reading of the memory device is used in the ECC decoding. | 02-17-2011 |
20110047441 | CHIEN SEARCH DEVICE AND CHIEN SEARCH METHOD - To provide a Chien search device and a Chien search method capable of performing a Chien search process at a high speed. The Chien search device calculates an error position at the time of correcting an error included in data read from a nonvolatile memory, and includes a first processing unit that performs a search process of an error position in at least one-bit unit to an error-correction area of input data, and a second processing unit that processes at one time plural bits in an non-error-correction-target area of the input data. | 02-24-2011 |
20110047442 | FORWARD ERROR CORRECTION FOR MEMORIES - Methods, systems, and devices are described for forward error correction for flash memory. Encoded data from flash memory may be used to generate a number of data streams. At each of a number of error detection sub-modules operating in parallel, a different one of the data streams is processed. Each error detection sub-module may detect whether a portion of the respective received stream contains an error, and forward the portion to an error correction module. The error correction module, physically separate from the error detection sub-modules, may correct the forwarded portions of the respective received streams containing an error. The age and error rate associated with the flash memory may be monitored, and a coding rate or other aspects may be dynamically adapted to account for these factors. | 02-24-2011 |
20110060967 | Systems and Methods for Re-Designating Memory Regions as Error Code Corrected Memory Regions - Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location. | 03-10-2011 |
20110060968 | Systems and Methods for Implementing Error Correction in Relation to a Flash Memory - Various embodiments of the present invention provide systems, methods and circuits for memories and utilization thereof. As one example, a memory system is disclosed that includes a flash memory device and a flash access circuit. The flash access circuit is operable to perform an error code encoding algorithm on a data set to yield an error code, to write the data set to the flash memory device at a first location, and to write the error code to the flash memory device at a second location. | 03-10-2011 |
20110060969 | METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY - A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels. | 03-10-2011 |
20110066922 | Error correction for multilevel flash memory - An integrated circuit is provided with an array of multilevel flash memory cells. In one embodiment these flash memory cells have a storage signal level which is Gray coded to output data bits thereby increasing the independence between bit errors. The error correction circuitry targets independent identical distributed error patterns. In another embodiment, the storage signal levels are read to generate n-bit symbols which are then subject to error correction with an error correction mechanism targeted at the error properties of those n-bit symbols. The data is read in sets of symbols such that the error correction targeted at those symbols will be more efficient. | 03-17-2011 |
20110066923 | NONVOLATILE MEMORY APPARATUS, MEMORY CONTROLLER, AND MEMORY SYSTEM - Disclosed herein is a nonvolatile memory apparatus including, a nonvolatile memory section, a standard error correction code processing section, an extended error correction code processing section, and a control section. | 03-17-2011 |
20110072333 | CONTROL METHOD FOR FLASH MEMORY BASED ON VARIABLE LENGTH ECC - A control method for flash memory based on variable length ECC is provided in the present invention. A first channel of the flash memory is set to have a first ECC with a first length based on the size of data page and the length of first management data; and a second channel of the flash memory is set to have a second ECC with a second length based on the size of data page and the length of second management data. The first ECC and the second ECC are designated with different identification codes respectively, wherein the first length is shorter than the second length. | 03-24-2011 |
20110078544 | Error Detection and Correction for External DRAM - One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost. | 03-31-2011 |
20110087950 | DATA WRITING METHOD FOR A FLASH MEMORY, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME - A data writing method for writing data from a host system into a flash memory chip is provided, and the flash memory chip have a plurality of physical blocks. The method includes receiving a host writing command and write data thereof, and executing the host writing command. The method also includes giving a data program command for writing the write data into one of the physical blocks to the flash memory chip, and giving a command for determining whether data stored in the physical block has any error bit. Accordingly, the method can effectively ensure the correctness of data to be written into the flash memory chip. | 04-14-2011 |
20110093765 | FLASH MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A nonvolatile memory device comprises a memory cell array configured to store one or more bits per memory cell, a read and write circuit configured to access the memory cell array, a control logic component configured to control the read and write circuit to sequentially execute read operations of a selected memory cell at least twice to output a read data symbol, and an error correcting unit configured to correct an error in the read data symbol based on a pattern of the read data symbol to output an error-corrected symbol. | 04-21-2011 |
20110093766 | PROGRAMMING MANAGEMENT DATA FOR A MEMORY - Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Methods, apparatus, systems, and data structures may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additionally, various methods, apparatus, systems, and data structures may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector. | 04-21-2011 |
20110099460 | Non-Volatile Memory And Method With Post-Write Read And Adaptive Re-Write To Manage Errors - Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced. | 04-28-2011 |
20110107188 | SYSTEM AND METHOD OF DECODING DATA - A decoder is disclosed that can reduce power consumption at different stages of a decoding process. At a first stage where the decoder calculates residual values, the decoder can reduce power consumption by calculating residual values using less than a full set of division circuits. A reduced number of division circuits may be sufficient to successfully calculate residuals associated with the codeword to complete the decoding process. Division circuits that are not used may be disabled to reduce power consumption. At another stage of the decoding process where the decoder generates coefficients that are used to identify locations of errors in the codeword, the decoding process can limit power consumption by reducing the number of iterations of a polynomial generator by incorporating termination decision circuitry. | 05-05-2011 |
20110113305 | HIGH THROUGHPUT INTERLEAVER / DEINTERLEAVER - Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM. | 05-12-2011 |
20110113306 | MEMORY DEVICE WITH ERROR DETECTION - Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller. | 05-12-2011 |
20110119564 | FLASH MEMORY DEVICE AND MEMORY SYSTEM COMPRISING SAME - A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data. | 05-19-2011 |
20110131472 | SOLID-STATE STORAGE SYSTEM WITH PARALLEL ACCESS OF MULTIPLE FLASH/PCM DEVICES - Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate. | 06-02-2011 |
20110131473 | Method For Decoding Data In Non-Volatile Storage Using Reliability Metrics Based On Multiple Reads - Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge. | 06-02-2011 |
20110138253 | RAM LIST-DECODING OF NEAR CODEWORDS - Certain embodiments of the present invention are efficient run-time methods for creating and updating a RAM list of dominant trapping-set profiles for use in (LDPC) list decoding. A decoded correct codeword is compared to a near codeword to generate a new trapping-set profile, and the profile written to RAM. Record is kept of how many times RAM has been searched since a profile was last matched. Profiles that have not been matched within a specified number of searches are purge-eligible. Purge-eligible profiles are further ranked on other factors, e.g., number of times a profile has been matched since it was added, number of unsatisfied check nodes, number of erroneous bit nodes. If there is insufficient free space in RAM to store a newly-discovered profile, then purge-eligible profiles are deleted, beginning with the lowest-ranked profiles, until either (i) sufficient free space is created or (ii) there are no more purge-eligible profiles. | 06-09-2011 |
20110138254 | METHOD FOR REDUCING UNCORRECTABLE ERRORS OF A MEMORY DEVICE REGARDING ERROR CORRECTION CODE, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. An associated memory device and the controller thereof are further provided. | 06-09-2011 |
20110145681 | SOFT DECODING FOR QUANTIZIED CHANNEL - Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, an apparatus includes a soft decoder configured to decode a signal received from a quantized channel based, at least in part, on one or more log likelihood ratios (LLRs). The apparatus may also include a reliability memory configured to store one or more known LLRs, and a controller configured to repetitively and selectively provide the soft decoder with known LLRs chosen from the reliability memory, to control the soft decoder to decode the signal, and to selectively update the reliability memory upon determining that the soft decoder successfully decoded the signal. | 06-16-2011 |
20110154162 | DATA WRITING METHOD FOR A FLASH MEMORY, AND FLASH MEMORY CONTROLLER AND FLASH MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for a flash memory, and a flash memory controller and a flash memory storage apparatus using the same are provided. First, data is received from a host system. Next, the data is divided into at least one frame. Afterwards, an error checking and correcting (ECC) code corresponding to the frame is generated so as to form at least one ECC frame. Then, the ECC frame is divided into a plurality of frame segments. Finally, the frame segments are written into a flash memory chip according to a non-sequentially ranking order. | 06-23-2011 |
20110154163 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 06-23-2011 |
20110167320 | FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. | 07-07-2011 |
20110191654 | ADJUSTABLE ERROR CORRECTION CODE LENGTH IN AN ELECTRICAL STORAGE DEVICE - An apparatus includes a memory that is allocated to reported portions and overprovisioned portions. The apparatus includes an error correction circuit that communicates with the memory in error correction coded data that has a controllable ECC length. The ECC length is a function of a history of error reports. A memory allocation engine balances a size of the overprovisioned portions to maintain a size of the reported portions. The balancing is performed as a function of an average of ECC lengths in the ECC length table over a time interval in which a size of the memory decreases with accumulated erase cycles of the memory. | 08-04-2011 |
20110191655 | MEMORY ARRAY ERROR CORRECTION APPARATUS, SYSTEMS, AND METHODS - Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles. | 08-04-2011 |
20110197109 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code. | 08-11-2011 |
20110197110 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code. | 08-11-2011 |
20110202818 | NON-VOLATILE MEMORY DEVICE AND OPERATION METHOD USING THE SAME - The non-volatile memory system includes a non-volatile memory and a controller. The non-volatile memory includes a data region including a sector region for storing sector data, and an uncorrectable information region for storing uncorrectable sector information on the sector region. The controller includes an information generation unit for generating the uncorrectable sector information that indicates whether the sector region is assigned to an uncorrectable sector region, according to a command output from a host. | 08-18-2011 |
20110209032 | Nonvolatile Memory Devices with Age-Based Variability of Read Operations and Methods of Operating Same - Integrated circuit memory systems include a nonvolatile memory device having an array of nonvolatile memory cells therein and a memory controller, which is electrically coupled to the nonvolatile memory device. The memory controller is configured to apply signals to the nonvolatile memory device that cause the nonvolatile memory device to modify how data is read from the array of nonvolatile memory cells. This modification occurs in response to detecting an increase in an age of the nonvolatile memory device. The age of the nonvolatile memory device may be determined by keeping a count of how many times the nonvolatile memory device has undergone a program/erase cycle. | 08-25-2011 |
20110231738 | ERROR CORRECTION DECODING APPARATUS AND ERROR CORRECTION DECODING METHOD - According to one embodiment, an error correction decoding apparatus including a hard-decision decoding module which performs hard-decision decoding using a signal with 2 levels per bit as input data and runs a parity check on the input data, a soft-decision decoding module which performs soft-decision decoding using a signal with the number of multiple levels per bit larger than 2 as input data, a start-up control module which controls the start-up of each of the decoding modules, and an output selection module which selects one of the output signals of the decoding modules. The start-up control module causes the output selection module to select the decoding result of the hard-decision decoding module when the parity errors is a permitted value and causes the output selection module to select the decoding result of the soft-decision decoding module when the parity errors has exceeded the permitted value. | 09-22-2011 |
20110231739 | COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION - A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data. | 09-22-2011 |
20110231740 | Method for Recovering From Errors in Flash Memory - Methods, devices and computer readable code for reading data from one or more flash memory cells, and for recovering from read errors are disclosed. In some embodiments, in the event of an error correction failure by an error detection and correction module, the flash memory cells are re-read at least once using one or more modified reference voltages, for example, until a successful error correction may be carried out. In some embodiments, after successful error correction a subsequent read request is handled without re-writing data (for example, reliable values of the read data) to the flash memory cells in the interim. In some embodiments, reference voltages associated with a reading where errors are corrected may be stored in memory, and retrieved when responding to a subsequent read request. In some embodiments, the modified reference voltages are predetermined reference voltages. Alternatively or additionally, these modified reference voltages may be determined as needed, for example, using randomly generated values or in accordance with information provided by the error detection and correction module. Methods, devices and computer readable code for reading data for situations where there is no error correction failure are also provided. | 09-22-2011 |
20110239092 | MEMORY SYSTEM - According to one embodiment, a memory system includes a semiconductor memory, a converter configured to convert an input data input from the semiconductor memory into a log likelihood ratio based on a conversion function, a conversion function optimizing unit configured to optimize the conversion function used for the converter, and a decoding operation unit configured to input the log likelihood ratio output from the converter to execute a decoding operation of an error correcting code. The conversion function optimizing unit optimizes the conversion function based on information related to a number of times of using the semiconductor memory. | 09-29-2011 |
20110239093 | FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY - Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices. | 09-29-2011 |
20110246859 | METHODS AND APPARATUS FOR COMPUTING SOFT DATA OR LOG LIKELIHOOD RATIOS FOR RECEIVED VALUES IN COMMUNICATION OR STORAGE SYSTEMS - Methods and apparatus are provided for computing soft data or log likelihood ratios for received values in communication or storage systems. Soft data values or log likelihood ratios are computed for received values in a communication system or a memory device by obtaining at least one received value; identifying a segment of a function corresponding to the received value, wherein the function is defined over a plurality of segments, wherein each of the segments has an associated set of parameters; and calculating the soft data value or log likelihood ratio using the set of parameters associated with the identified segment. The computed soft data values or log likelihood ratios are optionally provided to a decoder. | 10-06-2011 |
20110246860 | Semiconductor Integrated Circuit - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 10-06-2011 |
20110258517 | DATA WRITING METHOD AND SYSTEM - A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased. | 10-20-2011 |
20110283164 | CONFIGURABLE CODING SYSTEM AND METHOD OF MULTIPLE ECCS - A configurable coding system and method of multiple error correcting codes (ECCs) for a memory device or devices are disclosed. The system includes an ECC codec that selectively performs different error corrections with different parameters. The system also includes means for providing a selected parameter to the ECC codec for initializing the ECC codec. The parameter used for initializing the ECC codec is an error-free parameter. | 11-17-2011 |
20110283165 | MEMORY SYSTEM AND DATA TRANSFER METHOD OF THE SAME - According to one embodiment, a memory system includes a nonvolatile memory, a first buffer configured to temporarily store data transferred from the nonvolatile memory, a correction circuit configured to correct an error of data transferred from the first buffer, a second buffer configured to temporarily store data transferred from the correction circuit, a bus configured to receive data transferred from the second buffer, a command sequencer group configured to issue commands for data transfer between the nonvolatile memory and the bus, a command decoder group configured to decode the commands, and generate control signals for controlling data transfer, a CPU connected to the bus, and an interrupt circuit configured to generate an interrupt in the CPU if a read error occurs because of an error correction failure. The command sequencer group continues data transfer from the nonvolatile memory even when an interrupt occurs because of the read error. | 11-17-2011 |
20110283166 | STORAGE DEVICE HAVING A NON-VOLATILE MEMORY DEVICE AND COPY-BACK METHOD THEREOF - A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation. | 11-17-2011 |
20110289388 | PERSISTENT MOVING READ REFERENCE - A device, method, machine-readable medium, and system are disclosed. In one embodiment the device is a memory controller capable of modifying a reference voltage to a persistent moving read reference (MRR) voltage level for use during one or more subsequent reads to a non-volatile memory array. This modification is in response to a change in a reference voltage supplying the non-volatile memory array from a previous reference voltage level to a temporary MRR voltage level. | 11-24-2011 |
20110289389 | Optimized Flash Memory Access Method and Device - A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different data storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing error correction codes of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region. | 11-24-2011 |
20110296276 | Dynamic Buffer Management In A NAND Memory Controller To Minimize Age Related Performance Degradation Due To Error Correction - An output buffer circuit for a non-volatile memory stores a plurality of data bits and a plurality of error correction check (“ECC”) bits associated with the plurality of data bits. The output buffer circuit comprises an error check circuit for receiving the plurality of data bits and the plurality of ECC bits to determine if the plurality of data bits need to be corrected. The error check circuit supplies the plurality of data bits as its output, and generates a correction signal. An error correction circuit receives the plurality of data hits and the plurality of ECC bits and generates a plurality of corrected data bits in response to the correction signal. The output buffer circuit further has three or more storage circuits with each storage circuit having an input/output port. A bus connects to each of the storage circuits and to each other and supplies data bits between each storage circuit and between the nonvolatile memory and the storage circuits, and supplies data bits as the output of the output buffer circuit. A switch circuit is associated with each storage circuit for receiving the plurality of data bits; or the plurality of corrected data bits, and supplies same to the input/output port of the associated storage circuit and stores same as storage bits in the storage circuit, and supplies the storage bits as output of the storage circuit. | 12-01-2011 |
20110296277 | APPARATUS, SYSTEM, AND METHOD FOR A FRONT-END, DISTRIBUTED RAID - An apparatus, system, and method are disclosed for a front-end, distributed redundant array of independent drives (“RAID”). A storage request receiver module receives a storage request to store object or file data in a set of autonomous storage devices forming a RAID group. The storage devices independently receive storage requests from a client over a network, and one or more of the storage devices are designated as parity-mirror storage devices for a stripe. The striping association module calculates a stripe pattern for the data. Each stripe includes N data segments, each associated with N storage devices. The parity-mirror association module associates a set of the N data segments with one or more parity-mirror storage devices. The storage request transmitter module transmits storage requests to each storage device. Each storage request is sufficient to store onto the storage device the associated data segments. The storage requests are substantially free of data. | 12-01-2011 |
20110296278 | MEMORY DEVICE INCLUDING MEMORY CONTROLLER - A memory device includes a semiconductor memory including a plurality of memory cells, and a controller including a buffer which temporarily stores data, a data pattern check circuit which checks a predetermined data pattern of data that are stored in the buffer and are to be stored in a plurality of neighboring ones of the memory cells, and sends an address in accordance with a result of the check, and a data correction circuit which corrects a value of data at the address that is sent, and sends the corrected value to the semiconductor memory. | 12-01-2011 |
20110302477 | Data Hardening to Compensate for Loss of Data Retention Characteristics in a Non-Volatile Memory - Method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells. In accordance with various embodiments, a controller is adapted to harden data stored in a first location of said memory in relation to a detected loss of retention characteristics of the first location. In some embodiments, the data are hardened by storing redundancy information associated with said data in a second location of said memory. The redundancy information can be a redundant set of the data or higher level error correct codes (ECC). The hardened data can be recovered to the host during a read operation by accessing the data stored in both the first and second locations. | 12-08-2011 |
20110307764 | Data transfer protection apparatus for flash memory controller - The invention discloses a data transfer protection apparatus for a flash memory controller, placed between BCH and NAND Flash Chip. In encode path the hardware module selects a sequence of constant values, exclusive-or the original parity with that constant value. In decode path the hardware module detects the parity period, exclusive-or the parity which is read out from NAND Flash Chip with the same constant value sequence. | 12-15-2011 |
20110320915 | METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE AND/OR RELIABILITY OF A SOLID-STATE DRIVE - A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page. | 12-29-2011 |
20120005558 | SYSTEM AND METHOD FOR DATA RECOVERY IN MULTI-LEVEL CELL MEMORIES - A system and method are provided for data recovery in a multi-level cell memory device. One or more bits may be programmed sequentially in one or more respective levels of multi-level cells in the memory device. An interruption of programming a subsequent bit in a subsequent second or greater level of the multi-level cells may be detected. Data may be recovered from the multi-level cells defining the one or more bits programmed preceding the programming interruption of the second or greater level. | 01-05-2012 |
20120005559 | APPARATUS AND METHOD FOR MANAGING A DRAM BUFFER - An apparatus and method for managing a dynamic random access memory (DRAM) buffer are disclosed. The DRAM buffer managing apparatus and method may generate an error correction code (ECC) for data to be written in a DRAM buffer, and may write the data and the ECC in the DRAM buffer. | 01-05-2012 |
20120011416 | ECC CONTROLLER FOR USE IN FLASH MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - An ECC (error correction code) controller of a flash memory device which stores an M-bit data (M being a positive integer equal to or greater than 2) comprises a first ECC block which generates a first ECC data from a program data to be stored in the flash memory device according to a first error correcting method and a second ECC block which generates a second ECC data from the first ECC data and the program data output from the first ECC block according to a second error correcting method, the program data, the first ECC data, and the second ECC data being stored in the flash memory device. | 01-12-2012 |
20120017138 | Adaptive Flash Interface - A structure, and corresponding operating techniques, are presented for the internal controller to memory circuit interface for memory systems such a flash memory card or other similarly structured devices. The interface between the controller circuit and memory circuit (or circuits) includes a feedback process where the amount of error that arises due to controller-memory transfers is monitored and the transfer characteristics (such as clock rate, drive strength, etc.) can be modified accordingly. For example, in addition to transferring a set of data, the transmitting side also generates and transmits a corresponding hash value for the set of data. When the set of data is received on the other side, a hash value is also generated there and compared to the received hash value to determine if these was transmission error. If there is no error, the transfer rate could, for example, be increased, while if there were error, it could be decreased. | 01-19-2012 |
20120017139 | INFORMATION RECORDING AND REPRODUCING APPARATUS - An information recording and reproducing apparatus writes user data received from an external device into a recording medium and reads the user data from the recording medium so as to transmit the user data to the external terminal. The information recording and reproducing apparatus includes an external interface unit operable to transmit and receive the user data to and from the external device, a first ECC generator operable to generate parity data corresponding to the user data, an access unit operable to control recording and reading of the user data or the parity data to and from the recording medium, a recording controller operable to record the user data and the first parity data to the recording medium via the access unit, an ECC correcting unit operable to correct an error of the user data read from the recording medium using the parity data read from a nonvolatile memory via the access unit, and a reproducing controller having a first reproducing mode for reading and reproducing the user data without reading the parity data from the recording medium at the time of reproducing data and a second reproducing mode for reading and reproducing at least the parity data from the recording medium, the reproducing controller operable to detect presence or non-presence of an error of the user data read from the recording medium during execution of the first reproducing mode and executing the second reproducing mode when the presence of an error is detected. | 01-19-2012 |
20120023387 | CONTROLLING METHODS AND CONTROLLERS UTILIZED IN FLASH MEMORY DEVICE FOR REFERRING TO DATA COMPRESSION RESULT TO ADJUST ECC PROTECTION CAPABILITY - A controlling method utilized in a flash memory device includes: compressing first data received from a host to generate second data; generating record data according to the first data and the second data where the record data records error correct coding (ECC) control information at least; executing ECC protection upon specific data selected from the first and second data to generate third data; and writing the third data into the flash memory device. | 01-26-2012 |
20120030545 | ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING - Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes. | 02-02-2012 |
20120066571 | KEY EXTRACTION IN AN INTEGRATED CIRCUIT - A method of extraction of a key from a physical unclonable function exploiting the states of cells of a volatile memory after a powering on, wherein: cells are read according to addresses stored in a non-volatile memory; an error-correction code corrects the read states; and, in case an error has been corrected, the address of the cell providing an erroneous state is replaced in the non-volatile memory with that of another cell providing the non-erroneous state. | 03-15-2012 |
20120072805 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD THEREOF FOR GENERATING LOG LIKELIHOOD RATIO - A memory storage device, a memory controller, and a log likelihood ratio (LLR) generation method are provided. A read data corresponding to a first storage state is obtained from memory cells of a flash memory chip in the memory storage device by using bit data read voltages. An error checking and correcting procedure is performed on the read data to obtain a second storage state corresponding to the read data when the read data is written. An amount of storage error is obtained in storage states satisfying a statistic number, and a storage error means that data is in the second storage state when being written and is in the first storage state when being read. A logarithmic operation is executed according to the statistic number, an amount of the storage states, and the amount of storage error to generate a first LLR of the read data. | 03-22-2012 |
20120072806 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory including an array of memory cells. A buffer comprises latches to hold data from the memory cells. The latches constitute latch groups. The latches of each latch group are connected to corresponding one common line through a transfer circuit. An error corrector is connected to the common lines and detects an error bit in received data. A data transfer controller causes the buffer to read out data from memory cells to be verified, repeats reading out of all data in the latches in one latch group to corresponding one of common lines as to-be-verified data segment for different latch groups, and transfers the to-be-verified data segments to the error corrector. A verify controller causes the error corrector to determine whether an error bit is included in to-be-verified data includes the to-be-verified data segments. | 03-22-2012 |
20120072807 | ACCESSING METADATA WITH AN EXTERNAL HOST - Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host. | 03-22-2012 |
20120079353 | Memory Quality Monitor Based Compensation Method and Apparatus - In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected. | 03-29-2012 |
20120079354 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit. | 03-29-2012 |
20120096332 | SELECTIVE ERROR CONTROL CODING IN MEMORY DEVICES - A method includes determining that a received data stream includes metadata and content, applying error control coding to the received metadata, disabling error control coding for the received content, and storing the metadata, the error control coding, and the content in a memory device. | 04-19-2012 |
20120096333 | DATA INPUT AND OUTPUT METHOD OF NAND FLASH MEMORY AND EMBEDDED SYSTEM USING THE SAME - A data input method of a NAND flash memory includes: determining whether a size of a writing-requested data is less than a reference value; calculating an error correction code (ECC) for the data using a software ECC method when the data size is less than the reference value; and writing the data and the ECC to a data region of the NAND flash memory. A data output method of the NAND flash memory includes: determining whether a size of a reading-requested data is less than a reference value; reading the data and an error correction code (ECC) from the NAND flash memory; calculating an ECC for the read data using a software ECC method when the data size is less than the reference value; and performing an error detection and correction by comparing the calculated ECC and the read ECC. | 04-19-2012 |
20120096334 | Error Detecting/Correcting Scheme For Memories - A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation. | 04-19-2012 |
20120096335 | DATA PROCESSING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - A read process is performed on an ith designated block storing an ith divided data string. If the ith divided data string is not normally read, the read process is sequentially executed on ith ordinary blocks each storing the ith divided data string, where the ith ordinary blocks are included in ordinary block groups, respectively. When the ith divided data string is normally read, it is determined whether or not reading p divided data strings has been completed. If it is determined that the reading the p divided data strings has not been completed, the read process is performed on an (i+1)th designated block storing an (i+1)th divided data string following the ith divided data string. | 04-19-2012 |
20120110417 | HYBRID ERROR CORRECTION CODING TO ADDRESS UNCORRECTABLE ERRORS - A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data. | 05-03-2012 |
20120110418 | Advanced Data Encoding With Reduced Erasure Count For Solid State Drives - Technologies are generally described herein for encoding a message. Technologies are also generally described herein for decoding an encoded message. The message may be encoded and/or decoded according to a mapping rule. The mapping rule may enable multiple messages to be successively written to the same block in a solid state drive without an erasure operation. | 05-03-2012 |
20120110419 | Data Structure for Flash Memory and Data Reading/Writing Method Thereof - A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively. | 05-03-2012 |
20120124450 | METHOD FOR ENHANCING ERROR CORRECTION CAPABILITY, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for enhancing error correction capability of a controller of a memory device without need to increase a basic error correction bit count of an Error Correction Code (ECC) engine includes: according to an error correction magnification factor, respectively obtaining a plurality of portions of data, where the portions are partial data to be encoded/decoded; and regarding the portions that are the partial data to be encoded/decoded, respectively performing encoding/decoding corresponding to the error correction magnification factor, in order to generate encoded/decoded data corresponding to a predetermined error correction bit count, where a ratio of the predetermined error correction bit count to the basic error correction bit count is equal to the error correction magnification factor. An associated memory device and the controller thereof are further provided. | 05-17-2012 |
20120124451 | OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION CODE STORAGE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. In some embodiments, the memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N. | 05-17-2012 |
20120144272 | PROBABILISTIC MULTI-TIER ERROR CORRECTION IN NOT-AND (NAND) FLASH MEMORY - Error correction in not-and (NAND) flash memory including a system for retrieving data from memory. The system includes a decoder in communication with a memory. The decoder is for performing a method that includes receiving a codeword stored on a page in the memory, the codeword including data and first-tier check symbols that are generated in response to the data. The method further includes determining that the codeword includes errors that cannot be corrected using the first-tier check symbols, and in response second-tier check symbols are received. The second-tier check symbols are generated in response to receiving the data and to the contents of other pages in the memory that were written prior to the page containing the codeword. The codeword is corrected in response to the second-tier check symbols. The corrected codeword is output. | 06-07-2012 |
20120144273 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N≧2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits. | 06-07-2012 |
20120151301 | SEMICONDUCTOR MEMORY DEVICE - This memory includes: bit lines; word lines crossing the bit lines; a memory cell array including memory cells provided to correspond to intersections between the bit lines and the word lines, respectively. A sense amplifier is connected to the bit lines and detects data stored in the memory cells. A word line driver controls a voltage of the word lines. An error-correcting unit includes a first error-correcting circuit having a first error-correcting capability and a second error-correcting circuit having a second error-correcting capability. The memory cells connected to each of the word lines in the memory cell block constitute a page. The error-correcting unit drives one of or both of the first and second error-correcting circuits during a data read operation or a data write operation according to a step count which is number of times of stepping up the voltage of the word lines during the data write operation. | 06-14-2012 |
20120166913 | Non-Volatile Memory And Methods With Asymmetric Soft Read Points Around Hard Read Points - A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits. | 06-28-2012 |
20120173955 | DATA WRITING AND READING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A data writing method for a rewritable non-volatile memory module is provided. The present method includes compressing an original data to generate a first data and determining whether the length of the first data is smaller than a predetermined length. The present method also includes outputting the first data as a compressed data when the length of the first data is not smaller than the predetermined length. The present method further includes generating an ECC code corresponding to the compressed data, generating an ECC frame according to the compressed data and the ECC code, and writing the ECC frame into the rewritable non-volatile memory module. Accordingly, when data corresponding to the original data is read from the rewritable non-volatile memory module, error bits in the data can be corrected and the original data can be restored according to the ECC code. | 07-05-2012 |
20120173956 | MEMORY DEVICE USING ERROR CORRECTING CODE AND SYSTEM THEREOF - A memory device using error correcting code and a system including the same are provided. The memory system includes a memory device, and a storage block connected to the memory device. The memory device includes a normal cell region including a first plurality of memory cells for storing data bits, and an error correcting code (ECC) cell region including a second plurality of memory cells for storing first through mth sets of ECC bits. The storage block includes a third plurality of memory cells for storing first through nth sets of the ECC bits. Each memory cell of the first and second plurality of memory cells is a first type of memory cell and each memory cell of the third plurality of memory cells is a second type of memory cell different from the first type of memory cell. | 07-05-2012 |
20120179953 | Semiconductor Integrated Circuit - A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information, and the second nonvolatile memory area can be prioritized to guarantee the number of times of rewrite operation of memory information more. | 07-12-2012 |
20120185753 | Structure of ECC Spare Bits in 3D Memory - A structure of 3D memory comprises a plurality of stacking layers and a plurality of cells. The stacking layers are arranged in a three-dimensional array and disposed parallel to each other on a substrate, and the stacking layers comprises a plurality of stacking memory layers. The cells comprises a first group of cells (such as m of cells) for storing information data and a second group of cells (such as n of cells) for storing ECC (error checking and correcting) spare bits. All of the first group and the second group of cells are read out at the same time for performing an ECC function. The ECC spare bits in the 3D memory according to the present disclosure can be constructed at the same physical layer or at the different physical layers. The embodiments can be implemented, but not limited, by a vertical-gate (VG) structure or a finger VG structure. | 07-19-2012 |
20120185754 | FLASH MEMORY ARCHITECTURE WITH SEPARATE STORAGE OF OVERHEAD AND USER DATA - A memory device has a plurality of dedicated data blocks for storing only user data and a plurality of dedicated overhead blocks for storing only overhead data that comprises ECC data that is used for error checking with respect to the user data in the dedicated data blocks. The dedicated data blocks can be erased without erasing the ECC data that is used for error checking with respect to the user data in the dedicated data blocks. | 07-19-2012 |
20120198313 | METHOD OF READING AND WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE - A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort. | 08-02-2012 |
20120226963 | BAD BLOCK MANAGEMENT FOR FLASH MEMORY - Bad block management for flash memory including a method for storing data. The method includes receiving a write request that includes write data. A block of memory is identified for storing the write data. The block of memory includes a plurality of pages. A bit error rate (BER) of the block of memory is determined and expanded write data is created from the write data in response to the BER exceeding a BER threshold. The expanded write data is characterized by an expected BER that is lower than the BER threshold. The expanded write data is encoded using an error correction code (ECC). The encoded expanded write data is written to the block of memory. | 09-06-2012 |
20120240011 | METHODS, DEVICES, AND SYSTEMS FOR DATA SENSING - The present disclosure includes methods and devices for data sensing. One such method includes performing a number of successive sense operations on a number of memory cells using a number of different sensing voltages, determining a quantity of the number memory cells that change states between consecutive sense operations of the number of successive sense operations, and determining, based at least partially on the determined quantity of the number of memory cells that change states between consecutive sense operations, whether to output hard data corresponding to one of the number of successive sense operations. | 09-20-2012 |
20120240012 | APPARATUS AND METHOD FOR MULTI-MODE OPERATION OF A FLASH MEMORY DEVICE - Disclosed is an apparatus and method for operating a multi-level cell (MLC) flash memory circuit. Data is read from a memory block of a plurality of memory blocks in the MLC flash memory circuit, wherein each of the plurality of memory blocks can operate in one of at least three modes of operation comprising an MLC mode, a single-level cell (SLC) mode and a defective mode, and wherein the memory block is initially operating in the MLC mode. Error correction is performed on the read data to correct read errors in the read data. A determination is made if a number of bits corrected by the error correction exceeds a predetermined threshold value. If the number of bits corrected by the error correction exceeds the predetermined threshold value, the operating mode of the memory block is switched from the MLC mode to the SLC mode. | 09-20-2012 |
20120246545 | METHOD FOR ENHANCING DATA PROTECTION PERFORMANCE, AND ASSOCIATED PERSONAL COMPUTER AND STORAGE MEDIUM - A method for enhancing data protection performance is provided. The method is applied to a personal computer that includes/is electronically connected to a memory device, and the memory device includes a Flash memory. The method includes: with regard to data to be written/programmed into the Flash memory of the memory device by the personal computer, generating at least one Error Correction Code (ECC) corresponding to the data, and storing the ECC into a file within the personal computer, wherein the file is stored in a storage of the personal computer; and when it is detected that an uncorrectable error of at least one portion of the data stored in the Flash memory occurs, performing error correction according to the ECC stored in the file, in order to correct the data stored in the Flash memory. An associated personal computer and a storage medium storing an associated driver are further provided. | 09-27-2012 |
20120254699 | DYNAMIC READ CHANNEL CALIBRATION FOR NON-VOLATILE MEMORY DEVICES - Embodiments of the invention describe a dynamic read reference voltage for use in reading data from non-volatile memory cells. In embodiments of the invention, the read reference voltage is calibrated as the non-volatile memory device is used. Embodiments of the invention may comprise of logic and or modules to read data from a plurality of non-volatile memory cells using a first read reference voltage level (e.g., an initial read reference voltage level whose value is determined by the non-volatile device manufacturer). An Error Checking and Correction (ECC) algorithm is performed to identify whether errors exist in the data as read using the first read reference voltage level. If errors in the data as read are identified, a pre-determined value is retrieved to adjust the first read reference voltage level to a second read reference voltage level. | 10-04-2012 |
20120254700 | MECHANISMS AND TECHNIQUES FOR PROVIDING CACHE TAGS IN DYNAMIC RANDOM ACCESS MEMORY - A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page. | 10-04-2012 |
20120260148 | SYSTEM AND METHOD FOR HANDLING BAD BIT ERRORS - A method and system for detecting and correcting a bad bit error in a solid-state nonvolatile memory device. The device includes a bad bit detection module that receives an old page from the memory device and determines whether a page has a bad bit. The device further includes a bad bit correction module that generates a new page, determines a location of the bad bit, determines a preferred value of the bad bit, determines a user value of the bad bit and inserts the preferred value into a string of bits corresponding to substantive data of the old page, recording the string of bits with the preferred value inserted therein and stores the new page at an address of the old page. | 10-11-2012 |
20120260149 | DUMMY DATA PADDING AND ERROR CODE CORRECTING MEMORY CONTROLLER, DATA PROCESSING METHOD THEREOF, AND MEMORY SYSTEM INCLUDING THE SAME - A data processing method of a memory controller includes receiving first partial data of a last sector data among a plurality of sector data to be stored in an n-th page of a non-volatile memory in a program operation; padding the first partial data with first dummy data and generating a first error correction code (ECC) parity in the program operation; and transferring the first partial data and the first ECC parity to the non-volatile memory in the program operation, while refraining from transferring the first dummy data to the non-volatile memory. Related devices and systems are also described. | 10-11-2012 |
20120260150 | DATA MANAGEMENT IN SOLID STATE STORAGE SYSTEMS - Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords. | 10-11-2012 |
20120266050 | Data Management in Solid State Storage Devices - A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory, An indication of validity of data stored in each data write location is also maintained, Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data. | 10-18-2012 |
20120272123 | DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data writing method for writing page data into a rewritable non-volatile memory module is provided, the rewritable non-volatile memory module has a plurality of physical blocks, and each of the physical blocks has a plurality of physical pages. The data writing method includes grouping the physical pages into a plurality of physical page groups according to write speed of each physical page. The data writing method also includes compressing the page data to generate compressed data and calculating a data compression ratio corresponding to the compressed data. The data writing method further includes writing the compressed data into one of the physical pages in a corresponding physical page group among the physical page groups according to the data compression ratio. Accordingly, the data writing method can effectively ensure the accuracy of data stored in the rewritable non-volatile memory module. | 10-25-2012 |
20120278684 | SOLID STATE STORAGE ELEMENT AND METHOD - A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity. | 11-01-2012 |
20120278685 | Store Handling in a Processor - In one embodiment, a processor may be configured to write ECC granular stores into the data cache, while non-ECC granular stores may be merged with cache data in a memory request buffer. In one embodiment, a processor may be configured to detect that a victim block writeback hits one or more stores in a memory request buffer (or vice versa) and may convert the victim block writeback to a fill. In one embodiment, a processor may speculatively issue stores that are subsequent to a load from a load/store queue, but prevent the update for the stores in response to a snoop hit on the load. | 11-01-2012 |
20120284587 | Super-Endurance Solid-State Drive with Endurance Translation Layer (ETL) and Diversion of Temp Files for Reduced Flash Wear - A flash drive has increased endurance and longevity by reducing writes to flash. An Endurance Translation Layer (ETL) is created in a DRAM buffer and provides temporary storage to reduce flash wear. A Smart Storage Switch (SSS) controller assigns data-type bits when categorizing host accesses as paging files used by memory management, temporary files, File Allocation Table (FAT) and File Descriptor Block (FDB) entries, and user data files, using address ranges and file extensions read from FAT. Paging files and temporary files are never written to flash. Partial-page data is packed and sector mapped by sub-sector mapping tables that are pointed to by a unified mapping table that stores the data-type bits and pointers to data or tables in DRAM. Partial sectors are packed together to reduce DRAM usage and flash wear. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 11-08-2012 |
20120290899 | METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR DECODING A CODEWORD - A method and apparatus for decoding a codeword received from a flash memory. The flash memory comprises multi-level flash memory cells, wherein each multi-level flash memory cell stores one symbol of the codeword. An ECC decoder is arranged for decoding the codeword into a decoded codeword and correcting a maximum number of errors. The method determines the number of errors in the codeword. If the number of errors is more than the maximum number of errors that the ECC decoder can correct, the method generates modified codewords, calculates a corrective effect of a modified codeword, and determines a decoded codeword based on the corrective effect. | 11-15-2012 |
20120297273 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY APPARATUS AND DECODING METHOD - A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed. | 11-22-2012 |
20120304039 | BIT ERROR REDUCTION THROUGH VARIED DATA POSITIONING - Devices, apparatuses, systems, and methods are disclosed for bit error reduction through varied data positioning. A write request module is configured to receive data for storage in an array of solid-state storage elements. The solid-state storage elements are accessible in parallel. A write module is configured to store the data in parallel to the array of solid-state storage elements with varied data positions for the data relative to different solid-state storage elements of the array. A read module is configured to read the data in parallel from the array of solid-state storage elements. | 11-29-2012 |
20120311408 | NONVOLATILE MEMORY, MEMORY CONTROLLER, NONVOLATILE MEMORY ACCESSING METHOD, AND PROGRAM - Disclosed herein is a nonvolatile memory including: a nonvolatile memory cell device including at least a nonvolatile memory cell array accessible in units of a word and further accessible at least with a fixed latency in a first access mode and with a variable latency in a second access mode; a first access path used in the first access mode; a second access path used in the second access mode; a first ECC processing part configured to be connected to the first access path and to perform error detection and correction using an ECC on the data output from the nonvolatile memory cell array in the first access mode; and a second ECC processing part configured to be connected to the second access path and to perform error detection and correction using the ECC on the data output from the nonvolatile memory cell array in the second access mode. | 12-06-2012 |
20120317460 | IDENTIFICATION AND MITIGATION OF HARD ERRORS IN MEMORY SYSTEMS - Embodiments provide a method comprising estimating a first set of log-likelihood ratio (LLR) values for a plurality of memory cells of a memory; based on the first set of LLR values, performing a first error correcting code (ECC) decoding operation; in response to determining a failure of the first ECC decoding operation, generating, by adjusting the first set of LLR values, a second set of LLR values for the plurality of memory cells; and based on the second set of LLR values, performing a second ECC decoding operation. | 12-13-2012 |
20120324314 | Low Power Retention Random Access Memory with Error Correction on Wake-Up - Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode. | 12-20-2012 |
20130007566 | Memory Device with Adaptive Capacity - A method for data storage in a memory that includes a plurality of analog memory cells includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities. | 01-03-2013 |
20130013980 | Data Management in Solid State Storage Devices - A mechanism is provided for controlling a solid state storage device in which the solid state storage comprises erasable blocks each comprising a plurality of data write locations. Input data is stored in successive groups of data write locations, each group comprising write locations in a set of erasable blocks in each of a plurality of logical subdivisions of the solid state storage. The input data is error correction encoded such that each group contains an error correction code for the input data in that group. Metadata, indicating the location of input data in the solid state storage, is maintained in memory. An indication of validity of data stored in each data write location is also maintained. Prior to erasing a block, valid input data is recovered from the or each said group containing write locations in that block. The recovered data is then re-stored as new input data. | 01-10-2013 |
20130013981 | TEMPORARY MIRRORING, LOGICAL SEGREGATION, AND REDUNDANT PROGRAMMING OR ADDRESSING FOR SOLID STATE DRIVE OPERATION - The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event. | 01-10-2013 |
20130024747 | SYSTEMS AND METHODS OF STORING DATA - A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page. | 01-24-2013 |
20130024748 | SYSTEMS AND METHODS OF STORING DATA - A method of writing data includes receiving data pages to be stored in a data storage device and generating codewords corresponding to the received data pages. The codewords are stored to physical pages of a first memory portion of the data storage device. A first portion of a particular codeword that corresponds to a particular data page is stored at a first physical page of the first memory portion. A second portion of the particular codeword is stored at a second physical page of the first memory portion. The codewords are copied from the physical pages of the first memory portion to a physical page of a second memory portion of the data storage device. | 01-24-2013 |
20130024749 | MULTILEVEL ENCODING WITH ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed. | 01-24-2013 |
20130031443 | METHOD OF OPERATING MEMORY CONTROLLER, AND MEMORY SYSTEM, MEMORY CARD AND PORTABLE ELECTRONIC DEVICE INCLUDING THE MEMORY CONTROLLER - A method of operating a memory controller includes reading data from a first block of a memory device; detecting degraded pages from a plurality of pages of the first block and counting a number of the degraded pages in the first block; and recharging or reclaiming the first block, which includes the degraded pages, based on the counted number of the degraded pages. | 01-31-2013 |
20130042164 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a memory unit including a plurality of memory cells, each of the plurality of memory cells to perform a multi-level storage operation by assigning a value including a plurality of bits to at least four data states defined according to a threshold level; and a controller to control the memory unit, wherein the controller sets at least one of the plurality of bits to an error correction bit that indicates one of a first state and a second state; assigns the first state to the error correction bits that correspond to the data states having a minimum threshold level and a maximum threshold level and the second state to the error correction bits that correspond to the data state having other threshold level; and resets the error correction bit to the first state when the error correction bit indicates the second state. | 02-14-2013 |
20130047056 | FLASH MEMORY DEVICE WITH RECTIFIABLE REDUNDANCY AND METHOD OF CONTROLLING THE SAME - A flash memory device connected to a host includes: a flash memory; and a control circuit comprising a first error correcting code unit and a second error correcting code unit. The data length of a redundancy generated by the second error correcting code unit is longer than the data length of a redundancy generated by the first error correcting code unit. The first error correcting code unit is adopted to process with a data transmitted to the flash memory from the host when a damage risk of the flash memory is lower than a specific value; and the first and second error correcting code units are adopted to process with the data transmitted to the flash memory from the host when the damage risk of the flash memory is higher than the specific value. | 02-21-2013 |
20130055048 | BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM - A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information. | 02-28-2013 |
20130067294 | APPARATUS, SYSTEM, AND METHOD FOR A FRONT-END, DISTRIBUTED RAID - An apparatus, system, and method are disclosed for a front-end, distributed redundant array of independent drives (“RAID”). A storage request receiver module receives a storage request to store object or file data in a set of autonomous storage devices forming a RAID group. The storage devices independently receive storage requests from a client over a network, and one or more of the storage devices are designated as parity-mirror storage devices for a stripe. The striping association module calculates a stripe pattern for the data. Each stripe includes N data segments, each associated with N storage devices. The parity-mirror association module associates a set of the N data segments with one or more parity-mirror storage devices. The storage request transmitter module transmits storage requests to each storage device. Each storage request is sufficient to store onto the storage device the associated data segments. The storage requests are substantially free of data. | 03-14-2013 |
20130073926 | MEMORY WITH ON-CHIP ERROR CORRECTION - A memory device is configured to correct errors in codewords written to a memory array. Errors, if any, in a first codeword are corrected and a codeword corrector output is generated including a corrected first codeword. A data buffer receives the codeword corrector output and a first user data associated with the addressed page and generates a data buffer output including the corrected first codeword, as modified by the first user data, defined as a first codeword output. A codeword encoder receives the data buffer output and encodes the first codeword output to generate an encoded first codeword output included in a codeword encoder output. A write buffer receives the codeword encoder output and saves the same for writing to the memory array. Writing to the memory array is performed while receiving a second user data, which has a second codeword associated therewith, and correcting the second codeword. | 03-21-2013 |
20130080857 | FLASH MEMORY CONTROLLER ADAPTIVELY SELECTING ERROR-CORRECTION SCHEME ACCORDING TO NUMBER OF PROGRAM/ERASE CYCLES OF FLASH MEMORY - A flash memory controller includes an encoding block, a decoding block and a control unit. The encoding block is utilized for encoding raw bits with a target forward error-correction (FEC) coding scheme selected from a plurality of candidate FEC coding schemes. The decoding block is utilized for decoding encoded bits with a target FEC decoding scheme selected from a plurality of candidate FEC decoding schemes, wherein the target FEC decoding scheme corresponds to the target FEC coding scheme. The control unit is coupled to the encoding block and the decoding block, and utilized for controlling a selection of the target FEC coding scheme utilized by the encoding block and a selection of the target FEC decoding scheme utilized by the decoding block according to a number of program/erase cycles of a flash memory. | 03-28-2013 |
20130080858 | METHOD OF READING DATA FROM A NON-VOLATILE MEMORY AND DEVICES AND SYSTEMS TO IMPLEMENT SAME - Methods of performing a read retry, including reading a non-volatile memory with new read parameters, and devices for performing such methods are disclosed. The read retry operation and/or subsequent read retry operation may be initiated and/or completed before it is determined that such read retry operation is warranted. For example, a page of a NAND flash memory may be read in a read retry operation with new read voltage levels applied to a word line of the page. For example, a read retry operation may be performed on a target page prior to determining errors of a previous read page of data of the target page are uncorrectable via an ECC operation. | 03-28-2013 |
20130080859 | METHOD FOR PROVIDING DATA PROTECTION FOR DATA STORED WITHIN A MEMORY ELEMENT AND INTEGRATED CIRCUIT DEVICE THEREFOR - A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory. | 03-28-2013 |
20130080860 | DATA RECOVERY IN A SOLID STATE STORAGE SYSTEM - Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data is recovered by an XOR operation on the remaining good data and associated RAID data to reconstruct the defective data. The defective data is excluded from the XOR operation. | 03-28-2013 |
20130086453 | SYSTEMS AND METHODS INVOLVING MANAGING A PROBLEMATIC MEMORY CELL - Subject matter described pertains to managing problematic memory cells in a memory array. | 04-04-2013 |
20130086454 | ADJUSTABLE MEMORY ALLOCATION BASED ON ERROR CORRECTION - An apparatus may comprise a memory including a first area of total usable storage capacity of the memory reported to a host device, a second area occupied by error correction code (ECC) appended to data stored in the first area, and a third area of usable data storage capacity not reported to the host device. The apparatus may further comprise a controller configured to balance sizes of the second area and third area to maintain a size of the first area as the length of ECC of data stored in the first area increases. The controller may be further configured to exchange data having an ECC of a controllable length with the memory based on a data storage location, and adjust the controllable length of the ECC based on an error history of the data storage location. | 04-04-2013 |
20130091405 | INDEPENDENT ORTHOGONAL ERROR CORRECTION AND DETECTION - A data memory is organized as a logical matrix having multiple virtual data words. Along with the physical representation of the data as being associated with physical memory cells, other virtual data words and their virtual check bits are formed that intersect (logically) with the real data word in a multi-dimensional array. Each of these virtual words can possess errors that can be quickly corrected using independent EDAC methodology. The validity of the virtual word can be used to verify the validity of a single bit in the real word thus correcting multiple bit errors. | 04-11-2013 |
20130104004 | RAM MEMORY DEVICE - A RAM memory device includes a selection unit that supplies the access reaching one of two interfaces to a RAM in one cycle of a clock signal in response to a control signal. The RAM memory device also includes a storage unit that stores another access that has reached the other of the two interfaces at least till the next cycle following the above-mentioned one cycle in response to the control signal. The selection unit supplies the above-mentioned another access from the storage unit to the RAM in or after the above-mentioned next cycle. | 04-25-2013 |
20130104005 | FLASH MEMORY APPARATUS AND METHODS USING A PLURALITY OF DECODING STAGES INCLUDING OPTIONAL USE OF CONCATENATED BCH CODES AND/OR DESIGNATION OF "FIRST BELOW" CELLS - A method for decoding a plurality of flash memory cells which are error correction-coded, the method may include: comparing physical values residing in the plurality of flash memory cells to a first set of decision thresholds thereby to provide a first item of comparison information for each of the plurality of cells; comparing physical values residing the plurality of flash memory cells to a second set of decision thresholds, thereby to provide a second item of comparison information for each of the plurality of cells, wherein neither of the first and second sets of decision thresholds is a subset of the other; and determining logical values for the plurality of flash memory cells by combining said first and second items of comparison information. | 04-25-2013 |
20130117635 | MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY DEVICE AND CONTROLLING METHOD OF CONTROLLING NONVOLATILE MEMORY DEVICE - Disclosed is a method of controlling a nonvolatile memory device which includes programming data in a user data area of the nonvolatile memory device and state information on logical states of the data in a meta area of the nonvolatile memory device; and adjusting levels of a plurality of read voltages using the state information to read the data from the user data area using the plurality of read voltages having the adjusted levels. | 05-09-2013 |
20130117636 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM HAVING REDUNDANCY CELLS - In one embodiment, the memory device includes a memory cell array, a data line selection circuit and selection control logic. The memory cell array has at least a first memory cell group and a redundancy memory cell group. The first memory cell group includes a plurality of first memory cells associated with a first data line, and the redundancy memory cell group includes a plurality of redundancy memory cells associated with a redundancy data line. The selection control logic is configured to detect if a defective memory cell in the first memory cell group is being accessed, and is configured to control the data line selection circuit to replace access via the first data line with access via the redundancy data line such that a detected defective memory cell in the first memory cell group is replaced with one of the plurality of redundancy memory cells. | 05-09-2013 |
20130117637 | ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells. | 05-09-2013 |
20130124944 | MEMORY CONTROLLER FOR NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING MEMORY CONTROLLER, AND RELATED METHODS OF OPERATION - A nonvolatile memory device comprises a memory controller having a memory cell status estimator that generates status estimation information indicating the status of a memory cell based on status register data, a coupling group index selector configured to generate a select signal for selecting a page and coupling group index from the status estimation information, and a memory cell status value generator configured to map the status estimation information to the data reliability decision bits and the coupling group index and generate a status value of the memory cell for error correction code decoding. | 05-16-2013 |
20130124945 | DYNAMIC LDPC CODE RATE SOLUTION - The subject technology includes adjusting an error correcting code rate in a solid-state drive. A first plurality of memory operations are performed on a flash memory device of the solid-state drive using a first code rate. During operation of the drive, a controller monitors an operating condition associated with one or more memory units of the flash memory device for a trigger event. On the trigger event, the first code rate is adjusted in accordance with the operating condition to produce a second code rate, and a second plurality of memory operations is performed on the flash memory device using the second code rate. | 05-16-2013 |
20130124946 | SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND - A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device. | 05-16-2013 |
20130132802 | DATA AND ERROR CORRECTION CODE MIXING DEVICE AND METHOD - Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy. | 05-23-2013 |
20130139035 | LDPC Erasure Decoding for Flash Memories - A Solid-State Disk (SSD) controller uses LDPC decoding to enable flash memory accesses with improved latency and/or error correction capabilities. With SLC flash memory having a BER less than a predetermined value, the SSD controller uses a 1-bit read (single read) hard-decision LDPC decoder to access the flash memory. If the hard-decision LDPC decoder detects an uncorrectable error, then the SSD controller uses a 1.5-bit read (two reads) erasure-decision LDPC decoder to access the flash memory. With flash memory having a raw BER between two other predetermined values, the SSD controller omits the use of the hard-decision LDPC decoder and uses only the erasure-decision LDPC decoder to access the flash memory. Variations of the SSD controller similarly access MLC flash memory. Some SSD controllers dynamically switch between hard-decision and erasure-based decoders based on dynamic decoder selection criteria. | 05-30-2013 |
20130139036 | Flash Memory System and Read Method in Flash Memory System - Methods of operating nonvolatile memory devices include reading a first plurality of multi-bit nonvolatile memory cells in the nonvolatile memory device using a first plurality of read voltages to thereby generate first read data, and then rereading the first plurality of multi-bit nonvolatile memory cells using a second plurality of read voltages that differ, at least in part, from the first plurality of read voltages, to thereby generate second read data. An operation is then undertaken to perform first and second ECC decoding operations on the first and second read data, respectively, to thereby identify whether the first read data or the second read data more accurately reflects data stored in the first plurality of multi-bit nonvolatile memory cells during the reading and rereading. | 05-30-2013 |
20130139037 | Systems and Methods for Error Correction and Decoding on Multi-Level Physical Media - Apparatus and methods for operating a flash device characterized by use of Lee distance based codes in a flash device so as to increase the number of errors that can be corrected for a given number of redundancy cells, compared with Hamming distance based codes. | 05-30-2013 |
20130145233 | MEMORY MODULE AND SEMICONDUCTOR STORAGE DEVICE - A memory module includes a plurality of memory chips stacked on top of one another, each of the plurality of memory chips including a memory cell unit that is divided into a plurality of blocks, and an address scrambling circuit that processes an input address signal and that selects a block to be operated. | 06-06-2013 |
20130145234 | Memory Systems and Block Copy Methods Thereof - Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using an address-scrambled reprogramming technique, for example. | 06-06-2013 |
20130145235 | DETECTION AND DECODING IN FLASH MEMORIES WITH SELECTIVE BINARY AND NON-BINARY DECODING - Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently. | 06-06-2013 |
20130151931 | MULTIPLE-LEVEL MEMORY CELLS AND ERROR DETECTION - Memory, modules and methods for using error detection with multi-level memory cells where the number of storage levels of the memory cells is an integer power of a non-binary prime number are provided. Additional circuit and methods are disclosed. | 06-13-2013 |
20130159814 | SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST METHOD, AND MEDIUM - According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block. | 06-20-2013 |
20130159815 | ADAPTIVE COPY-BACK METHOD AND STORAGE DEVICE USING SAME - During a garbage collection process for a non-volatile memory device of a storage device, an adaptive copy-back method selectively performs either an external or an internal copy-back operation in view of certain performance conditions for a storage device. The external copy-back operation is performed when a number of error-corrected bits per unit size of read data exceeds a given threshold value, and the internal copy-back operation is performed when the number of error-corrected bits does not exceed the threshold value. | 06-20-2013 |
20130173997 | MEMORY CONTROLLER, MEMORY SYSTEM, AND MEMORY WRITE METHOD - A memory controller includes a memory interface that has multiple channels and carries out writing into a nonvolatile memory through each of the channels, a data buffer, an ECC (error correcting code) encoder for applying an error correction encoding processing on write data which are to be written into the nonvolatile memory to generate ECC data, a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory, a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder, and a channel scheduler for transferring the write data stored in the data buffer and the ECC data to the channels of the memory interface as allocated by the channel allocation part. | 07-04-2013 |
20130179752 | STORAGE DEVICE AND NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A storage device which includes a user area of a memory cell array; a buffer area configured to temporarily store compressed data to be written into the user area; and compressed data management logic configured to control the user area and the buffer area such that compressed data stored in the buffer area is written into the user area. The compressed data management logic manages compressed data to be written into the user area by an ECC block unit rather than by a page-size unit. | 07-11-2013 |
20130179753 | SYSTEMS AND METHODS FOR ADAPTIVE DATA STORAGE - A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising two or more solid-state storage elements. The data segments may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The data arrangement may determine input/output performance characteristics. An optimal adaptive data storage configuration may be based on read and/or write patterns of storage clients, read time, stream time, and so on. Data of failed storage elements may be reconstructed by use of parity data and/or other ECC codewords stored within the array. | 07-11-2013 |
20130179754 | DECODING IN SOLID STATE MEMORY DEVICES - In a solid state memory device, codewords stored in a unit of the memory device are decoded using an error correcting iterative decoding process. An average number of iterations needed for successfully decoding codewords of the unit is determined, and the average number of iterations is monitored. The average number of iterations can be taken as a measure of wear of the subject unit. | 07-11-2013 |
20130185612 | FLASH MEMORY SYSTEM AND READ METHOD OF FLASH MEMORY SYSTEM - A read method in a flash memory system containing a flash memory and a memory controller includes updating a selected one of indexes of a selected one of blocks of the flash memory, in a wear-out table for indexing each of the blocks of the flash memory, and setting a start read level to start read retry on the selected block by referring to a read retry table corresponding to a wear-out degree included in the selected index when a current request of read retry on the selected block is received. | 07-18-2013 |
20130191704 | MEMORY MANAGEMENT IN A NON-VOLATILE SOLID STATE MEMORY DEVICE - A non-volatile solid state memory device and method for balancing write/erase cycles among blocks to level block usage. The non-volatile solid state memory device includes a memory unit having data stored therein and a controller with logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device and programming the memory unit according to the monitored occurrence of the error. | 07-25-2013 |
20130191705 | SEMICONDUCTOR STORAGE DEVICE - According to an embodiment, a semiconductor storage device includes an error correction processing unit that executes encoding process related data to be dispersedly written over a plurality of memory areas and decoding process related data dispersedly written over the plurality of memory areas. A transfer management unit determines whether or not data related to the data transfer request is a target of the error correction process and causes the error correction processing unit to execute the error correction process only with respect to the data determined as the target of the error correction process. | 07-25-2013 |
20130198589 | METHOD OF OPERATING MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE MEMORY CONTROLLER - According to example embodiments, a method of controlling a memory controller includes executing an error correction code (ECC) on first page data that has been read from a non-volatile memory device using a first read voltage level, estimating a second read voltage level for reading the first page data using metadata of second page data when an uncorrectable error is detected in the first page data according to a result of executing the ECC. | 08-01-2013 |
20130205183 | SYSTEMS AND METHODS FOR ADAPTIVE ERROR-CORRECTION CODING - A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising a plurality of columns. The ECC codewords may comprise ECC codeword symbols. The ECC symbols of a data segment may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The individual ECC symbols may be stored within respective columns of the array (e.g., may not cross column boundaries). Data of an unavailable ECC symbol may be reconstructed by use of other ECC symbols stored on other columns of the array. | 08-08-2013 |
20130212450 | HIGH THROUGHPUT DECODER ARCHITECTURE FOR LOW-DENSITY PARITY-CHECK CONVOLUTIONAL CODES - A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder ( | 08-15-2013 |
20130212451 | REDUCED COMPLEXITY NON-BINARY LDPC DECODING ALGORITHM - A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component. | 08-15-2013 |
20130219249 | METHOD FOR DETERMINING PARITY CHECK MATRIX UTILIZED IN FLASH MEMORY SYSTEM AND RELATED FLASH MEMORY SYSTEM THEREOF - A method for determining a parity check matrix utilized in a flash memory system is disclosed. The parity check matrix comprises M×N blocks. The method comprises generating a first set of candidate blocks as candidates of a first set of blocks of the M×N blocks; calculating a plurality of first estimated results corresponding to the first set of candidate blocks; determining content of a first block of the M×N blocks according to a best result of the first estimated results; generating a second set of candidate blocks as candidates of a second set of blocks of the M×N blocks; calculating a plurality of second estimated results corresponding to the second set of candidate blocks by considering the content of the first block; determining content a second block of the M×N blocks according to the second estimated results. | 08-22-2013 |
20130232393 | ERROR DETECTION AND CORRECTION CODES FOR CHANNELS AND MEMORIES WITH INCOMPLETE ERROR CHARACTERISTICS - A channel has a first and a second end. The first end of the channel is coupled to a transmitter. The channel is capable of transmitting symbols selected from a symbol set from the first end to the second end. The channel exhibits incomplete error introduction properties. A code comprises a set of code words. The elements of the set of code words are one or more code symbols long. The code symbols are members of the symbol set. The minimum modified Hamming separation between the elements of the set of code words in light of the error introduction properties of the channel is greater than the minimum Hamming distance between the elements of the set of code words. A memory device, a method of using the channel, and a method of generating the code are also described. | 09-05-2013 |
20130238958 | APPARATUSES AND METHODS INCLUDING ERROR CORRECTION CODE ORGANIZATION - Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described. | 09-12-2013 |
20130238959 | MITIGATING INTER-CELL COUPLING EFFECTS IN NON VOLATILE MEMORY (NVM) CELLS - A system, computer readable medium and a method of operating a non volatile memory (NVM) array that comprises multiple NVM cells, the method comprises: receiving input data to be written to the non volatile memory; performing constraint coding on the input data to provide encoded data; wherein the constraint coding prevents the encoded data from comprising forbidden combinations of values; wherein the forbidden combinations of values are defined based on expected inter-cell coupling induced errors resulting from coupling between NVM cells; and writing the encoded data to the non volatile memory. | 09-12-2013 |
20130246891 | PHYSICAL PAGE, LOGICAL PAGE, AND CODEWORD CORRESPONDENCE - The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory. | 09-19-2013 |
20130246892 | ARCHITECTURE FOR STORAGE OF DATA ON NAND FLASH MEMORY - Systems, methods, apparatus, and techniques are provided for processing data from a storage medium. A stripe of data stored on the storage medium is read, where the stripe comprises a plurality of data allocation units (AUs) and a parity AU. Error correction decoding is applied to each of the plurality of data AUs to produce a plurality of decoded data AUs. It is determined whether a value of the parity AU is satisfied by values of bytes in the plurality of decoded data AUs. The plurality of decoded data AUs are output in response to a determination that the value of the parity AU is satisfied by the values of bytes in the plurality of decoded data AUs. | 09-19-2013 |
20130254628 | SEMICONDUCTOR MEMORY SYSTEM INCLUDING REED-SOLOMON LOW DENSITY PARITY CHECK DECODER AND READ METHOD THEREOF - A semiconductor memory system may include a read data manager configured to store data read from a memory device, a likelihood value mapper configured to map likelihood values to the data output from the data manager and output mapping data, and a decoder configured to perform low density parity check decoding on the mapping data by using a parity check matrix. The parity check matrix may be a k*N×M matrix including k*N×M submatrices, where k, N and M are independently an integer equal to or greater than 2. | 09-26-2013 |
20130254629 | DATA ACCESSING METHOD FOR FLASH MEMORY MODULE - A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet. | 09-26-2013 |
20130254630 | PROGRAMMING MANAGEMENT DATA FOR A MEMORY - Methods, apparatus, systems, and data structures may operate to combine block management data with a portion of data, to generate error correction data for the combined portion, and to store the data, the block management data, the error correction data for the combined portion, and error correction data for the data in a memory. Additional embodiments may operate to generate or store error correction data for each of a plurality of sectors of a page except for a particular sector in the page and combine block management data with the particular sector to generate a modified sector. Additional embodiments may operate to generate or store error correction data for the modified sector and combine the plurality of sectors, the error correction data for each of the plurality of sectors other than the particular page, and the block management data and the error correction data for the modified sector. | 09-26-2013 |
20130262960 | SOLID-STATE MASS STORAGE DEVICE AND METHOD FOR FAILURE ANTICIPATION - A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases. | 10-03-2013 |
20130268825 | SECONDARY MEMORY TO STORE A VARYING AMOUNT OF OVERHEAD INFORMATION - A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied. | 10-10-2013 |
20130275835 | FABRIC-BASED SOLID STATE DRIVE ARCHITECTURE - Embodiments of apparatus, methods and systems of solid state drive are disclosed. One embodiment of a solid state drive includes a non-blocking fabric, wherein the non-blocking fabric comprises a plurality of ports, wherein a subset of the plurality of ports are each connected to a flash controller that is connected to at least one array of flash memory. Further, this embodiment includes a flash scheduler for scheduling data traffic through the non-blocking fabric, wherein the data traffic comprises a plurality of data packets, wherein the flash scheduler extracts flash fabric header information from each of the data packets and schedules the data traffic through the non-blocking fabric based on the extracted flash fabric header information. The scheduled data traffic provides transfer of data packets through the non-blocking fabric from at least one array of flash memory to at least one other array of flash memory. | 10-17-2013 |
20130275836 | MEMORY MANAGEMENT METHOD, STORAGE DEVICE, AND COMPUTER WITH THE SAME - A storage device includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a free block management table, and a worn block management table. If the number of free blocks is equal to or larger than a threshold value 1, and errors of the number of equal to or larger than a threshold value 2 but smaller than a threshold value 3 are included in the data read from the nonvolatile memory, the memory controller registers the block in the worn block management table as a worn block. If the number of free blocks becomes smaller than the threshold value 1, the memory controller registers the worn block registered in the worn block management table in the free block management table as the free block. | 10-17-2013 |
20130283128 | Operating Method of Controller Controlling Nonvolatile Memory Device and Mapping Pattern Selecting Method of Selecting Mapping Pattern Mapping Polar Coded Code Word with Multi Bit Data of Nonvolatile Memory Device - An operating method of a nonvolatile memory device controller includes generating a code word through polar encoding of information bits, reading a mapping pattern, generating a repeated mapping pattern through iteration of the mapping pattern, and mapping each bit of the code word onto a specific bit of multi-bit data of the nonvolatile memory device, based upon the repeated mapping pattern. | 10-24-2013 |
20130283129 | SOLID-STATE MASS STORAGE DEVICE AND METHOD FOR FAILURE ANTICIPATION - A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases. | 10-24-2013 |
20130283130 | ERROR RECOVERY STORAGE ALONG A MEMORY STRING - Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes. | 10-24-2013 |
20130290813 | Method and System For Error Correction in Flash Memory - A controller is described for a multi-level, solid state, non-volatile memory array having memory cells. The memory cells are configured to store data using a first number of digital levels. The controller is configured to encode multiple data bits to generate multiple encoded data bits, convert the multiple encoded data bits into multiple data symbols, and send the multiple data symbols for storage in a memory cell of the multi-level, solid state, non-volatile memory array. The controller is further configured to generate an output signal, using a second number of digital levels, based on data associated with the multiple data symbols stored in the memory cell. The second number of digital levels is greater than the first number of digital levels used to store the multiple data symbols in the memory cell. The controller is further configured to output multiple output data symbols based on the output signal. | 10-31-2013 |
20130297987 | Method and Apparatus for Reading NAND Flash Memory - A page buffer for a NAND memory array has a data register and a cache register that are suitably organized and operated to eliminate gaps and discontinuities in the output data during a continuous page read. The cache register may be organized in two portions, and the page data in the cache may be output from the cache portions in alternation. ECC delay may be eliminated from the output by performing the ECC computation on one cache portion while the other is being output. The data register may also be organized in two portions corresponding to the cache portions, so that data may be transferred to one cache portion while the other is being output. In a variation, the continuous page read may be done without ECC. | 11-07-2013 |
20130297988 | LOW-DENSITY PARITY-CHECK DECODER DISPARITY PREPROCESSING - Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device. | 11-07-2013 |
20130297989 | Memory Device Readout Using Multiple Sense Times - A method for data storage includes storing data in a group of analog memory cells by writing respective storage values into the memory cells in the group. One or more of the memory cells in the group are read using a first readout operation that senses the memory cells with a first sense time. At least one of the memory cells in the group is read using a second readout operation that senses the memory cells with a second sense time, longer than the first sense time. The data stored in the group of memory cells is reconstructed based on readout results of the first and second readout operations. | 11-07-2013 |
20130305124 | Memory Read-Out - A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information. | 11-14-2013 |
20130311854 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD OF NONVOLATILE MEMORY - A memory controller adds the redundant information that is used to correct an error for each of data of a predetermined length and stores the data into the nonvolatile memory in the case in which data is written to the nonvolatile memory, the memory controller reads data and the redundant information that has been added to the data from the nonvolatile memory in the case in which data is read from the nonvolatile memory, and the memory controller corrects an error based on the redundant information in the case in which the data includes an error. The memory controller stores data that is in a basic unit that is a unit of an error correction configured by the data of a predetermined length and the redundant information that is added to the data of a predetermined length into a plurality of predetermined pages in a dispersed manner. | 11-21-2013 |
20130311855 | METHOD FOR PROCESSING A NON-VOLATILE MEMORY, IN PARTICULAR A MEMORY OF THE EEPROM TYPE, FOR THE STORAGE THEN THE EXTRACTION OF INFORMATION, AND CORRESPONDING MEMORY DEVICE - Method for processing a non-volatile memory designed to store words containing data bits and control bits allowing an error correction with an error correction code, the method comprising the storage of information in the memory plane comprising an operation for writing in the memory plane at least one digital word modified with respect to at least one initial digital word not having any erroneous bit, said at least one modified digital word containing a bit having a modified value with respect to the value of this bit in said at least one initial digital word, the other bits of the modified digital word having values identical to those of these same bits in the initial digital word, the position of the modified bit in said at least one modified digital word defining the value of the digital information. | 11-21-2013 |
20130318419 | FLASH MEMORY SYSTEM INCLUDING READ COUNTER LOGIC - A flash memory system which includes a flash memory and a memory controller. The flash memory is configured to perform a read operation using a plurality of read levels. The memory controller is configured to recover original data using a counter value provided from the flash memory. The flash memory converts read result values obtained using the plurality of read levels into the counter value to provide the counter value to the memory controller. | 11-28-2013 |
20130318420 | CODE MODULATION ENCODER AND DECODER, MEMORY CONTROLLER INCLUDING THEM, AND FLASH MEMORY SYSTEM - Disclosed is a bit-state mapping method of a flash memory system which maps m-bit data (m being a natural number more than 2) onto one of 2 | 11-28-2013 |
20130326312 | STORAGE DEVICE INCLUDING NON-VOLATILE MEMORY DEVICE AND REPAIR METHOD - Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block. | 12-05-2013 |
20130332800 | SECONDARY MEMORY TO STORE ERROR CORRECTION INFORMATION - A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types. | 12-12-2013 |
20130332801 | METHOD, CONTROLLER, AND MEMORY DEVICE FOR CORRECTING DATA BIT(S) OF AT LEAST ONE CELL OF FLASH MEMORY - A method for correcting data bit of at least a cell of a flash memory includes: determining a contributing factor of level distribution corresponding to an electric level of a first cell to generate a first determination result; and, correcting/modifying the data bit corresponding to the electric potential of the first cell according to the first determination result. | 12-12-2013 |
20130332802 | SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST METHOD, AND MEDIUM - According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block. | 12-12-2013 |
20130339820 | THREE DIMENSIONAL (3D) MEMORY DEVICE SPARING - According to one embodiment of the present invention, a method for operating a three dimensional (“3D”) memory device includes detecting, by a memory controller, a first error on the 3D memory device and detecting, by the memory controller, a second error in a first chip in a first rank of the 3D memory device, wherein the first chip has an associated first chip select. The method also includes powering up a second chip in a second rank, sending a command from the memory controller to the 3D memory device to replace the first chip in the first chip select with the second chip and correcting the first error using an error control code. | 12-19-2013 |
20130339821 | THREE DIMENSIONAL(3D) MEMORY DEVICE SPARING - According to one embodiment of the present invention, a method for bank sparing in a 3D memory device that includes detecting, by a memory controller, a first error in the 3D memory device and detecting a second error in a first element in a first rank of the 3D memory device, wherein the first element in the first rank has an associated first chip select. The method also includes sending a command to the 3D memory device to set mode registers in a master logic portion of the 3D memory device that enable a second element to receive communications directed to the first element and wherein the second element is in a second rank of the 3D memory device, wherein the first element and second element are each either a bank or a bank group that comprise a plurality of chips. | 12-19-2013 |
20130339822 | BAD WORDLINE/ARRAY DETECTION IN MEMORY - A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word. | 12-19-2013 |
20130339823 | BAD WORDLINE/ARRAY DETECTION IN MEMORY - A technique for error detection is provided. A controller is configured to detect errors by using error correcting code (ECC), and a cache includes independent ECC words for storing data. The controller detects the errors in the ECC words for a wordline that is read. The controller detects a first error in a first ECC word on the wordline and a second error in a second ECC word on the wordline. The controller determines that the wordline is a failing wordline based on detecting the first error in the first ECC word and the second error in the second ECC word. | 12-19-2013 |
20140006903 | Utilizing Error Correcting Code Data Associated With A Region of Memory | 01-02-2014 |
20140006904 | ENCODING INFORMATION IN ERROR CORRECTING CODES | 01-02-2014 |
20140006905 | Systems and Methods for Multi-Stage Decoding Processing | 01-02-2014 |
20140006906 | MEMORY DEVICE | 01-02-2014 |
20140013187 | USING SLOW RESPONSE MEMORY DEVICE ON A FAST RESPONSE INTERFACE - A method includes receiving a request to read data at a data storage device from an external device. In response to determining that the data is in a first memory of the data storage device, a first read operation is initiated to read the data from the first memory and a response is sent to the external device. The response indicates an error correction code (ECC) error. A read latency of the first read operation exceeds a reply time period corresponding to the request. The response is sent prior to completion of the first read operation and within reply time period. | 01-09-2014 |
20140013188 | ERROR RECOVERY FOR FLASH MEMORY - A set of data associated with a page in flash storage is received. Error correction decoding is performed on the set of data; if event error correction decoding fails, it is determined whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page. If it is determined the page is a MSB page, one or more MSB read thresholds are adjusted and the is re-read page using the adjusted MSB read threshold(s). If it is determined the page is a LSB page, one or more LSB read thresholds are adjusted and the page is re-read using the adjusted LSB read threshold(s). | 01-09-2014 |
20140019826 | SPLIT DATA ERROR CORRECTION CODE CIRCUITS - Split data error correction code (ECC) circuits including a control circuit coupled to an error correction code (ECC) circuit. The ECC circuit is adapted to generate at least one ECC code from user data of a first physical sector during a data access. The split data ECC circuit is adapted to write the at least one ECC code to a second physical sector if the data access is a write access and to compare the at least one generated ECC code with at least one ECC code stored in a second physical sector if the data access is a read access. | 01-16-2014 |
20140026018 | METHOD FOR READING DATA FROM BLOCK OF FLASH MEMORY AND ASSOCIATED MEMORY DEVICE - A method for reading data from a block of a flash memory is provided, where the block includes a plurality of pages and at least one parity page, each of the pages includes a plurality of sectors used for storing data and associated row parities, each of the sectors of the parity page is used to store a column parity. The method includes: reading data from a specific page of the pages; decoding the data of the specific page; and when a specific sector of the specific page fails to be decoded, sequentially reading all original data of the pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the original data of the pages and the parity page corresponding to the specific sector. | 01-23-2014 |
20140026019 | INFORMATION PROCESSING SYSTEM, SHARED MEMORY DEVICE, AND METHOD FOR SAVING MEMORY DATA - An information processing system includes a plurality of clusters and a shared memory device having a shared memory shared by computer programs that operate on the clusters. The shared memory device includes an operating system (OS) stop detecting unit and a solid state drive (SSD) control unit. The OS stop detecting unit detects stop of computer programs that operate on all the clusters allocated to a certain storage area among storage areas of the shared memory shared by the clusters during an operation of the system. The SSD control unit saves, when the OS stop detecting unit detects the stop of the computer programs that operate on all the clusters allocated to the certain storage area, data stored in the certain storage area to a nonvolatile storage area. The information processing system can reduce time required to save data stored in the shared memory device when a power failure occurs. | 01-23-2014 |
20140032992 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM, AND MEMORY CONTROL METHOD - According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit. | 01-30-2014 |
20140032993 | METHOD FOR MANAGING DATA STORED IN FLASH MEMORY AND ASSOCIATED MEMORY DEVICE AND CONTROLLER - A method for managing data stored in a flash memory is provided, where the flash memory includes a plurality of blocks. The method includes: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a detecting result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and to delete the contents of the first block according to the detecting result. | 01-30-2014 |
20140040704 | SOFT-DECISION COMPENSATION FOR FLASH CHANNEL VARIATION - In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation. | 02-06-2014 |
20140047301 | SEMICONDUCTOR MEMORY DEVICE AND A METHOD THEREIN - The disclosed semiconductor memory device includes an operating environment information storing unit for storing memory characteristics representing a correlation between an operating environment of a first memory unit and a data error rate; first and second error correction units making a stepwise correction of a bit error in data, based on data stored in the first memory unit; an error rate estimation unit that compares each of parameters retained in an access counts retaining unit, a temperature information retaining unit, and a data retention period retaining unit with relevant memory characteristics and estimates an error rate of data to be accessed within the memory, and a power supply controller that controls power supply to the second error correction unit depending on an error correction step, based on the estimated error rate. | 02-13-2014 |
20140047302 | CYCLING ENDURANCE EXTENDING FOR MEMORY CELLS OF A NON-VOLATILE MEMORY ARRAY - Examples are disclosed for cycling endurance extending for memory cells of a non-volatile memory array. The examples include implementing one or more endurance extending schemes based on program/erase cycle counts or a failure trigger. The one or more endurance extending schemes may include a gradual read window expansion, a gradual read window shift, an erase blank check algorithm, a dynamic soft-program or a dynamic pre-program. | 02-13-2014 |
20140053043 | Interference-Aware Assignment of Programming Levels in Analog Memory Cells - A method for data storage includes accepting data for storage in a memory including multiple analog memory cells. For each memory cell, a respective set of nominal analog values is assigned for representing data values to be stored in the memory cell, by choosing the nominal analog values for a given memory cell in a respective range that depends on interference between the given memory cell and at least one other memory cell in the memory. The data is stored in each memory cell using the respective selected set of the nominal analog values. | 02-20-2014 |
20140059405 | SOLID-STATE DRIVE RETENTION MONITOR USING REFERENCE BLOCKS - A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed. | 02-27-2014 |
20140059406 | REDUCED LEVEL CELL MODE FOR NON-VOLATILE MEMORY - Apparatuses, systems, methods, and computer program products are disclosed for reduced level cell solid-state storage. A method includes determining that an erase block of a non-volatile storage device is to operate in a reduced level cell (RLC) mode. The non-volatile storage device may be configured to store at least three bits of data per storage cell. A method includes instructing the non-volatile storage device to program first and second pages of the erase block with data. A method includes instructing the non-volatile storage device to program a third page of the erase block with a predefined data pattern. Programming of a predefined data pattern may be configured to adjust which abodes of the erase block are available to represent stored user data values. | 02-27-2014 |
20140068382 | SYSTEMS AND METHODS TO INITIATE UPDATING OF REFERENCE VOLTAGES - In a data storage device that includes a non-volatile memory, a method includes determining that a current error correction code page count (CEC) is at least as large as a target error correction code page count (TEC). The CEC is a page count of error correction code (ECC) pages of data read from the memory during a time period from a previous time to a particular time using a set of reference voltages. In response to the CEC being at least as large as the TEC, the method includes updating a subset of the set of reference voltages conditioned upon a difference between a current mean error count (CMEC) and a previous mean error count being at least as large as a target mean delta error. The CMEC is based on a count of read errors associated with the ECC pages read during the time period. | 03-06-2014 |
20140068383 | METHOD OF STORING SYSTEM DATA, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of storing system data, and a memory controller and a memory storage apparatus using the same are provided. The method includes determining whether the unused storage space of a system physical erase unit is enough for storing updated system data. The method further includes, if the unused storage space of the system physical erase unit is not enough for storing the updated system data, selecting an empty physical erase unit, writing the updated system data into at least one first physical program unit of the selected physical erase unit and writing dummy data into a second physical program unit of the selected physical erase unit. | 03-06-2014 |
20140068384 | FLASH MEMORY SYSTEM HAVING ABNORMAL WORDLINE DETECTOR AND ABNORMAL WORDLINE DETECTION METHOD - A flash memory controller for a flash memory system includes an ECC circuit that receives first page data and second page data read from the flash memory, and respectively counts a first number of fail bits in the first page data and a second number of fail bits in the second page data, an abnormal wordline detector configured to compare the first number of fail bits and second number of fail bits to derive a fail bit change rate between the first page data and the second page data, and generate an abnormal wordline detection signal in response to the fail bit change rate, and a control unit that controls operation of the flash memory in response to the abnormal wordline detection signal. | 03-06-2014 |
20140075268 | METHOD FOR DODGING BAD PAGE AND BAD BLOCK CAUSED BY SUDDENLY POWER OFF - A method for dodging bad page and bad block caused by suddenly power off is disclosed. This method is to avoid a new data from host program to potential hurt block or page caused by power off during NAND flash erasing or programming. | 03-13-2014 |
20140082459 | MEASURING CELL DAMAGE FOR WEAR LEVELING IN A NON-VOLATILE MEMORY - An NVM controller measures cell damage for wear leveling in an NVM, thus improving performance, reliability, lifetime, and/or cost of a storage sub-system, such as an SSD. In a first aspect, the controller determines that an error reading a page of NVM was caused by cell damage and/or cell leakage. The controller reprograms and immediately reads back the page, detecting that the error was caused by cell damage if an error is detected during the immediate read. In a second aspect, the cell damage is tracked by updating cell damage counters for pages and/or blocks of NVM. In a third aspect, wear leveling is performed based at least in part upon measured cell damage for pages and/or blocks of NVM. | 03-20-2014 |
20140082460 | DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE - Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed. | 03-20-2014 |
20140089762 | Techniques Associated with a Read and Write Window Budget for a Two Level Memory System - Examples are disclosed for techniques associated with a read and write window budget for a two level memory (2LM) system. In some examples, a read and write window budget may be established for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. Other examples are described and claimed. | 03-27-2014 |
20140089763 | FLASH MEMORY AND ACCESSING METHOD THEREOF - A flash memory and an accessing method thereof are provided. The accessing method includes steps of receiving a plurality of contiguous accessing commands, sequentially selecting a plurality of word lines corresponding to the accessing commands, and accessing a plurality of memory cells on each of the word lines according to the accessing commands sequentially. Here, any two of the contiguously selected word lines do not neighbor with each other. | 03-27-2014 |
20140089764 | METHOD AND APPARATUS FOR TREATMENT OF STATE CONFIDENCE DATA RETRIEVED FROM A NON-VOLATILE MEMORY ARRAY - An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed. | 03-27-2014 |
20140089765 | ERROR ESTIMATION MODULE AND ESTIMATION METHOD THEREOF FOR FLASH MEMORY - The present invention relates to the field of data storage, and more particularly to an estimation technology in an error correction process of a flash memory. The present invention provides an error estimation module and an error estimation method thereof for a flash memory. The estimation module mainly includes a timer, a quantification index table, a storage page table, and an error index table. The error estimation method of a flash memory includes: creating rewriting and programming error a priori data, and estimating an error rate of the flash memory by using special physical signals in a flash memory device to provide proper error estimation for an error correction algorithm of the flash memory. The present invention is applicable to a solid-state hard disk controller, a flash memory controller, and the like, where the flash memory device is used as a storage medium, so that the reliability of the flash memory device is improved. | 03-27-2014 |
20140095962 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor device may comprise monitoring error handling information for a data read from a semiconductor memory device; and generating a refresh request for one or more memory cells of the semiconductor memory device according to the error handling information. | 04-03-2014 |
20140101519 | NON-VOLATILE MEMORY DEVICE HAVING ADJUSTABLE READ VOLTAGE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF OPERATING SAME - A nonvolatile memory device comprises a memory cell array comprising a selected page comprising multiple error correction code (ECC) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ECC units according to data detection results for each of the ECC units. During a read retry section performed with respect to selected ECC units of the selected page for which read errors have been detected, a re-read operation of the selected ECC units is performed according to the respective read voltage levels set for the selected ECC units. | 04-10-2014 |
20140108891 | MANAGING NON-VOLATILE MEDIA - Apparatuses, systems, and methods are disclosed to manage non-volatile media. A method includes determining a configuration parameter for a set of storage cells of a non-volatile recording medium. A method includes reading data from a set of storage cells using a determined configuration parameter. A method includes adjusting a configuration parameter based on read data. | 04-17-2014 |
20140115427 | ADAPTIVE ERROR CORRECTION CODES FOR DATA STORAGE SYSTEMS - A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved. | 04-24-2014 |
20140115428 | SYSTEMS AND METHODS FOR PROACTIVELY REFRESHING NONVOLATILE MEMORY - System and methods for proactively refreshing portions of a nonvolatile memory including a memory system that proactively refreshes a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory, when meeting certain criteria determined from the data, may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed. | 04-24-2014 |
20140122973 | DISTRIBUTED CODEWORD PORTIONS - Embodiments of the present disclosure describe apparatus, methods, computer-readable media and system configurations for dividing error correcting code (“ECC”) codewords into portions and storing the portions among multiple memory components. For example, a device may include non-volatile memory (“NVM”) including m die. A memory controller may be configured to store portions of an ECC codeword among the m die. In various embodiments, a memory controller and/or an iterative decoder such as a low-density parity-check (“LDPC”) decoder may be configured to decode ECC codewords based at least in part on reliability metrics associated with the m die. Other embodiments may be described and/or claimed. | 05-01-2014 |
20140122974 | MEMORY MODULE, MEMORY SYSTEM HAVING THE SAME, AND METHODS OF READING THEREFROM AND WRITING THERETO - A method of reading from a memory module which includes a plurality of memories is provided. The method includes reading data corresponding to a plurality of burst length units from the plurality of memories; correcting an error of the read data using a storage error correction code; and outputting the error corrected data by a unit of data corresponding to one burst length unit. | 05-01-2014 |
20140122975 | OPPORTUNISTIC DECODING IN MEMORY SYSTEMS - Approaches for decoding data read from memory cells of a nonvolatile, solid state memory involve attempting to decode hard data using a hard decoding process prior to a time that soft data is available to the decoder. The hard data includes information about the digital symbols stored in the memory cells without data confidence information. The soft data includes information about the digital symbols stored in the memory cells and data confidence information. In response to the hard decoding process failing to achieve convergence, after the soft data becomes available to the decoder, the soft data is decoded using a soft decoding process. The decoder generates an output of the decoded data after the hard decoding process or the soft decoding process achieves convergence. | 05-01-2014 |
20140129906 | DATA AND ERROR CORRECTION CODE MIXING DEVICE AND METHOD - Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy. | 05-08-2014 |
20140136928 | PROGRAMMING A NON-VOLATILE MEMORY (NVM) SYSTEM HAVING ERROR CORRECTION CODE (ECC) - A method of programming a non-volatile semiconductor memory device includes determining a number of bit cells that failed to program verify during a program operation. The bit cells are included in a subset of bit cells in an array of bit cells. The method further determines whether an Error Correction Code (ECC) correction has been previously performed for the subset of bit cells. The program operation is considered successful if the number of bit cells that failed to program verify after a predetermined number of program pulses is below a threshold number and the ECC correction has not been performed for the subset of bit cells. | 05-15-2014 |
20140136929 | STORAGE MEDIUM, SYSTEM AND METHOD UTILIZING THE SAME - A storage medium receiving write data provided by a host device, providing read data to the host and including a first module and a second module is disclosed. The first module includes a first memory cell and a first controller. The first memory cell stores the write data. The first controller reads the first memory cell to generate a first accessing result. The second module includes a second memory cell and a second controller. The second memory cell stores the write data. The second controller reads the second memory cell. When the first accessing result has an error and the error cannot be corrected by the first controller, the first controller requests the second controller to read the second memory cell to generate a second accessing result, and the second controller serves the second accessing result as the read data and provides the read data to the host. | 05-15-2014 |
20140143637 | LOG-LIKELIHOOD RATIO (LLR) DAMPENING IN LOW-DENSITY PARITY-CHECK (LDPC) DECODERS - Described embodiments provide a media controller to read data stored in a media. The media controller determines a value for each bit of a shortened codeword from the media. The shortened codeword includes a plurality of non-shortened bits of a full codeword, where the full codeword includes the plurality of non-shortened bits and one or more shortened bits. Shortened bits correspond to bits unused in the shortened codeword. The media controller converts the determined values for each bit of the shortened codeword into a first set of log-likelihood ratio (LLR) values. The full codeword is decoded using the first set of LLR values for the shortened codeword. The media controller dampens one or more LLR values corresponding to non-shortened bits of the codeword to produce a second set of LLR values and decodes the second set of LLR values. | 05-22-2014 |
20140149828 | SOLID STATE DRIVE AND JOINT ENCODING/DECODING METHOD THEREOF - A joint encoding/decoding method for a solid state drive is provided. Firstly, a data-writing process is implemented for encoding a user data by a hard codec and a soft codec respectively, thereby generating a first number of parity bits and a second number of parity bits. Then, the user data, the first number of parity bits and the second number of parity bits are written into a flash memory module. Then, a data-reading process is implemented for decoding the user data by the hard codec according to the first number of parity bits. If the user data is successfully decoded, the user data is outputted. If the user data is unsuccessfully decoded, a step of decoding the user data by the soft codec according to the second number of parity bits is performed. | 05-29-2014 |
20140157086 | STORAGE AND RETRIEVAL OF SHAPED DATA - Systems and methods of encoding and decoding shaped data include determining a bit representation corresponding to a bit in a representation of a codeword that is read from a non-volatile memory of a data storage device. A soft metric corresponding to the bit representation is determined at least partially based on an amount of shaping of data. | 06-05-2014 |
20140157087 | Bad Column Handling in Flash Memory - In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns. | 06-05-2014 |
20140157088 | MRAM Smart Bit Write Algorithm with Error Correction Parity Bits - Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location. | 06-05-2014 |
20140157089 | FORWARD ERROR CORRECTION WITH PARALLEL ERROR DETECTION FOR FLASH MEMORIES - Methods, systems, and devices are described for forward error correction for flash memory. Encoded data from flash memory may be used to generate a number of data streams. At each of a number of error detection sub-modules operating in parallel, a different one of the data streams is processed. Each error detection sub-module may detect whether a portion of the respective received stream contains an error, and forward the portion to an error correction module. The error correction module, physically separate from the error detection sub-modules, may correct the forwarded portions of the respective received streams containing an error. The age and error rate associated with the flash memory may be monitored, and a coding rate or other aspects may be dynamically adapted to account for these factors. | 06-05-2014 |
20140157090 | Programming Schemes for Multi-Level Analog Memory Cells - A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits. | 06-05-2014 |
20140164878 | Data Recovery on Cluster Failures and ECC Enhancements with Code Word Interleaving - Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability. | 06-12-2014 |
20140164879 | Data Recovery on Cluster Failures and ECC Enhancements with Code Word Interleaving - Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability. | 06-12-2014 |
20140164880 | ERROR CORRECTION CODE RATE MANAGEMENT FOR NONVOLATILE MEMORY - An apparatus having an interface and a circuit is shown. The interface is coupled to a memory that is nonvolatile. The circuit is configured to (i) read a plurality of codewords from a block in the memory based on a program/erase count associated with the block, (ii) count a number of iterations used to decode the codewords and (iii) decrease a code rate of an error correction coding used to program the block in response to the number of iterations exceeding a threshold. | 06-12-2014 |
20140164881 | POLICY FOR READ OPERATIONS ADDRESSING ON-THE-FLY DECODING FAILURE IN NON-VOLATILE MEMORY - An apparatus includes a non-volatile memory and a controller. The controller is operatively coupled to the non-volatile memory and configured to perform read and write operations on the non-volatile memory using codewords as a unit of read access. The controller includes an error correction engine configured to perform an error correction on codewords read from the non-volatile memory, and, if the error correction fails, to perform one or more retry procedures. The controller is further configured to perform one or more background procedures as a result of the error correction or one or more of the retry procedures not being successful and send an error message as a result of all of the retry procedures not being successful. The one or more background procedures are directed to determining a cause of the error correction failure. | 06-12-2014 |
20140173382 | INSPECTION OF NON-VOLATILE MEMORY FOR DISTURB EFFECTS - A method performed in a data storage device including a non-volatile memory includes reading a representation of data, the representation corresponding to one or more selected states of storage elements of a group of storage elements of the non-volatile memory. The method includes, in response to a count of errors in the representation of the data exceeding a threshold, scheduling a remedial action to be performed on the group of storage elements. | 06-19-2014 |
20140173383 | MULTILEVEL ENCODING WITH ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by responding to bits of the plurality of bits by changing the logic levels of corresponding groups of memory cells of the plurality of memory cells. Other embodiments may be described and claimed. | 06-19-2014 |
20140181621 | METHOD OF ARRANGING DATA IN A NON-VOLATILE MEMORY AND A MEMORY CONTROL SYSTEM THEREOF - A method of arranging data in a non-volatile memory and an associated memory control system are disclosed. A data area is divided into a plurality of valid data divisions, each having a link header followed by associated data and error correction code (ECC). At least one linking parameter is set in each said link header, and at least one obsolete data division including a bad column or columns is set, each said obsolete data division being flexible in size. Valid data divisions are linked and the obsolete data divisions are skipped, when accessing the non-volatile memory, according to the at least one linking parameter. | 06-26-2014 |
20140189468 | MEMORY DEVICES AND SYSTEMS CONFIGURED TO ADJUST A SIZE OF AN ECC COVERAGE AREA - Memory devices and systems having an array of memory cells arranged in a plurality of sectors and a plurality of ECC coverage areas, and control circuitry configured to adjust a size of one or more of the ECC coverage areas. | 07-03-2014 |
20140189469 | Nonvolatile Memory Devices with Age-Based Variability of Read Operations and Methods of Operating Same - Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ECC) when the error of the data read according to the first read condition is correctable. | 07-03-2014 |
20140201599 | ERROR PROTECTION FOR INTEGRATED CIRCUITS IN AN INSENSITIVE DIRECTION - A method for providing error detection, or error detection combined with error correction, to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding an error control mechanism to the array of storage cells in the insensitive direction. The insensitive direction is a direction perpendicular to a width of a gate conductor of the storage cells. | 07-17-2014 |
20140201600 | APPARATUS AND METHOD FOR ENCODING DATA FOR STORAGE IN MULTI-LEVEL NONVOLATILE MEMORY - A controller for a nonvolatile memory includes an encoder and a decoder. The memory includes memory cells that each store data using more than two levels. The encoder generates first data for storage in first memory cells. For first and second subsets of cells of the first memory cells, the first data is stored at first and second levels, respectively. Measurable values of the first subset of cells are characterized by a first probability density function having a first width. Measurable values of the second subset of cells are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first data such that a size of the first subset of cells is less than a size of the second subset of cells. The decoder decodes encoded data from the memory. | 07-17-2014 |
20140201601 | INFORMATION PROCESSING DEVICE AND METHOD, AND RECORDING MEDIUM - The present technology relates to an information processing device and method, and a recording medium, which make it possible for a data recording system and so forth to be optimized in accordance with use. Provided are: a recording system decision unit that, on the basis of characteristics which are characteristics of data to be recorded in a recording medium, and include a lifespan value representing the retention period of the data and an error rate representing the percentage of errors assumed to be generated when the data is read, generates a plurality of recording regions of a logical device configured from the recording medium, and also decides recording systems to be applied in each of the recording regions; and a logical device initialization unit that initializes each of the recording regions of the logical device on the basis of the decided recording systems. | 07-17-2014 |
20140208188 | Variable Code Rate Transmission - An integrated circuit device includes an output buffer circuit that provides a first output having a first code rate. The first output is provided in response to a first indication of a change in a parameter that affects an error rate of the first output. The first output includes redundant information. The output buffer circuit provides a second output having a second code rate. The second output is provided in response to a second indication of the second output having an error rate that is different than the error rate of the first output. The second code rate of the second output is different than the first code rate. | 07-24-2014 |
20140215291 | SYSTEMS AND METHODS FOR ERROR DETECTION AND CORRECTION IN A MEMORY MODULE WHICH INCLUDES A MEMORY BUFFER - The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another. | 07-31-2014 |
20140223263 | CONTROLLER - According to one embodiment, a controller includes a generator and a creator. The generator generates a channel matrix by counting a number of times a combination of a correct bit value and a read level appears for each bit forming a decoded first frame, based on readout data indicating a read level of each of a plurality of bits forming a frame and the decoded frame. The creator creates a table by statistically calculating a likelihood of a correct bit value of each read level based on the channel matrix. | 08-07-2014 |
20140223264 | LDPC DECODER WITH A VARIABLE NODE UPDATER WHICH USES A SCALING CONSTANT - A first message, associated with going from one of a plurality of variable nodes to one of a plurality of check nodes is computed, wherein: (1) one or more connections between the plurality of variable nodes and the plurality of check nodes are specified by an LDPC parity check matrix and (2) a scaling constant is used to compute the first message. A second message, associated with going from one of the plurality of check nodes to one of a plurality of variable nodes, is computed, wherein the scaling constant is not used to compute the second message. | 08-07-2014 |
20140237321 | SOLID STATE DRIVE CACHE RECOVERY IN A CLUSTERED STORAGE SYSTEM - A storage system that includes multiple nodes, each node comprises a SSD cache and a management module and hard disk drives that are coupled to the nodes. The management module of each node is arranged to manage a SSD cache map that comprises multiple entries for storing mappings from logical addresses to SSD cache physical addresses and to physical addresses in the hard disk drives. The mappings are related to data units stored in the SSD cache. Upon a rejoin of a certain node following a shut-down or a failure of the certain node, the certain node is arranged to: obtain from at least one other node, current mappings between logical addresses and physical addresses in the hard disk drives, and perform a validation process of the data units stored in the SSD cache in response to relationships between the current mappings and the entries of the SSD cache map. | 08-21-2014 |
20140237322 | STORAGE AT M BITS/CELL DENSITY IN N BITS/CELL ANALOG MEMORY CELL DEVICES, M>N - A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set. | 08-21-2014 |
20140245108 | ECC Management for Variable Resistance Memory Cells - A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell. | 08-28-2014 |
20140245109 | MEMORY SYSTEM AND WEAR-LEVELING METHOD THEREOF - Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly. | 08-28-2014 |
20140250348 | Controller and Method for Interfacing Between a Host Controller in a Host and a Flash Memory Device - The embodiments described herein provide a controller and method for interfacing between a host controller in a host and a flash memory device. In one embodiment, a controller comprises a first NAND interface, a second NAND interface, and one or more of the following modules: a data scrambling module, a column replacement module, and a module that manages at least one of had blocks and spare blocks. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. | 09-04-2014 |
20140281819 | Managing Data Reliability - An apparatus, system, and method are disclosed for managing data reliability. A priority module is configured to receive a storage request for a non-volatile memory device. The storage request may include data associated with a priority. The non-volatile memory device includes a plurality of cells, and each cell encodes a plurality of bits. The bits for a cell provide distinct levels of quality of service. A select module is configured to select a bit for storing the data based on the priority of the data and the level of quality of service of the selected bit. A data management module is configured to manage the data to satisfy a write order for the plurality of bits. | 09-18-2014 |
20140281820 | METHOD AND SYSTEM FOR ADAPTIVE SETTING OF VERIFY LEVELS IN FLASH MEMORY - A system and method for computing MLC flash memory cell programming parameters to dynamically adjust verify voltage levels is provided. The method may use an iterative guess and check process that will result in a distribution of states, specifically a cell voltage distribution (CVD) that minimizes the cell error rate in cells encoded in interleaved error correction code (ECC) mode, and that balances the bit error rate between pages in cells encoded in non-interleaved ECC mode. | 09-18-2014 |
20140281821 | TRANSIENT PARITY/REDUNDANCY - Mass storage uses additional error correction codes. The additional codes can be stored in a storage medium (e.g., volatile solid state memory) separate from the associated data. The additional codes may be written to a nonvolatile medium. The additional codes may be transient. The additional codes may be cached. As long as present, the additional codes may be used to correct user data in synch with or in addition to other error detection and correction codes. | 09-18-2014 |
20140281822 | METHOD AND APPARATUS FOR GENERATION OF SOFT DECISION ERROR CORRECTION CODE INFORMATION - A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device. | 09-18-2014 |
20140281823 | SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSITY PARITY CHECK DECODING - A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword. | 09-18-2014 |
20140281824 | NONVOLATILE MEMORY DEVICE AND DATA WRITE METHOD - A data write method of a nonvolatile memory device is provided which includes receiving write data to be stored in selected memory cells; reading data stored in the selected memory cells; processing the write data according to a plurality of data modulation manners to generate a plurality of modulated data values; calculating the number of flip bits and the number of switching bits when the write data and the plurality of modulated data values are overwritten on the selected memory cells, each flip bit indicating that a logical value of a selected memory cell is reversed and each switching bit indicating that a logical value of a selected memory cell is switched from a first logical value to a second logical value; and selecting one of the write data and the plurality of modulated data values according to calculating the number of flip bits and the number of switching bits. | 09-18-2014 |
20140281825 | Method for Reducing Effective Raw Bit Error Rate in Multi-Level Cell NAND Flash Memory - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 09-18-2014 |
20140281826 | ERROR CORRECTION METHOD AND MEMORY DEVICE - The present invention discloses an error correction method applied to a memory device, wherein the memory device has a plurality of pages. The error correction method includes: sequentially retrieving data of a plurality of first sectors of a first page of the pages in response to a first read command; performing a first error correction by an error correction module during retrieval the data of the first page; producing a second read command when the data of the first sectors of the first page are all retrieved; and starting to sequentially retrieve data of a plurality of second sectors of a second page of the pages in response to the second read command after the data of the first sectors of the first page are all retrieved. | 09-18-2014 |
20140281827 | MEMORY CONTROLLER, METHOD OF OPERATING THE SAME, AND SYSTEM INCLUDING THE SAME - A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data. | 09-18-2014 |
20140281828 | SYSTEM AND METHOD FOR ACCUMULATING SOFT INFORMATION IN LDPC DECODING - A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding. | 09-18-2014 |
20140298142 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY APPARATUS AND DECODING METHOD - A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed. | 10-02-2014 |
20140304567 | METHOD OF CONTROLLING A SEMICONDUCTOR STORAGE DEVICE - A method of controlling a nonvolatile semiconductor memory includes checking a first group at a first interval period, the first group including a plurality of blocks, and when a first block in the first group satisfies a first condition, assigning the first block to a second group. The method includes checking, at a second interval period, an error count of data stored in the second group, and when a second block in the second group satisfies a second condition, moving data stored in the second block to an erased block in which stored data is erased among the plurality of blocks. | 10-09-2014 |
20140310573 | SYSTEMS AND METHODS TO IMPROVE THE RELIABILITY AND LIFESPAN OF FLASH MEMORY - A method for controlling flash memory is described. The method includes selecting a new forward error correction (FEC) parameter set that provides more redundancy than a current FEC parameter set. The method also includes coding source information bits, using the new FEC parameter set, during write operations to a first corrupted page in the flash memory. The method further includes mapping the first corrupted page and at least one additional corrupted page in the flash memory to a single logical page with an expected page size. | 10-16-2014 |
20140310574 | Green eMMC Device (GeD) Controller with DRAM Data Persistence, Data-Type Splitting, Meta-Page Grouping, and Diversion of Temp Files for Enhanced Flash Endurance - A controller for a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD) increases flash endurance using a DRAM buffer. Host accesses to flash are intercepted by the controller and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type in the DRAM before storage by lower-level flash devices such as eMMC, UFS, or iSSD. Caches in the DRAM buffer for storing each data type are managed and flushed to the flash devices by the controller. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails. | 10-16-2014 |
20140310575 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written. | 10-16-2014 |
20140310576 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written. | 10-16-2014 |
20140317473 | IMPLEMENTING ECC REDUNDANCY USING RECONFIGURABLE LOGIC BLOCKS - A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic. | 10-23-2014 |
20140317474 | PHASE CHANGE MEMORY WITH SWITCH (PCMS) WRITE ERROR DETECTION - Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed. | 10-23-2014 |
20140325316 | DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS - Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks. | 10-30-2014 |
20140325317 | ERROR RECOVERY STORAGE ALONG A MEMORY STRING - Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes. | 10-30-2014 |
20140325318 | SOLID STATE DEVICE CODING ARCHITECTURE FOR CHIPKILL AND ENDURANCE IMPROVEMENT - A first decoder performs decoding on each data set in a first plurality of data sets using a first code; each data set in the first plurality is stored on a different chip. It is determined if the first decoding is successful; if not, a second decoder performs a second decoding on each data set in a second plurality of data sets using a second code; each data set in the second plurality includes at least some data, after the first decoding using the first code, from each data set in the first plurality. The first decoder performs a third decoding on each data set in the first plurality using the first code, where each data set in the first plurality includes at least some data, after the second decoding using the second code, from each data set in the second plurality. | 10-30-2014 |
20140331107 | METHOD OF STORING SYSTEM DATA, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of storing system data, and a memory controller and a memory storage apparatus using the same are provided. The method includes determining whether the unused storage space of a system physical erase unit is enough for storing updated system data. The method further includes, if the unused storage space of the system physical erase unit is not enough for storing the updated system data, selecting an empty physical erase unit, writing the updated system data into at least one first physical program unit of the selected physical erase unit and writing dummy data into a second physical program unit of the selected physical erase unit. | 11-06-2014 |
20140337689 | METHOD AND SYSTEM TO IMPROVE THE PERFORMANCE AND/OR RELIABILITY OF A SOLID-STATE DRIVE - A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page. | 11-13-2014 |
20140344647 | NAND FLASH MEMORY SYSTEMS WITH EFFICIENT SOFT INFORMATION INTERFACE - A controller for a nonvolatile memory device includes a transfer control module and a decoder module. The transfer control module is configured to request a read of data from a flash memory module. The data to be read includes data corresponding to a first codeword. The transfer control module is configured to receive hard decisions corresponding to the first codeword from the flash memory module. The transfer control module is configured to receive soft information corresponding to the first codeword from the flash memory module. Both the hard decisions corresponding to the first codeword and the soft information corresponding to the first codeword are received without receiving any intervening hard decisions or soft information corresponding to another codeword. The decoder module is configured to decode the first codeword using the hard decisions and the soft information corresponding to the first codeword. | 11-20-2014 |
20140351675 | CONTROLLER TO MANAGE NAND MEMORIES - In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system. | 11-27-2014 |
20140359398 | Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block. | 12-04-2014 |
20140359399 | STORAGE INTEGRITY VALIDATOR - This disclosure relates to validating data written to logical blocks on a storage subsystem adapted so that during write operations an additional sequence code is written to each logical block of data, where the sequence code remains constant for each write operation batch and where the sequence code is incremented for each new write operation batch. A sequence code verification system may comprise a data reader, a validity engine, and an error notifier. The data reader may read sequence codes from consecutive logical blocks. The validity engine may invalidate write operations in response to checking data validity by applying comparison operations to sequence codes and block offsets of batch write operations. The error notifier may notify a user of an error for each invalidated write operation batch. | 12-04-2014 |
20140359400 | Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block. | 12-04-2014 |
20140359401 | Field-Repair System and Method - The present invention discloses a field-repair system and method for three-dimensional mask-programmed memory (3D-MPROM). Most 3D-MPROM data are not checked in factory, but checked and repaired in field. The field-repair system comprises a playback device with a communicating means. Once the playback device detects bad data from the 3D-MPROM, it uses the communicating means to fetch good data to replace the bad data from a remote server, which stores at least a correct copy of the 3D-MPROM data. | 12-04-2014 |
20140372833 | DATA PROTECTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE - A data protecting method, a memory controller, and a memory storage device are provided. The data protecting method includes following steps. A first flush command and a first write command instructing to write a first data are received from a host system. A first error correcting code and a corresponding second error correcting code having different protection capabilities are generated according to the first data. A second write command instructing to write a second data is received. After the first write command is received, a second flush command is received from the host system, and the second error correcting code corresponding to the first data is then written into a rewritable non-volatile memory module. A second error correcting code corresponding to the second data is not generated or is generated but not written into the rewritable non-volatile memory module. Thereby, data from the host system is protected. | 12-18-2014 |
20140380129 | MEMORY SYSTEM AND METHOD OF READING DATA THEREOF - Provided is a method of reading data in a memory system including a non-volatile memory device. The method includes reading first data stored in a first block using a first read scheme capable of detecting/correcting an error in the first data, and upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block and reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme. | 12-25-2014 |
20140380130 | APPARATUS, SYSTEM, AND METHOD TO INCREASE DATA INTEGRITY IN A REDUNDANT STORAGE SYSTEM - In various embodiments, an apparatus, system, and method may increase data integrity in a redundant storage system. In one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, where one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality of storage elements is unavailable, the unavailable storage element being a functional storage element and including at least a portion of the data. Responsive to the determination, the data is reconstructed based on at least a portion of the parity information and data from one or more of the plurality of storage elements other than the unavailable storage element; a response is provided to the request such that the response includes the reconstructed data. | 12-25-2014 |
20150012801 | METHOD OF DETECTING AND CORRECTING ERRORS WITH BCH AND LDPC ENGINES FOR FLASH STORAGE SYSTEMS - A method of detecting and correcting errors with BCH and LDPC engines for flash storage systems is provided and the steps of the method comprise: deciding the number i of sub-channels CH1˜CHi divided from the data channel depending on requirement; deriving the width selection of each sub-channel CHi; checking if the sum of width of each sub-channel CHi is equal to the length of the original channel | 01-08-2015 |
20150012802 | Write Operations for Defect Management in Nonvolatile Memory - Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. | 01-08-2015 |
20150026540 | FLASH DEVICE AND OPERATING METHOD THEREOF - A flash device is provided. A flash memory includes a plurality of pages. A controller coupled to the flash memory includes an operating unit, an error correction code (ECC) decoder and a processing unit. The operating unit receives a plurality of bytes of the page which are from the flash memory and corresponding to a read command, and obtains an operating result according to a logic level of each bit of each of the bytes. The ECC decoder decodes the bytes of the page according to an ECC code. The processing unit determines whether the page is valid data according to the decoded bytes, and determines whether the page is an empty page according to the operating result when the page is not the valid data. | 01-22-2015 |
20150033096 | MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE - A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells in a first configuration comprising one or more groups of overhead data memory cells, and to configure a second block of memory cells in a second configuration comprising one or more groups of user data memory cells and at least one group of overhead data memory cells. The first configuration is different than the second configuration. At least one group of overhead data memory cells of the second block of memory cells comprises a different storage capacity than at least one group of overhead data memory cells of the first block of memory cells. | 01-29-2015 |
20150033097 | STORAGE DEVICE - A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device. | 01-29-2015 |
20150039970 | SYSTEMS AND METHODS OF STORING DATA - A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page. | 02-05-2015 |
20150039971 | RAID STORAGE SYSTEMS HAVING ARRAYS OF SOLID-STATE DRIVES AND METHODS OF OPERATION - RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value. | 02-05-2015 |
20150046774 | SEMICONDUCTOR DEVICE AND ERROR CORRECTION INFORMATION WRITING METHOD - A semiconductor device includes first and second memory cell arrays, each including a plurality of memory cells, each of which is connected between first and second terminals and is configured to be written to a first resistance state by applying a first current in a first direction between the first and second terminals and be written to a second resistance state by applying a second current in a second direction opposite to the first direction between the first and second terminals. The semiconductor device further includes an error-correction circuit and a control circuit. Additional apparatus and methods are disclosed. | 02-12-2015 |
20150052416 | Determining Data Retention Time in a Solid-State Non-Volatile Memory - Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time. | 02-19-2015 |
20150052417 | MEMORY SYSTEM AND CONTROL METHOD - According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory. | 02-19-2015 |
20150058697 | STORAGE DEVICE, CONTROLLER AND MEMORY CONTROLLING METHOD - A nonvolatile memory device includes a plurality of memory regions, and a memory controller that controls data transfer operations to and from the memory regions. When generating an error checking and correcting code (ECC) for data including a plurality of data units and writing the data and the ECC in at least one of a plurality of memory regions, the memory controller acquires ECC information and adjusts a size of the data units and a size of the ECC on the basis of the acquired ECC information, to form a plurality of data frames each including the data unit and the ECC for the data unit. | 02-26-2015 |
20150058698 | DATA RECOVERY FROM BLOCKS WITH GATE SHORTS - A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors. | 02-26-2015 |
20150058699 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A multiplexer is controlled to couple a DRAM (Dynamic Random Access Memory) to a buffer. A DMA (Direct Memory Access) controller is directed to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in multiple batches. After a first condition is satisfied, the processing unit controls the multiplexer to couple the RAID-encoding unit to the buffer and directs the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch. | 02-26-2015 |
20150058700 | Methods for Accessing a Storage Unit of a Flash Memory and Apparatuses using the Same - An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit. | 02-26-2015 |
20150058701 | FLASH MEMORY CONTROLLER AND METHOD OF DATA TRANSMISSION BETWEEN FLASH MEMORIES - Provided is a flash memory controller and a method for transmitting data between flash memories. The method includes: implementing parallel processing in a manner of separating data transmission from error detection processing, and performing delayed acknowledgment on correctness of data transmitted to a target flash memory. In addition, an error detection unit performs correction processing on data in which an error occurs, and performs an update with correct data after correction and overwrites erroneous data in a buffer of the flash memory. The foregoing technical solution may make full use of bandwidth between a flash memory controller and a flash memory array, thereby enhancing data transmission efficiency; furthermore, correction processing is also hidden in the process of data transmission, and data transmission performance of the flash memory controller in the flash memory array is further enhanced; the technical solution is applicable to a controller for various storage devices in which a flash memory device is used as a storage medium. | 02-26-2015 |
20150058702 | MULTI-LEVEL MEMORY CONTROLLER WITH PROBABILITY-DISTRIBUTION-BASED ENCODING - A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells. | 02-26-2015 |
20150067447 | METHOD, APPARATUS AND DEVICE FOR DATA PROCESSING - An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information. | 03-05-2015 |
20150067448 | METHOD OF OPERATING MEMORY DEVICE AND METHODS OF WRITING AND READING DATA IN MEMORY DEVICE - In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word. | 03-05-2015 |
20150067449 | FLASH SUBSYSTEM ORGANIZED INTO PAIRS OF UPPER AND LOWER PAGE LOCATIONS - A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith. | 03-05-2015 |
20150067450 | SOLID STATE DISK CONTROLLER APPARATUS - A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus. | 03-05-2015 |
20150074496 | MEMORY CONTROLLER, STORAGE DEVICE, AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller is provided, the memory controller including an encoding unit that performs 1 | 03-12-2015 |
20150082124 | SPATIALLY DECOUPLED REDUNDANCY SCHEMES FOR A SOLID STATE DRIVE (SSD) - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to write user data using a redundancy scheme. Information about the redundancy is (i) stored in a location separate from the data and (ii) used to recover potentially corrupted user data. | 03-19-2015 |
20150082125 | Semiconductor Device - An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction. | 03-19-2015 |
20150089329 | ELECTRONIC CIRCUIT FOR FITTING A VIRTUAL ADDRESS RANGE TO A PHYSICAL MEMORY CONTAINING FAULTY ADDRESS - A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location. | 03-26-2015 |
20150089330 | Systems and Methods for Enhanced Data Recovery in a Solid State Memory System - Systems and method relating generally to data processing, and more particularly to systems and methods for recovering data from a solid state memory. | 03-26-2015 |
20150095741 | DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved. | 04-02-2015 |
20150095742 | MULTILEVEL ENCODING WITH ERROR CORRECTION - Embodiments of the present disclosure provide methods, systems, and apparatuses related to multilevel encoding with error correction. In some embodiments, a plurality of bits may be encoded into a plurality of memory cells by level-shifting a subset of the plurality of multilevel memory cells for a bit of the plurality of bits. Other embodiments may be described and claimed. | 04-02-2015 |
20150100851 | ADAPTIVE EPWR (ENHANCED POST WRITE READ) SCHEDULING - A system and method for adaptive enhanced post write reads (EPWRs) is provided. An error rate of a block of solid state memory may be determined. Foldings may be performed more times between two consecutive enhanced post write reads on the block when the determined error rate of the block is a lower value than when the determined error rate is a higher value. The foldings may be performed by folding data into the block of the solid state memory. | 04-09-2015 |
20150100852 | ECC METHOD FOR DOUBLE PATTERN FLASH MEMORY - A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC. | 04-09-2015 |
20150100853 | APPARATUSES AND METHODS FOR STORING VALIDITY MASKS AND OPERATING APPARATUSES - Apparatuses and methods for storing a validity mask and operating apparatuses are described. A number of methods for operating an apparatus include storing a validity mask that is associated with a number of pages of memory cells in a group of pages and that provides validity information for the number of pages of memory cells in the group of pages. | 04-09-2015 |
20150100854 | ADAPTIVE ERROR CORRECTION CODES FOR DATA STORAGE SYSTEMS - A data storage system configured to adaptively code data is disclosed. In one embodiment, a data storage system controller determines a common memory page size, such as an E-page size, for a non-volatile memory array. Based on the common memory page size, the controller selects a low-density parity-check (LDPC) code word length from a plurality of pre-defined LDPC code word lengths. The controller determines LDPC coding parameters for coding data written to or read from the memory array based on the selected LDPC code word length. By using the plurality of pre-defined LDPC code word lengths, the data storage system can support multiple non-volatile memory page formats, including memory page formats in which the common memory page size does not equal any LDPC code word length of the plurality of pre-defined LDPC code word lengths. Flexibility and efficiency of data coding can thereby be achieved. | 04-09-2015 |
20150106678 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor system includes a memory configured to output a parity bit during a read operation and receive a data mask (DM) signal during a write operation. The semiconductor system also includes a System On Chip (SOC) configured to detect errors by decoding the parity bit during the read operation, and output the DM signal to the memory during the write operation. Since the parity bit is generated in the memory based on data received from outside the memory, the semiconductor device and a corresponding semiconductor system may reduce the size of a storage space for parity bits. | 04-16-2015 |
20150113358 | DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data management method, a memory controller and a memory storage apparatus are provided. The method includes grouping a plurality of physical units of a rewritable non-volatile memory module into at least a data area and a free area. The method also includes configuring a plurality of logical units for mapping a part of the physical units. The method further includes receiving at least two pieces of update data, which are corresponding to different logical pages of the logical units. The method further includes getting a physical unit from the physical units. The method further includes writing the at least two pieces of update data into the same one physical page of the gotten physical unit. Accordingly, the use efficiency of the physical units could be improved. | 04-23-2015 |
20150121173 | Systems and Methods for Internal Disk Drive Data Compression - The present invention is related to systems and methods for data storage compression. | 04-30-2015 |
20150121174 | SEMICONDUCTOR STORING DEVICE AND REDUNDANCY METHOD THEREOF - A semiconductor storing device and a redundancy method thereof are provided. The semiconductor storing device is for example a NAND flash memory, which includes: a storing array including a storing area and a redundancy storing area with a redundancy element; a page buffer; a row selecting circuit; an ECC circuit; and an I/O buffer. The row selecting circuit transforms defect data included in core data retained by a cache register into redundancy data retained by a redundancy cache register, and provides the transformed data to the ECC circuit, and the data corrected by the ECC circuit as the core data is written to the cache register again. During this period, the row selecting circuit outputs the corrected data retained in the cache register to the I/O buffer. | 04-30-2015 |
20150128011 | METHODS, CIRCUITS, SYSTEMS AND COMPUTER EXECUTABLE INSTRUCTION SETS FOR PROVIDING ERROR CORRECTION OF STORED DATA AND DATA STORAGE DEVICES UTILIZING SAME - Disclosed are methods for reading a set of bits from a NVM array (such as a SPI or parallel NOR NVM or otherwise) including: retrieving each of the set of bits from the NVM array substantially in parallel, applying substantially in parallel to each of the retrieved bits a segmented search, each search indexed using an order number of the respective bit being checked, and correcting a bit whose search indicates an error. | 05-07-2015 |
20150135038 | POST PACKAGE REPAIR OF MEMORY DEVICES - Apparatuses and methods for post package repair are disclosed. An apparatus can include memory cells in a package. A storage element can store information responsive to a post-package repair mode being activated. The information can identify an address mapped to a portion of the memory cells to be repaired. The storage element can store the information responsive to data received from nodes of the package. A walking token circuit can interrogate the information stored in the storage element in a serial fashion responsive to the post-package repair mode being activated. A mapping circuit can remap, responsive to the interrogation, the address to be repaired to another portion of the memory cells. | 05-14-2015 |
20150135039 | BLOCK CLOSURE TECHNIQUES FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line. | 05-14-2015 |
20150135040 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled. | 05-14-2015 |
20150143201 | ERROR-CORRECTING CODE DISTRIBUTION FOR MEMORY SYSTEMS - According to one embodiment, a memory system includes a plurality of memory devices and a memory controller operatively coupled to the memory devices. The memory controller is configured to partition write data into a plurality of data blocks, where each data block is associated with one of the memory devices. The memory controller is further configured to generate an instance of a local error-correcting code (ECC) corresponding to each data block, and merge each data block with the corresponding instance of the local ECC to form an encoded data block for each memory device. Additionally, the memory controller is configured to write each encoded data block to the memory devices such that each memory device stores one of the data blocks with the corresponding instance of the local ECC. A global ECC and a local ECC of the global ECC can also be included in the memory system. | 05-21-2015 |
20150143202 | Systems and Methods for Soft Decision Generation in a Solid State Memory System - Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. | 05-21-2015 |
20150143203 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a memory device suitable for outputting health monitoring data including information on a threshold voltage distribution, and outputting read data read from memory cells included in the memory device, and a controller suitable for receiving a predetermined quantity of the read data from the memory device based on the health monitoring data, and performing a decoding operation for an error correction by using the received read data. | 05-21-2015 |
20150149871 | Flash Channel With Selective Decoder Likelihood Dampening - An apparatus for reading a flash memory includes a read controller operable to read the flash memory to yield read patterns, a likelihood generator operable to map the read patterns to likelihood values, a decoder operable to decode the likelihood values, a data state storage operable to retrieve the likelihood values for which decoding failed, and a selective dampening controller operable to select at least one dampening candidate from among the likelihood values for which decoding failed, to dampen the likelihood values of the at least one dampening candidate to yield dampened likelihood values, and to provide the dampened likelihood values to the decoder for decoding. | 05-28-2015 |
20150149872 | DATA ENCODING IN SOLID-STATE STORAGE APPARATUS - A method for encoding an input data block for storage in q-level cells of solid-state memory includes producing a preliminary block from the input data block by modulation encoding at least part of the input block into a first group of q | 05-28-2015 |
20150149873 | ERROR CORRECTION METHOD AND MODULE FOR NON-VOLATILE MEMORY - There is provided an error correction method for a non-volatile memory. The method includes receiving a codeword read from the non-volatile memory, computing a reliability information for each bit of the codeword received, and performing a reduced-complexity soft-decision decoding (SDD) technique to decode the received codeword. In particular, the SDD technique includes forming a set of test patterns based on the reliability data, and determining whether to perform a HDD of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern. There is also provided an error correction module for a non-volatile memory and a memory system incorporating the error correction module. | 05-28-2015 |
20150293811 | DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved. | 10-15-2015 |
20150301933 | Multi-Level Redundancy Code for Non-Volatile Memory Controller - In the controller circuit of a non-volatile memory system, data is protected by CRC (cyclic redundancy code) between functional blocks of the controller: Before a data set is transmitted from one functional block (such the host interface) to another functional block (such as data encryption or ECC), corresponding CRC is generated and transferred with the data. At the second block, the data set can be checked with the CRC at the second block before it operates on the data. This allows the controller to check for internal transfer errors early, allow for corrupted data to be re-requested, such as from a host when this process is applied to a data write operation. After the second block finishes with the data, a new CRC can then be generated to protect the data on its next internal transfer. This arrangement can particularly useful for functional blocks that transform the data set. | 10-22-2015 |
20150309867 | COMPOSITE SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION - A composite semiconductor memory device, comprising: a plurality of nonvolatile memory devices; and an interface device connected to the plurality of nonvolatile memory devices and for connection to a memory controller, the interface device comprising an error correction coding (ECC) engine. Also, a memory system, comprising: a memory controller; and at least one composite semiconductor memory device configured for being written to and read from by the memory controller and comprising a built-in error correction coding (ECC) engine. Also, a memory system, comprising: a composite semiconductor memory device comprising a plurality of nonvolatile memory devices; and a memory controller connected to the at least one composite semiconductor memory device, for issuing read and write commands to the composite semiconductor memory device to cause data to be written to or read from individual ones of the nonvolatile memory devices; the composite semiconductor memory device providing error-free writing and reading of the data. | 10-29-2015 |
20150317203 | Code-Based Read Control for Data Storage Devices - A method is introduced for improving the data reliability of a memory device by jointly designing error-correcting codes and the reading process. In this method, simple and efficient error-correcting codes with a constant-composition part are designed for encoding data, and when reading data from memory cells, the reading reference levels may be dynamically adjusted based on the constant-composition information, which reduces the reading latency and improves the reading accuracy. | 11-05-2015 |
20150324251 | ERROR CORRECTING CODE TECHNIQUES FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION - A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes encoding first data to be stored at a first physical page. The first physical page is disposed within the memory at a first distance from a substrate of the memory, and the first data is encoded using a first encoding technique. The method further includes encoding second data to be stored at a second physical page. The second physical page is disposed within the memory at a second distance from the substrate that is greater than the first distance. The second data is encoded using a second encoding technique that is different than the first encoding technique. | 11-12-2015 |
20150339073 | SELECTION OF REDUNDANT STORAGE CONFIGURATION BASED ON AVAILABLE MEMORY SPACE - A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory. | 11-26-2015 |
20150349798 | CONTROLLER THAT RECEIVES A CYCLIC REDUNDANCY CHECK (CRC) CODE FROM AN ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICE - A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition. | 12-03-2015 |
20150355965 | HIGH SPEED FLASH CONTROLLERS - A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed. | 12-10-2015 |
20150363262 | ERROR CORRECTING CODE ADJUSTMENT FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory and a controller operationally coupled to the non-volatile memory. The controller is configured to access information stored at the non-volatile memory. The information includes a user data portion and an error correcting code (ECC) portion corresponding to the user data portion. The controller is further configured to modify the ECC portion in response to an error rate associated with the information exceeding a threshold. The one or more ECC parameters are modified without erasing or re-programming the user data portion. | 12-17-2015 |
20150365106 | DETERMINISTIC READ RETRY METHOD FOR SOFT LDPC DECODING IN FLASH MEMORIES - A method is disclosed for performing LDPC soft decoding of data stored in a flash storage device. Upon occurrence of a hard read failure, one or more retries with soft decoding after each retry are performed until soft decoding is successful or a maximum iteration count is reached. For each retry thresholds for sensing a level of a cell are adjusted according to a specific sequence. Likewise, the LLR table for each retry is selected from pre-determined LLR tables each corresponding to a retry attempt and the thresholds used for the retry attempt. The LLR table is not adjusted between retries or based on outcomes of any retries. A step size by which thresholds adjusted may be tuned to improve performance. | 12-17-2015 |
20150370631 | WRITE MAPPING TO MITIGATE HARD ERRORS VIA SOFT-DECISION DECODING - An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states. | 12-24-2015 |
20150370632 | Bad Column Handling in Flash Memory - In a flash memory, redundant columns are used alternatively as replacement columns for replacing bad columns or to provide additional redundancy for ECC encoding. Locations of bad columns are indicated to a soft-input ECC decoder so that data bits from bad columns are treated as having a lower reliability than data bits from other columns. | 12-24-2015 |
20150370633 | ERROR CORRECTING CODE ENCODER SUPPORTING MULTIPLE CODE RATES AND THROUGHPUT SPEEDS FOR DATA STORAGE SYSTEMS - Embodiments of ECC encoders supporting multiple code rates and throughput speeds for data storage systems are disclosed. In one embodiment, an encoder can provide for flexible and scalable encoding, particularly when quasi-cyclic low-density parity-check code (QC-LDPC) encoding is used. The encoder can be scaled in size based on, for example, the desired encoding throughput and/or computational cycle duration. The encoder can thus be used to support multiple code rates and throughput speeds. Accordingly, encoding speed and efficiency and system performance is improved. | 12-24-2015 |
20150370634 | ECC METHOD FOR DOUBLE PATTERN FLASH MEMORY - A method of operating a memory device storing ECCs for corresponding data is provided. The method includes writing an extended ECC during a first program operation, the extended ECC including an ECC and an extended bit derived from the ECC. The method includes overwriting the extended ECC with a pre-determined state during a second program operation to indicate the second program operation. The method includes, setting the ECC to an initial ECC state before the first program operation; during the first program operation, computing the ECC, changing the ECC to the initial ECC state if the computed ECC equals the pre-determined state; and changing the extended bit to an initial value if the ECC equals the initial ECC state. The method includes reading an extended ECC including an extended bit and an ECC for corresponding data, and determining whether to enable ECC logic using the extended ECC. | 12-24-2015 |
20150381204 | ENCODER WITH TRANSFORM ARCHITECTURE FOR LDPC CODES OVER SUBFIELDS USING MESSAGE MAPPING - A low-density parity-check (LDPC) encoder is configured to encode data for storage into a non-volatile memory of a data storage device. The LDPC encoder includes a message mapping circuit configured to receive an input message and to generate a mapped message based on the input message. The LDPC encoder also includes a matrix multiplier circuit configured to multiply the mapped message with columns of a Fourier transform of an LDPC generator matrix to generate at least a portion of a transform of an LDPC codeword. The LDPC encoder is configured to provide the transform of the LDPC codeword to an inverse Fourier transform circuit to generate the LDPC codeword. | 12-31-2015 |
20150381205 | ENCODER FOR QUASI-CYCLIC LOW-DENSITY PARITY-CHECK CODES OVER SUBFIELDS USING FOURIER TRANSFORM - A quasi-cyclic low-density parity-check (QC-LDPC) encoder includes a Fourier transform circuit configured to receive an input message and to generate a transformed message based on the input message. The transformed message includes leading symbols with indices corresponding to leading elements of cyclotomic cosets of a finite field with respect to a subfield. The QC-LDPC encoder further includes a matrix multiplier circuit configured to multiply the leading symbols of the transformed message by leading symbols of a transformed LDPC generator matrix to generate leading symbols of transformed parity symbols associated with an LDPC codeword. The QC-LDPC encoder is configured to provide the leading symbols of the transformed parity symbols to an inverse Fourier transform circuit to generate parity information of the LDPC codeword. | 12-31-2015 |
20160004596 | DATA STORAGE DEVICE WITH IN-MEMORY PARITY CIRCUITRY - A data storage device includes a memory die. The memory die includes parity circuitry and a memory having a three-dimensional (3D) memory configuration. The memory includes a first block, a second block, and a third block. A method includes generating parity information based on first data associated with a first word line of the first block and further based on second data associated with a second word line of the second block. The parity information is generated by the parity circuitry. The method further includes writing the parity information to a third word line of the third block. | 01-07-2016 |
20160026525 | MULTIPLE ECC CODEWORD SIZES IN AN SSD - Methods for writing multiple codewords having multiple sizes to a solid-state device are provided. In one aspect, a method includes receiving a plurality of host data units for storage in a solid-state non-volatile memory. The method includes dividing the plurality of host data units among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit. The method includes encoding the first data payload into a first codeword having a first codeword size. The method includes encoding the second data payload into a second codeword having a second codeword size, the second codeword size being different from the first codeword size. The method includes writing the first codeword and the second codeword to a first page in the solid-state non-volatile memory. Systems and machine-readable media are also provided. | 01-28-2016 |
20160034352 | NAND Flash Memory Having an Enhanced Buffer Read Capability and Method of Operation Thereof - A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit. | 02-04-2016 |
20160041790 | EARLY DE-ALLOCATION OF WRITE BUFFER IN AN SSD - A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical segments of data from a host; a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory; a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer; and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register. | 02-11-2016 |
20160041868 | Data Rebuild on Feedback from a Queue in a Non-Volatile Solid-State Storage - A storage cluster is provided. The storage cluster includes a plurality of storage nodes, each of the plurality of storage nodes having nonvolatile solid-state memory and a plurality of operations queues coupled to the solid-state memory. The plurality of storage nodes is configured to distribute the user data and metadata throughout the plurality of storage nodes such that the plurality of storage nodes can access the user data with a failure of two of the plurality of storage nodes. Each of the plurality of storage nodes is configured to determine whether a read of 1 or more bits in the solid-state memory via a first path is within a latency budget. The plurality of storage nodes is configured to perform a read of user data or metadata via a second path, responsive to a determination that the read of the bit via the first path is not within the latency budget. | 02-11-2016 |
20160041869 | Masking Defective Bits in a Storage Array - A method of failure mapping is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes as a storage cluster. Each of the plurality of storage nodes has a non-volatile solid-state storage with flash memory or other types of non-volatile memory and the user data is accessible via the erasure coding from a remainder of the plurality of storage nodes in event of two of the plurality of storage nodes being unreachable. The method includes determining that a non-volatile memory block in the memory has a defect and generating a mask that indicates the non-volatile memory block and the defect. The method includes reading from the non-volatile memory block with application of the mask, wherein the reading and the application of the mask are performed by the non-volatile solid-state storage. | 02-11-2016 |
20160041870 | Adjustable Error Correction Based on Memory Health in a Storage Unit - A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable. | 02-11-2016 |
20160062825 | MEMORY DEVICE AND MEMORY SYSTEM WITH SENSOR - According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command. | 03-03-2016 |
20160077911 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR ADDRESS AND DATA INTEGRITY CHECKING IN FLASH MEMORY OPERATIONS - Methods, systems, and computer readable media for address and data integrity checking in flash memory operations are disclosed. One method includes, at a storage controller, generating, for an address unit, an address parity unit. The method further includes generating a command sequence including the address unit, the address parity unit, and an operation command specifying an operation to be performed on a flash memory array. The method further includes providing the command sequence to a flash memory device that includes the non-volatile memory array. The method further includes performing, by the flash memory device, an address integrity check on the address unit using the address parity unit. The method further includes determining whether or not to perform an operation specified by the command sequence based at least in part on a result of the address integrity check. | 03-17-2016 |
20160092302 | INITIALIZATION SCHEME DURING DUAL PROGRAMMING OF A MEMORY SYSTEM - A memory system or flash memory device may include mechanism for handling power loss with a dual programming architecture. The state of primary and secondary blocks may be reconstructed to a state immediately preceding a power loss. The reconstruction may include comparing error correction code (ECC) headers of blocks to recreate a block exchange with fewer control updates. The comparison can be used to identify a primary and secondary block. The header may identify a particular stream, identify a free block, identify a release block, and other information. | 03-31-2016 |
20160098319 | SYSTEM AND METHOD FOR PRE-ENCODING OF DATA FOR DIRECT WRITE TO MULTI-LEVEL CELL MEMORY - A method and system for reducing data transfers between memory controller and multi-level cell (MLC) non-volatile memory during programming passes of a word line (WL) in the non-volatile memory. The system includes a controller and non-volatile memory having multiple WLs, each WL having a plurality of MLC memory cells. The controller stores received data in volatile memory until a target WL amount of data is received. The controller pre-encodes the received data into direct WL programming data for each programming pass necessary to program a target MLC WL. All direct WL programming data for all programming passes are stored in the volatile memory before programming. Different portions of direct WL programming data are transmitted from the controller to the non-volatile memory each pass. The received data may be deleted from the volatile memory before transmitting at least a portion of the direct WL programming data to the non-volatile memory. | 04-07-2016 |
20160139639 | RESOURCE ALLOCATION AND DEALLOCATION FOR POWER MANAGEMENT IN DEVICES - In general, techniques are described for resource allocation and deallocation that facilitates power management. A device comprising one or more processors and a memory may be configured to perform the techniques. The processor may be configured to determine usage of a first non-zero subset of a plurality of resources, the plurality of resources allocated and released in accordance with a thermometer data structure. The processors may further be configured to compare the usage of the first non-zero subset of the plurality of resources to a threshold separating the first non-zero subset of the plurality of resources from a second non-zero subset of the plurality of resources, and power on the second non-zero subset of the plurality of resources based at least on the comparison. The memory may be configured to store the threshold. | 05-19-2016 |
20160139981 | TECHNIQUES FOR INFORMATION PROTECTION IN A SOLID-STATE DEVICE BASED STORAGE POOL - A technique for protecting stored information from read disturbance includes receiving a first write request to a solid-state device (SSD) in a storage pool that employs an erasure code. The first write request has an associated identifier and associated data. In response to receiving the first write request, the first write request is assigned to two or more SSD blocks of the SSD device based on the identifier. Pages of the associated data are then written to the assigned SSD blocks, such that each SSD block holds data associated with only a single identifier. | 05-19-2016 |
20160147594 | METHOD AND APPARATUS FOR PREVENTING AND MANAGING CORRUPTION OF FLASH MEMORY CONTENTS - The present invention relates to methods and apparatuses for eliminating or mitigating the effects of the corruption of contents in a flash memory, such as that which can occur during a power interruption. Embodiments of the invention include methods for preventing the corruption of code stored in flash memory. Such methods can include partitioning code in separate physical blocks as data in a flash memory. Embodiments of the invention also include methods for mitigating the effects of corruption of data stored in flash memory. Such methods can include a book-keeping mechanism that allows for the detection of corruption events, along with the affected locations in flash memory. | 05-26-2016 |
20160162352 | SYSTEMS AND METHODS FOR ADAPTIVE ERROR CORRECTIVE CODE MECHANISMS - Systems and methods for managing the endurance of a solid state drive by assigning error corrective codes (ECC) to a plurality of solid state drive blocks are provided. The disclosed systems and methods can provide a plurality of error corrective codes, each code having a corresponding correction capability and assign to each solid state drive block an error corrective code, according to a reliability of the solid state drive block. Moreover, the disclosed systems and methods can group the solid state drive blocks into groups according to their assigned error corrective codes and apply, for each group of solid state drive block, a level of ECC correction according to the assigned error corrective code of each group. | 06-09-2016 |
20160173136 | DYNAMIC ADJUSTMENT OF DATA PROTECTION SCHEMES IN FLASH STORAGE SYSTEMS BASED ON TEMPERATURE, POWER OFF DURATION AND FLASH AGE | 06-16-2016 |
20160179613 | NONVOLATILE MEMORY APPARATUS AND CONTROL METHOD OF NONVOLATILE MEMORY APPARATUS | 06-23-2016 |
20160180926 | NONVOLATILE MEMORY SYSTEM STORING SYSTEM DATA IN MARGINAL WORD LINES | 06-23-2016 |
20160188404 | OPTIMIZING RECLAIMED FLASH MEMORY - A memory system or flash card may optimize usage of reclaimed memory. The optimization may include lists for Uncorrectable Error Correction Code (UECC) and Correctable Error Correction Code (CECC) that can be used along with a dual programming scheme. Dual programming may be utilized for blocks on the lists, but not for blocks that are not on the lists. The lists can be updated by reading data programmed to blocks on the lists. | 06-30-2016 |
20170235522 | NONVOLATILE MEMORY CAPABLE OF OUTPUTTING DATA USING WRAPAROUND SCHEME, COMPUTING SYSTEM HAVING THE SAME, AND READ METHOD THEREOF | 08-17-2017 |
20180024877 | OPTIMIZE DATA PROTECTION LAYOUTS BASED ON DISTRIBUTED FLASH WEAR LEVELING | 01-25-2018 |
20180024880 | BAD COLUMN HANDLING IN FLASH MEMORY | 01-25-2018 |
20190146867 | Systems and Methods for Adaptive Data Storage | 05-16-2019 |