| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714768000 | Error correction code for memory address | 85 |
| 20080215955 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory configured to store data at a first address and store an error detecting code corresponding to the data at a second address which is set up in a predetermined relation with the first address and different from the first address; and an address storage portion configured to store information on address relation between the first address and the second address. | 09-04-2008 |
| 20080229176 | METHOD FOR FAST ECC MEMORY TESTING BY SOFTWARE INCLUDING ECC CHECK BYTE - The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry. | 09-18-2008 |
| 20080301531 | FAULT TOLERANT ENCODING OF DIRECTORY STATES FOR STUCK BITS - A method of handling a stuck bit in a directory of a cache memory, by defining multiple binary encodings to indicate a defective cache state, detecting an error in a tag stored in a member of the directory (wherein the tag at least includes an address field, a state field and an error-correction field), determining that the error is associated with a stuck bit of the directory member, and writing new state information to the directory member which is selected from one of the binary encodings based on a field location of the stuck bit within the directory member. The multiple binary encodings may include a first binary encoding when the stuck bit is in the address field, a second binary encoding when the stuck bit is in the state field, and a third binary encoding when the stuck bit is in the error-correction field. The new state information may also further be selected based on the value of the stuck bit, e.g., a state bit corresponding to the stuck bit is assigned a bit value from the new state information which matches the value of the stuck bit. | 12-04-2008 |
| 20090125789 | BUS WITH ERROR CORRECTION CIRCUITRY - A data bus including a plurality of logic blocks coupled in series, each logic block including at least one buffer for buffering at least one data bit transmitted via the data bus and at least one of the logic blocks further including circuitry coupled in parallel with the at least one buffer and arranged to determine a first bit of error correction code associated with the at least one data bit. | 05-14-2009 |
| 20090217135 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR ADDRESS GENERATION CHECKING - A method for address generation checking including receiving a starting memory address for a data, an ending memory address for the data, a length value of the data, and an address wrap indicator value that indicates if the data wraps from an end of a memory block to a start of the memory block, determining whether the ending memory address is equal to a sum of the starting memory address added to a difference of the length value to the address wrap indicator value, and transmitting an error signal that indicates an error occurred in a generation of the starting memory address or the ending memory address if the ending memory address is not equal to the sum. | 08-27-2009 |
| 20100005368 | ENCODER OF CYCLIC CODES FOR PARTIALLY WRITTEN CODEWORDS IN FLASH MEMORY - Provided is a systematic encoder of cyclic codes for partially written codewords in flash memories wherein all bits of an erased but unwritten area have a default value such as one. In the case where the host writes data to one or a plurality of discontinuous fragments in an area reserved for storing the message section of a codeword in the flash memory, the encoder computes the parity of the codeword by using only the data written to the flash memory as input and by asserting that all bits in the gaps between the written fragments have the default erased value, such that after both the data and the parity are written to the flash memory, the area reserved for storing the codeword would contain a valid codeword. On read back, the host reads the entire codeword area from the flash memory without having to distinguish between the written and unwritten fragments. | 01-07-2010 |
| 20100332950 | BIT ERROR THRESHOLD AND CONTENT ADDRESSABLE MEMORY TO ADDRESS A REMAPPED MEMORY DEVICE - Subject matter disclosed herein relates to remapping memory devices. | 12-30-2010 |
| 20110055664 | SYSTEMS AND METHODS FOR COMPRESSING DATA IN NON-VOLATILE SEMICONDUCTOR MEMORY DRIVES - A non-volatile semiconductor memory (NVSM) storage system includes a NVSM drive interface configured to receive host data sectors (HDSs) from a host interface. A buffer managing module is configured to store the HDSs in a buffer. A compression module is configured to compress the HDSs to generate compressed HDSs of different lengths. A drive data sector (DDS) generating module is configured to add nuisance data to the compressed HDSs to generate DDSs. The DDSs are stored in NVSM. | 03-03-2011 |
| 20110087949 | RECONFIGURABLE TURBO INTERLEAVERS FOR MULTIPLE STANDARDS - A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system ( | 04-14-2011 |
| 20110107184 | DATA DISTRIBUTION UTILIZING UNIQUE READ PARAMETERS IN A DISPERSED STORAGE SYSTEM - A method begins by a processing module receiving a plurality of requests to record a broadcast of data. The method continues with the processing module encoding the data using an error coding dispersal storage function to produce a plurality of sets of encoded data slices when the data is broadcast and in response to a request of the plurality of requests. The method continues with the processing module generating a unique retrieval matrix for each of the plurality of requests based on an identity of a requesting device and the error coding dispersal storage function to produce a plurality of unique retrieval matrixes. The method continues with the processing module storing the plurality of sets of encoded data slices and the plurality of unique retrieval matrixes in a dispersed storage network memory as a plurality of unique copies of the data. | 05-05-2011 |
| 20110107185 | MEDIA CONTENT DISTRIBUTION IN A SOCIAL NETWORK UTILIZING DISPERSED STORAGE - A method begins by a dispersed storage processing module receiving media content determining social media metadata regarding the media content. The method continues with the dispersed storage processing module encoding the media content in accordance with an error coding dispersal storage function to produce a plurality of sets of encoded data slices, identifying a plurality of memories to store the plurality of sets of encoded data slices, and sending the plurality of sets of encoded data slices to the plurality of memories when the social media metadata indicates that the media content is to be available for a local social network. | 05-05-2011 |
| 20110119563 | Semiconductor memory - In order to correct an error in input data to thereby obtain write data, in a memory core, an EXOR element performs arithmetic processing based on an output result of an output data latch for latching read data and a result of inputted array input data, and a selector selects a result of the arithmetic processing to prepare write data. Thus, data obtained after performance of the arithmetic processing can be generated in a semiconductor memory by an operation performed immediately after data read. In addition, it is unnecessary to transfer data to an external logic circuit. Therefore, the result of the arithmetic processing can be written to a memory cell block in a subsequent clock. | 05-19-2011 |
| 20110126081 | REQUEST-COMMAND ENCODING FOR REDUCED-DATA-RATE TESTING - Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling. | 05-26-2011 |
| 20110126082 | MICRO CONTROLLER UNIT INCLUDING AN ERROR INDICATOR MODULE - A micro controller unit including an error indicator hardware module, the error indicator module being arranged to respond to event signals representative of internal and external fault and error events perturbing the micro controller unit function by registering in non-volatile memory a record of the nature of each of the events, wherein the record of the events is inaccessible to alteration. | 05-26-2011 |
| 20110161783 | METHOD AND APPARATUS ON DIRECT MATCHING OF CACHE TAGS CODED WITH ERROR CORRECTING CODES (ECC) - An apparatus and method is described herein directly matching coded tags. An incoming tag address is encoded with error correction codes (ECCs) to obtain a coded, incoming tag. The coded, incoming tag is directly compared to a stored, coded tag; this comparison result, in one example, yields an m-bit difference between the coded, incoming tag and the stored, coded tag. ECC, in one described embodiment, is able to correct k-bits and detect k+1 bits. As a result, if the m-bit difference is within 2k+2 bits, then valid codes—coded tags—are detected. As an example, if the m-bit difference is less than a hit threshold, such as k-bits, then a hit is determined, while if the m-bit difference is greater than a miss threshold, such as k+1 bits, then a miss is determined. | 06-30-2011 |
| 20110161784 | Method and Controller for Performing a Copy-Back Operation - The embodiments described herein provide a method and controller for performing a copy-back command. In one embodiment, a controller receives the data and error correction code associated with a copy-back operation from at least one flash memory device. The controller determines if the error correction code indicates there is an error in the data. If the error correction code does not indicate there is an error in the data, the controller sends a destination address and copy-back program command received from a host to the at least one flash memory device. If the error correction code indicates there is an error in the data, the controller corrects the data and sends the destination address, the corrected data, and a program command to the at least one flash memory device. Additional embodiments relate to modifying data during the copy-back operation. | 06-30-2011 |
| 20110231736 | Low-Power Redundancy for Non-Volatile Memory - A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array. | 09-22-2011 |
| 20110246858 | Information Processing Apparatus and Information Processing Method - According to one embodiment, there is provided an information processing apparatus including: a flash memory storing data and a first error correcting code at a physical storage area thereof, the physical storage area including a plurality of blocks, each block including a plurality of columns; a first error correcting portion configured to perform, when there is an erroneous part in the data physically read from the flash memory, a first error correction based on the first error correcting code physically read from the flash memory to thereby correct the erroneous part; and a second error correcting portion configured to perform, when the erroneous part is not corrected through the first error correction, a second error correction based on a second error correcting code obtained from the read data to thereby correct the erroneous part. | 10-06-2011 |
| 20110258516 | Method, a device and a computer program support for verification of checksums for self-modified computer code - A function of a software program is stored in a memory during execution in a device of the software program. A processor relocates the function in a region of the memory comprising dummy code, transforms the dummy code in a predictable manner, generates a predicted checksum for the region based on a previous checksum, generates a calculated checksum over the region, and verifies the integrity of the function by comparing the predicted checksum and the calculated checksum. Also provided are a device and a computer program product. | 10-20-2011 |
| 20110289387 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 11-24-2011 |
| 20110307762 | VIRTUALIZED ECC NAND - A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. | 12-15-2011 |
| 20120096331 | Multiple sector parallel access memory array with error correction - The present invention is a method for accessing more than one block of correctable information at a time when it is most efficient to access more bits of information at a time on a given dimension, for example from a multiple bit per cell (MLC) memory element, than the error correction algorithm can correct. Since it may be more efficient to access more bits of information at a time on a given dimension than the error correction algorithm can correct, that access is performed in this most efficient way, but the information is divided into correctable blocks within this information such that the error correction algorithm can still compensate for a serious fault along a given dimension. Furthermore, the present invention can be employed even when the number of bits retrieved along a given dimension is less than the number of correctable bits when it is desired to protect against a given number of faults which could, in total, exceed the number of correctable bits. | 04-19-2012 |
| 20120110416 | DATA STORAGE APPARATUS WITH ENCODER AND DECODER - According to one embodiment, an encoder/decoder apparatus includes an encoder module, a decoder module, and a transposing module. The encoder module is configured to generate a Hamming code from the input data, in accordance with a check matrix having a specific regularity. The decoder module is configured to detect an error position in the output data composed of the Hamming code, in accordance with the check matrix. The transposing module is configured to perform a transposing process of transposing some of the columns of the check matrix, while maintaining the regularity of the check matrix, and to change the error position in accordance with the transposing process, during the decoding process. | 05-03-2012 |
| 20120151300 | Error Correcting - An example apparatus has an interface to a first memory and to a second memory. The example apparatus also has a control logic that functions to control the interface. The control logic can control the interface to write a data word to the first memory and to write an error checking and correcting (ECC) word associated with the data word to the second memory. | 06-14-2012 |
| 20120159286 | DATA TRANSMISSION DEVICE, MEMORY CONTROL DEVICE, AND MEMORY SYSTEM - There is provided a data transmission device including a data information storage area including a plurality of areas for storing a first memory address of the first memory device of a data transmission source, a second memory address of the second memory device of a data transmission destination, an error signal indicating whether or not an error is detected in transmission data, and an validity signal indicating whether or not data stored in the second memory device are valid after completing the error correction; and a control unit that outputs a second memory validity address which is a memory address in which data are valid out of data stored in the second memory device, reads data from the second memory validity address of the second memory device, and transmits an address of the first memory device corresponding to the second memory validity address along with the read data. | 06-21-2012 |
| 20120179952 | PHYSICALLY UNCLONABLE FUNCTION WITH TAMPER PREVENTION AND ANTI-AGING SYSTEM - Systems for generating an identifying response pattern comprising a memory ( | 07-12-2012 |
| 20120185752 | DRAM ADDRESS PROTECTION - In one embodiment, a system includes a memory, and a memory controller coupled to the memory via an address bus, a data bus, and an error code bus. The memory stores data at an address and stores an error code at the address. The error code is generated based on a function of the corresponding data and address. | 07-19-2012 |
| 20120198312 | METHODS AND DEVICES TO INCREASE MEMORY DEVICE DATA RELIABILITY - A first data set is written to first memory units identified as having a higher data reliability and a second data set is written to second memory units identified as having a lower data reliability than the first memory units. In some cases, the second data set may include metadata or redundancy information that is useful to aid in reading and/or decoding the first data set. The act of writing the second data set increases the data reliability of the first data set. The second data set may be a null pattern, such as all erased bits. | 08-02-2012 |
| 20120216097 | Non-volatile Memory Module, Non-volatile Memory Processing System, and Non-volatile Memory Managing Method thereof - By using a processor to share certain burdens originally handled by a controller of a nonvolatile memory module, the controller is able to process more complicated procedures. The procedures include an error correction code generating procedure, a data scrambling procedure, a data recovery procedure, an address translation procedure configured to translate a logical address into a physical address, and a wear leveling procedure. | 08-23-2012 |
| 20120266048 | Dynamic Optimization of Back-End Memory System Interface - Techniques are presented for dynamically optimizing the performance of the controller-memory (or “back-end”) interface of a non-volatile memory system. Memory systems are usually designed to have a certain amount of error tolerance for error that can then be corrected by ECC. In may circumstances, such as when a device is new, the ECC capabilities of the system exceed what is needed to correct data storage errors. In these circumstances the memory system internally allots a non-zero portion of this error correction capacity to the back-end interface. This allows for the interface to operate at, for example, higher speed or lower power, even though this will likely lead to transmission path error. The system can also calibrate the back-end interface to determine that amount of error that result from various operating conditions, allowing the operating parameters of the back-end interface to be set according to amount of error that is allotted to the transfer process. | 10-18-2012 |
| 20120290898 | ADAPTIVE ENDURANCE CODING OF NON-VOLATILE MEMORIES - Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data. | 11-15-2012 |
| 20120311406 | DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS - Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks. | 12-06-2012 |
| 20120311407 | METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME - A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address. | 12-06-2012 |
| 20130132799 | PROVIDING LOW-LATENCY ERROR CORRECTING CODE CAPABILITY FOR MEMORY - A memory controller provides low-latency error correcting code (ECC) capability for a memory. In some implementations, the controller is configured to receive a memory access command that includes an address and a length associated with data that is to be transferred to or from the memory device, and transfer one or more bytes of data and one or more bytes of ECC information to or from locations of the memory device associated with the address and the length. | 05-23-2013 |
| 20130151930 | Injecting A Data Error Into A Writeback Path To Memory - In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed. | 06-13-2013 |
| 20140006902 | SEMICONDUCTOR DEVICE INCLUDING ECC CIRCUIT | 01-02-2014 |
| 20140013185 | ON CHIP REDUNDANCY REPAIR FOR MEMORY DEVICES - On chip redundancy repair for memory devices. An embodiment of a memory device includes a dynamic random-access memory (DRAM); and a system element coupled with the DRAM. The system element includes a memory controller for control of the DRAM, and repair logic coupled with the memory controller, the repair logic to hold addresses identified as failing addresses for defective areas of the DRAM. The repair logic is configured to receive a memory operation request and to implement redundancy repair for an operation address for the request. | 01-09-2014 |
| 20140059404 | MEMORY CONTROL DEVICE, MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND MEMORY CONTROL METHOD - There is provided a memory control device, including a request determining unit that determines a type of a request, and a control unit that writes read data read from a memory cell array in the memory cell array in units of predetermined pages of the memory cell array when the request is a refresh request, and divides the page of write data into units of groups and writes the page of the write data in the memory cell array over twice or more when the request is a write request. | 02-27-2014 |
| 20140068380 | METHOD AND APPARATUS TO PERFORM CONCURRENT READ AND WRITE MEMORY OPERATIONS - Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. In some embodiments, the contents of the particular partition may be indirectly read during the write process without delaying the response to the read request. The contents of the particular partition can be indirectly read by determining the contents of the particular partition based, at least in part, on an error correction code based, at least in part, on contents of memory partitions of the memory array. | 03-06-2014 |
| 20140089761 | METHOD, APPARATUS AND SYSTEM FOR PROVIDING ERROR CORRECTION INFORMATION - A memory controller to detect for an unintentional access to an incorrect location of a memory device and to provide error detection for data retrieved from an intended location of the memory device. In an embodiment, the memory controller services a read request, including retrieving data and an error correction code from a memory location. In another embodiment, the retrieved error correction code is evaluated, based on a combination of the retrieved data and an address identifier of the read request, to determine whether the address identifier of the read request corresponds to the memory location from which the data and error correction code were retrieved. | 03-27-2014 |
| 20140108888 | ERROR TOLERANT OR STREAMING STORAGE DEVICE - A method of storing data includes receiving general purpose (GP) data and special Error Tolerant or Streaming (ETS) data, storing the GP data using a data storage method, and storing the ETS data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required Quality of Service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification. For disk drives these differences include spacing between tracks; overlap between tracks; spiral track formatting; concentric track formatting, and size of blocks, and for flash memories these differences include levels per cell and number of cells. | 04-17-2014 |
| 20140108889 | MEMORY SYSTEM FOR ERROR DETECTION AND CORRECTION COVERAGE - A memory system supporting error detection and correction (EDC) coverage. The system includes a memory controller and a memory buffer. The memory buffer includes an interface to a first group of memory devices and an interface to a second group of memory devices. The memory buffer accesses data from the first group of memory devices and accesses first error information corresponding to the data from the second group of devices. The memory buffer also accesses additional data from the second group of memory devices and accesses second error information corresponding to the additional data from a device in the first group of memory devices. EDC coverage may also be configured by the memory controller so that some data accesses have EDC coverage and other data accesses do not have EDC coverage. | 04-17-2014 |
| 20140122972 | STORAGE CONTROL APPARATUS, STORAGE APPARATUS, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - A storage control apparatus includes a standard read request unit, an error correcting unit, and a high-accuracy read request unit. The standard read request unit is configured to issue a request for a read with standard accuracy to a read address in a memory. The error correcting unit is configured to perform error correction on the basis of an error correcting code and data returned by the memory in response to the read request with the standard accuracy. The high-accuracy read request unit is configured to issue, when an error incapable of being corrected by the error correction is caused, a request again for a read with higher accuracy than the standard accuracy to the read address. | 05-01-2014 |
| 20140129904 | ERROR DETECTION AND CORRECTION APPARATUS, MISMATCH DETECTION APPARATUS, MEMORY SYSTEM AND ERROR DETECTION AND CORRECTION METHOD - An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected. | 05-08-2014 |
| 20140136927 | ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE - Adaptive ECC techniques for use with flash memory enable improvements in flash memory lifetime, reliability, performance, and/or storage capacity. The techniques include a set of ECC schemes with various code rates and/or various code lengths (providing different error correcting capabilities), and error statistic collecting/tracking (such as via a dedicated hardware logic block). The techniques further include encoding/decoding in accordance with one or more of the ECC schemes, and dynamically switching encoding/decoding amongst one or more of the ECC schemes based at least in part on information from the error statistic collecting/tracking (such as via a hardware logic adaptive codec receiving inputs from the dedicated error statistic collecting/tracking hardware logic block). The techniques further include selectively operating a portion (e.g., page, block) of the flash memory in various operating modes (e.g. as an MLC page or an SLC page) over time. | 05-15-2014 |
| 20140143636 | MEMORY SYSTEM WITH VARIABLE LENGTH PAGE STRIPES INCLUDING DATA PROTECTION INFORMATION - Methods and apparatuses for enhanced protection of data stored in a non-volatile memory system involve a controller capable of adapting to the failure of one or more non-volatile memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different non-volatile memory device. The controller also detects failure of a non-volatile memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed non-volatile memory device. | 05-22-2014 |
| 20140157084 | DISTORTION ESTIMATION AND CANCELLATION IN MEMORY DEVICES - A method for operating a memory ( | 06-05-2014 |
| 20140157085 | REDUNDANT DATA STORAGE SCHEMES FOR MULTI-DIE MEMORY SYSTEMS - A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block. | 06-05-2014 |
| 20140215290 | HIGH-SPEED MEMORY SYSTEM - The disclosed embodiments relate to a Flash-based memory module having high-speed serial communication. The Flash-based memory module comprises, among other things, a plurality of I/O modules, each configured to communicate with an external device over one or more external communication links, a plurality of Flash-based memory cards, each comprising a plurality of Flash memory devices, and a plurality of crossbar switching elements, each being connected to a respective one of the Flash-based memory cards and configured to allow each one of the I/O modules to communicate with the respective one of the Flash-based memory cards. Each I/O module is connected to each crossbar switching element by a high-speed serial communication link, and each crossbar switching element is connected to the respective one of the Flash-based memory cards by a plurality of parallel communication links. | 07-31-2014 |
| 20140223262 | System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. | 08-07-2014 |
| 20140281816 | MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME - A method of operating a memory controller is provided. The method includes determining a data state based on an input stream including multiple alphabet letters, converting a part of the input stream, which corresponds to a conversion size, into alphabet letters in a lower numeral system when the data state is determined to be a first state among multiple predetermined data states, inserting one of the converted alphabet letters into the input stream, and outputting each of the alphabet letters in the input stream as is when the data state is determined to be a second state among the predetermined data states. | 09-18-2014 |
| 20140289588 | MEMORY SYSTEM - A memory system ( | 09-25-2014 |
| 20140298140 | APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY - An apparatus and method are described for detecting and correcting instruction fetch errors within a processor core. For example, in one embodiment, an instruction processing apparatus for detecting and recovering from instruction fetch errors comprises, the instruction processing apparatus performing the operations of: detecting an error associated with an instruction in response to an instruction fetch operation; and determining if the instruction is from a speculative access, wherein if the instruction is not from a speculative access, then responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core. | 10-02-2014 |
| 20140298141 | UPDATING USER DEVICE CONTENT DATA USING A DISPERSED STORAGE NETWORK - A method for updating content data for user devices begins where a processing module encodes updated content to produce sets of encoded updated content data slices. The method continues with the processing module storing the sets of encoded updated content data slices in storage units and updating an entry in a directory. The method continues with the processing module receiving, from a user device, a read request for the content data and accessing the updated entry. The method continues with the user device receiving a decode threshold number of encoded data slices for each set of encoded updated content data slices and encoded unaltered content data slices. The method continues with the user device decoding each decode threshold number of encoded data slices and the encoded unaltered content data slices to recover the updated content data. | 10-02-2014 |
| 20150046772 | METHOD AND DEVICE FOR ERROR CORRECTING CODE (ECC) ERROR HANDLING - A data storage device includes a non-volatile memory and a controller. A method includes determining a decoding error associated with information stored at a page of a first block of the non-volatile memory. In response to the decoding error, a physical address is accessed from the management table. The physical address corresponds to a trial logical address. In response to the physical address corresponding to the page, the method further includes moving data from the page to a second block of the non-volatile memory. | 02-12-2015 |
| 20150046773 | READ REQUEST PROCESSING APPARATUS - A wrapping burst read determination unit determines whether or not a read request is a request of a wrapping read. If the read request is the request of the wrapping read, a memory address conversion unit extracts a plurality of addresses that includes an address in which payload data requested by the read request is stored, and designates a read out order of data from the plurality of addresses extracted. If the read request is the request of the wrapping read, a first data holding unit inputs first data read out from an address to which a forefront position in the read out order has been designated among the plurality of addresses, and stores the first data. If the read request is the request of the wrapping read, a data alignment unit, inputs trailing data read out from an address to which an end position in the read out order has been designated, and extracts payload data and an ECC which are correlated with each other from the first data and the trailing data. | 02-12-2015 |
| 20150052415 | DATA STORAGE DEVICE, OPERATING METHOD THEREOF AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller comprises a victim block setup unit suitable for setting a victim block for performing a merge operation, based on an error count, which is detected when a read operation of the nonvolatile memory device is performed, and for storing information of the victim block. | 02-19-2015 |
| 20150067446 | DECODING METHOD, MEMORY STORAGE DEVICE AND REWRITABLE NON-VOLATILE MEMORY MODULE - A decoding method, a memory storage device and a rewritable non-volatile memory module are provided. The method includes: reading a plurality of bits from the rewritable non-volatile memory module according to a reading voltage; performing a parity check of a low density parity check (LDPC) algorithm on the bits to obtain syndromes, and each of the bits is corresponding to at least one of the syndromes; determining whether the bits have an error according to the syndromes; if the bits have the error, obtaining a syndrome weight of each of the bits according to the syndromes corresponding to each of the bits; obtaining an initial value of each of the bits according to the syndrome weight of each of the bits; and performing a first iteration decoding of the LDPC algorithm on the bits according to the initial values. Accordingly, the decoding speed is increased. | 03-05-2015 |
| 20150074494 | SELF-REPAIR DEVICE - A self-repair device includes an ARE (array rupture electrical fuse) array block configured to store fail addresses; an ARE control block configured to control a repair operation of fuse sets according to the fail addresses, compare a plurality of the fail addresses, and determine a failed state; and a redundancy block configured to store fuse data of the fail addresses, compare an input address with the fail addresses, and control row and column redundancy operations. | 03-12-2015 |
| 20150074495 | ADDRESS ERROR DETECTION - Address error detection including a method that receives a read address corresponding to a read location in a memory. Data is read from the read location in the memory. The data is transformed at a computer based on the data and the read address to produce read data. Error correction codes (ECC) bits associated the read data are read from the read location in the memory. The ECC bits were generated based on the write data. It is determined whether the read data has an address error responsive to the read data and the ECC bits associated with the write data. An error is generated in response to determining that the read address has an address error. | 03-12-2015 |
| 20150082123 | USER STATION OF A BUS SYSTEM AND METHOD FOR TRANSMITTING MESSAGES BETWEEN USER STATIONS OF A BUS SYSTEM - A user station for a bus system is described and a method for transmitting messages between user stations of a bus system. The user station has a CAN-Controller for reading data of a message to be sent directly from a RAM without buffer storage in a buffer store, and a memory access error detection/processing device for detecting a memory access error of the CAN controller and for processing a detected memory access error. | 03-19-2015 |
| 20150089327 | SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region. | 03-26-2015 |
| 20150113357 | DATA STREAMING FOR SOLID-STATE BULK STORAGE DEVICES - Methods facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists containing mixed data types facilitate receiving and outputting user data, and to insert or ignore, respectively, metadata corresponding to that user data without interrupting flow of the user data. | 04-23-2015 |
| 20150128009 | MEMORY SYSTEM AND MEMORY CONTROLLER - A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2| 05-07-2015 | |
| 20150128010 | PROTECTION AGAINST WORD LINE FAILURE IN MEMORY DEVICES - A method for data storage includes providing a mapping of data pages to physical pages, in which each physical page holds a non-integer number of the data pages, for storage of data in at least one memory block, including a plurality of the physical pages, in a memory device. The data pages that are mapped to the memory block are partitioned into groups, such that failure of any memory unit, which consists of a predefined number of the physical pages in the memory device, will produce errors in no more than one data page in each group. The data pages is stored in the physical pages of the memory block in accordance with the mapping, while a redundant storage scheme is applied among the data pages of each group. | 05-07-2015 |
| 20150135037 | APPARATUSES AND METHODS INCLUDING ERROR CORRECTION CODE ORGANIZATION - Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described. | 05-14-2015 |
| 20150143198 | METHOD AND APPARATUS FOR MULTIPLE-BIT DRAM ERROR RECOVERY - A system for replacing a page stored in system memory when reading the page incurs a multiple-bit error. Upon reading a page in system memory for which a multiple-bit error is detected, backup data in flash memory is loaded into a redundant page in the system memory, and a re-mapper is configured so that future accesses to the page are redirected to the redundant page. | 05-21-2015 |
| 20150143199 | COMPUTER MEMORY POWER MANAGEMENT - A method of operating a computer memory system with ECC features that will enable operational modes with less electrical power consumption. A chip mark normally used to mark a failing DRAM device may instead be used to mark a non-failing DRAM device before a computer memory system shuts off electrical power to the marked non-failing DRAM device to reduce power consumption, putting the rank of memory that contains the DRAM device in a low power consumption mode. Upon a request from the computer memory system, the chip mark may be removed from the marked non-failing DRAM device in order to return the non-failing DRAM device to normal operation. | 05-21-2015 |
| 20150149866 | EARLY DATA TAG TO ALLOW DATA CRC BYPASS VIA A SPECULATIVE MEMORY DATA RETURN PROTOCOL - A bypass mechanism allows a memory controller to transmit requested data to an interconnect before the data's error code has been decoded, e.g., a cyclical redundancy check (CRC). The tag, tag CRC, data, and data CRC are pipelined from DRAM in four frames, each having multiple clock cycles. The tag includes a bypass bit indicating whether data transmission to the interconnect should begin before CRC decoding. After receiving the tag CRC, the controller decodes it and reserves a request machine which sends a transmit request signal to inform the interconnect that data is available. Once the transmit request is granted by the interconnect, the controller can immediately start sending the data, before decoding the data CRC. So long as no error is found, the controller completes transmission of the data to the interconnect, including providing an indication that the data as transmitted is error-free. | 05-28-2015 |
| 20150149867 | STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data. | 05-28-2015 |
| 20150149868 | DATA PROTECTION SYSTEM - The present invention provides systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format. The present invention also provides systems and methods for protecting data stored on data storage medium so that the data may be recovered without errors. | 05-28-2015 |
| 20150309868 | METHOD AND APPARATUS TO PERFORM CONCURRENT READ AND WRITE MEMORY OPERATIONS - Subject matter disclosed herein relates to read and write processes of a memory device. During a write process to a particular partition in a memory array, a response to a read request of contents of the particular partition may be delayed. In some embodiments, the contents of the particular partition may be indirectly read during the write process without delaying the response to the read request. The contents of the particular partition can be indirectly read by determining the contents of the particular partition based, at least in part, on an error correction code based, at least in part, on contents of memory partitions of the memory array. | 10-29-2015 |
| 20150309959 | System and Method of Interfacing Co-Processors and Input/Output Devices via a Main Memory System - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. | 10-29-2015 |
| 20150324253 | RANK-MODULATION REWRITING CODES FOR FLASH MEMORIES - Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory. | 11-12-2015 |
| 20150331741 | ERROR CORRECTION PROCESSING CIRCUIT IN MEMORY AND ERROR CORRECTION PROCESSING METHOD - A method for correcting error in a memory comprises setting a protected scope for at least part of unit data to be written in the memory according to an operation voltage of the memory; implementing error correction encoding for protected data corresponding to the protected scope among the unit data; and writing the unit data in the memory while matching them with parity data generated as a result of the error correction encoding. | 11-19-2015 |
| 20150347225 | SYSTEMS AND METHODS FOR IMPROVING EFFICIENCIES OF A MEMORY SYSTEM - A memory device includes a memory component that store data. The memory device also includes a processor that receives a signal indicating that the memory component is coupled to the processor and retrieves information from the memory component. The information may include one or more algorithms capable of being performed by the memory component. The processor may then receive one or more packets associated with one or more data operations regarding the memory component. The processor may then perform the one or more data operations by using the memory component to employ the one or more algorithms. | 12-03-2015 |
| 20150378814 | EXTENSIBLE MEMORY HUB - The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub includes an upstream interface port configured to couple the first EN hub to an NVM controller or to a second EN hub; a downstream interface port configured to couple the first EN hub to a third EN hub or to a NVM device; at least one NVM device port, each NVM device port configured to couple the first EN hub to a respective NVM device via a NVM channel; and an EN hub controller. The EN hub controller includes command logic configured to initialize the first EN hub in response to an initialize chain command from the NVM controller, the initializing including enumerating each NVM device coupled to the first EN hub and each of one or more associated NVM dies. | 12-31-2015 |
| 20160085624 | MEMORY CONTROLLER WITH READ UNIT LENGTH MODULE - Technologies are generally described for systems, devices and methods relating to generation of an instruction to store data. Read unit length information may be identified for data. The read unit length information may include a read unit length. The data may have a data length. The data length may implicate a first error correction code of a first size. The read unit length may relate to an amount of the data to be read as a unit from a memory. The read unit length may be different from the data length. A second error correction code may be determined to store the data. The second error correction code may be based on the read unit length information. The second error correction code may have a second size. The instruction may be effective to store the second error correction code in association with the data in a memory. | 03-24-2016 |
| 20160139982 | GREEN NAND SSD APPLICATION AND DRIVER - A GNSD Driver coupled to host DRAM, and having a memory manager, a data grouper engine, a data ungrouper engine, a power manager, and a flush/resume manager. The GNSD driver is coupled to a GNSD application, and the host DRAM to a Non-Volatile Memory Device. The GNSD Driver further includes a compression/decompression engine, a de-duplication engine, an encryption/decryption engine, or a high-level error correction code engine. The encryption/decryption engine encrypts according to DES or AES. A method of operating a GNSD Driver and a GNSD application coupled to DRAM of a host, includes coupling: Configuration and Register O/S Settings to the host and the GNSD Application; a data grouper and data ungrouper to the host DRAM and to Upper and a Lower Filter; a power manager and a memory manager to the host; a flush/resume manager to the DRAM; and the DRAM to an SEED SSD. | 05-19-2016 |
| 20160139985 | RECOVERY IMPROVEMENT FOR QUIESCED SYSTEMS - Methods and apparatuses for performing a quiesce operation during a processor recovery action is provided. A processor performs a processor recovery action. A processor retrieves a quiesce status of a computer system from a shared cache with a second processor. A processor determines a quiesce status of the first processor based, a least in part, on the retrieved quiesce status of the computer system. | 05-19-2016 |
| 20160147598 | OPERATING A MEMORY UNIT - A method for operating a memory unit is disclosed. The method includes encoding data from a cache line divided in a plurality of groups and generating a plurality of codewords. The method further includes storing the LED data for the cache line combined with the data of the cache line retrieved from a first portion of the codewords across a plurality of chips in the memory unit to create a first tier of protection. The method also includes storing the GEC data for the cache line retrieved from a second portion of the codewords across the plurality of chips to create a second tier of protection for the cache line. The method also includes receiving information corresponding to the first tier of protection, determining whether an error exists in the data of the cache line, decoding the data of the cache line, and outputting the data of the cache line at the controller. | 05-26-2016 |
| 20160147619 | HYPERVISOR ASSISTED VIRTUAL MEMORY OBFUSCATION - Remote computing resource service providers allow customers to execute one or more applications in a virtual environment on computer systems provided by the computing resource service provider. The virtual machines may be managed by a hypervisor executing on computer systems operated by the service provider. The virtual machines' memory may be protected by a memory obfuscation service and the hypervisor. The memory obfuscation service may enable the virtual machines to maintain at least a portion of sensitive information in an obfuscated format. The virtual machines may request access to the virtual machines' memory, the memory obfuscation service may obtain the requested memory in an obfuscated format and un-obfuscate the memory such that it may be used by the virtual machines. | 05-26-2016 |
| 20160170921 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DATA TRANSFER PROCESSING THE SAME | 06-16-2016 |
| 20160173128 | MEMORY CONTROLLER AND METHOD OF DATA BUS INVERSION USING AN ERROR DETECTION CORRECTION CODE | 06-16-2016 |
| 20160378590 | CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes. | 12-29-2016 |
