| Entries |
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| 20080256419 | Configurable Split Storage of Error Detecting and Correcting Codes - Memory space of a digital device may be configured for both instructions/data (op-code) and ECC or parity when required, otherwise the entire memory space may be configured for just the program instructions/data. A standard word width memory may be configured for ECC or non-ECC functionality, or parity or non-parity functionality, based upon a desired application. The last portion of the memory may be allocated for ECC or parity data rather then application code when an ECC or parity implementation is required. When an ECC or parity implementation is not required, the entire memory may be used for the application code. This allows a digital device and memory to be used in applications having different robustness (e.g., application code integrity) requirements without have to fabricate different digital devices. | 10-16-2008 |
| 20090089646 | SEMICONDUCTOR STORAGE DEVICE - Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path system is formed in bit slices. Further, parity bits are equally distributed so as to cause delay times of bits to be uniform. | 04-02-2009 |
| 20090249169 | SYSTEMS, METHODS, AND APPARATUSES TO SAVE MEMORY SELF-REFRESH POWER - Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors. | 10-01-2009 |
| 20100332949 | SYSTEM AND METHOD OF TRACKING ERROR DATA WITHIN A STORAGE DEVICE - Systems and methods of tracking error data are disclosed. A method includes receiving a first checksum associated with error locations of a first error correction code operation and receiving a second checksum associated with error locations of a second error correction code operation. The first checksum is compared to the second checksum and an action is initiated on a region of a memory array based on a result of the comparison. | 12-30-2010 |
| 20110004807 | LOADING SECURE CODE INTO A MEMORY - A method of verifying the integrity of code in a programmable memory, the method including: receiving the code from an insecure memory; generating error detection bits for the code as it is received from the insecure memory; storing the code and the error detection bits in the programmable memory; and verifying the integrity of the code stored in the programmable memory by performing an authentication check on the code and the error detection bits stored in the programmable memory. | 01-06-2011 |
| 20110119562 | SYSTEM AND METHOD FOR UNCODED BIT ERROR RATE EQUALIZATION VIA INTERLEAVING - A device, method, and computer readable medium for programming a codeword are presented. The method includes writing a first codeword portion to portions of nonvolatile memory rows, and writing a second codeword portion to portions of nonvolatile memory rows, wherein the first group of memory rows and the second group belong to non-overlapping groups. The device includes multiple nonvolatile memory rows, and a controller receiving a codeword comprising a first codeword portion and a second codeword portion. The controller writing the first codeword portion to portions of nonvolatile memory rows, and writing the second codeword portion to portions of nonvolatile memory rows, wherein the first group of nonvolatile memory rows differs and the second group of nonvolatile memory rows belong to non-overlapping groups, and the first and second groups of memory rows belong to multiple rows. A computer readable medium having stored thereon instructions performing methods described herein. | 05-19-2011 |
| 20120030543 | PROTECTION OF APPLICATION IN MEMORY - A method, a memory controller and a processor architecture for protecting an application in a memory are disclosed. The application is cached as memory lines according to a size of a cache line. For example, the method comprises: in response to a load access request from a processor, reading from the memory a flagged memory line and an ECC checksum corresponding to the memory line, wherein the flagged memory line is obtained by performing a logic operation on a predetermined bit of the memory line and a flag bit for identifying the memory line; performing an ECC check on the flagged memory line by using the ECC checksum to obtain a value of the flag bit of the memory line; restoring the flagged memory line to the memory line according to the value of the flag bit; and determining whether or not to load the memory line according to the value of the flag bit and the type of the load access request from the processor. | 02-02-2012 |
| 20120047418 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM - An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet. | 02-23-2012 |
| 20120066569 | MEMORY SYSTEM, MEMORY SYSTEM CONTROLLER, AND A DATA PROCESSING METHOD IN A HOST APPARATUS - A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system. | 03-15-2012 |
| 20120066570 | APPARATUS AND METHODS HAVING MAJORITY BIT DETECTION - Electronic apparatus and fabrication of the electronic apparatus that includes detection of the majority of values in a plurality of data bits may be used in a variety of applications. Embodiments include application of majority bit detection to process data bits in a device for further analysis in the device based on the results of the majority bit detection. In an embodiment, such further processing in a memory device after majority bit detection may include data bit inversion prior to outputting the data from the memory device. | 03-15-2012 |
| 20120185751 | SERIAL PROCESSING METHOD, PARALLEL PROCESSING METHOD OF BIT RATE MATCHING AND DEVICE THEREOF - A serial processing method and a parallel processing method of bit rate matching and apparatuses thereof are disclosed in the present invention. The serial processing method includes: receiving a system bit data stream, a check | 07-19-2012 |
| 20120192035 | MEMORY SYSTEM AND OPERATION METHOD THEREOF - A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory. | 07-26-2012 |
| 20120226962 | WEAR-FOCUSING OF NON-VOLATILE MEMORIES FOR IMPROVED ENDURANCE - Storing data in memory using wear-focusing techniques for improved endurance. A method for storing the data includes receiving write data to be written into a memory that is logically divided into a plurality of regions. The plurality of regions includes a first region and a second region that are implemented by the same memory technology. The memory is subject to degradation as a result of write operations. The write data is classified as dynamic data or static data. The write data is encoded using a first type of encoding in response to the write data being classified as dynamic. The write data encoded using the first type of encoding is stored in the first region of the memory. The write data is encoded using a second type of encoding and stored in the second region of the memory in response to classifying the write data as static data. | 09-06-2012 |
| 20120290897 | DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND ON-CHIP BUFFER PROGRAM METHOD THEREOF - A data storage device includes a multi-bit memory device including a memory cell array, the memory cell array including a first memory region and a second memory region, and a memory controller including a buffer memory and configured to control the multi-bit memory device. The memory controller is configured to control the multi-bit memory device to execute a buffer program operation in which data stored in the buffer memory is stored in the first memory region, and to control the multi-bit memory device to execute a main program operation in which the data stored in the first memory region is stored in the second memory region. The memory controller is further configured to generate parity data based upon the data stored to the first region, the parity data being copied from the first memory region to the second memory region via the main program operation. | 11-15-2012 |
| 20120297271 | DATA SCRAMBLING SCHEMES FOR MEMORY DEVICES - A method for data storage includes defining a set of scrambling sequences, each sequence including bits in respective bit positions having bit values, such that a distribution of the bit values in any give bit position satisfies a predefined statistical criterion. Each data word is scrambled using a respective scrambling sequence selected from the set. The scrambled data words are stored in the memory device. | 11-22-2012 |
| 20130024746 | SYSTEMS AND METHODS OF STORING DATA - A method of storing data includes receiving data including a first group of bits and a second group of bits and initiating a shaping encoding operation on the second group of bits to generate a third group of bits. The third group of bits has more bits than the second group of bits. The shaping encoding operation is configured to produce a non-uniform probability distribution of bit values in the third group of bits. The first group of bits and first error correction coding (ECC) parity bits corresponding to the first group of bits are stored to a first logical page that is within a physical page of a MLC memory and the third group of bits and second ECC parity bits corresponding to the third group of bits are stored to a second logical page that is within the physical page of the MLC memory. | 01-24-2013 |
| 20130080856 | NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed. | 03-28-2013 |
| 20130111301 | BLOCK MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE THEREOF | 05-02-2013 |
| 20130124942 | Techniques For Storing Data in Stuck and Unstable Memory Cells - A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault value to the stuck-at fault value. The control circuit is operable to generate encoded data bits by inverting each of the data bits having a different value than the stuck-at fault value of the corresponding one of the memory cells and by maintaining a digital value of each of the data bits having the stuck-at fault value of the corresponding one of the memory cells. The control circuit is operable to prevent any of the data bits from being stored in the memory cells determined to have unstable values. The control circuit is operable to generate redundant bits that indicate at least one operation to perform on the encoded data bits to regenerate the data bits. | 05-16-2013 |
| 20130124943 | Techniques For Storing Data in Stuck Memory Cells - A data storage system includes a memory circuit and a control circuit. The control circuit is operable to receive data bits provided for storage in memory cells of the memory circuit. The control circuit is operable to compare each of the data bits provided for storage in a corresponding one of the memory cells having a stuck-at fault to a value of the stuck-at fault, and to invert each of the data bits having a different value than the value of the stuck-at fault of the corresponding one of the memory cells to generate encoded data bits. The control circuit is operable to generate redundant bits that indicate the encoded data bits to invert to regenerate the data bits. | 05-16-2013 |
| 20130132798 | Bit Stream Aliasing in Memory System with Probabilistic Decoding - An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing. | 05-23-2013 |
| 20130139033 | TECHNIQUES FOR EMBEDDED MEMORY SELF REPAIR - Techniques are provided for classifying and correcting errors in a bit sequence. At a memory control device, access is requested to a first bit sequences that is stored in a bit sequence database of a memory component and associated with an address. An error is detected in the first bit sequence, and the address associated with the bit sequence is compared to addresses stored in an address database of a content addressable memory component to determine if there is a match. When there is a match, the error is classified as a hard bit error. When there is not a match, the error is classified as a soft bit error. | 05-30-2013 |
| 20130151929 | Efficient Storage of Meta-Bits Within a System Memory - Mechanisms are provided for efficient storage of meta-bits within a system memory. The mechanisms combine an L/G bit and an SUE bit to form meta-bits. The mechanisms then determine the local/global state of a cache line on the first cycle of data. The mechanisms forward the data to the requesting cache, and the requesting cache may reissue the request globally based on the local/global state of the cache line. The mechanisms then determine the special uncorrectable error state of the cache line on the second or subsequent cycle of data. The mechanisms perform error processing regardless of whether the request was reissued globally. | 06-13-2013 |
| 20130166992 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b | 06-27-2013 |
| 20130185611 | BIT ERROR CORRECTION FOR REMOVING AGE RELATED ERRORS IN A BIT PATTERN - A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier. | 07-18-2013 |
| 20130191702 | FORWARD ERROR CORRECTION WITH CONFIGURABLE LATENCY - A method of performing forward error correction with configurable latency, where a configurable latency algorithm evaluates a target Bit Error Rate (BER) against an actual BER and adjusts the size of a configurable buffer such that the target BER may be achieved when utilizing the smallest buffer size possible. When errors are corrected without the utilization of each of the configurable buffer locations, the algorithm reduces the size of the buffer by y buffer locations; the algorithm may continue to successively reduce the size of said buffer until the minimum number of buffer locations are utilized to achieve the target BER. If the buffer locations have been reduced such that the buffer size is too small and the target BER cannot be achieved, the algorithm may increase the size of the buffer until the minimum number of buffer locations are utilized to achieve the target BER. | 07-25-2013 |
| 20130219247 | Method for Accessing Flash Memory and Associated Flash Memory Controller - An exemplary method for accessing a flash memory. The method comprising obtaining a first random sequence; utilizing the first random sequence as a first seed for generating a second random sequence, wherein the first random sequence is not equivalent to the second random sequence; scrambling data according to the second random sequence for generating scrambled data; performing an error correction encoding operation upon the first random sequence and the scrambled data for generating parity check code; and storing the scrambled data and the parity check code to the flash memory. | 08-22-2013 |
| 20130219248 | STORAGE CONTROL APPARATUS AND STORAGE CONTROL METHOD - A storage control apparatus receives a write request for a storage apparatus. When the storage control apparatus receives the write request, the storage control apparatus duplicates into a specific storage area, data stored in a storage area of the storage apparatus and parity data whose generation source is the data. The storage control apparatus determines whether one of the storage apparatuses is started up for which a writing process is executed in response to the write request. When the storage apparatus is re-started, the storage control apparatus writes the data duplicated in the specific storage area into the storage area of the duplication source of the storage apparatus and writes the parity data duplicated in the specific storage area into the storage area of the duplication source of the storage apparatus. | 08-22-2013 |
| 20130232392 | MANAGING MEMORY UTILIZATION IN A DISTRIBUTED STORAGE AND TASK NETWORK - A method begins by a distributed storage (DS) processing module retrieving a data slice from a local memory and performing a partial task on the data slice. When the performing of the partial task is complete, the method continues with the DS processing module determining whether at least a retrieval number of slices of a set of slices of a data segment that includes the data slice is available from a set of DST execution units. When the at least a retrieval number of slices is available, the method continues with the DS processing module deleting the data slice from the local memory. When the at least a retrieval number of slices of the set of slices is not available, the method continues with the DS processing module determining whether execution of a task on the data segment is complete and deleting the data slice when the execution is complete. | 09-05-2013 |
| 20130262959 | TEMPORARILY STORING AN ENCODED DATA SLICE - A processing module encodes data using a dispersed storage error coding function to produce a set of encoded data slices and identifies storage units for storage of the set of encoded data slices. The processing module determines that a storage unit of the storage units is unavailable, where the storage unit is targeted to store an encoded data slice of the set of encoded data slices. The processing module selects a foster storage unit of the storage units for temporarily storing the encoded data slice. When the storage unit is available, the processing module transfers the encoded data slice from the foster storage unit to the storage unit. | 10-03-2013 |
| 20130311853 | NON-VOLATILE MEMORY WITH EXTENDED ERROR CORRECTION PROTECTION - Embodiments of the present disclosure provide methods and apparatuses related to NVM devices with extended error correction protection. In some embodiments, a parity cache is used to store parity values of data values stored in a plurality of codewords of an NVM device. Other embodiments may be described and claimed. | 11-21-2013 |
| 20140006901 | MEMORY SYSTEM | 01-02-2014 |
| 20140026014 | SOFT DECODING FOR QUANTIZIED CHANNEL - Systems, methods, and other embodiments associated with soft decoding for a quantized channel are described. According to one embodiment, a method includes repetitively controlling the soft decoder to attempt to decode the signal based, at least in part, on a reliability measure selected from a pre-determined collection of reliability measures. When the soft decoder fails to decode the signal, the method includes computing a new reliability measure and repetitively controlling the soft decoder to attempt to decode the signal based, at least in part, on the new reliability measure. When the soft decoder decodes the signal with the new reliability measure, the method includes adding the new reliability to the pre-determined collection of reliability measures. | 01-23-2014 |
| 20140026015 | SYSTEMS AND METHODS FOR EFFICIENT LOW DENSITY PARITY CHECK (LDPC) DECODING - A method for low density parity code decoding according to one embodiment includes sequentially processing groups of variable node (vim& values associated with a codeword using a plurality of vnode logic modules and outputting updated vnode values; storing the vnode values and updated vnode values in a vnode memory; sequentially processing groups of cnode values using a plurality of check node (cnode) logic modules and outputting updated vnode values; storing the (mode values and updated (mode values in a mode memory; and checking the codeword using the updated vnode values and the updated mode values. | 01-23-2014 |
| 20140026016 | MEMORY WITH SELECTIVELY WRITABLE ERROR CORRECTION CODES AND VALIDITY BITS - Memory and method for storing a plurality of memory bits. The memory has a data storage element and a processor. The data storage element has a plurality of lines, each having a plurality of segments having a plurality of data bits. A plurality of error correction codes are each associated with one of the lines. A plurality of validity bits, each being associated with one of the lines, are configured to indicate that one of the error correction codes associated with the one of the lines is valid or invalid. The processor is configured to generate one of the error correction codes for all of the data bits in the segments associated with one of the lines. | 01-23-2014 |
| 20140040702 | MANAGING A STORAGE ARRAY - The present invention provides a method and apparatus of managing a storage array. The method comprises: striping the storage array to form a plurality of stripes; selecting F storage chunks from each stripe as local parity chunks, and selecting another L storage chunks from the storage array as global parity chunks; performing (F+L) fault tolerant erasure coding on all data chunks in a stripe to generate (F+L) groups of parity data, and storing F groups of parity data therein into the F local parity chunks; performing cross-stripe operation on another L groups of parity data to generate L groups of global parity data, and storing them into the L global parity chunks, respectively. The apparatus corresponds to the method. With the invention, a plurality of errors in the storage array can be detected and/or recovered to improve fault tolerance and space utilization of the storage array. | 02-06-2014 |
| 20140047300 | MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROCESSING DATA THEREOF - A data processing method adapted for a rewritable non-volatile memory module is provided. The method includes receiving a first data stream and performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting (ECC) code corresponding to the first data stream. The method also includes converting the original ECC code into a second ECC code according to a second rearrangement rule, and the original ECC code is different from the second ECC code. The method further includes respectively writing the first data stream and the second ECC code into a data bit area and an error-correction code bit area of the same or different physical programming units in the rewritable non-volatile memory module. | 02-13-2014 |
| 20140089759 | Error Correction Circuit for Data Communication Providing Parallelizable Linear Programming Decoding - An error detection/correction system provides an electronic circuit detecting and correcting transmission errors using linear programming. Linear programming techniques are made practical for real-time error correction and decoding by dividing the linear programming problem into independent parallelizable problems so that separate independent portions of the electronic circuit may simultaneously address solutions related to individual bits and/or parity rules. Linear programming is believed to avoid error floors inherent in conventional belief propagation error detection and correction techniques providing a decoding system suitable for high reliability applications. | 03-27-2014 |
| 20140089760 | STORAGE OF CODEWORD PORTIONS - Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for dividing error correcting code (“ECC”) codewords into portions and storing the portions among multiple die of non-volatile memory (“NVM”). For example, a device may include memory including a first die and a second die, and a memory controller configured to store a first portion of a codeword for use with an error correcting code in a first segment of the first die and to store a second portion of the codeword in a first segment of the second die. In various embodiments, the first segment of the second die may be offset from the first segment of the first die. Other embodiments may be described and/or claimed. | 03-27-2014 |
| 20140101516 | Encoding and Decoding Data to Accommodate Memory Cells Having Stuck-At Faults - A data storage system includes a memory circuit that has memory cells and a control circuit that is operable to receive data bits provided for storage in the memory cells. The control circuit is operable to receive a first matrix. Each row of the first matrix corresponds to a unique one of the data bits. The control circuit is operable to generate a second matrix having only the rows of the first matrix that correspond to the data bits provided for storage in a subset of the memory cells having stuck-at faults. The control circuit is operable to generate a third matrix having linearly independent columns of the second matrix. The control circuit is operable to encode the data bits to generate encoded data bits and redundant bits using the third matrix. | 04-10-2014 |
| 20140101517 | Encoding and Decoding Redundant Bits to Accommodate Memory Cells Having Stuck-At Faults - A data storage system has a memory circuit that comprises memory cells and a control circuit that receives data bits provided for storage in the memory cells. The control circuit encodes the data bits to generate a first set of redundant bits and encoded data bits, such that the encoded data bits selected for storage in a first subset of the memory cells with first stuck-at faults have digital values of corresponding ones of the first stuck-at faults. The control circuit encodes the first set of redundant bits to generate a second set of redundant bits. The control circuit performs logic functions on the second set of redundant bits and the encoded data bits to generate a third set of redundant bits, such that redundant bits in the third set of redundant bits selected for storage in a second subset of the memory cells with second stuck-at faults have digital values of corresponding ones of the second stuck-at faults. | 04-10-2014 |
| 20140122971 | LEH Memory Module Architecture Design in the Multi-Level LDPC Coded Iterative System - A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue. | 05-01-2014 |
| 20140136926 | NON-SYSTEMATIC CODED ERROR CORRECTION - Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption. | 05-15-2014 |
| 20140143635 | TECHNIQUES FOR STORING ECC CHECKBITS IN A LEVEL TWO CACHE - A partition unit that includes a cache for storing both data and error-correcting code (ECC) checkbits associated with the data is disclosed. When a read command corresponding to particular data stored in a memory unit results in a cache miss, the partition unit transmits a read request to the memory unit to fetch the data and store the data in the cache. The partition unit checks the cache to determine if ECC checkbits associated with the data are stored in the cache and, if the ECC checkbits are not in the cache, the partition unit transmits a read request to the memory unit to fetch the ECC checkbits and store the ECC checkbits in the cache. The ECC checkbits and the data may then be compared to determine the reliability of the data using an error-correcting scheme such as SEC-DED (i.e., single error-correcting, double error-detecting). | 05-22-2014 |
| 20140195876 | Memory Module Architecture - In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments. | 07-10-2014 |
| 20140201598 | SOLID STATE DRIVE AND DATA RETENTION METHOD THEREOF - A data retention method is provided. After the solid state drive is powered on, a current date information is received from a host. If a control command is generated by the host and the control command is a write command, the control command is executed, so that a new data is written into a flash memory. If no control command is generated, a first stored data is read out from the flash memory. Then, a stored date information of the first stored data is compared with the current date information, thereby acquiring a calculated time period. If the calculated time period is larger than a predetermined time period, the first stored data is updated by changing the stored date information to the current date information, and the updated first stored data is written into another location of the flash memory. | 07-17-2014 |
| 20140237320 | MEMORY SYSTEM - A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page. | 08-21-2014 |
| 20140245107 | REARRANGING WRITE DATA TO AVOID HARD ERRORS - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 08-28-2014 |
| 20140250346 | Memory System And Operation Method Thereof - A memory system includes: a first non-volatile memory used for storing data to be accessed in block units; a second non-volatile memory used for storing data to be accessed in word units in random accesses to the second non-volatile memory; and a control section configured to control operations of the first and second non-volatile memories, wherein error correction codes to be applied to data stored in the second non-volatile memory are held in the first non-volatile memory. | 09-04-2014 |
| 20140258810 | ERROR CORRECTION CODE SEEDING - The technology disclosed herein provides a method of verifying data read from a data block when the cell number of the data block does not match an ECC value stored in the data block. In particular, the method includes accessing a data block in an indexed sequence of data blocks based on a cell number, wherein each data block in the indexed sequence includes a stored ECC value; retrieving an offset associated with the cell number of the data block; generating an ECC value based on the cell number and the offset; and determining whether the generated ECC value and the stored ECC value satisfy an integrity condition. | 09-11-2014 |
| 20140258811 | STORAGE SCHEME FOR BUILT-IN ECC OPERATIONS - A device includes a memory array storing data and error correcting codes ECCs corresponding to the data, and a multi-level buffer structure between the memory array and an input/output data path. The memory array includes a plurality of data lines for page mode operations. The buffer structure includes a first buffer having storage cells connected to respective data lines in the plurality of data lines for a page of data, a second buffer coupled to the storage cells in the first buffer for storing at least one page of data, and a third buffer coupled to the second buffer and to the input/output data path. The device includes logic coupled to the multi-level buffer to perform a logical process over pages of data during movement between the memory array and the input/output path through the multi-level buffer for at least one of page read and page write operations. | 09-11-2014 |
| 20140281813 | DATA INTEGRITY MANAGEMENT IN MEMORY SYSTEMS - Data management logic allocates a portion such as a single plane of a respective multi-plane non-volatile memory device to store parity information for corresponding data striped across multiple planes of multiple non-volatile memory devices. According to one configuration, the data management logic as discussed herein generates parity data based on (a data stripe of) non-parity data stored in multiple planes of multiple different memory devices. The data management logic stores the parity data in the storage plane allocated to store the parity information. Additional configurations include: reserving a parity block amongst multiple non-parity data blocks to store parity data and reserving a parity page amongst multiple non-parity data pages to store parity data. | 09-18-2014 |
| 20140281814 | CORRECTION OF BLOCK ERRORS FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for correction of block errors for a system having non-volatile memory (“NVM”). In particular, the system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This can be a space efficient approach for recovering from single-block data errors such as, for example, single-page uncorrectable error-correcting codes (“uECCs”) and/or errors caused by word line shorts. | 09-18-2014 |
| 20140281815 | Dispersed storage network file system directory - A dispersed storage device manages a file system directory of a dispersed storage network by receiving a data object to be stored and a user file name of the data object, calculating a data compression function of the data object, creating a file identifier based on a result of the data compression function, creating a source name for the data object using the file identifier and linking the user file name to the source name in the file system directory. | 09-18-2014 |
| 20140331106 | CALCULATION OF ANALOG MEMORY CELL READOUT PARAMETERS USING CODE WORDS STORED OVER MULTIPLE MEMORY DIES - A method includes, in a memory that includes two or more memory units, storing a code word of an Error Correction Code (ECC) that is representable by a plurality of check equations, such that a first part of the code word is stored in a first memory unit and a second part of the code word is stored in a second memory unit. A subset of the check equations, which operate only on code word bits belonging to the first part stored in the first memory unit, is identified. The first part of the code word is retrieved from the first memory unit, and a count of the check equations in the identified subset that are not satisfied by the retrieved first part of the code word is evaluated. One or more readout parameters, for readout from the first memory unit, are set depending on the evaluated count. | 11-06-2014 |
| 20140365846 | Apparatuses and Methods for Encoding Using Error Protection Codes - Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device. | 12-11-2014 |
| 20140380125 | ERASURE CODING ACROSS MULTIPLE ZONES - In various embodiments, methods and systems for erasure coding data across multiple storage zones are provided. This may be accomplished by dividing a data chunk into a plurality of sub-fragments. Each of the plurality of sub-fragments is associated with a zone. Zones comprise buildings, data centers, and geographic regions providing a storage service. A plurality of reconstruction parities is computed. Each of the plurality of reconstruction parities computed using at least one sub-fragment from the plurality of sub-fragments. The plurality of reconstruction parities comprises at least one cross-zone parity. The at least one cross-zone parity is assigned to a parity zone. The cross-zone parity provides cross-zone reconstruction of a portion of the data chunk. | 12-25-2014 |
| 20140380126 | ERASURE CODING ACROSS MULTIPLE ZONES AND SUB-ZONES - In various embodiments, methods and systems for erasure coding data across multiple storage zones are provided. This may be accomplished by dividing a data chunk into a plurality of sub-fragments. Each of the plurality of sub-fragments is associated with a zone. Zones comprise buildings, data centers, and geographic regions providing a storage service. A plurality of reconstruction parities is computed. Each of the plurality of reconstruction parities computed using at least one sub-fragment from the plurality of sub-fragments. The plurality of reconstruction parities comprises at least one cross-zone parity. The at least one cross-zone parity is assigned to a parity zone. The cross-zone parity provides cross-zone reconstruction of a portion of the data chunk. | 12-25-2014 |
| 20150012799 | DATA PROTECTING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLER - A data protecting method, a memory storage device, and a memory controller are provided for a rewritable non-volatile memory module. The data protecting method includes: generating a first error correcting code by using data stored in first memory cells of a plurality of memory cells. The first memory cells are located on first word lines and first bit lines. Among the memory cells located on each of the first bit lines, only one of the memory cells stores the data used to generate the first error correcting code. Accordingly, the data in the memory cells is efficiently protected. | 01-08-2015 |
| 20150039968 | ERROR CODE MANAGEMENT IN SYSTEMS PERMITTING PARTIAL WRITES | 02-05-2015 |
| 20150039969 | STORING DATA IN A DIRECTORY-LESS DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module of a dispersed storage network (DSN) sending a plurality of sets of encoded data slices to DSN memory for storage in accordance with a plurality of sets of DSN data addresses. The method continues with the DS processing module generating retrieval data that is based on a data object number and data storage information. The method continues with the DS processing module dispersed storage error encoding the retrieval data to produce a set of encoded retrieval data slices and generating a set of DSN retrieval data addresses based on the data name and on retrieval data storage information. The method continues with the DS processing module sending the set of encoded retrieval data slices to the DSN memory for storage in accordance with the set of DSN retrieval data addresses. | 02-05-2015 |
| 20150067444 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device according to the present embodiment comprises a memory cell array including a plurality of memory cells. An output part is configured to output data based on a strobe signal. An error correction part is configured to correct an error in first data read from the memory cell array. The output part fixes level of the strobe signal when outputting the first data, if the number of error bits of the first data exceeds a first number, he error correction part being capable of correcting error of the first number in the first data. | 03-05-2015 |
| 20150067445 | ADJUSTING A DISPERSAL PARAMETER OF DISPERSEDLY STORED DATA - A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method continues with the processing module determining whether to adjust redundancy of the dispersed storage error coding function based on performance of the DSN. When the redundancy of the dispersed storage error coding function is to be adjusted, changing a ratio between the pillar width parameter and the decode threshold parameter and adjusting storage of one or more sets of the plurality of sets of encoded data slices based on the changing of the ratio. | 03-05-2015 |
| 20150089324 | METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit. | 03-26-2015 |
| 20150089325 | METHOD AND DEVICE FOR WRITE ABORT PROTECTION - A data storage device includes a non-volatile memory that includes a three-dimensional (3D) memory. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit. | 03-26-2015 |
| 20150100850 | SEMICONDUCTOR DEVICE, MEMORY DEVICE, AND SYSTEM INCLUDING THE SAME - A memory device includes a memory array suitable for storing write data of the memory device and providing the stored data as read data of the memory device, a programmable storage unit suitable for storing information for the memory device, a command decoder suitable for storing decoding one or more command signals, and generating a write command for writing the write data, a read command for outputting the read data, and an information read command for outputting information stored in the programmable storage unit, a control unit suitable for controlling the information stored in the programmable storage unit to be sequentially read in response to activation of the information read command, and an output unit suitable for outputting the read information to an outside of the memory device in response to the information read command. | 04-09-2015 |
| 20150121169 | WRITING DATA ACROSS STORAGE DEVICES IN AN ERASURE-CODED SYSTEM - A computing device writes data across storage devices in an erasure-coded system. The computing device computes data blocks and parity blocks from data and computes a portion of the data to be stored in the system. The computing is performed by one or more controllers included in a redundant array of an independent disks controller. The computing device provides the locations of the data blocks and the parity blocks in storage devices of an erasure-coded system. The location is determined using one or more placement nodes. The placement nodes are configured for managing placement schemes of data blocks and parity blocks on the storage devices. | 04-30-2015 |
| 20150121170 | Storing Data by an ECC Memory - Methods, systems and apparatus for storing data by an ECC memory are provided. In one aspect, when an ECC memory configured to be used for data blocks with a first data length is used for data blocks with a reduced second data length, a method includes storing at least one data block with the second data length in a data bit storage part of a storage array and storing parity bits generated for only one data block of the at least one data block according to a relevant encoding rule in a parity bit storage part of the storage array. When the at least one data block is two or more data blocks, one or more judgment bits, which indicate that the stored parity bits correspond to the only one data block, are stored in one or more storage bits of the parity bit storage part that are not occupied. | 04-30-2015 |
| 20150121171 | Computer Memory Access - A computer memory access method includes: receiving external data with a prefetching length, the external data having an unmasked first data portion and a masked second data portion; writing the unmasked first data portion to a corresponding data storage unit of a computer memory by a writing unit and reading a third data portion corresponding to the masked second data portion from the data storage unit by a reading unit; producing modified external data by merging the unmasked first data portion and the third data portion in place of the masked second data portion; generating parity bits from the modified external data by an error correction code encoding circuit according to a given rule; and then writing the parity bits to a parity bit storage unit of the computer memory by the writing unit, in substitution of previous information in the parity bit storage unit. | 04-30-2015 |
| 20150121172 | Computer Memory Access - A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory. | 04-30-2015 |
| 20150128008 | TRACK-BAND SQUEEZED-SECTOR ERROR CORRECTION IN MAGNETIC DATA STORAGE DEVICES - Data storage devices using a two-level ECC scheme are described. Embodiments of the invention allow the recovery of sectors in a squeezed group of tracks in a that includes both a single track level ECC scheme and a track band ECC scheme that functions across the set of tracks in the band. The track band ECC scheme uses additional parity information calculated using input data from multiple tracks to allow correction across tracks. | 05-07-2015 |
| 20150135036 | MEMORY CONTROLLER WITH DISTRIBUTION TRANSFORMER - Methods, apparatuses, and systems are described related to memory controllers for memory. In one embodiment, a memory controller may include a distribution transformer configured to receive data to be stored into a memory, wherein the data has a distribution of m | 05-14-2015 |
| 20150149864 | BIT RECOVERY SYSTEM - A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device. | 05-28-2015 |
| 20150149865 | CACHE STRUCTURE WITH PARITY-PROTECTED CLEAN DATA AND ECC-PROTECTED DIRTY DATA - A method includes generating error detection information associated with data to be stored at a cache in response to determining that the data is clean. The method also includes storing the clean data at a first region of the cache. The method further includes generating error correction information associated with data to be stored at the cache in response to determining that the data is dirty. The method also includes storing the dirty data at a second region of the cache. | 05-28-2015 |
| 20150309865 | MEMORY CONTROL UNIT AND DATA STORAGE DEVICE INCLUDING THE SAME - A data storage device includes a storage memory device; a signal generation block suitable for generating control signals to be provided to the storage memory device; and an error correction code (ECC) block suitable for ECC-encoding data to be stored in the storage memory device, wherein the ECC block operates before the signal generation block. | 10-29-2015 |
| 20150309873 | Memory Controllers To Form Symbols Based On Bursts - A memory controller is to interface with a memory, associated with a plurality of pins, based on a codeword. The codeword is to include a plurality of n-bit symbols. An n-bit symbol of the codeword is to be formed from a plurality of n bursts over time associated with one of the pins of the memory. | 10-29-2015 |
| 20150309874 | A METHOD AND APPARATUS FOR CODE LENGTH ADAPTATION FOR ACCESS TO KEY-VALUE BASED CLOUD STORAGE SYSTEMS - A method and apparatus is disclosed herein for code length adaptation for access to key-value based storage systems. In one embodiment, the method comprises receiving a data object and a request; dividing the data object into K portions, where K is an integer; selecting an FEC coding rate based on backlog associated with at least one queue; applying FEC coding based on the FEC rate set to the K portions to create N FEC coded data blocks, where N is an integer greater than or equal to K; and sending the N FEC coded data blocks to the storage system. | 10-29-2015 |
| 20150309875 | ERROR-CORRECTION ENCODING AND DECODING - A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n′, thereby to define a codeword, having n | 10-29-2015 |
| 20150317205 | RESOLVING WRITE REQUEST CONFLICTS IN A DISPERSED STORAGE NETWORK - A method to resolve conflicts arising from substantially concurrent write requests regarding a data object begins by a computing device of a dispersed storage network (DSN) issuing a write request for a dispersed storage error encoded version of the data object to storage units of the DSN. The method continues with the computing device receiving write responses, each including either a lock indication or a non-lock indication and conflict information. The method continues with the computing device determining whether at least a write threshold number of received write responses include the lock indication. When less than the at least a write threshold number of write responses have been received that include the lock indication, the method continues with the computing device processing the conflict information to identify one or more other write requests that have a higher priority than the write request and establishing a write request retry time frame. | 11-05-2015 |
| 20150319244 | RETRIEVING MULTI-GENERATIONAL STORED DATA IN A DISPERSED STORAGE NETWORK - A method begins by a processing module a dispersed storage network (DSN) generating, based on a data object name, a first retrieval request for retrieving metadata addressing information, where the first retrieval request is formatted in accordance with a read request format of the DSN. The method continues with the processing module generating, based on retrieved metadata addressing information, a second retrieval request for retrieving metadata, where the second retrieval request is formatted in accordance with the read request format of the DSN. The method continues with the processing module generating, based on retrieved metadata, a third retrieval request for retrieving at least a portion of a data object associated with the data object name, where the third retrieval request is formatted in accordance with the read request format of the DSN. | 11-05-2015 |
| 20150324252 | CODEWORDS THAT SPAN PAGES OF MEMORY - The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword. | 11-12-2015 |
| 20150331747 | DETECTING SINGLE EVENT UPSETS AND STUCK-AT FAULTS IN RAM-BASED DATA PATH CONTROLLERS - In one embodiment, a system includes a processor and logic configured to receive data including a plurality of data elements, each data element having one or more bits, and pass each data element along with a corresponding parity bit to an input of a data path, a first binary sequence generator configured to create a binary sequence having a plurality of bonus bits, wherein a total length of the binary sequence is equal to or greater than a maximum burst size of the data, and a first parity module configured to provide a parity calculation using bits of each data element of the data with a bonus bit from the binary sequence to produce a parity bit for each data element. Other systems, methods, and computer program products for providing end-to-end parity generation and checking that the scheme provides coverage for both data and sequencing faults are also disclosed. | 11-19-2015 |
| 20150331750 | Object Storage System for an Unreliable Storage Medium - A method and computer device for storage and retrieval of a data object on a storage medium. The method includes steps of disassembling the data object into a predetermined number of redundant sub blocks, storing the redundant sub blocks on the storage medium, retrieving at least a predetermined multiple of a minimal spreading requirement of the redundant sub blocks from the storage medium, and assembling the data object from any combination of a particular number of the redundant sub blocks, the particular number corresponding to a predetermined multiple of a minimal spreading requirement. The computer device includes modules for performing the steps. | 11-19-2015 |
| 20150333777 | REDUNDANT INFORMATION COMPRESSION METHOD, AND SEMICONDUCTOR DEVICE - A redundancy information compression method is configured to compress redundancy information among a plurality of macros for which redundancy processing is performed. The redundancy information compression method includes setting faulty bit position information, included in the redundancy information, for a macro of the plurality of macros including a faulty bit, the faulty bit position information indicating a position of the faulty bit included in the macro; and organizing macro numbers, included in the redundancy information, of macros of the plurality of macros having the same faulty bit position information as the set faulty bit position information together. | 11-19-2015 |
| 20150339187 | SYSTEM AND METHOD OF STORING REDUNDANCY DATA - A data storage device includes a controller operatively coupled to a non-volatile memory. The non-volatile memory includes a plurality of blocks. When the controller is configured to operate according to a first mode, a portion of a first redundancy block of the plurality of blocks stores first redundancy data corresponding to a first group of multiple data portions. The multiple data portions stored in multiple blocks of the plurality of blocks. When the controller is configured to operate according to a second mode, the portion of the first redundancy block stores second redundancy data corresponding to a single block of the plurality of blocks. | 11-26-2015 |
| 20150339190 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping. | 11-26-2015 |
| 20150339191 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF10/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. | 11-26-2015 |
| 20150339192 | CHANNEL ROTATING ERROR CORRECTION CODE - A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory. | 11-26-2015 |
| 20150339193 | SENDING A ZERO INFORMATION GAIN FORMATTED ENCODED DATA SLICE - A method includes encoding, in accordance with a dispersed storage error encoding function, a data segment of a data object to produce a set of encoded data slices. The method further includes creating a subset of encoded data slices, wherein the subset of encoded data slices includes less than the decode threshold number of encoded data slices. The method further includes creating one or more partial encoded data slices representing one or more encoded data slices of the set of encoded data slices that are not within the subset of encoded data slices based on the dispersed storage error encoding function and at least some of the encoded data slices of the subset of encoded data slices. The method further includes outputting the subset of encoded data slices to storage units of the DSN and outputting the one or more partial encoded data slices to another device of the DSN. | 11-26-2015 |
| 20150341047 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 64-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping. | 11-26-2015 |
| 20150341048 | BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND QUADRATURE PHASE SHIFT KEYING, AND BIT INTERLEAVING METHOD USING SAME - A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation. | 11-26-2015 |
| 20150355844 | REMAPPING IN A MEMORY DEVICE - Methods for remapping and/or compacting data in memory devices, memory devices, and systems are disclosed. One such method of remapping and/or compacting data includes reducing a first quantity of write operations that are received from a host to a second quantity of write operations for programming to a page of a memory device that are within the specifications of partial page write operations for the memory device. The second quantity of write operations can also remap data that were originally intended to be programmed to memory address ranges that conflict with a memory map of the memory device. | 12-10-2015 |
| 20150355966 | VERIFYING A STATUS LEVEL OF STORED ENCODED DATA SLICES - A method begins by a processing module of a dispersed storage network (DSN) retrieving a decode threshold number of encoded data slices of a set of encoded data slices from a first grouping of storage units of the DSN. The method continues with the processing module determining a first status level indication of the retrieved decode threshold number of encoded data slices and sending check status request messages to a second grouping of storage units of the DSN. The method continues with the processing module receiving check status response messages and processing the check response messages to produce a second status level indication. When the second status level indication is substantially equal to the first status level indication, the method continues with the processing module indicating that the decode threshold number of encoded data slices is of a common status level as other encoded data slices of encoded data slices. | 12-10-2015 |
| 20150363266 | PARITY SCHEME FOR A DATA STORAGE DEVICE - A data storage device includes a non-volatile memory. The non-volatile memory may include a first word line, a second word line, and a third word line. The second word line may be between the first word line and the third word line. The non-volatile memory may further include a first string and a second string. The first string may be adjacent to the second string. The data storage device may further include circuitry configured to store parity information at a fourth word line of the non-volatile memory. The parity information may correspond to a combination of first data associated with the first word line and the first string, second data associated with the first word line and the second string, third data associated with the third word line and the first string, and fourth data associated with the third word line and the second string. | 12-17-2015 |
| 20150363269 | ERASURE CODING AND REPLICATION IN STORAGE CLUSTERS - A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated. | 12-17-2015 |
| 20150370637 | FAILURE RESILIENT DISTRIBUTED REPLICATED DATA STORAGE SYSTEM - A failure resilient distributed replicated data storage system is described herein. The storage system includes zones that are independent, and autonomous from each other. The zones include nodes that are independent and autonomous. The nodes include storage devices. When a data item is stored, it is partitioned into a plurality of data objects and a plurality of parity objects calculated. Reassembly instructions are created for the data item. The data objects and parity objects are spread across all nodes and zones in the storage system. Reassembly instructions are also spread across the zones. When a read request is received, the data item is prepared from the lowest latency nodes according to the reassembly instructions. This provides for data resiliency while keeping the amount of storage space required relatively low. | 12-24-2015 |
| 20150370638 | EFFICIENTLY ACCESSING AN ENCODED DATA SLICE IN A MEMORY CONTAINER UTILIZING A MEMORY BIN - A method includes determining whether a substantially similar data object to a data object is stored in a dispersed storage network (DSN). When the substantially similar data object is not stored in the DSN, the method includes dividing the data object into a plurality of data segments; encoding the plurality of data segments to produce a plurality of encoded data segments, wherein an encoded data segment of the plurality of encoded data segments includes a first number of data blocks and a second number of parity blocks; arranging the data blocks and the parity blocks of the plurality of encoded data segments into a matrix; establishing a set of encoded data slices from the matrix; and outputting the set of encoded data slices to storage units of the DSN for storage therein. | 12-24-2015 |
| 20150370708 | Soft Error Protection For Content Addressable Memory - In one embodiment of the invention, a method for protecting a content addressable memory is disclosed. The method includes storing a marker bit associated with each data block stored in a random access memory (RAM), states of the marker bit representing whether the data block was recently read from the RAM or recently written into the RAM; receiving a client address pointing to a starting address of a data block stored in the RAM; comparing the client address against one or more addresses stored in a content addressable memory (CAM) to determine a hit indicating the client address was stored in the CAM or a miss indicating the client address was not stored in the CAM; and in response to a miss, the method further includes checking a state of the marker bit associated with the data block pointed to by the client address. | 12-24-2015 |
| 20150378816 | STORAGE APPARATUS, STORAGE SYSTEM, AND STORAGE APPARATUS CONTROL METHOD - A control device stores information associating each of a plurality of physical areas with a plurality of logical areas. The control device respectively stores a plurality of first user data included in a first stripe and a first parity data created on the basis thereof in each of the plurality of physical areas, and, in accordance with receiving a write request for updated user data that updates the user data, which is stored in a first physical area, for a first logical area associated with the first physical area, creates a second parity data on the basis of a data group formed using the updated user data and a plurality of second user data that differs from the plurality of first user data. | 12-31-2015 |
| 20150378820 | High Reliability Erasure Code Distribution - Example apparatus and methods treat some erasure codes differently than other erasure codes. For example, erasure codes that are only involved in error-recovery may never be read and thus may be stored using a different approach than erasure codes that are involved in more regular data reading. If different types of data stores are available, then the erasure codes that are more likely to be read may be stored in data stores having a first (e.g., higher, faster) type of read performance while the erasure codes that are less likely to be read may be stored in data stores having a second (e.g., lower, slower, less expensive) type of read performance. Different data stores may be located on different data storage devices. Different data stores may even be located on a single data storage device. | 12-31-2015 |
| 20150378824 | MANAGING MEMORY UTILIZATION IN A DISTRIBUTED STORAGE AND TASK NETWORK - A method includes encoding data into pluralities of sets of encoded data slices. The method further includes outputting the pluralities of sets of encoded data slices to DST units, wherein each of the DST units stores a slice grouping of encoded data slices. The method further includes dividing the task into a decode threshold number of partial tasks. The method further includes sending a slice deletion policy to the DST units. On a data chunkset by data chunkset basis: the method further includes selecting a decode threshold number of DST units; assigning the decode threshold number of partial tasks to the decode threshold number of DST units; executing the decode threshold number of partial tasks on the slice groupings to produce partial results; and deleting the plurality of sets of encoded data slices of the given data chunkset in accordance with the slice deletion policy. | 12-31-2015 |
| 20150378825 | SECURELY STORING DATA IN A DISPERSED STORAGE NETWORK - A method includes monitoring write processing performance while storing a plurality of sets of encoded data slices in storage units. The method includes comparing the write processing performance with a desire write performance range. When the write processing performance compares unfavorably to the desire write performance range, the method includes establishing a data partition between the data segments of the data encoded using the first dispersed storage error encoding parameters and subsequent data segments of the data; determining second dispersed storage error encoding parameters based on the unfavorable comparison between the write processing performance and the desired write performance range; encoding the subsequent data segments of the data using the second dispersed storage error encoding parameters to produce a second plurality of sets of encoded data slices; and monitoring write processing performance while storing the second plurality of sets of encoded data slices in the storage units. | 12-31-2015 |
| 20150378826 | CIRCUITS, APPARATUSES, AND METHODS FOR CORRECTING DATA ERRORS - One example apparatus includes a first circuit configured to receive first and second data words, to correct one or more errors in the first data word, to merge the corrected first data word and the second data word responsive to a control signal to generate a final merged data word, and to provide the final merged data word to a write circuit. The apparatus also includes a second circuit configured to also receive the first and second data words, to preliminarliy merge the first and second data words responsive to the control signal to generate an initial merged data word, to generate an initial parity code for the initial merged data word, to correct the initial parity code, and to provide the corrected parity code to the write circuit. | 12-31-2015 |
| 20150380087 | Data Encoding in Solid-State Storage Devices - Methods and apparatus | 12-31-2015 |
| 20160006461 | METHOD AND DEVICE FOR IMPLEMENTATION DATA REDUNDANCY - Provided are a method and device for implementing data redundancy. The method includes: a storage strategy identifier of data to be stored is acquired; and the data to be stored is stored in a storage manner corresponding to the storage strategy identifier, wherein the storage strategy identifier is used for indicating the data to be stored is stored in at least one of the following storage manners: a copy redundancy processing manner and an eraser encoding and decoding processing manner. The problem of incapability of ensuring a higher storage space utilization rate in the related art is solved, so that the security and reliability of the data are ensured, meanwhile, the utilization rate of a storage space is increased, and data redundancy implementation flexibility is improved. | 01-07-2016 |
| 20160006463 | THE CONSTRUCTION OF MBR (MINIMUM BANDWIDTH REGENERATING) CODES AND A METHOD TO REPAIR THE STORAGE NODES - This invention gives a coding method of MBR (Minimum Bandwidth Regenerating) codes. The related method includes the following steps: equally divide the original file of size B into k(k+1)/2 blocks, obtaining the first packets; construct a symmetrical k×k system matrix S with these first packets; generate k ID codes, wherein each ID code contains k elements; obtain the coded packet through operations between one column of the system matrix and the ID code; repeat the above steps with (n−k) different columns of the system matrix separately to get the (n−k) coded packets; construct the (n−k)×k check matrix P with the column number g which is the serial number of the ID codes in the coded packet set P | 01-07-2016 |
| 20160011938 | STORAGE APPARATUS AND DATA CONTROL METHOD | 01-14-2016 |
| 20160011941 | ENABLING EFFICIENT RECOVERY FROM MULTIPLE FAILURES TOGETHER WITH ONE LATENT ERROR IN A STORAGE ARRAY | 01-14-2016 |
| 20160013815 | Data Deduplication With Adaptive Erasure Code Redundancy | 01-14-2016 |
| 20160018996 | STORING AND ACCESSING DATA - A method of storing an amount of data D in association with a device, the method comprising: obtaining a characteristic C of the device; generating error correction data R for the characteristic C, the error correction data R enabling correction of up to a predetermined number of errors in a version of the characteristic C; combining the characteristic C with the amount of data D and an authentication key K to generate storage data P, wherein said combining is arranged so that the amount of data D and the authentication key K are obtainable using the characteristic C and the storage data P; generating a signature using a signature key, the signature being a digital signature of a quantity of data comprising the storage data P, the amount of data D and the authentication key K, wherein the signature key corresponds to a verification key accessible by the device; generating an authentication code for the error correction data R using the authentication key K, wherein the authenticity of the error correction data R is verifiable using the authentication code and the authentication key K; and storing the error correction data R, the storage data P, the signature and the authentication code to thereby store the amount of data D. | 01-21-2016 |
| 20160019112 | INCREMENTAL ERROR DETECTION AND CORRECTION FOR MEMORIES - A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance. | 01-21-2016 |
| 20160034345 | MEMORY LATENCY MANAGEMENT - Apparatus, systems, and methods to manage memory latency operations are described. In one embodiment, an electronic device comprises a processor and a memory control logic to receive data from a remote memory device, store the data in a local cache memory, receive an error correction code indicator associated with the data, and implement a data management policy in response to the error correction code indicator. Other embodiments are also disclosed and claimed. | 02-04-2016 |
| 20160034347 | MEMORY SYSTEM - According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes first number of storage areas. The first number is two or more. The controller generates a plurality of second data by encoding a plurality of first data. The controller writes each piece of the second data to any one of the first number of storage areas. The controller successively repeats parallel read processing to read each piece of third data from the storage area. The parallel read processing is processing for reading, in parallel, a piece of third data from each of a second number of storage areas among the first number of storage areas. The second number is two or more. The controller determines a write destination of each piece of second data so that the second number becomes uniform for each parallel read processing. | 02-04-2016 |
| 20160054920 | Distributed Data Storage System with Key-Based Addressing - In a Distributed Virtual Array data storage system, a storage pool receives, from at least one writing entity within a host, a request to write a container of data that is identified by a unique key that is independent of physical storage identifiers and that comprises a set of data chunks. The key indicates a plurality of storage devices in which to store the data chunks, which are accordingly stored in those storage devices. Different combinations, each comprising a layout map, of storage devices are represented in a layout table. Information in the container key is used to select which layout map to use for the chunks of each container. An error-correction chunk is preferably also stored along with the chunks of each container so as to enable data container reconstruction in case of storage device failure. | 02-25-2016 |
| 20160062826 | LEE METRIC ERROR CORRECTING CODE - A memory device may include memory components for storing data. The memory device may also include a controller that determines whether one or more errors exist in a data packet stored in the memory components. The controller may read a code word associated with the data packet, such that the code word may be used to indicate whether the errors exist in the data packet. The controller may then determine a syndrome polynomial based on the code word and determine an inverse of the syndrome polynomial when the syndrome polynomial is not zero. The controller may then determine a first error locator polynomial and a second error locator polynomial based on the inverse of the syndrome polynomial. The first error locator polynomial and the second error locator polynomial may be used to identify one or more locations of one or more errors in the code word. | 03-03-2016 |
| 20160062828 | DATA ACCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - A data accessing method, a memory storage device and a memory controlling circuit unit are provided. The data accessing method includes: determining whether a first physical programming unit storing first data belongs to a first type physical programming unit or a second type physical programming unit; if the first physical programming unit belongs to the first type physical programming unit, generating a first verification code corresponding to the first data and a second verification code for being combined with the first verification code, and writing the first data and the first verification code into the first physical programming unit; and if the first data is decoded unsuccessfully by using the first verification code, combining the second verification code and the first verification code to decode the first data. | 03-03-2016 |
| 20160062831 | ERROR CORRECTION CODE FOR UNIDIRECTIONAL MEMORY - A memory array and a method of writing to a unidirectional non-volatile storage cell are disclosed whereby a user data word is transformed to an internal data word and written to one or more unidirectional data storage cells according to a cell coding scheme. A check word may be generated that corresponds to the internal data word. In some embodiments, the check word may be generated by inverting one or more bits of an intermediate check word. Other embodiments may be described and claimed. | 03-03-2016 |
| 20160062832 | WIDE SPREADING DATA STORAGE ARCHITECTURE - Technology is disclosed for a data storage architecture for providing enhanced storage resiliency for a data object. The data storage architecture can be implemented in a single-tier configuration and/or a multi-tier configuration. In the single-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data fragments, which are stored across many storage devices. In the multi-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data segments, which are sent to one or more tiers of storage nodes. Each of the storage nodes further encodes the data segment to generate many data fragments representing the data segment, which are stored across many storage devices associated with the storage node. The I/O operations for rebuilding the data in case of device failures is spread across many storage devices, which minimizes the wear of a given storage device. | 03-03-2016 |
| 20160062834 | HIERARCHICAL DATA STORAGE ARCHITECTURE - Technology is disclosed for a data storage architecture for providing enhanced storage resiliency for a data object. The data storage architecture can be implemented in a single-tier configuration and/or a multi-tier configuration. In the single-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data fragments, which are stored across many storage devices. In the multi-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data segments, which are sent to one or more tiers of storage nodes. Each of the storage nodes further encodes the data segment to generate many data fragments representing the data segment, which are stored across many storage devices associated with the storage node. The I/O operations for rebuilding the data in case of device failures is spread across many storage devices, which minimizes the wear of a given storage device. | 03-03-2016 |
| 20160070616 | OFF-MEMORY-MODULE ECC-SUPPLEMENTAL MEMORY SYSTEM - A system includes off-memory-module ECC-supplemental memory. In a process, an ECC-capable memory controller converts non-ECC data words to ECC data words and distributes each ECC data word between a non-ECC memory module set (of one or more non-ECC memory modules) and the ECC-supplemental memory. A host computer system can include a baseboard on which are mounted an ECC-capable memory controller, off-memory-module ECC-supplemental memory, and sockets for installing non-ECC memory modules. | 03-10-2016 |
| 20160070617 | MAINTAINING A DESIRED NUMBER OF STORAGE UNITS - A method begins by a processing module of a dispersed storage network (DSN) determining that a set of storage units has less than a desired number of active storage units, where the DSN includes a plurality of storage units that randomly are active or inactive. The method continues with the processing module identifying another active storage unit of the storage units that is not currently part of the set of storage units and adding the other active storage unit to the set of storage units. For encoded data stored by the set of storage units, the method continues with the processing module increasing a pillar width number of a dispersed storage error encoding function, maintaining a decode threshold number of the dispersed storage error encoding function, creating new encoded data slices for the encoded data, and storing the new encoded data slices in the other active storage unit. | 03-10-2016 |
| 20160072525 | ACCELERATED ERASURE CODING SYSTEM AND METHOD - An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data. | 03-10-2016 |
| 20160085625 | SELF-ACCUMULATING EXCLUSIVE OR PROGRAM - Methods and apparatus for Exclusive OR (XOR) programming of a memory device are described. A program internal to a device calculates parity or other values using an XOR Program Rule. In some embodiments, the program generates and stores a parity result directly in the memory device itself without intervention by an external controller. A method of parity generation in a memory device comprises executing an internal self-accumulating parity program, wherein the program accumulates a parity sum by superimposing newly accumulated parity information over previously stored parity information in the auxiliary memory system. In a stand-alone device embodiment, a new command “XOR program” is received with address and input data parameters causing stored data to be read at the input address and an XOR operation of the read data and new input data is performed. The results of the computation are written into memory. | 03-24-2016 |
| 20160085629 | MODIFYING A DISPERSED STORAGE NETWORK MEMORY DATA ACCESS RESPONSE PLAN - A method includes segmenting a data object into data segments based on segmenting information. For a first data segment, the method further includes dispersed storage error encoding the first data segment. The method further includes identifying a first set of storage units from a pool of storage units. The method further includes issuing a first set of write requests to the first set of storage units. The method further includes receiving write responses from the first set of storage units. The method further includes, when a write threshold number of favorable write responses have been received, generating a first DSN addresses for encode data slices based on Internet addresses of storage units that provided the favorable write responses and based on the temporary slice names of the encoded data slices. The method further includes storing an association of the first DSN addresses and the first encode data slices. | 03-24-2016 |
| 20160098320 | EFFICIENTLY STORING DATA IN A DISPERSED STORAGE NETWORK - A method includes determining that one or more data blocks of a permanently stored data blocks are to be deleted. In response, the method further includes obtaining a group of partial redundancy data for the permanently stored data blocks. The method further includes identifying a temporarily stored plurality of data blocks for which partial redundancy data does not yet exist. The method further includes creating a new plurality of data blocks from data blocks of the permanently stored plurality of data blocks that are to remain permanently stored and data blocks from the temporarily stored plurality of data blocks that are to be permanently stored. The method further includes permanently storing the new plurality of data blocks. The method further includes generating a new group of partial redundancy data. The method further includes sending the new group of partial redundancy data and the group of partial redundancy data. | 04-07-2016 |
| 20160098321 | Efficient Memory Architecture for Low Density Parity Check Decoding - A low density parity check (LDPC) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The LDPC decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells. The first-type cells may be a first one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. The second-type cells may be a second one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. | 04-07-2016 |
| 20160098322 | Background Initialization for Protection Information Enabled Storage Volumes - Technology is disclosed for performing background initialization on protection information enabled storage volumes or drives. In some embodiments, a storage controller generates multiple I/O requests for stripe segments of each drive (e.g., disk) of multiple drives of a RAID-based system (e.g., RAID-based disk array). The I/O requests are then sorted for each of the drives according to a pre-determined arrangement and initiated in parallel to the disks while enforcing the pre-determined arrangement. Sorting and issuing the I/O requests in the manner described herein can, for example, reduce drive head movement resulting in faster storage subsystem initialization. | 04-07-2016 |
| 20160110250 | CACHE MEMORY WITH FAULT TOLERANCE - The exemplary embodiments of the invention relates to fault tolerance of a cache memory which recovers an error occurred in the cache memory or reports an error. A cache memory may include a first layer cache configured to store data requested from a processor, together with a tag related to the data and parity check bits for detecting data error and tag error; a second layer cache configured to store data requested from the first layer cache, together with parity check bits and an error correction code(ECC) bit for detecting data error and tag error; and a fault tolerance unit configured to generate an error signal indicating whether the data error or tag error occurred in at least one of the first layer cache and the second layer cache is recoverable. | 04-21-2016 |
| 20160110252 | DISTRIBUTING STORAGE OF ECC CODE WORDS - Apparatuses, systems, methods, and computer program products are disclosed for distributing error-correction codes. A correction module is configured to determine an error correction code (ECC) code word for storage on one or more non-volatile storage media. A mapping module is configured to determine one or more addresses for the ECC code word so that a portion of the ECC code word is stored at a first physical address within a first set of strings of storage cells of the one or more non-volatile storage media and a portion of the ECC code word is stored at a different physical address within a second set of strings of storage cells of the one or more non-volatile storage media. A storage module is configured to cause the ECC code word to be stored in the one or more non-volatile storage media based on the determined one or more addresses. | 04-21-2016 |
| 20160110254 | Partial Cloud Data Storage - Technologies are generally described for partial cloud data storage. In one example, a method includes dividing, by a system comprising a processor, a file into a set of source packets in response to an indication that the file is to be stored in a data store of a network device. The method also includes transforming the set of source packets into a set of encoded packets by encoding the set of packets into codeword symbols of an error correcting code. Further, the method includes facilitating storage of a first portion of the set of encoded packets to the data store of the network device and a second portion of the set of encoded packets to one or more user devices. A first number of packets in the first portion is more than a second number of packets in the second portion and the second portion is at least used to decode the file. | 04-21-2016 |
| 20160110255 | DATA STORAGE SYSTEM, DATA STORAGE DEVICE AND RAID CONTROLLER - Provided are a data storage system, a data storage device and a RAID controller, which can control RAID operation and a RAID operating method of a memory device by transmitting a RAID configuration signal to the memory device. The data storage system includes a memory device that may include m nonvolatile memories, where m is a natural number, and a memory controller that may program data to at least the first to mth pages. The data storage system also includes a RAID controller that may generate a RAID configuration signal, including a RAID operation signal for determining whether to activate or deactivate a RAID operation of the memory device, and that may transmit the data and the RAID configuration signal to the memory controller. The memory controller may generate a RAID parity using first to (m−1)th data from the RAID controller and program the first to (m−1)th data to the first to (m−1)th pages and the RAID parity to the mth page when the RAID operation signal is activated, but program the first to mth data received from the RAID controller to the first to mth pages when the RAID operation signal is deactivated. | 04-21-2016 |
| 20160124809 | STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a storage device includes simultaneously buffering first data in a first nonvolatile memory device and a second nonvolatile memory device, simultaneously buffering second data in the second nonvolatile memory device and a third nonvolatile memory device, performing a parity operation on the first data and the second data in the second nonvolatile memory device to generate a parity, and programming the first data, the second data, and the parity into the first nonvolatile memory device, the third nonvolatile memory device, and the second nonvolatile memory device, respectively. | 05-05-2016 |
| 20160132387 | DATA ACCESS METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data access method for a rewritable non-volatile memory module is provided. The method includes: filling dummy data to first data in order to generate second data, and writing the second data and an error checking and correcting code (ECC code) corresponding to the second data into a first physical programming unit. The method also includes: reading data stream from the first physical programming unit, wherein the data stream includes third data and the ECC code. The method further includes: adjusting the third data according to a pattern of the dummy data in order to generate fourth data when the third data cannot be corrected by using the ECC code, and using the ECC code to correct the fourth data in order to obtain corrected data, wherein the corrected data is identical to the second data. | 05-12-2016 |
| 20160132392 | NON-VOLATILE MEMORY DATA STORAGE WITH LOW READ AMPLICATION - In one embodiment, an apparatus includes one or more memory devices, each memory device having non-volatile memory configured to store data, and a memory controller connected to the one or more memory devices, the memory controller being configured to receive data to be stored to the one or more memory devices, store read-hot data within one error correction code (ECC) codeword as aligned data, and store read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. According to another embodiment, a method for storing data to non-volatile memory includes receiving data to store to one or more memory devices, each memory device including non-volatile memory configured to store data, storing read-hot data within one ECC codeword as aligned data, and storing read-cold data to straddle two or more ECC codewords as non-aligned data and/or dispersed data. | 05-12-2016 |
| 20160132393 | System and Method for Improving Read Performance of a Distributed Parity RAID Solution - An information handling system includes a plurality of storage disks arranged as a redundant array of independent disks and a controller. The controller communicates with each of the storage disks. The controller determines a total amount of storage space utilized to store parity information within the storage disks based on a smallest disk size of the storage disks and a number of storage disks in the redundant array of independent disks, calculates an amount of storage space utilized to store parity information on each of the disks based on the total amount of storage space utilized to store parity information and the number of storage disks, and allocates a parity region of sectors within each of the storage disks to store the parity information. The parity region is an inner most region of a disk. | 05-12-2016 |
| 20160139840 | ERROR TOLERANT OR STREAMING STORAGE DEVICE - A method of storing data includes receiving general purpose (GP) data and special Error Tolerant or Streaming (ETS) data, storing the GP data using a data storage method, and storing the ETS data using a different data storage method which affects the access rate, resilience to errors, data integrity, storage density, or storage capacity. The storage medium, which can include a disk drive, flash memory, or holographic memory, is utilized differently depending on the required Quality of Service in aspects including block size, storage of error correction codes, utilization of error correction codes, storage area density, physical format pattern, storage verification, or reaction to failed storage verification. For disk drives these differences include spacing between tracks; overlap between tracks; spiral track formatting; concentric track formatting, and size of blocks, and for flash memories these differences include levels per cell and number of cells. | 05-19-2016 |
| 20160139988 | MEMORY UNIT - Operating a memory unit during a memory access operation. The memory unit includes a configuration of N data chips. A line of data stored in the memory unit is divided, with a controller, into a first portion and a second portion. The first portion of the line of data is encoded, with an outer code encoder, to generate an outer code output. The second portion of the line of data and the outer code output from the outer code encoder are encoded, with an inner code encoder, to generate an inner code output. A first layer of protection for the line of data is generated based on the inner code output and is stored to the memory unit, where the first layer of protection includes local error detection (LED) information combined with the line of data. A second layer of protection for the line of data is generated based on the first layer of protection and is stored to the memory unit. A decoding operation to retrieve the line of data is performing at the controller. | 05-19-2016 |
| 20160139990 | STORAGE SYSTEM AND STORAGE APPARATUS - A storage apparatus includes a processor. The processor is configured to sequence a plurality of data pieces. The plurality of data pieces are respectively stored in a plurality of memory devices. The processor is configured to set compensation ranges to be respectively compensated by a first predetermined number of parities. The compensation ranges are respective portions of consecutive data pieces among the sequenced data pieces. The compensation ranges include a variably set number of data pieces for the respective parities. Each of the plurality of data pieces is included in a second predetermined number of compensation ranges. | 05-19-2016 |
| 20160149591 | TURBO DECODERS WITH STORED COLUMN INDEXES FOR INTERLEAVER ADDRESS GENERATION AND OUT-OF-BOUNDS DETECTION AND ASSOCIATED METHODS - A turbo decoder decodes encoded data using a regenerated interleaver sequence. An addressable column index memory stores column indexes of the encoded data during an input phase of a turbo decode operation. An address generator generates the regenerated interleaver sequence based on the column indexes and computed data. In embodiments the address generator can read column indexes from the addressable column index memory, compute the computed data by permuting row indexes in a same row permuting order as an encoder that encoded the encoded data, combine the column indexes so read and the row indexes so permuted, use a row counter, and identify out of bounds addresses using the regenerated interleaver sequence. | 05-26-2016 |
| 20160149596 | TURBO DECODER WITH A LOW-POWER INPUT FORMAT AND ASSOCIATED METHOD - A turbo decoder stores received data in words in systematic memory and parity memory in a way that is known that it will be used for later iterations by turbo decoder engines arranged to operate in parallel. A loader receives and separates LLRs into systematic and parity data and stores them into a portion of a word per cycle until a word is full in a corresponding one of the systematic memory and parity memory. The turbo decoder engines read the LLRs from one word of the systematic memory and one word of the parity memory in a single cycle. The data can be rearranged within the words in an order format for the turbo decoder engines to later read them by providing sub-words corresponding to respective ones of the plurality of turbo decoder engines. | 05-26-2016 |
| 20160154697 | ERROR CORRECTION CODING WITH HIGH-DEGREE OVERLAP AMONG COMPONENT CODES | 06-02-2016 |
| 20160154698 | COORDINATING STORAGE OF DATA IN DISPERSED STORAGE NETWORKS | 06-02-2016 |
| 20160154699 | LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME | 06-02-2016 |
| 20160162356 | METHODS AND SYSTEMS FOR IMPLEMENTING REDUNDANCY IN MEMORY CONTROLLERS - The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data. | 06-09-2016 |
| 20160179614 | WORKLOAD-ADAPTIVE DATA PACKING ALGORITHM | 06-23-2016 |
| 20160179620 | MULTI-STAGE DECODER | 06-23-2016 |
| 20160196181 | SYNCHRONIZED TRANSFER OF DATA AND CORRESPONDING ERROR CORRECTION DATA | 07-07-2016 |
| 20160253239 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF | 09-01-2016 |
| 20160378404 | SYSTEM AND METHOD OF INTERFACING CO-PROCESSORS AND INPUT/OUTPUT DEVICES VIA A MAIN MEMORY SYSTEM - A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit. | 12-29-2016 |
| 20160380650 | FLEXIBLE ERASURE CODING WITH ENHANCED LOCAL PROTECTION GROUP STRUCTURES - In various embodiments, methods and systems for erasure coding with enhanced local protection groups are provided. An erasure coding scheme can be defined based on a Vertical Local Reconstruction Code (VLRC) that achieves high storage efficiency by combining the Local Reconstruction Code and conventional erasure coding, where the local reconstruction code (LRC) is carefully laid out across zones. Thus, when a zone is down, remaining fragments form an appropriate LRC. Further, an inter-zone erasure coding scheme—Zone Local Reconstruction Code (ZZG-2 code)—is provided having both local reconstruction within every zone and a-of-b recovery property across zones. An inter-zone adaptive erasure coding (uber code) scheme is provided, the uber code is configurable to produce near optimal performance in different environments characterized by intra and inter-zone bandwidth and machine failure rates. It is contemplated that embodiments described herein include functionality for recognizing correctable patterns and decoding techniques for coding schemes. | 12-29-2016 |
