Entries |
Document | Title | Date |
20080215954 | BIT ERROR REPAIR METHOD AND INFORMATION PROCESSING APPARATUS - An information processing apparatus has an error correction function for checking an error of stored data read out from a flash memory. If an error is found, error information thereof is temporarily stored into a register and then stored in a nonvolatile memory at an appropriate timing. At an appropriate timing such as power-on, the information processing apparatus reads the stored data in which the error is found again on the basis of the error information stored in the nonvolatile memory, corrects the error and then rewrites the stored data into the flash memory. It is thereby possible to repair a recoverable bit error such as a read disturb. Therefore, a normal read operation can be performed without a hitch, and this can avoid giving any uncomfortable feeling to users. | 09-04-2008 |
20080235560 | Flash Error Correction - A data processing device for detecting and correcting data errors of a re-writable memory via an error correction algorithm. In one embodiment, the data processing device includes a coding unit implemented in hardware and an error correction unit implemented in software. In one embodiment, the coding unit is capable receiving a first set of data to be written to the memory and processing that data in accordance with an error correction algorithm to form a second set of data. The second set of data may be output to memory. In one embodiment, the coding unit receives data from the memory and processes that data in accordance with the error correction algorithm to determine whether the data contains an error. In one embodiment, the error correction unit receives data that contains an error and produces corrected data via an error correction algorithm. The corrected data may be output to the memory. | 09-25-2008 |
20080263429 | Method and Device for Correcting Code Data Error - A method and a device for correcting a code data error are disclosed. A main processor included in a digital processing device in accordance with an embodiment of the present invention writes in a shared memory third code data error-corrected by a predetermined error correcting method or second code data written in a backup area if there is an error in first code data written in a code data area of a nonvolatile memory. The main processor or an application processor performs an operation corresponding to the third code data. With the present invention, a system can be stably operated thanks to promptly dealing with an error when the error in boot codes is detected or generated | 10-23-2008 |
20080270869 | Data reproducing apparatus - A data reproducing apparatus has a nonvolatile memory in addition to a memory for data processing. When data error is uncorrected, data and error correction codes other than uncorrected data are accumulated in the memory for data processing. Corrected data is coupled and repaired, and the repaired data is stored in the nonvolatile memory. It is possible to reproduce data without retry, even if data error is uncorrected when the data of an optical disc is reproduced at the next time. | 10-30-2008 |
20080301526 | Memory Device with Error Correction Capability and Preemptive Partial Word Write Operation - A memory device comprises a memory array and error correction circuitry coupled to the memory array. The memory device is configured to perform a partial word write operation in which an error correction code encode process for the given retrieved word is initiated prior to completion of an error correction code decode process for the given retrieved word based on an assumption that the error correction code decode process will not indicate an error in the given retrieved word. If the error correction code decode process when completed indicates an error in the given retrieved word, the error in the given retrieved word is corrected in the error correction circuitry, and the error correction code encode process is restarted using the corrected word. The error correction code decode process and an associated correct process are thereby removed from a critical timing path of the partial word write operation. | 12-04-2008 |
20080301527 | SYSTEMS AND METHODS FOR JOINT LDPC ENCODING AND DECODING - Various embodiments of the present invention provide systems and methods for LDPC encoding and decoding. For example, a system for performing LDPC encoding and decoding is disclosed that includes a joint LDPC encoder/decoder. The joint LDPC encoder/decoder includes both an LDPC decoder and an LDPC encoder that each utilize a common LDPC decoder circuit to perform the respective functions of encoding and decoding. | 12-04-2008 |
20080301528 | Method and apparatus for controlling memory - A memory control apparatus includes a reading unit, an inserting unit, an identifying unit, a determining unit, and an outputting unit. The reading unit reads data from the memory. The inserting unit inserts a dummy error at an insertion position in the data thereby obtaining error data. The identifying unit identifies an error position at which an error has occurred in the error data. The determining unit determines whether the insertion position matches the error position. When the insertion position matches the error position, the outputting unit outputs corrected data obtained by correcting an error at the error position. | 12-04-2008 |
20090024903 | NIBBLE ENCODING FOR IMPROVED RELIABILITY OF NON-VOLATILE MEMORY - A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in which the initial nibble value is Fh and on program operations that result in a nibble value of 0h. The non-volatile memory uses multiple writes to program a nibble more than once with non-zero data between erase cycles. | 01-22-2009 |
20090031194 | ERROR-DETECTING AND CORRECTING FPGA ARCHITECTURE - A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated. | 01-29-2009 |
20090044075 | Failure tolerant data storage - An arrangement for storing data has a plurality of N storage devices S | 02-12-2009 |
20090044076 | MEMORY ACCESS SYSTEM - The ECC circuit generates the first syndrome of write data, which have not been written to the memory. The EDC circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced. | 02-12-2009 |
20090044077 | FLASH MEMORY SYSTEM HAVING ENCRYPTED ERROR CORRECTION CODE AND ENCRYPTION METHOD FOR FLASH MEMORY SYSTEM - A flash memory system includes a flash memory for storing input data, and a memory controller controlling the flash memory, wherein the memory controller generates a first error correction code corresponding to the input data, and encrypts the first error correction code, and the flash memory includes a main area for storing the input data and a spare area for storing the encrypted first error correction code. | 02-12-2009 |
20090055714 | OPTIMIZING THE SIZE OF MEMORY DEVICES USED FOR ERROR CORRECTION CODE STORAGE - Embodiments of the invention are generally directed to systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. In some embodiments, the memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N. | 02-26-2009 |
20090063934 | MULTI-CHANNEL MEMORY SYSTEM INCLUDING ERROR CORRECTION DECODER ARCHITECTURE WITH EFFICIENT AREA UTILIZATION - A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory. | 03-05-2009 |
20090094504 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a parity generating circuit for generating parity data corresponding to input data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for selectively outputting the input data or the parity data; a parity data latching section for latching and outputting the output from the input selection circuit or data read out from the parity memory cell array; and an error correction circuit for performing an error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing an error correction if an error is detected, to output the obtained result. The parity data latching section outputs the data latched by itself externally of the semiconductor memory device. | 04-09-2009 |
20090125787 | Operation Method of Mram - An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits. | 05-14-2009 |
20090125788 | Hardware based memory scrubbing - This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to detect errors in data that has been read from associated memory in response to the request for the data, the error system maintaining a log of entries corresponding to errors detected by the error system. An identifier is associated with each of the entries in the log that result from the request initiated by the engine to differentiate from other entries in the log. | 05-14-2009 |
20090132891 | STORAGE MEDIUM REPRODUCING APPARATUS, STORAGE MEDIUM REPRODUCING METHOD, AND COMPUTER PROGRAM PRODUCT FOR READING INFORMATION FROM STORAGE MEDIUM - A storage medium reproducing apparatus includes a storage unit, a correction history storage unit, a correction history implementing unit, and a correcting unit. The storage unit includes a plurality of information storage units storing information depending on whether a charge quantity is greater than a predetermined charge quantity threshold value, and a correction code storage unit storing error correction codes for the information stored in the information storage units. The correction history storage unit stores a correction history containing identification information for the information storage unit corrected with an error correction code is performed, and a content of the correction. The correction history implementing unit corrects information in compliance with the content of the correction when the information is read from the information storage unit. The correcting unit performs a correcting operation using an error correction code on the corrected information, and registers the correction history of the corrected information storage unit. | 05-21-2009 |
20090138783 | CONTENT DATA RECORDING APPARATUS AND METHOD - A content data recording apparatus includes a code addition unit adding an error correction code to an input content data, a data storing unit temporarily storing the content data, and outputting it, a plurality of nonvolatile memories that enable writing/reading of the content data, a generator generating a write address and a read address, a read buffer temporarily storing the read content data, and outputting it, an error correction unit correcting an error of the content data based on the error correction code, and giving correction impossible notification when the error is not corrected by the error correction code, and a controller carrying out a read control for reading content data from the nonvolatile memories, and carrying out a first rewrite control for controlling the data storing unit so that the data storing unit again outputs content data, and writing the content data again output to the nonvolatile memories. | 05-28-2009 |
20090158125 | RECORDING/REPRODUCING APPARATUS AND RECORDING/REPRODUCING METHOD - A recording/reproducing apparatus includes an encoding section, a decoding section, and a first judging section. The encoding section is configured to encode data that is to be recorded onto a recording medium into an LDPC (Low Density Parity Check) code. The decoding section is configured to decode the LDPC code read out from the recording medium. The judging section is configured to judge a block with a recording error based on one of a block error flag and an iterative decoding count output from the decoding section. | 06-18-2009 |
20090164870 | Apparatus and method for error correction of data values in a storage device - A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage device, error detection circuitry detects if an error is present in that data value and, if necessary, error correction circuitry corrects the read data value. An error cache having at least one entry stores corrected replacement data values, a corrected data value being allocated into an entry of the error cache for every corrected data value that is generated, and the read access request is re-performed. Replacement data values are read from the error cache in preference to data values stored in the storage device. This ensures that the retry mechanism will succeed irrespective of whether the error was a soft error or a hard error. Thus, if any hard errors do occur during normal operation of the storage device, they can effectively be temporarily corrected through use of the error cache to ensure that the retry mechanism proceeds correctly. | 06-25-2009 |
20090164871 | Semiconductor Memory Devices that are Configured to Analyze Read Failures and Related Methods of Operating Such Devices - Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit. Related methods are also disclosed. | 06-25-2009 |
20090172498 | Error correction in copy back memory operations - A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, the predetermined margin being such as to allow subsequent error correction to compensate for errors accumulated from the cache storage area and the main storage area. In this way the memory die copy back operation can be used for copying the data from the cache to the main memory and two out of four transfers over the data bus to the flash controller are avoided. | 07-02-2009 |
20090210772 | DATA MEMORY SYSTEM - A data memory system includes a nonvolatile memory cell array which includes a plurality of memory cells, a page adjacently formed by the plurality of memory cells being collectively erased in the nonvolatile memory cell, at least binary pieces of digital data of “1” and “0” being stored as charges of a charge accumulation layer in the memory cell, a programming bit and an erasing bit being formed by a difference between the charges of the charge accumulation layer. And the system includes an error correcting code generation circuit, an error correcting code decoding circuit, and a code conversion circuit. | 08-20-2009 |
20090241010 | MEMORY SYSTEM - A memory system includes a controller that manages data stored in the first and second storing areas. The controller determines, when a readout error occurs when the stored data in the second storing area is read out, success or failure of error correction to the read-out data based on the result of the error correction stored in a storage buffer, writes, when the error correction is successful, correction data corresponding to the read-out data stored in the storage buffer, and writes, when the error correction fails, the read-out data itself not subjected to error correction processing. | 09-24-2009 |
20090259918 | POSITION DETECTION ERROR CORRECTING METHOD - A position detection error correcting method that corrects position detection errors using a limited storage capacity, by calculating position detection error correction values by four simple arithmetic operations at startup to reduce a startup time delay and consumption of a storage capacity even when a portion containing steep error variations exists. Detection error correction values of a position detector are expressed by a correction function using a periodic function, and correction parameters of the correction values are stored in advance in a non-volatile memory. At startup, these correction parameters are read out, and a position detection error correction value corresponding to each detected position is calculated and stored in a random access memory. The output position detection error correction value detector corresponding to each detected position is read out from the random access memory and a corrected detected position value corrected for the detected position value error is calculated. | 10-15-2009 |
20090319870 | SEMICONDUCTOR MEMORY DEVICE AND ERROR CORRECTING METHOD - A decoding unit is arranged between a reading unit that reads data with an error correction code added from memory cells on a specific one of the first data lines and an output unit that selectively outputs certain data of the read out data. The decoding unit corrects any errors in the data read out by the reading unit in accordance with the error correction code. The data in which the errors are corrected by the decoding unit is written back in the memory cells on the specific first data line. | 12-24-2009 |
20090327838 | MEMORY SYSTEM AND OPERATING METHOD FOR IT - A memory system includes a writable data memory and means for recognizing an error in a data word read out from the data memory, correcting the error, and storing the corrected data word at a new address in a free area of the data memory. | 12-31-2009 |
20100011276 | STORAGE DEVICE FOR REFRESHING DATA PAGES OF FLASH MEMORY BASED ON ERROR CORRECTION CODE AND METHOD FOR THE SAME - A storage device for refreshing pages of a flash memory comprises a flash memory, an ECC detector and a controller. The flash memory has a plurality of pages, and each page comprises a data area for storing data and a spare area for storing error correction code (ECC) corresponding to the data. The ECC detector is used to get the number of error bits of each page. The controller coupled to the ECC detector is used for storing data and ECC in a first page to a second page when a number of used bytes of the ECC stored in a spare area of the first page exceeds a first predetermined value. A number of used bytes of the ECC stored in a spare area of the second page is less than the first predetermined value. The second page is a blank page. | 01-14-2010 |
20100042900 | Write Failure Handling of MLC NAND - In a memory system, content in a defined “risk zone” of non-volatile memory is copied into volatile memory. When a write failure occurs on non-volatile memory, the risk zone is scanned sequentially to determine corrupted content. The corrupted content is restored by writing the corresponding content previously copied to volatile memory to new blocks in non-volatile memory. | 02-18-2010 |
20100050052 | PIPELINED ERROR DETERMINATION IN AN ERROR-CORRECTING COMMUNICATION SYSTEM - A sequence of data packets is received within an integrated circuit device and stored within a first memory thereof. Error descriptor values are updated within a second memory of the integrated circuit device based on error information associated with the sequence of data packets. The error descriptor values each include an address field to specify a corresponding storage region of the first memory and an error field to specify an error status of data values stored within the storage region. A sequence of multiple-bit error values are generated based, at least in part, on the error fields and address fields within respective subsets of the error descriptor values. Concurrently with generation of at least one of the multiple-bit error values the state of one or more bits of the data values stored in the first memory based are changed based on a previously-generated one of the multiple-bit error values. | 02-25-2010 |
20100058145 | STORAGE DEVICE AND METHOD OF CONTROLLING STORAGE DEVICE - A control method is for controlling a storage device that writes data in a storage medium including a plurality of groups each having a plurality of sectors and a redundancy sector in which error correction information is stored to perform error correction on data stored in the sectors per each of the groups. The control method includes: rewriting data stored in the sectors included in one of the groups; and writing invalidation data indicating that the error correction information is invalid in the redundancy sector if the error correction information stored in the redundancy sector of the one of the groups has not been rewritten. | 03-04-2010 |
20100107039 | SEMICONDUCTOR MEMORY WITH REED-SOLOMON DECODER - A semiconductor memory device with an error checking/correction system includes a memory cell array. The error checking/correction system is capable of symbolizing data to a symbol, searching errors of data read from the memory cell array by solving equations with decoders representing a solution, correcting data based on the searched errors, and outputting the corrected data in parallel with the other process to the other data. | 04-29-2010 |
20100125774 | SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF - To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained. | 05-20-2010 |
20100131828 | SYSTEM-ON-A-CHIP STORING CHIP DATA AND/OR SECURITY DATA AND METHOD OF PROCESSING CHIP DATA AND/OR SECURITY DATA FOR A DEVICE - A system-on-a-chip (SOC) includes a memory system, a data processor and a read only memory (ROM). The memory system includes random access memory and a memory controller. The data processor includes at least one functional block that communicates data with the memory system via the memory controller. The ROM stores data and one or more parity bits for detecting and correcting errors in the data. The data includes chip information and/or security information for the SOC. A method of using the SOC includes storing data in the ROM that includes chip information and/or security information for the SOC; storing in the ROM the one or more parity bits for the data; reading the data and the one or more parity bits from the ROM; detecting and correcting errors in the data using the one or more parity bits; and outputting the corrected data. | 05-27-2010 |
20100162083 | FLASH MEMORY CONTROLLER, ERROR CORRECTION CODE CONTROLLER THEREIN, AND THE METHODS AND SYSTEMS THEREOF - An ECC controller comprises an ECC encoder, an ECC divider, an ECC constructor and an ECC decoder. The ECC encoder is configured to generate ECC data with different lengths in response to information data to be stored into a flash memory. The ECC divider is configured to divide each ECC datum generated by the ECC encoder into one or more ECC segments according to the length of the ECC datum. The ECC constructor is configured to generate an ECC datum by combining one or more ECC segments for each information datum read from the flash memory. The ECC decoder is configured to correct the errors of the information data read from the flash memory device by using the ECC data generated by the ECC constructor. | 06-24-2010 |
20100169742 | FLASH MEMORY SOFT ERROR RECOVERY - In an embodiment, the invention provides a method for correcting soft errors in memory. A block of data is written in memory wherein all rows and all columns have a first checksum appended to it. A second checksum for each row and each column is generated after reading each row and each column from memory. The first and second checksum for each row and each column are compared for a compare such that when one and only one column has a miscompare, the logical value of any bit at an intersection of the one and only one column that has a miscompare and any row that has a miscompare is reversed. | 07-01-2010 |
20100218073 | Resistive Memory Devices and Methods of Controlling Operations of the Same - To control operations of a resistive memory device, an input-output operation of an error check and correction (ECC) code is separated from an input-output operation of data. A condition of the input-output operation of the ECC code is determined stricter than a condition of the input-output operation of the data. reliability of the input-output operation of the ECC code may be enhanced, thereby reducing errors due to defect memory cells, noise, etc. | 08-26-2010 |
20100223531 | SEMICONDUCTOR STORAGE - A semiconductor storage includes a receiver configured to receive a write request from a host device; a storage unit configured to hold redundancy data generation/non-generation information; a writing unit configured to write data in a semiconductor memory array and write redundancy data generation/non-generation information of the written data in the storage unit; a first data extracting unit configured to extract data whose redundancy data is not generated from among the data held by the semiconductor memory array; a first redundancy data generating unit configured to generate redundancy data; a first redundancy data writing unit configured to write the generated redundancy data in the semiconductor memory array; and a first redundancy data generation/non-generation information updating unit configured to update the redundancy data generation/non-generation information of the data whose redundancy data held by the storage unit is generated. | 09-02-2010 |
20100269021 | Method for Performing Error Correction Operations in a Memory Hub Device of a Memory Module - A method is provided for performing error correction operations in a memory module. A memory hub device, which is integrated in the memory module, receives an access request for accessing a set of memory devices of the memory module coupled to the memory hub device. Data is transferred between a link interface of the memory hub device and the set of memory devices. Error correction logic, which is integrated in the memory hub device, performs one or more error correction operations on the data transferred between the link interface and the set of memory devices. The memory hub device transmits and receives data, via a memory channel between an external memory controller and the link interface, without any error correction code, thereby reducing an amount of bandwidth used on the memory channel. | 10-21-2010 |
20100269022 | Circuits And Methods For Dual Redundant Register Files With Error Detection And Correction Mechanisms - Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein. | 10-21-2010 |
20100293440 | APPARATUS, SYSTEM, AND METHOD TO INCREASE DATA INTEGRITY IN A REDUNDANT STORAGE SYSTEM - An apparatus, system, and method are disclosed to increase data integrity in a redundant storage system. The receive module receives a read request to read data from a logical page spanning an array of N+P number of storage elements. The array of storage elements includes N number of the storage elements each storing a portion of an ECC chunk and P number of the storage elements storing parity data. The data read module reads data from at least a portion of a physical page on each of X number of storage elements of the N+P number of storage elements where X equals N. The regeneration module regenerates missing data. The ECC module determines if the read data and any regenerated missing data includes an error. The read data combined with any regenerated missing data includes the ECC chunk. | 11-18-2010 |
20100306623 | Error Correction Devices and Correction Methods - An error correction device is provided. When an error of an incorrect data group stored in a memory is detected, a memory controller of the error correction device executes a burst read, burst write or burst read-modify-write (RMW) operations to the memory instead of the conventional single read-modify-write (RMW) operation, thereby reducing the occupied bandwidth of the memory. | 12-02-2010 |
20110041038 | DYNAMIC ELECTRONIC CORRECTION CODE FEEDBACK TO EXTEND MEMORY DEVICE LIFETIME - Unrecoverable electronic correction code (ECC) errors in memory storage devices are usually preceded by recoverable ECC errors. A memory storage device controller is provided notice of the recoverable errors and associated information. The memory storage device controller can cause the data having the recoverable information to be rewritten on the memory storage device. Rewriting the data on the memory storage device (often in a different location) normally reduces the probability of encountering data with unrecoverable data errors. | 02-17-2011 |
20110047440 | Systems and Methods to Respond to Error Detection - Systems and methods to respond to error detection are provided. First data may be received at a first memory controller port in response to a read command issued from the first memory controller port. The read command may be issued as a second read command from a second memory controller port after determining that the first data contains a first uncorrectable error. Second data may be received at the second memory controller port in response to the second read command. A repair write command may be issued from the first memory controller port after determining that the second data does not contain any errors. The repair write command may initiate writing the second data from the first memory controller port. | 02-24-2011 |
20110119561 | Flash Memory Device Error Correction Code Controllers and Related Methods and Memory Systems - An ECC controller for a flash memory device storing M-bit data (M: a positive integer equal to or greater than 2) includes an encoder and a decoder. The encoder generates first ECC data for input data to be stored in the flash memory device using a first error correction scheme and generates second ECC data for the input data using a second error correction scheme. The input data, the first ECC data, and the second ECC data are stored in the flash memory device. The decoder calculates the number of errors in data read from the flash memory device and corrects the errors in the read data using one of the first ECC data and the second ECC data selectively based on the number of the errors. | 05-19-2011 |
20110231734 | MEMORY SYSTEM - A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page. | 09-22-2011 |
20110289385 | DATA INPUT / OUTPUT CONTROL DEVICE AND SEMICONDUCTOR MEMORY DEVICE SYSTEM - When detected number of errors data Nerror exceeds the upper limit number of errors Nmax, an error correction circuit of a memory controller stores twice as long data length as stored data length for execution Sdata as the data length for execution Sdata in a correction information memory unit, and code length Scref longer than the data length for execution Sdata and detectable more errors than the upper limit number of errors as the code length for execution Scode in the correction information memory unit | 11-24-2011 |
20110289386 | Method and apparatus for scrubbing accumulated data errors from a memory system - A data scrubbing apparatus corrects disturb errors occurring in a memory cell array, such as SMT MRAM cells. The data scrubbing apparatus activates scrubbing of the data and associated error correction bits based on a number of errors corrected, at a power up of the memory cell array, or a programmed time interval. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data, the associated error correction bits, and reference bits. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data. | 11-24-2011 |
20120030542 | DATA STORAGE DEVICE - A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a copy command from the host using the interface, read data from a source memory device in response to the copy command, write the data to a destination memory device in response to the copy command and communicate results to the host using the interface. | 02-02-2012 |
20120066568 | STORAGE DEVICE, ELECTRONIC DEVICE, AND DATA ERROR CORRECTION METHOD - According to one embodiment, a storage device includes an error detector, a check module, and a replacement module. The error detector detects a bit error that occurs in entry data related to conversion to a physical address corresponding to a logical address based on an error detecting code assigned to the entry data. The check module checks whether data obtained by inverting a predetermined bit contained in the entry data where the bit error is detected is normal entry data. The replacement module replaces the entry data where the bit error is detected with the normal entry data. | 03-15-2012 |
20120079351 | Systems and Methods for Memory Devices - A method for writing data to a memory array includes receiving a write request including data from a processor, compressing the data, assigning a page strength to the compressed data, the page strength defined by a compression ratio used to compress the data, generating a parity data block associated with the compressed data, and saving the compressed data and the parity data block in a page of the memory array, the page of the memory array having a page strength corresponding to the assigned page strength of the compressed data. | 03-29-2012 |
20120110415 | DECODING APPARATUS, METHOD, AND PROGRAM - The present disclosure provides a decoding apparatus including, a storage section configured to store a reception value, a detection section configured to detect an error in the reception value, an error correction section configured to correct an error detected by the detection section with respect to the reception value, and a control section configured to control reading of the reception value from the storage section, wherein the control section controls first reading such that the reception value is read into the detection section and, after detection of an error by the detection section, second reading such that substantially the same reception value as that in the first reading is read into the error correction section. | 05-03-2012 |
20120151299 | Embedded DRAM having Low Power Self-Correction Capability - Apparatuses and methods for low power combined self-refresh and self-correction of a Dynamic Random Access Memory (DRAM) array. During a self-refresh cycle, a first portion of a first row of the DRAM array is accessed and analyzed for one or more errors, wherein a bit width of the first portion is less than a bit width of the first row. If one or more errors are detected, the one or more errors are corrected to form a corrected first portion. The corrected first portion is selectively written back to the first row. If no errors are detected in the first portion, a write back of the first portion to the first row is prevented. | 06-14-2012 |
20120246544 | METHOD AND APPARATUS FOR MEMORY READ-REFRESH, SCRUBBING AND VARIABLE-RATE REFRESH - A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described. | 09-27-2012 |
20120254698 | Memory scrubbing - A data processing apparatus is provided which comprises a processor unit configured to perform data processing operations in response to a sequence of instructions and a storage unit configured to store data values for access by the processor unit when performing its data processing operations. Redundant error control data is stored in association with the data values, the redundant error control data enabling identification of an error in the data values. The data processing apparatus also comprises a data scrubbing unit configured to perform a data scrubbing process on at least a subset of the data values, the data scrubbing process comprising determining with reference to the redundant error control data if an error is present in that subset of data values and, where possible, correcting that error with reference to the redundant error control data. The data scrubbing unit is configured to receive a scrub transaction issued within said data processing apparatus, and to perform the data scrubbing process upon receipt of the scrub transaction. | 10-04-2012 |
20130055046 | MEMORY REFRESH METHODS AND APPARATUSES - Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed. | 02-28-2013 |
20130055047 | SYSTEM AND METHOD OF COPYING DATA - A method of copying data includes receiving a command instructing copying of data from a source location in the memory die to a destination location in the memory die. The method includes determining if a criterion is met, including comparing a predefined parameter to a dynamic threshold. In response to determining that the criterion is met, the method includes executing the copying by moving the data from the source location in the memory die to the controller die and, after moving the data to the controller die, moving an error-corrected version of the data from the controller die to the destination location in the memory die. In response to determining that the criterion is not met, the method includes executing the copying by moving the data inside the memory die source location to the destination location without moving the data to the controller die. | 02-28-2013 |
20130097473 | FLASH MEMORY - A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal. | 04-18-2013 |
20130104003 | MEMORY SYSTEM AND METHOD FOR RECORDING/REPRODUCING DATA THEREOF - A memory system and a method for recording/reproducing data thereof, the memory system including a flash memory, and a memory controller configured control an operation to record data on the flash memory or to reproduce the recorded data from the flash memory, wherein the memory controller includes an encoder configured to generate an Error Correction Code (ECC) from data that is to be recorded in the flash memory and to convert the generated ECC by using a particular ECC, a memory interface configured to record the data and the converted ECC to the flash memory, and a decoder configured to restore the converted ECC, which is read from the flash memory, by using the particular ECC and to detect and correct an error of the data, which is read from the flash memory, by using the restored ECC, and the particular ECC is an ECC with respect to 0xff data. | 04-25-2013 |
20130132797 | CONTROL METHOD FOR A SEMICONDUCTOR MEMORY DEVICE - To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained. | 05-23-2013 |
20130139032 | Memory System With Error Detection And Retry Modes Of Operation - A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. | 05-30-2013 |
20130166990 | MEMORY CIRCUIT INCORPORATING RADIATION-HARDENED MEMORY SCRUB ENGINE - An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry. | 06-27-2013 |
20130166991 | Non-Volatile Semiconductor Memory Device Using Mats with Error Detection and Correction and Methods of Managing the Same - A non-volatile semiconductor memory device can include a RAID controller configured to, upon data recording, distributively record a plurality of pieces of division data obtained by dividing the corresponding data and parity data generated from the division data in respective non-faulty blocks of a plurality of memory mats with reference to a bad block table, upon data reading, read a plurality of pieces of division data and parity data corresponding to designated data from respective blocks of the plurality of memory mats, and when an error occurs, recover data of a memory mat in which the error has occurred using data of another memory mat, store the recovered data in a block of the same memory mat in which the error has occurred other than a previous block, and store data representing the block in which the error has occurred in the bad block table. | 06-27-2013 |
20130173992 | MEMORY CONTROL DEVICE AND MEMORY CONTROL METHOD - A memory control device includes a CPU, a flash ROM that records therein first information having undergone an error-correction coding process and second information not having undergone an error-correction coding process, an address line switch that switches between a first path that connects an address bus to the ROM so that the CPU can read the first information and a second path that connects the address bus to the ROM so that the second information can be erased, written, and read, a decoder that performs error correction on the first information and performs decoding, and a second switch that switches between a third path that connects the decoder to the data bus so that information decoded by the decoder is transmitted to the data bus and a fourth path that connects the ROM to the data bus so that the second information can be erased, written, and read. | 07-04-2013 |
20130173993 | DECODING APPARATUS AND DECODING METHOD - A control device ( | 07-04-2013 |
20130191701 | METHOD FOR MONITORING A DATA MEMORY - A method is described for monitoring a data memory in which an error detection method is used to detect and/or correct incorrect data words stored in memory lines of the data memory, an address of the data memory at which a data word evaluated as incorrect by the error detection method is stored being written to an auxiliary memory and being made available to a checking program. | 07-25-2013 |
20130212449 | SELF-REPAIRING MEMORY - A memory array has a plurality of rows including a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the associated memory word has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. A corrected data cache has at least one repair word configured to store corrected data and at least one status bit associated with the at least one repair word, the status bit indicating whether the corrected data stored in the repair word is a pending repair. The corrected data cache is configured to write the corrected data stored in the repair word to at least one of a counterpart memory word or a counterpart redundancy word. | 08-15-2013 |
20130232391 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes semiconductor memory chips in which data requested to be written. The data has one or more pieces of first data in a predetermined unit. The device includes a write controller that writes the first data and redundancy information calculated by using a predetermined number of pieces of the first data and used for correcting an error in the predetermined number of pieces of the first data into different semiconductor memory chips; and a storage unit that stores identification information and region specifying information so as to be associated with each other. The identification information associates the first data and the redundancy information, and the region specifying information specifies a plurality of storage regions in the semiconductor memory chips to which the pieces of the first data and the redundancy information associated with each other are written. | 09-05-2013 |
20130246890 | ARCHITECTURE TO ALLOW EFFICIENT STORAGE OF DATA ON NAND FLASH MEMORY - Systems, methods, apparatus, and techniques are provided for writing data to a storage medium. A stripe of the storage medium is interfaced via one or more data transfer channels, where the stripe comprises a plurality of pages of the storage medium. A data stream is received and the data stream is portioned into a plurality of allocation units (AUs), where each AU in the plurality of AUs has a pre-determined byte length. A first portion of a selected AU from the plurality of AUs is written to a first page of the plurality of pages and a second portion of the selected AU is written to a second page of the plurality of pages by consecutively writing bytes of the selected AU from a starting byte on the first page to an ending byte on the second page. | 09-19-2013 |
20130254626 | MEMORY SYSTEM AND METHOD USING ECC WITH FLAG BIT TO IDENTIFY MODIFIED DATA - A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device, The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data. | 09-26-2013 |
20130254627 | STRIPE-BASED MEMORY OPERATION - The present disclosure includes methods and devices for stripe-based memory operation. One method embodiment includes writing data in a first stripe across a storage volume of a plurality of memory devices. A portion of the first stripe is updated by writing updated data in a portion of a second stripe across the storage volume of the plurality of memory devices. The portion of the first stripe is invalidated. The invalid portion of the first stripe and a remainder of the first stripe are maintained until the first stripe is reclaimed. Other methods and devices are also disclosed. | 09-26-2013 |
20130275831 | SEMICONDUCTOR DEVICE, CONFIDENTIAL DATA CONTROL SYSTEM, CONFIDENTIAL DATA CONTROL METHOD - A semiconductor device, a confidential data control system and a confidential data control method are provided capable of safeguarding confidential data even in cases of unauthorized access. Control is performed to alternately store confidential data segments of divided confidential data and respective corresponding segment parity data in a memory. When reading the confidential data, errors in the confidential data segment are checked for with the segment parity data, corrected when an error has occurred, and read. The confidential data is not stored altogether in the memory, and so the confidential data is rendered difficult to discern even in cases in which unauthorized access (hacking) has occurred to the confidential data control system. | 10-17-2013 |
20130275832 | DATA RECOVERY USING ADDITIONAL ERROR CORRECTION CODING DATA - A method in a data storage device including a memory and an error correction coding (ECC) engine. A first ECC page including a data block and first main ECC data is stored to the memory. The first main ECC data is usable by the ECC engine to correct errors in the first ECC page. A second ECC page including first additional ECC data is also stored to the memory. The first additional ECC data is usable by the ECC engine to correct errors in a single sub-block of multiple sub-blocks within the data block. | 10-17-2013 |
20130275833 | METHOD AND APPARATUS FOR REBUILDING DATA IN A DISPERSED DATA STORAGE NETWORK - A method begins a first rebuilder application identifying a data slice having a storage error. The method continues with the first rebuilder application or a second rebuilder application identifying a data segment based on the identified data slice. The method continues with the second rebuilder application identifying one or more other slice servers that are storing other data slices of the encoded data segment. The method continues with the second rebuilder application receiving a sufficient number of the other data slices to reconstruct the data segment and decoding them to reconstruct the data segment. The method continues with the second rebuilder application encoding the reconstructed data segment in accordance with the information dispersal algorithm to produce a new set of data slices and selecting one of them as the rebuild data slice. | 10-17-2013 |
20130275834 | METHOD AND APPARATUS FOR STORAGE INTEGRITY PROCESSING BASED ON ERROR TYPES IN A DISPERSED STORAGE NETWORK - A storage integrity system in a dispersed storage network scans an address range of data slices to identify errors in one of a plurality of encoded data slices, wherein the plurality of encoded data slices are generated from a data segment using an error encoding dispersal function. When the storage integrity system detects an error, it identifies one of the encoded data slices for rebuilding. The identified data slice is rebuilt in response to the type of error. For example, when the type of the error includes a temporary error, the storage integrity system waits a predetermined time period to determine whether the error still exists prior to rebuilding the identified data slice. | 10-17-2013 |
20130290810 | DATA ARCHIVE SYSTEM, DATA RECORDING/REPRODUCING APPARATUS AND DATA LIBRARY APPARATUS - In a data recording and reproducing apparatus that includes a host computer and a drive in order to improve data reliability, in data recording, the host computer appends a first error correction code to the data and the drive appends a second error correction code to the data. When a failure has occurred in error correction performed by the drive using the second error correction code, the drive reads out the first error correction code and performs error correction using the first error correction code. Since error correction using the first error correction is possible even when error correction using the second error correction code ends in failure, the reliability of data is improved. | 10-31-2013 |
20130290811 | MEMORY QUALITY MONITOR BASED COMPENSATION METHOD AND APPARATUS - In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected. | 10-31-2013 |
20130305120 | MEMORY CONTROLLER, STORAGE DEVICE AND ERROR CORRECTION METHOD - According to one embodiment, a memory controller includes an encoding unit that generates a first parity for every user data and a second parity for two or more user data and the corresponding first parity, a memory interface unit that the non-volatile memory to write and read the user data and the parities to and from the non-volatile memory, and a decoding unit that performs an error correction decoding process using the user data, and the parities. The error correction decoding processing that uses both the first parity and the second parity has at least A (a correcting capability of the first parity)+B (a correcting capability of the second parity) bits of correcting capability for the first user data and its first and second parities and for the second user data and its first and second parities. | 11-14-2013 |
20130305121 | METHOD FOR REDUCING UNCORRECTABLE ERRORS OF A MEMORY DEVICE REGARDING ERROR CORRECTION CODE, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for reducing uncorrectable errors of a memory device regarding Error Correction Code (ECC) includes: performing majority vote according to data read at different times at a same address in order to generate majority vote data corresponding to the address; and checking whether the majority vote data has any uncorrectable error in order to determine whether to output the majority vote data as data of the address. For example, the method further includes: within the data read at different times at the same address, temporarily storing all of the data except for data of a last time into buffering regions/buffers, respectively, with the majority vote data being temporarily stored into a second buffering region/buffer to utilize a latest generated portion within the majority vote data to replace a latest retrieved portion within data in the second buffering region/buffer. An associated memory device and the controller thereof are further provided. | 11-14-2013 |
20130305122 | APPARATUS AND METHOD FOR STORING AND ASSIGNING ERROR CHECKING AND CORRECTING PROCESSING OF DATA TO STORAGE ARRAYS - A data processing module includes a first interface connected to (i) a host via a second interface, and (ii) storage arrays. The first interface receives, from the host via the second interface, blocks of data for storage in one or more of the storage arrays. A memory stores the blocks of data received by the first interface. A processor (i) determines error checking and correcting processing to be applied to each block of data of the blocks of data, and (ii) for each block of data, (a) transfers the block of data from the memory to a selected storage array of the storage arrays, and (b) assigns, to the selected storage array, the error checking and correcting processing to be applied to the block of data. The memory stores a map. The map indicates storage of the blocks of data among the storage arrays. | 11-14-2013 |
20130305123 | SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE - Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die. | 11-14-2013 |
20130332799 | RECURSIVELY DETERMINED INVERTIBLE SET APPROACH TO CORRECT MULTIPLE STUCK-AT FAULTS IN REWRITABLE MEMORY - Systems and methods are disclosed that facilitate storage and retrieval of data to/from memory with permanent faults. Permanent “stuck at” faults, associated with individual bits, interfere with Write operations. A memory bit with the SA-0 fault does not store the value “1” while a memory bit with the SA-1 fault does not store the value “0”. Hence, when later retrieved by a Read operation, stored data located on one or more bits having a permanent fault may be different from the data that was originally written. Techniques are disclosed that facilitate correct retrieval of data in the presence of “stuck at” faults by keeping track of the positions of the bits that are stuck at a value different from the ones that are written and then, at Read time, inverting the values read from those positions. | 12-12-2013 |
20130346829 | FLASH MEMORY DEVICE AND STORAGE CONTROL METHOD - When writing data to a first-type FM part, an FM controller of a flash memory device (A1) generates a redundant code, and (A2) writes the data and the redundant code. when reading the written data, the flash memory controller (B1) reads the data and the redundant code, (B2) corrects any bit errors based on the redundant code, (B3) generates error correction information including positions of the bit errors occurring and values before the bit errors occurred, and (B4) writes the error correction information to a second-type FM part. Subsequently, when reading the data, the flash memory controller (C1) reads the data and the redundant code, (C2) reads the error correction information, (C3) corrects the data and the redundant code based on the error correction information, (C4) corrects any bit errors based on the corrected redundant code, (C5) updates the error correction information by adding, to the error correction information, positions of the corrected bit errors and values before the bit errors occurred, and (C6) writes the updated error correction information to the second-type FM part. | 12-26-2013 |
20140006900 | MEMORY CONTROLLER UTILIZING AN ERROR CODING DISPERSAL FUNCTION | 01-02-2014 |
20140026013 | STORAGE CONTROL APPARATUS AND ERROR CORRECTION METHOD - A controller of a storage control apparatus creates a fixed value, which is one or higher values conforming to a prescribed data pattern, with respect to first data, which is smaller than the size of a storage area of a storage device, creates a guarantee code related to a data area comprising the first data and the fixed value, and writes the data group comprising the data area and the guarantee code to the storage area. The controller reads a data group from the storage area, and determines whether or not more errors than the number of errors correctable by the guarantee code are included in this data group. In a case where the result of this determination is affirmative, the controller determines whether or not an error exists in the fixed value inside the data group. In a case where the result of this determination is affirmative, the controller corrects the fixed value, in which there is an error, to a correct fixed value, and in a case where the number of errors included in the data group is equal to or less than the number of errors correctable by the guarantee code, uses the guarantee code to correct errors in the data group. | 01-23-2014 |
20140040701 | NON-VOLATILE SEMICONDUCTOR STORAGE APPARATUS - According to one embodiment, a non-volatile semiconductor storage apparatus is configured to decide determination periods respectively corresponding to each of management blocks based on rewrite count information items and a temperature, and to perform a determination processing for each of management blocks for each determination period. The determination processing includes determining whether first data read from a block in the blocks is normal based on the number of errors that are occurred in the first data. The apparatus is configured to perform a rewrite processing of rewriting the first data to second data which is error-corrected when it is determined that the first data is not normal. | 02-06-2014 |
20140047299 | CONTROL DEVICE FOR VEHICLE AND ERROR PROCESSING METHOD IN CONTROL DEVICE FOR VEHICLE - A control device for a vehicle including a nonvolatile memory which is electrically erasable and writable detects, on start-up, whether or not an error occurs in updated data read from the nonvolatile memory, and when an error has been detected, performs a reset after saving error information. When being restarted by the reset, the control device for a vehicle determines on the basis of the error information whether or not there is updated data in which an error has occurred, and when there is updated data in which an error has occurred, overwrites the updated data with a fixed value prior to the error detection. Accordingly, there can be suppressed a case in which the error detection is performed while the updated data with an abnormality is present causing the reset and the error detection to be repeated. | 02-13-2014 |
20140068377 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - Semiconductor memory device and method of operating same includes reading data stored in memory cells of a page; performing an error correction loop (ECC loop) including performing an error checking and correcting operation (ECC) on the read data; determining a number of bit errors in the read data; and when the number of bit errors is greater than a maximum number of correctable bits, incrementing the number of ECC iterations (ECC count) and increasing the maximum number of correctable bits; storing the ECC count until the number of bit errors is less than the maximum number of correctable bits; and programming corrected data to the memory cells when the stored ECC count is more than preset number. | 03-06-2014 |
20140068378 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY CONTROLLER - According to an embodiment, a semiconductor storage device includes a memory, an encoding unit that generates a parity, and a decoding unit that includes a syndrome calculating unit, an error position polynomial calculating unit, and an error searching and correcting unit, and performs an error correcting process based on data and the parity read from the memory. At the time of performing a compaction process, a process of the error searching and correcting unit is not performed, when the number of error bits acquired by an error position polynomial is equal to or less than a first threshold value based on valid data. | 03-06-2014 |
20140068379 | MEMORY SYSTEM - According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device. | 03-06-2014 |
20140075267 | GALOIS FIELD ARITHMATIC OPERATION CIRCUIT AND MEMORY DEVICE - A Galois field arithmetic operation circuit substituting (2̂m−1) elements (m is an integer) expressed by m bits of Galois field GF(2̂m) includes: a base calculation unit configured to calculate m linear independent elements out of the (2Am−1) elements; and a linear development unit configured to calculate the remaining (2̂m−1−m) elements not included in the m linear independent elements by combination of the m linear independent elements respectively. The Galois field arithmetic operation circuit may be included in a memory device or other system. | 03-13-2014 |
20140082456 | DATA STORAGE DEVICE WITH INTERMEDIATE ECC STAGE - A data storage device includes a non-volatile memory and a controller including a first error correction coding (ECC) engine configured to generate a first codeword corresponding to data to be stored at the non-volatile memory. The data storage device also includes a second ECC engine coupled to the controller and to the non-volatile memory. The second ECC engine is configured to receive a representation of the first codeword from the controller and to perform a decode operation of the representation of the first codeword to correct transmission errors prior to storage of the data in the non-volatile memory. | 03-20-2014 |
20140082457 | ERROR CORRECTING FOR IMPROVING RELIABILITY BY COMBINATION OF STORAGE SYSTEM AND FLASH MEMORY DEVICE - According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an FET which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger. | 03-20-2014 |
20140082458 | Methods of Performing Error Detection/Correction in Nonvolatile Memory Devices - Methods of operating nonvolatile memory devices include testing strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other strings. An identity of the at least one weak string may be stored as weak column information, which may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on bits of data read from the strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the data bits. | 03-20-2014 |
20140108886 | Pipelined Data Relocation and Improved Chip Architectures - The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped. | 04-17-2014 |
20140108887 | STORAGE DEVICE - According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits. | 04-17-2014 |
20140122970 | SYSTEM AND METHOD FOR ACCESSING A DATA OBJECT STORED IN A DISTRIBUTED STORAGE NETWORK - A user device includes a browser module, a DSN interface to a local or external DSN memory and a DS processing module coupled to the DSN interface for storing and retrieving the data object from the DSN memory, wherein the data object is divided into a plurality of data segments and wherein each of the plurality of data segments is stored in the DSN memory as a plurality of encoded data slices that are generated based on an error encoding dispersal function. The browser module is operable to interpret a user input as a request to display a data object, determine the data object is stored in the DSN memory, request the DS processing module to retrieve the data object from the DSN memory and request an application program to open the data object for display. | 05-01-2014 |
20140129901 | MEMORY SYSTEM - A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host. | 05-08-2014 |
20140129902 | APPARATUS AND METHOD OF OPERATING MEMORY DEVICE - A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array. | 05-08-2014 |
20140129903 | METHOD OF OPERATING MEMORY DEVICE - A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage. | 05-08-2014 |
20140136924 | METHOD AND SYSTEM FOR DETERMINING STORING STATE OF FLASH MEMORY - A method for determining a storing state of a flash memory is provided. The method includes the following steps. Firstly, plural first specific cell patterns are programmed into the flash memory. Then, plural second specific cell patterns are programmed into the flash memory. Then, a slicing voltage is adjusted to allow a distinguishable error percentage to be lower than a predetermined value. Afterwards, a first storing state and a second storing state of other cells of the flash memory are distinguished from each other according to the adjusted slicing voltage. | 05-15-2014 |
20140136925 | METHOD OF OPERATING A DATA STORAGE DEVICE - A method of operating a data storage device including a nonvolatile memory device includes reading last programmed data from the nonvolatile memory device, detecting an error included in the data read in the reading, correcting the error of if the error is correctable, and reprogramming the corrected data to the nonvolatile memory device. | 05-15-2014 |
20140143632 | Method to Extend Data Retention for Flash Based Storage in a Real Time Device Processed on Generic Semiconductor Technology - This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention provides a manner to re-energize the Flash memory array to improve the retention characteristics of the memory without altering the clock cycle determinism of the system. Under certain conditions the Flash memory bit cells will lose their charge/non-charge over time. In this particular FLASH technology, an ECC is used to correct single bit errors within a 32 bit word. If there is time before multiple errors occur within a word, the single error cases are identified and “ReFlashed” to bring the value of the cell back to its “newly” programmed levels. This dramatically improves the long term retention characteristics of the memory while requiring some control logic and an area of non-volatile scratch/status information. | 05-22-2014 |
20140143633 | APPARATUS AND METHOD FOR CORRECTING ERRORS IN DATA ACCESSED FROM A MEMORY DEVICE - An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected. | 05-22-2014 |
20140143634 | NON-REGULAR PARITY DISTRIBUTION DETECTION VIA METADATA TAG - This can relate to non-regular parity distribution of a non-volatile memory (“NVM”), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword. | 05-22-2014 |
20140149825 | SCALING FACTORS FOR HARD DECISION READS OF CODEWORDS DISTRIBUTED ACROSS DIE - Embodiments include methods, apparatuses, and instructions for encoding a codeword of data as codeword portions stored across multiple die in a non-volatile memory. Embodiments further include a decoder which may be configured to decode the portions of the codeword using hard decision reads. The decoder may then be configured to estimate the quality of each die, and apply a scaling factor to the decoded codeword portions such that confidence or reliability information can be determined for the codeword. | 05-29-2014 |
20140149826 | DATA RELIABILITY SCHEMES FOR DATA STORAGE SYSTEMS - A data storage system configured to implement a data reliability scheme is disclosed. In one embodiment, a data storage system controller detects uncorrectable errors using intra page parity when data units are read from a set of pages. When an uncorrectable error is detected, the data storage system controller attempts to recover user data using inter page parity without using all data from each page of the set of pages. Recovery of user data can thereby be performed without reading all data from each page. As a result, the amount of time needed to read data can be reduced in some cases and overall data storage system performance can be increased. | 05-29-2014 |
20140149827 | SEMICONDUCTOR MEMORY DEVICE INCLUDING NON-VOLATILE MEMORY, CACHE MEMORY, AND COMPUTER SYSTEM - In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number. | 05-29-2014 |
20140164870 | SYSTEM AND METHOD FOR LOWER PAGE DATA RECOVERY IN A SOLID STATE DRIVE - In some embodiments of the present invention, a data storage system includes a controller and a non-volatile memory array having a plurality of memory pages. The controller performs a method that efficiently resolves the lower page corruption problem. In one embodiment, the method selects programmed lower page(s) for which paired upper page(s) have not been programmed, reads data from those selected lower page(s), corrects the read data, and reprograms the read data into those lower page(s). Since the number of lower pages in this condition is typically low (e.g., several pages in a block with hundreds or thousands of pages), this is a much more efficient method than reprogramming the entire block. In another embodiment, a similar reprogramming method is applied as a data recovery scheme in situations in which only lower pages are programmed (e.g., SLC memory, MLC memory in SLC mode, etc.). | 06-12-2014 |
20140164871 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140164872 | ERROR CORRECTED PRE-READ FOR UPPER PAGE WRITE IN A MULTI-LEVEL CELL MEMORY - Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data. | 06-12-2014 |
20140164873 | Techniques For Storing Bits in Memory Cells Having Stuck-at Faults - A data storage system includes a memory circuit comprising memory cells and a control circuit. The control circuit generates a first set of redundant bits indicating bit positions of the memory cells having stuck-at faults in response to a first write operation if a first rate of the stuck-at faults in the memory cells is greater than a first threshold. The control circuit is operable to encode data bits to generate encoded data bits and a second set of redundant bits that indicate a transformation performed on the data bits to generate the encoded data bits in response to a second write operation if a second rate of stuck-at faults in the memory cells is greater than a second threshold. The encoded data bits stored in the memory cells having the stuck-at faults match digital values of corresponding ones of the stuck-at faults. | 06-12-2014 |
20140164874 | DRAM ERROR DETECTION, EVALUATION, AND CORRECTION - This disclosure includes a method for correcting errors on a DRAM having an ECC which includes writing data to a DRAM row, reading data from the DRAM row, detecting errors in the data that cannot be corrected by the DRAM's ECC, determining erasure information for the row, evaluating the errors using the erasure information, and correcting the errors in the data. | 06-12-2014 |
20140164875 | MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME - A memory controller includes a register configured to store a parity check matrix, and an error correcting code (ECC) decoder configured to perform error bit correction on data supplied from a non-volatile memory device using the parity check matrix. The parity check matrix includes N column matrices, where N is a natural number. Each of the N column matrices includes multiple sub-matrices, and a last sub-matrix of the multiple sub-matrices of each column matrix, which is a non-zero valued matrix that comes last in an decoding sequence of the ECC decoder, is an identity matrix. | 06-12-2014 |
20140173379 | DIRTY CACHELINE DUPLICATION - A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory. | 06-19-2014 |
20140173380 | ERROR RECOVERY FOR FLASH MEMORY - An indication of a page type which failed error correction decoding is received. A threshold to adjust is selected from a plurality of thresholds based at least in part on the page type. A third adjusted threshold associated with the page type is generated, including by: determining a first number of flipped bits using a first adjusted threshold associated with the page type, determining a second number of flipped bits using a second adjusted threshold associated with the page type, and generating the third adjusted threshold using the first number of flipped bits and the second number of flipped bits. | 06-19-2014 |
20140181620 | System and Method for Using Solid State Storage Systems as a Cache for the Storage of Temporary Data - A method of storing data includes a storage device controller that receives a storage access operation to store data on at least one non-volatile storage device having a plurality of individually accessible blocks. In response to receiving the storage access operation to store data, the controller initiates a first program cycle to store the data as temporary data within one or more of the blocks. The program cycle has an associated first set of parameters for storage of temporary data. In response to a pre-determined period of time for the storage of temporary data being exceeded or a pre-determined capacity for temporary data has been exceeded, the controller initiates a second program cycle to store the temporary data as persistent data within one or more of the blocks. The second program cycle has an associated second set of parameters for storage of persistent data. | 06-26-2014 |
20140201596 | Adaptation of Analog Memory Cell Read Thresholds Using Partial ECC Syndromes - A method includes storing data that is encoded with an Error Correction Code (ECC) in a group of analog memory cells. The memory cells in the group are read using multiple sets of read thresholds. The memory cells in the group are divided into two or more subsets. N partial syndromes of the ECC are computed, each partial syndrome computed over readout results that were read using a respective set of the read thresholds from a respective subset of the memory cells. For each possible N-bit combination of N bit values at corresponding bit positions in the N partial syndromes, a respective count of the bit positions in which the combination occurs is determined, so as to produce a plurality of counts. An optimal set of read thresholds is calculated based on the counts, and data recovery is performed using the optimal read thresholds. | 07-17-2014 |
20140201597 | ERROR CORRECTION WITH EXTENDED CAM - A memory system includes a memory and a content addressable memory (CAM). The memory includes a plurality of address locations, wherein each address location configured to store data and one or more error correction bits corresponding to the data. The CAM includes a plurality of entries, wherein each entry configured to store an address value of an address location of the memory and one or more extended error correction bits corresponding to the data stored at the address location of the memory. | 07-17-2014 |
20140208187 | SEMICONDUCTOR APPARATUS AND METHOD OF OPERATING THE SAME - A semiconductor apparatus includes a memory device configured to include a buffer memory block and a main memory block, and to correct data read from the buffer memory block based on error information, and to perform a program loop to store corrected data in the main memory block, and a memory controller configured to perform an error checking and correction (ECC) operation on the data and to output the error information obtained through the ECC operation to the memory device. | 07-24-2014 |
20140237319 | NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A nonvolatile memory device includes a nonvolatile memory, a buffer memory configured to store a plurality of read data transmitted from the nonvolatile memory, an error detection and correction circuit configured to detect an error in partial data of each of the plurality of read data and judging whether the partial data is correctable or not on the basis of the detected error, and a controller configured to analyze the uncorrectable partial data with respect to the plurality of read data to determine a representative value, and to transmit the representative value to the error detection and correction circuit. The plurality of read data is read through a read operation with respect to a same page. | 08-21-2014 |
20140245106 | MEMEROY CIRCUITS, METHOD FOR ACCESSING A MEMORY AND METHOD FOR REPAIRING A MEMORY - A memory circuit is described comprising a plurality of memory elements, wherein each memory element is configured to store one data element of a plurality of data elements, an error correction information memory configured to store joint error correction information of the plurality of data elements, for each memory element, an error detection information memory storing error detection information for the data element stored in the memory element and a memory access circuit configured to, for an access to a memory element of the plurality of memory elements, check whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element and, depending on whether the error detection information for the data element stored in the memory element indicates an error of the data element stored in the memory element, to process the error correction information for the access. | 08-28-2014 |
20140281805 | SELECTIVE REMEDIAL ACTION BASED ON CATEGORY OF DETECTED ERROR FOR A MEMORY READ - Embodiments of apparatus, methods, systems, computer-readable storage media and devices are described herein for determining an error category for a detected error in data read from a volatile memory; and selectively performing or causing an additional remedial action based at least in part on the error category determined. In various embodiments, the determining and the performing or causing may be undertaken in response to the correcting. The memory may be volatile or non-volatile memory. Other embodiments may be described and/or claimed. | 09-18-2014 |
20140281806 | SYSTEM AND METHOD TO REDUCE READ LATENCY OF A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. The controller is configured to receive a read request that indicates a logical address. The controller is further configured to perform a first read operation to retrieve a representation of an entry of a logical mapping table from the memory, and perform a second read operation to retrieve a representation of a codeword from the memory. The controller is further configured to decode the representation of the codeword to determine whether an error exists at the entry, and, prior to completion of decoding, to initiate a third read operation to retrieve first read data from a first physical address corresponding to the logical address as determined based on the representation of the entry. | 09-18-2014 |
20140281807 | INFORMATION REPRODUCING APPARATUS AND INFORMATION REPRODUCING METHOD - An information reproducing apparatus includes a read unit configured to read data a multiple number of times, a data evaluation unit configured to generate data to be corrected, based on an evaluation on a bit basis of each of a plurality of pieces of data acquired as result of reading the data multiple number of times, and a correction unit configured to correct an error using the data to be corrected generated by the data evaluation unit. | 09-18-2014 |
20140281808 | ERROR CORRECTION OPERATIONS IN A MEMORY DEVICE - Error correction operations in memory devices are disclosed. In at least one embodiment, an internal controller of a memory device periodically performs internal error correction operations on stored user data and corrects user data in the memory device independently from instructions from an external memory access device. | 09-18-2014 |
20140281809 | Merging Independent Writes, Separating Dependent And Independent Writes, And Error Roll Back - In an embodiment, a method of updating a memory with a plurality of memory lines, the memory storing a tree, a plurality of buckets, and a plurality of rules, can include maintaining a copy of the memory with a plurality of memory lines. The method can further include writing a plurality of changes to at least one of the tree, the plurality of buckets, and the plurality of rules to the copy. The method can additionally include determining whether each of the plurality of changes is an independent write or a dependent write. The method can further include merging independent writes to the same line of the copy. The method further includes transferring updates from the plurality of lines of the copy to the plurality of lines of the memory. | 09-18-2014 |
20140281810 | MEMORY CIRCUIT INCORPORATING ERROR DETECTION AND CORRECTION (EDAC), METHOD OF OPERATION, AND SYSTEM - An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry. | 09-18-2014 |
20140281811 | OBJECT ORIENTED MEMORY IN SOLID STATE DEVICES - The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks. | 09-18-2014 |
20140281812 | Method and apparatus for nested dispersed storage - A method begins by a DS processing module generating a plurality of encoded slices from a data segment using an error encoding function. The method continues with the DS processing module identifying a plurality of DS storage units for storing the plurality of encoded slices. The method continues with the DS processing module selecting an encoded slice of the plurality of encoded slices for sub-slicing using a sub-slicing encoding function to produce a selected encoded slice. The method continues with the DS processing module outputting the plurality of encoded slices to the plurality of DS storage units. The method continues with the DS processing module outputting a command to a DS storage unit of the plurality of DS storage units corresponding to the selected encoded slice, wherein the command includes an instruction to sub-slice the selected encoded slice. | 09-18-2014 |
20140304566 | METHOD AND APPARATUS FOR MITIGATING EFFECTS OF MEMORY SCRUB OPERATIONS ON IDLE TIME POWER SAVINGS MODE - An approach for saving power in a memory subsystem that uses memory access idle timer to enable low power mode and memory scrub operation within computing system has been provided. The computing system determines that a memory subsystem is switched out of low power operation mode due to a memory scrub operation. In addition, the computing system bypasses the low power operation mode of an idle timer of the memory subsystem such that the memory subsystem is returned to the low power operation mode upon completion of the memory scrub operation. The computing system further sets a scrub flag of the memory subsystem to a high state, and clears the scrub flag to a low state to track if the idle timer should be bypassed. | 10-09-2014 |
20140310570 | STALE DATA DETECTION IN MARKED CHANNEL FOR SCRUB - Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel. | 10-16-2014 |
20140310571 | Local Erasure Codes for Data Storage - In some examples, an erasure code can be implemented to provide for fault-tolerant storage of data. Maximally recoverable cloud codes, resilient cloud codes, and robust product codes are examples of different erasure codes that can be implemented to encode and store data. Implementing different erasure codes and different parameters within each erasure code can involve trade-offs between reliability, redundancy, and locality. In some examples, an erasure code can specify placement of the encoded data on machines that are organized into racks. | 10-16-2014 |
20140310572 | EFFICIENT STORAGE OF ENCRYPTED DATA IN A DISPERSED STORAGE NETWORK - A method begins with a processing module obtaining data to store and determining whether substantially similar data to the data is stored. When the substantially similar data is not stored, the method continues with the processing module generating a first encryption key based on the data, encoding the first encryption key into encoded data slices in accordance with an error coding dispersal storage function, and storing the encoded data slices in a dispersed storage network (DSN) memory. The method continues with the processing module encrypting the data using an encryption key of the substantially similar data in accordance with an encryption function to produce encrypted data, compressing the encrypted data in accordance with a compression function to produce compressed data, storing the compressed data when the substantially similar data is stored. | 10-16-2014 |
20140317469 | MEMORY DEVICE FOR PERFORMING ERROR CORRECTION CODE OPERATION AND REDUNDANCY REPAIR OPERATION - Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword. | 10-23-2014 |
20140317470 | MEMORY DEVICES THAT PERFORM MASKED WRITE OPERATIONS AND METHODS OF OPERATING THE SAME - A method of operating a memory device includes: generating an internal read command in response to a received masked write command, the internal read command being generated one of (i) during a write latency associated with the received masked write command, (ii) after receipt of a first bit of masked write data among a plurality of bits of masked write data, and (iii) in synchronization with a rising or falling edge of a clock signal received with an address signal corresponding to the masked write command; reading, in response to the internal read command, a plurality of bits of data stored in a plurality of memory cells, the plurality of memory cells corresponding to the address signal; and storing, in response to an internal write command, the plurality of bits of masked write data in the plurality of memory cells. | 10-23-2014 |
20140317471 | SEMICONDUCTOR MEMORY DEVICES INCLUDING SEPARATELY DISPOSED ERROR-CORRECTING CODE (ECC) CIRCUITS - A semiconductor memory device may comprise: at least one bank, each of the at least one bank including a plurality of memory cells; an error-correcting code (ECC) calculator configured to generate syndrome data for detecting an error bit from among parallel data bits read out from the plurality of memory cells of each of the at least one bank; an ECC corrector separated from the ECC calculator, the ECC corrector configured to correct the error bit from among the parallel data bits by using the syndrome data and configured to output error-corrected parallel data bits; and/or a data serializer configured to receive the error-corrected parallel data bits and configured to convert the error-corrected parallel data bits into serial data bits. | 10-23-2014 |
20140325310 | THRESHOLD ADJUSTMENT USING DATA VALUE BALANCING IN ANALOG MEMORY DEVICE - A method, in a memory including multiple analog memory cells, includes segmenting a group of the memory cells into a common section and at least first and second dedicated sections. Each dedicated section corresponds to a read threshold that is used for reading a data page to be stored in the group. Data to be stored in the group is jointly balanced over a union of the common section and the first dedicated section, and over the union of the common section and the second dedicated section, to create a balanced page such that for each respective read threshold an equal number of memory cells will be programmed to assume programming levels that are separated by the read threshold. The balanced page is stored to the common and dedicated sections, and the read thresholds are adjusted based on detecting imbalance between data values in readout results of the balanced page. | 10-30-2014 |
20140325311 | HYBRID ERROR CORRECTION METHOD AND MEMORY REPAIR APPARATUS THEREOF - A hybrid error correction method and a memory repair apparatus thereof are provided for a dynamic random access memory (DRAM). The memory repair apparatus includes a mode register and a hybrid error correction code and redundancy (HEAR) module. When the DRAM enters a standby mode, the mode register switches the DRAM to be controlled by the HEAR module. The HEAR module generates parity data of the error correction code within a default refresh period. The HEAR module extends the refresh period of the DRAM and uses the parity data for error detection to locate a data retention error in the DRAM until the maximum allowable refresh period supported by the HEAR module is reached. Before the DRAM returns to a working mode from a standby mode, the HEAR module performs an error correction process according to fail bit data and writes corrected data into the DRAM. | 10-30-2014 |
20140325312 | METHOD AND SYSTEM FOR SCRUBBING DATA WITHIN A DATA STORAGE SUBSYSTEM - A method and system for scrubbing data within a data storage subsystem is disclosed. According to one embodiment, a method is provided for scrubbing data of a storage element within a data storage subsystem. In the described method embodiment, a request to access the storage element is processed utilizing a first processing module and access permission metadata associated with the storage element. A data scrub process is concurrently performed utilizing a second processing module by modifying the access permission metadata and validating data of the storage element substantially simultaneously with the processing. | 10-30-2014 |
20140325313 | MEMORY PROTECTION CACHE - Accessing data at a memory is described. A request associated with a read or write operation is received, wherein the request includes a logical address associated with the memory. A physical address is generated based at least in part on the logical address. A block of data at the memory that includes data associated with the physical address is determined. Data at the determined block of data and a corresponding set of ECC from the memory are accessed. Whether the accessed data can be decoded based at least in part on the corresponding set of ECC is determined. | 10-30-2014 |
20140325314 | READ BIAS MANAGEMENT TO REDUCE READ ERRORS FOR PHASE CHANGE MEMORY - Subject matter disclosed herein relates to a memory device, and more particularly to read performance of phase change memory. During a reading process, a bias condition can be applied to a memory cell to determine the memory cell's state. The determined state of the memory cell can depend on a threshold voltage of the memory cell. The threshold voltage of the memory cell may shift over time. The shift in threshold voltage may result in read errors. The applied bias condition may be modified based on the resulting read errors. | 10-30-2014 |
20140331105 | SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND - A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device. | 11-06-2014 |
20140337687 | SYSTEM AND METHOD FOR CORRECTING ERRORS IN DATA USING A COMPOUND CODE - Storage of digital data in non-volatile media such as NAND FLASH needs to take account of the errors in data retrieved from the memory. The error rate tends to increase with the number of write/erase cycles of a cell of memory and with the time that the data has been stored. To achieve a very low uncorrected bit error rate (UBER) a substantial amount of redundancy data needs to be stored for error correction purposes. A method and apparatus is disclosed where a first redundancy data is represented by a second redundancy data computed from the first redundancy data. The first redundancy data may not be stored and is reconstructed from the stored data using a same generation procedure as previously used. The reconstructed estimate of the first redundancy data is corrected by the second redundancy data, and is used to correct the underlying data. | 11-13-2014 |
20140337688 | SWITCHABLE ON-DIE MEMORY ERROR CORRECTING ENGINE - Subject matter disclosed herein relates to a user-switchable error correction coding (ECC) engine residing on a memory die. | 11-13-2014 |
20140344646 | DISTRIBUTED REBUILDING OF DATA IN A DISPERSED STORAGE NETWORK - A technique of rebuilding data slices in a dispersed storage network when detecting a plurality of data slices that require rebuilding. A plurality of rebuilding resources capable for use to rebuild the plurality of data slices are determined and based on an attribute associated with the determination, a rebuilding task is apportioned and the apportioned tasks are assigned to the plurality of rebuilding resources to rebuild the data slices. The apportionment of the tasks permit more than one rebuilding resource and associated distributed storage unit to perform the rebuild of the data slices. | 11-20-2014 |
20140351672 | MISCORRECTION DETECTION FOR ERROR CORRECTING CODES USING BIT RELIABILITIES - Miscorrection detection for error correction codes using bit reliabilities is disclosed, including: receiving a plurality of reliabilities corresponding to respective ones of a plurality of read values; receiving one or more proposed corrections corresponding to one or more of the plurality of read values; and determining a miscorrection metric based at least in part on one or more of the plurality of reliabilities corresponding to the one or more of the plurality of read values. | 11-27-2014 |
20140351673 | DRAM METHOD, COMPONENTS, AND SYSTEM CONFIGURATIONS FOR ERROR MANAGEMENT - A memory device is disclosed that includes a row of storage locations to store a data word, and a spare row element. The data word is encoded via an error code for generating error information for correcting X bit errors or detecting Y bit errors, where Y is greater than X. The spare row element has substitute storage locations. The logic is responsive to detected errors to (1) enable correction of a data word based on the error information where there are no more than X bit errors, and (2) substitute the spare row element for a portion of the row where there are at least Y bit errors in the data word. | 11-27-2014 |
20140351674 | UTILIZING CACHED ENCODED DATA SLICES IN A DISPERSED STORAGE NETWORK - A method begins with a processing module of a dispersed storage network (DSN) executing a write operation to write a plurality of sets of encoded data slices to DSN memory, where the write operation includes temporarily storing encoded data slices in cache memory. The processing module receives a read request for a portion of the data object and determines whether a decode threshold number of encoded data slices of a set is stored in the cache memory. When less than the decode threshold number of encoded data slices is stored in the cache memory, the processing module retrieves encoded data slices from the DSN memory to obtain the decode threshold number of encoded data slices, decodes the decode threshold number of encoded data slices to recover a corresponding data segment, and outputs the recovered corresponding data segment. | 11-27-2014 |
20140359396 | ITERATIVE DATA STORAGE READ CHANNEL ARCHITECTURE - In one embodiment, a method for iterative read channel operation includes executing digital front-end (DFE) functions on signal samples employing decisions provided by a detector executing a detection algorithm, executing an error correcting code (ECC) decoding algorithm on the signal samples using a decoder employing the decisions provided by the detector to generate decisions provided by the decoder, storing the signal samples and the decisions provided by the detector and the decoder, and in an iterative process: executing the DFE functions on the signal samples employing the decisions provided by the decoder, executing the detection algorithm on the signal samples using the detector employing the decisions provided by the decoder to regenerate the decisions provided by the detector, executing the decoding algorithm using the decisions provided by the detector to regenerate the decisions provided by the decoder, and outputting decoding information when the decoding algorithm produces a valid codeword. | 12-04-2014 |
20140359397 | MEMORY ACCESS APPARATUS AND METHOD FOR INTERLEAVING AND DEINTERLEAVING - A memory access apparatus and method for interleaving and deinterleaving are disclosed herein. The memory access apparatus includes a memory module unit, a block selection unit, and an address assignment unit. The memory module unit includes a plurality of pieces of memory for storing data interleaved by a first interleaver and a second interleaver using data decoded by a first decoder, and data deinterleaved by a deinterleaver using data decoded by a second decoder. The block selection unit selects any one of a plurality of memory blocks included in any one of the plurality of pieces of memory in response to the reception of an output signal for storing the interleaved or deinterleaved data in the memory module unit. The address assignment unit assigns an address to the output signal. | 12-04-2014 |
20140372830 | APPARATUSES AND METHODS FOR ERROR CORRECTION - This disclosure relates to error correction circuitry. In one aspect, an error correction circuit can serially receive a digit stream and parse the digit stream into substrings of a predetermined length of digits. Each of the substrings can include data digits and parity digits in certain embodiments. As the substring is received, parity can be tracked in defined regions of the substring. When the entire sub string has been received, an error in one of the data digits of the sub string can be corrected based on an indication of parity in at least one defined region in some embodiments. Then corrected data, which can include the corrected data digit and the other data digits of the substring, can be stored. According to certain embodiments, the error correction circuit can be implemented by asynchronous circuitry. | 12-18-2014 |
20140372831 | MEMORY CONTROLLER OPERATING METHOD FOR READ OPERATIONS IN SYSTEM HAVING NONVOLATILE MEMORY DEVICE - A memory controller operating method includes executing a read operation directed to read data including a correctable data unit and an uncorrectable data unit, the uncorrectable data unit containing data that is uncorrectable using a normal error correction operation. The method further including; performing the normal error correction operation on the correctable data unit to generate partial read data, communicating dummy data instead of the uncorrectable data unit along with the partial read data from the memory controller to a host, and performing an enhanced error correction operation on the uncorrectable data unit while at least in part the dummy data and partial data are being communicated from the memory controller to the host. | 12-18-2014 |
20140372832 | ONLINE DATA CONSISTENCY CHECKING IN A NETWORK STORAGE SYSTEM WITH OPTIONAL COMMITTAL OF REMEDIAL CHANGES - A network storage server includes a tool for detecting and fixing errors while the network storage server remains online (available for servicing client requests), which includes enabling a user to approve or disapprove remedial changes before the changes are committed. The technique bypasses the usual consistency point process for new or modified data blocks representing potential remedial changes. At a consistency point, dirty data blocks representing the potential remedial changes are written to a change log file residing outside the volume. The modified data blocks are written in sequential order to logical blocks of the change log file. In response to a user input indicating that a potential change should be committed, the corresponding modified data blocks are read from the change log file in the order in which they were written to the change log file, and they are written to persistent storage in that order. | 12-18-2014 |
20140380122 | METHODS AND APPARATUS FOR OPTIMIZING LIFESPAN OF A STORAGE DEVICE - Systems and methods for optimizing lifespan of a storage device are provided. A request to store data to the storage device is received. The storage device includes a plurality of regions. A determination is made that a first group of regions of the plurality of regions is associated with an error measurement threshold that is lower than a second group of regions of the plurality of regions. A region of the storage device that is in the first group of regions is selected based on the determination. The data is stored to the selected region. | 12-25-2014 |
20140380123 | MEMORY QUALITY MONITOR BASED COMPENSATION METHOD AND APPARATUS - In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected. | 12-25-2014 |
20140380124 | ACQUIRING A TRUSTED SET OF ENCODED DATA SLICES - A method for execution by a computing device, the method begins in response to a data segment access request, generating a set of access requests regarding a set of encoded data slices. The method continues by sending a subset of the access requests to storage units of a dispersed storage network (DSN) and sending an access request of the set of access requests to a trusted storage unit of the DSN. The method continues by receiving a trusted encoded data slice from the trusted storage unit and receiving a subset of encoded data slices from the storage units, wherein the trusted encoded data slice is utilized to authenticate the subset of encoded data slices and when the subset of encoded data slices are authenticated, the trusted encoded data slice and the subset of encoded data slices are decoded to recover the data segment. | 12-25-2014 |
20150012798 | UTILIZING LOCAL MEMORY AND DISPERSED STORAGE MEMORY TO ACCESS ENCODED DATA SLICES - A method begins by a processing module establishing a dispersed storage (DS) error coding function based on a number of local memories associated with the computing device, wherein a decode threshold number of the DS error coding function corresponds to the number of local memories. The method continues with the processing module encoding a data segment of data utilizing the DS error coding function to produce a set of encoded data slices, of which the decode threshold number of encoded data slices is required to recover the data and the set of encoded data slices includes a pillar width number of encoded data slices. The method continues with the processing module storing the decode threshold number of encoded data slices in the local memories and outputting a remaining number of encoded data slices of the set of encoded data slices to the dispersed storage network (DSN) memory for storage therein. | 01-08-2015 |
20150019934 | DATA STORAGE DEVICE, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM INCLUDING THE SAME - A data storage device and a method of operating the same. The method of operating the data storage device may include reading a first data group, detecting errors contained in the first data group and correcting the errors of the first data group, if the errors detected from the first data group can be corrected, and estimating a read retry estimation voltage based on error correction data generated based on the step of correcting the errors of the first data group. | 01-15-2015 |
20150019935 | EARLY DATA DELIVERY PRIOR TO ERROR DETECTION COMPLETION - A computer implemented method for early data delivery prior to error detection completion in a memory system includes receiving a frame of a multi-frame data block at a memory control unit interface. A controller writes the frame to a buffer control block in a memory controller nest domain. The frame is read from the buffer control block by a cache subsystem interface in a system domain prior to completion of error detection of the multi-frame data block. Error detection is performed on the frame by an error detector in the memory controller nest domain. Based on detecting an error in the frame, an intercept signal is sent from the memory controller nest domain to a correction pipeline in the system domain. The intercept signal indicates that error correction is needed prior to writing data in the frame to a cache subsystem. | 01-15-2015 |
20150019936 | ERROR DETECTION METHOD AND A SYSTEM INCLUDING ONE OR MORE MEMORY DEVICE - In accordance with various embodiments, a memory device and method of error detection and correction are disclosed. A memory device may include an input for receiving a command packet including an error detection code to facilitate command error detection. The memory device may include an error manager configured to detect, based on the error detection code, whether an error occurred in transmission of the command packet, a command register configured to store the command packet and configured to provide the command packet to the error manager, and an output to transmit the command packet to a subsequent device of the point-to-point ring topology. | 01-15-2015 |
20150026537 | MEMORY DEVICE WITH OVER-REFRESH AND METHOD THEREOF - A method for over-refreshing a memory device comprises in a refreshing cycle, refreshing normal cells and a weak cell, and additionally refreshing the weak cell at least once. | 01-22-2015 |
20150026538 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM AND STORAGE CONTROL METHOD - An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails. | 01-22-2015 |
20150026539 | UTILIZING A LOCAL AREA NETWORK MEMORY AND A DISPERSED STORAGE NETWORK MEMORY TO ACCESS DATA - A method begins by a processing module encoding data based on a decode threshold parameter and a pillar width parameter to produce a set of encoded data slices and selecting a local area network (LAN) pillar width value of encoded data slices of the set of encoded data slices for storage in LAN available memories, wherein the LAN pillar width value is based on the decode threshold parameter, the pillar width parameter, and quantities of the LAN available memories. The method continues with the processing module selecting a wide area network (WAN) pillar width value of encoded data slices of the set of encode data slices for storage in a dispersed storage network (DSN) memory of a wide area network, wherein the WAN pillar width value is based on the decode threshold parameter and the pillar width parameter. | 01-22-2015 |
20150039967 | MEMORY DEVICE HAVING ADJUSTABLE REFRESH PERIOD AND METHOD OF OPERATING THE SAME - A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory cells includes a first row and one or more second rows. The refresh period determination unit is configured to set a refresh period according to read data from the first row. A refresh control unit is configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval. | 02-05-2015 |
20150046770 | SENSING PARAMETER MANAGEMENT IN NON-VOLATILE MEMORY STORAGE SYSTEM TO COMPENSATE FOR BROKEN WORD LINES - Disclosed is a technology to change the parameters by which a read operation is performed in a block with a broken word line. The first method is for reading a broken word line, which may involve changing the voltage on word lines neighboring the broken word line to let the voltage on the broken word line reach the appropriate magnitude through capacitive coupling between word lines. The first method may also involve increasing the time delay before memory cells connected to the broken word line are sensed to allow the voltage on the word line to settle due to increased RC delay. The second method is for reading an unbroken word line in a block with a broken word line, which involves increasing the time delay before memory cells connected to the unbroken word line are sensed while raising the voltages on the word lines neighboring the broken word line. | 02-12-2015 |
20150046771 | OPERATING METHOD OF ERROR CORRECTION CODE DECODER AND MEMORY CONTROLLER INCLUDING THE ERROR CORRECTION CODE DECODER - An operating method of an ECC decoder includes receiving first chunk data and second chunk data from a nonvolatile memory device, the second chunk data subsequent to the first chunk data, performing error correction on the first chunk data, determining if the first chunk data includes an uncorrectable error bit and determining not to perform error correction on the second chunk data in response to the first chunk data including the uncorrectable error bit. | 02-12-2015 |
20150052414 | NON-VOLATILE SEMICONDUCTOR STORAGE APPARATUS - According to one embodiment, a non-volatile semiconductor storage apparatus is configured to decide determination periods respectively corresponding to each of management blocks based on rewrite count information items and a temperature, and to perform a determination processing for each of management blocks for each determination period. The determination processing includes determining whether first data read from a block in the blocks is normal based on the number of errors that are occurred in the first data. The apparatus is configured to perform a rewrite processing of rewriting the first data to second data which is error-corrected when it is determined that the first data is not normal. | 02-19-2015 |
20150067442 | INFORMATION PROCESSING APPARATUS AND DATA REPAIRING METHOD - A processor executes a procedure including performing a repair process including first detecting whether there is any abnormality in data read out from a first storage, repairing abnormal data that is the data in which abnormality is detected as a result of the first detection, and storing the repaired data in a second storage area, second detecting when an address of data changed in the repair process and an address of a read-out source of the abnormal data in the first storage area match, whether there is any abnormality in data read out from an area indicated by the address of data changed in the repair process and the address of the read-out source of the abnormal data in the first storage area, repairing and storing, in the second storage area, the data in which abnormality is found as a result of the second detection. | 03-05-2015 |
20150067443 | Method and Device for Recovering Erroneous Data - A method for recovering erroneous data is disclosed, the method includes: when data in a storage block that is included in a solid state disk (SSD) is read, performing a first error check on data on a certain page of the storage block to acquire erroneous data on the page; if a first number of pieces of the erroneous data on the page is smaller than or equal to a preset first threshold, performing an error checking and correction (ECC) recovery on the data on the page; and if the first number is greater than the preset first threshold, acquiring data from spare space according to a storage position of the erroneous data on the page and a fixed entry corresponding to the storage block, and replacing the erroneous data on the page with the acquired data, where the fixed entry includes a storage position of each data stored in the spare space. | 03-05-2015 |
20150074490 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, a nonvolatile semiconductor memory device includes a nonvolatile memory, an ECC decoder, and a write controller. The nonvolatile memory includes a memory cell array and a buffer. The buffer is capable of storing page data read from the memory cell array and generating degeneration data by performing an exclusive OR operation on page data read from the memory cell array. The ECC decoder is capable of performing ECC decode on the degeneration data input from the nonvolatile memory and determining whether the degeneration data passes ECC decode or not. The write controller is capable of causing the nonvolatile memory to rewrite the plurality of page data when the degeneration data does not pass ECC decode. | 03-12-2015 |
20150074491 | MAGNETIC RANDOM ACCESS MEMORY - According to one embodiment, a magnetic random access memory includes memory cells, a read circuit, (ECC) circuit, an address register, a flag register, a flag check circuit, and a write back circuit. The memory cells each include a magnetoresistive element. The address register stores the address at which the error has been detected by the ECC circuit. The data register stores corrected data in which the error has been corrected by the ECC circuit. The flag register sets an error flag in association with the address at which the error has been detected by the ECC circuit. The flag check circuit checks whether the error flag is set in the flag register. The write back circuit writes back the data to the memory cell designated by the address corresponding to the error flag. | 03-12-2015 |
20150074492 | MEMORY SYSTEM AND MEMORY CONTROLLER - According to one embodiment, a memory system includes nonvolatile memory, and a memory controller. The nonvolatile memory includes a plurality of blocks, each including a plurality of pages. The memory controller controls the nonvolatile memory. Here, the memory controller detects a first page of which a required minimum shift amount of a read voltage is largest for each block by reading data stored respectively in the plurality of pages while performing error detection. Further, the memory controller detects a second page of which the required minimum shift amount of a read voltage is larger than a predetermined first threshold by reading data stored in the first page of each of the blocks while shifting the read voltage in a first range, and performing error detection. Further, the memory controller refreshes data stored in the block having the second page. | 03-12-2015 |
20150074493 | SEMICONDUCTOR DEVICE AND ERROR CORRECTION METHOD - A device is provided with: memory cell array including plurality of first and second memory cells and one or more third memory cells; judging circuit that judges plurality of data values held by selected first and second memory cells of the first and second memory cells, by referring to reference potential corresponding to reference data held by a selected third memory cell; and error detection and correction circuit that detects whether or not there is error in the judged data values of the first and/or second memory cells, with judged data value of the first and second memory cells as error correcting code. When the error detection and correction circuit detects that there is error exceeding error correction capability in the judged data values, control is performed to write reference data to the selected third memory cell. | 03-12-2015 |
20150082120 | Selective In-Situ Retouching of Data in Nonvolatile Memory - In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge. | 03-19-2015 |
20150082121 | METHOD OF ERASE STATE HANDLING IN FLASH CHANNEL TRACKING - An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters. | 03-19-2015 |
20150082122 | LOCAL ERROR DETECTION AND GLOBAL ERROR CORRECTION - A system may use local error detection (LED) and global error correction (GEC) information to check data fidelity and correct an error. The LED may be calculated per cache line segment of data associated with a rank of a memory. Data fidelity may be checked in response to a memory read operation, based on the LED information, to identify a presence of an error and the location of the error among cache line segments of the rank. The cache line segment having the error may be corrected based on the GEC, in response to identifying the error. | 03-19-2015 |
20150089323 | ERROR RECOVERY USING ERASURES FOR NAND FLASH - Error correction decoding is performed on a codeword where the codeword is unable to be successfully decoded. One or more bits in the codeword are selected to be replaced with an erasure. The selected bits in the codeword is/are replaced with an erasure to obtain a codeword with one or more erasures. Error correction decoding is performed on the codeword with one or more erasures. | 03-26-2015 |
20150095740 | Error Detection and Correction in Binary Content Addressable Memory (BCAM) - A binary content addressable memory (BCAM) is disclosed. The BCAM includes a memory array, data signature circuitry, and a data match module and compare circuitry. The memory array is configured to store a data entry for a data word and a corresponding data signature for the data entry. The data signature circuitry is configured to calculate the data signature for the data entry and to calculate the data signature for an input word. The data match module compares the data entry to the input word to produce a content match output, and compares the data signature for the data entry to the data signature of the input word to produce a signature match output. The compare circuitry compares the content match output and the data signature match output. | 04-02-2015 |
20150100847 | RECOVERY FROM PROGRAMMING FAILURE IN NON-VOLATILE MEMORY - A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed. | 04-09-2015 |
20150100848 | DETECTING AND CORRECTING HARD ERRORS IN A MEMORY ARRAY - Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array. | 04-09-2015 |
20150100849 | MEMORY SYSTEM AND OPERATING METHOD THEREOF - A memory system and an operating method thereof are provided. The memory system includes a semiconductor memory device configured to perform a read operation and a controller configured to control the read operation of the semiconductor memory device, and the controller, by determining programmed states of memory cells located nearby selected memory cells, divides the selected memory cells into a plurality of groups depending on an amount of interference, and corrects data of one of the groups having a great amount of interference. | 04-09-2015 |
20150113354 | GENERATING SOFT DECODING INFORMATION FOR FLASH MEMORY ERROR CORRECTION USING HARD DECISION PATTERNS - A flash memory controller having soft-decoding error correcting code (ECC) logic generates log likelihood ratio or similar ECC decoder soft input information from decision patterns obtained from reading data from the same portion of flash memory two or more times. Each decision pattern corresponds to a voltage region bordering one of the reference voltages. Each decision pattern represents a combination of flash memory bit value decisions for a cell voltage within the voltage region corresponding to the decision pattern when a corresponding combination of the reference voltages are used to read the cell. Numerical values are then computed in response to combinations of the flash memory bit value decisions represented by the decision patterns. The numerical values are provided to the soft-decoding ECC logic to serve as soft input information. | 04-23-2015 |
20150113355 | DATA STORAGE DEVICE - A data storage device includes a nonvolatile memory device, an error correction code unit suitable for detecting and correcting a data error read from the nonvolatile memory device in response to an operation clock, and a clock unit suitable for selectively providing the operation clock to the error correction code unit depending on whether the data is read from the nonvolatile memory device or not. | 04-23-2015 |
20150113356 | SYSTEM-IN-PACKAGE MODULE WITH MEMORY - A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate. | 04-23-2015 |
20150121166 | ECC BYPASS USING LOW LATENCY CE CORRECTION WITH RETRY SELECT SIGNAL - A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit. | 04-30-2015 |
20150121167 | ECC BYPASS USING LOW LATENCY CE CORRECTION WITH RETRY SELECT SIGNAL - A memory controller is equipped with multiple error correction circuits for different complexity levels of errors, but requested data is initially sent to a requesting unit (e.g., processor) via a bypass path which provides the lowest memory latency. The requesting unit performs error detection and, if an error is found, sends a retry select signal to the memory controller. The retry select signal provides an indication of which error correction unit should be used to provide complete correction of the error but add the minimum latency necessary. On the retry transmission, the controller uses the particular error correction unit indicated by the retry select signal. The memory controller can also have a persistent error detection circuit which identifies an address as being defective when an error is repeatedly indicated by multiple retry select signals, and the control logic can automatically transmits the requested data using the appropriate error correction unit. | 04-30-2015 |
20150121168 | MEMORY SYSTEM INCLUDING RANDOMIZER AND DE-RANDOMIZER - A memory system according to an embodiment of the present invention may include a semiconductor memory device including a plurality of memory areas, and a controller suitable for writing data to the semiconductor memory device and reading data from the semiconductor memory device. The controller provides a combined seed, which is used to copy data in a first memory area to a second memory area, to the semiconductor memory device, the combined seed being obtained by performing an operation on a de-randomizing seed corresponding to the first memory area and a randomizing seed corresponding to the second memory area. | 04-30-2015 |
20150135034 | FLASH MEMORY CONTROL METHOD, CONTROLLER AND ELECTRONIC APPARATUS - A memory control method is used for controlling a flash memory. The flash memory includes a first memory element and a second memory element. The second memory element includes multiple blocks and each block includes multiple pages. In this method, original data are written to the first memory element. Input data are obtained by reading the original data from the first memory element. The input data includes multiple input data rows. The input data rows are divided into data groups. Each input data row corresponding to each data row is written to a corresponding data page on the second memory element. A parity row corresponding to each data group is written to a data page on the second memory element. The number of data rows for each data group is smaller than the number of each block in the second memory element. | 05-14-2015 |
20150135035 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code. | 05-14-2015 |
20150149863 | SEMICONDUCTOR STORAGE DEVICE, METHOD FOR CONTROLLING THE SAME AND CONTROL PROGRAM - According to one embodiment, a semiconductor memory stores a program for causing a memory controller to operate in at least one of first and second modes. In the first mode, for each of the blocks, the memory controller autonomously erases and writes data and reads the written data, and determines that the block or the semiconductor storage device is defective when a count of errors in the read data exceeds a correction capability or a threshold. In the second mode, when error correction of read substantial data fails, the memory controller reads the substantial data which failed in the error correction using a read level shifted from the present read level. | 05-28-2015 |
20150293812 | ERROR-CORRECTION CODING FOR HOT-SWAPPING SEMICONDUCTOR DEVICES - A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation. | 10-15-2015 |
20150293813 | DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT - A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit. | 10-15-2015 |
20150301755 | PROTECTION SCHEME WITH DUAL PROGRAMMING OF A MEMORY SYSTEM - A memory system or flash memory device may include a linking or grouping of blocks that are used for dual writing. In particular, meta-blocks in the memory may be linked in such a way that enables a data transfer to simultaneously occur in two meta-blocks. The dual versions of the programming may be used for error correction. If there is a failure or write error in one of the meta-blocks, then the data from the other meta-block may be used. If there is no failure then the secondary meta-block may be erased. | 10-22-2015 |
20150301887 | HIGH-SPEED MULTI-BLOCK-ROW LAYERED DECODER FOR LOW DENSITY PARITY CHECK (LDPC) CODES - High-speed multi-block-row layered decoding for low density parity check (LDPC) codes is disclosed. In a particular embodiment, a method, in a device that includes a decoder configured to perform an iterative decoding operation, includes processing, at the decoder, first and second block rows of a layer of a parity check matrix simultaneously to generate a first output and a second output. The method includes performing processing of the first output and the second output to generate a first result of a first computation and a second result of a second computation. A length of a “critical path” of the decoder is reduced as compared to a critical path length in which a common feedback message is computed. | 10-22-2015 |
20150301888 | METHOD, MEMORY CONTROLLER, AND MEMORY SYSTEM FOR READING DATA STORED IN FLASH MEMORY - An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination. | 10-22-2015 |
20150301890 | APPARATUS FOR ERROR DETECTION IN MEMORY DEVICES - The invention relates to an apparatus for transfer of data elements between a bus controller, such as a CPU, and a memory controller. An address translator is arranged to receive a write address from the CPU, to modify the write address and to send the modified write address to the memory controller. An ECC calculator is arranged to receive write input data associated with the write address, from the CPU, and to generate an error correction code on the basis of the write input data. A concatenator is arranged to receive the write input data from the CPU, and to receive the error correction code from the ECC calculator, and to concatenate the write input data and the error correction code to obtain write output data, and to send the write output data to the memory controller. | 10-22-2015 |
20150301891 | Data Recovery Method and Device - Technologies are described herein for recovering data in a storage device comprising a controller and a plurality of storage units. The controller receives a data stream, and divides the data stream into plurality of data blocks, obtains a code blocks using the plurality of data blocks. When there is one or more blocks with damaged data in the plurality of data blocks and the code block, the controller obtains a sub-block from the Mth bit to the Nth bit of each block in the plurality of data blocks and the code block as a set, and reconstructs data in one or more sub-blocks with damaged data using other sub-blocks with undamaged data in the set. | 10-22-2015 |
20150301892 | MEMORY SYSTEM - A memory system comprises an encoding processing circuit | 10-22-2015 |
20150302924 | REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES - Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level. | 10-22-2015 |
20150302928 | MEMORY SYSTEM AND READ RECLAIM METHOD THEREOF - A memory system includes a nonvolatile memory device including a first memory area formed of memory blocks which store n-bit data per cell and a second memory area formed of memory blocks which store m-bit data per cell, where n and m are different integers, and a memory controller configured to control the nonvolatile memory device. The memory controller is configured to execute a read operation, and to execute a read reclaim operation in which valid data of a target memory block of the second memory area is transferred to one or more memory blocks of the first memory area, the target memory block selected during the read operation. The read reclaim operation is processed as complete when all the valid data of the target memory block is transferred to the one or more memory blocks of the first memory area. | 10-22-2015 |
20150303948 | DATA DECODING METHOD OF NON-VOLATILE MEMORY DEVICE AND APPARATUS FOR PERFORMING THE METHOD - A method of decoding data of a non-volatile memory device is provided. The method includes a first decoding operation of reading first hard decision data from the non-volatile memory device using a first hard decision read level and performing decoding using the first hard decision data; a second decoding operation of reading first soft decision data from the non-volatile memory device when the decoding fails in the first decoding operation, and performing decoding using the first soft decision; and a third decoding operation of changing from the first hard decision read level to a second hard decision read level when the decoding fails in the second decoding operation, reading second hard decision data using the second hard decision read level, and performing decoding either using the second hard decision data or using both the second hard decision data and the first soft decision data. | 10-22-2015 |
20150303949 | [01] COST-EFFICIENT REPAIR FOR STORAGE SYSTEMS USING PROGRESSIVE ENGAGEMENT - An apparatus or method for minimizing the total accessing cost, such as minimizing repair bandwidth, delay or the number of hops including the steps of minimizing the number of nodes to be engaged for the recovery process using a polynomial-time solution that determines the optimal number of participating nodes and the optimal set of nodes to be engaged for recovering lost data, where in a distributed database storage system, for example a dynamic system, where the accessing cost or even the number of available nodes are subject to change results in different values for the optimal number of participating nodes. An MDS code is included which can be reused when the number of participating nodes varies without having to change the entire code structure and the content of the nodes. | 10-22-2015 |
20150309744 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD FOR SAME - A semiconductor storage device includes at least one memory from among a primary memory, a minor memory storing data corresponding to data stored in the primary memory, and a buffer memory; and a controller that controls the at least one memory so as to store data in the at least one memory and read data from the at least one memory. | 10-29-2015 |
20150309864 | DATA STORAGE DEVICE AND METHOD FOR OPERATING THE SAME - A method for operating a data storage device that includes reading data and storage parity data, generating transformation parity data through a masking operation on the storage parity data, and performing an error correcting operation on the data, based on the transformation parity data. | 10-29-2015 |
20150309869 | ERROR-CORRECTION ENCODING AND DECODING - A data encoding method includes storing K input data symbols; assigning the symbols to respective symbol locations in a notional square array, having n rows and n columns of locations, to define a plurality of k-symbol words in respective rows; encoding the words by encoding rows and columns of the array dependent on a product code having identical row and column codes, each being a reversible error-correction code of dimension k and length n=2n′, thereby to define a codeword, having n | 10-29-2015 |
20150309872 | DATA RECOVERY ONCE ECC FAILS TO CORRECT THE DATA - An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules each having a size less than a total size of the memory. The controller is configured to salvage data stored in a failed page of the memory determined to exceed a maximum number of errors. The controller copies raw data stored in the failed page. The controller identifies locations of a first type of data cells that fail erase identification. The controller identifies locations of a second type of data cells that have program errors. The controller flips data values in the raw data at the locations of the first type of data cells and the locations of the second type of data cells. The controller is configured to perform error correcting code decoding on the raw data having flipped data values. The controller salvages data stored in the failed page. | 10-29-2015 |
20150310911 | DETERMINING WHETHER A MEMORY CELL STATE IS IN A VALLEY BETWEEN ADJACENT DATA STATES - The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley. | 10-29-2015 |
20150311920 | DECODER FOR A MEMORY DEVICE, MEMORY DEVICE AND METHOD OF DECODING A MEMORY DEVICE - According to embodiments of the present invention, a decoder for a memory device is provided. The decoder includes an error detection circuitry configured to multiply a vector of one or more data words with a parity matrix to determine a plurality of syndrome values and generate a plurality of coefficients from multiplying a syndrome vector with an inverse of a syndrome matrix; and an error correction circuitry configured to perform a Chien search on a first part of the plurality of coefficients to determine error indicators indicating error locations in a first part of the one or more data words, and subsequently on a second part of the plurality of coefficients to determine error indicators indicating error locations in a second part of the one or more data words. According to further embodiments of the present invention, a memory device and method of decoding a memory device are also provided. | 10-29-2015 |
20150317204 | Systems and Methods for Efficient Data Refresh in a Storage Device - Systems and method relating generally to data storage processing, and more particularly to systems and methods for refreshing data in a data storage device. | 11-05-2015 |
20150318033 | MEMORY DEVICES HAVING A READ FUNCTION OF DATA STORED IN A PLURALITY OF REFERENCE CELLS - A semiconductor device is provided with normal memory cells constituted so as to store user data, reference memory cells constituted so as to generate a reference signal for reading out the normal memory cells, and a control circuit that carries out a defect detecting operation for detecting whether or not the reference memory cell and data stored in the reference memory cell are coincident with expected values on the stored data read out from the reference memory cells. Moreover, it is also provided with a control circuit for executing a defect correcting operation for correcting data to be stored in the reference memory cells that are detected as defective. Furthermore, it is also provided with a control circuit that is configured so as to cut off the reference memory cell detected as defective from the sense amplifier. | 11-05-2015 |
20150324141 | DATA PROTECTION SYSTEM - Systems and methods for logically organizing data for storage and recovery on a data storage medium using a multi-level format are described. Embodiments include systems and methods for protecting data stored on a data storage medium so that the data may be recovered without errors. | 11-12-2015 |
20150324283 | FLASH MEMORY CONTROL CHIP AND DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD - A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table. | 11-12-2015 |
20150331742 | DATA MANAGING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS - A data managing method, and a memory control circuit unit and a memory storage apparatus using the same are provided. The data managing method including: reading a first data stream from a first physical erasing unit according to a first reading command, wherein the first data stream includes first user data, a first error correcting code and a first error detecting code. The method also includes: using the first error correcting code and error detecting code to decode the first user data and determining whether the first user data is decoded successfully. The method further includes: if the first user data is decoded successfully, transmitting corrected user data obtained by correctly decoding the first user data to the host system in response to the first reading command. | 11-19-2015 |
20150331744 | DATA DEVICE GROUPING ACROSS MULTIPLE-DATA-STORAGE-DEVICES ENCLOSURES FOR DATA RECONSTRUCTION - In at least one embodiment, a method of operating a storage front-end system is disclosed. The method includes: receiving a read request with an object identifier for a data object; identifying a synchronous group of data storage devices across two or more multiple-data-storage-devices enclosures, wherein the synchronous group is associated with the object identifier; sending a request to the two or more multiple-data-storage-devices enclosures to immediately activate the data storage devices in the synchronous group; retrieving at least a subset of data fragments associated with the object identifier from at least one of the data storage devices; and erasure decoding at least the subset of the data fragments into a contiguous data range to reconstruct the data object | 11-19-2015 |
20150331745 | DRAM ERROR CORRECTION EVENT NOTIFICATION - A method in a memory device implementing error correction includes setting an error correction event register to a first value; assessing a memory location in the first memory array in response to a memory address; retrieving stored memory data from the assessed memory location in the first memory array and retrieving error correction check bits corresponding to the assessed memory location from the second memory array; checking the retrieved memory data for bit errors using the retrieved check bits; in response to a bit error being detected in the retrieved memory data, generating corrected memory data using the retrieved check bits and asserting an error correction event signal; and in response to the error correction event signal being asserted, setting the error correction event register to a second value. | 11-19-2015 |
20150331746 | STORAGE ELEMENT POLYMORPHISM TO REDUCE PERFORMANCE DEGRADATION DURING ERROR RECOVERY - A data storage system includes a plurality of storage devices forming a storage array for storing data and associated error correction codes and a controller coupled to the plurality of storage devices. The controller is configured to, responsive to an error in a data element among the data, rebuild the data element from other data elements and an error correction code in the storage array and overwrite the error correction code with the rebuilt data element. | 11-19-2015 |
20150331748 | METHOD TO DYNAMICALLY UPDATE LLRs IN AN SSD DRIVE AND/OR CONTROLLER - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform a first error correction code decoding on the memory units using a plurality of initial log likelihood ratio values. The controller may be configured to count a number of unsatisfied checks if the first error correction code decoding fails. The controller may be configured to generate a plurality of measured log likelihood ratio values if the number of unsatisfied checks is below a threshold. The plurality of measured log likelihood ratio values are (a) based on calculations using decoded bits of the first error correction code decoding, and (b) used to perform a second error correction code decoding on the memory units. | 11-19-2015 |
20150331749 | STORAGE ELEMENT POLYMORPHISM TO REDUCE PERFORMANCE DEGRADATION DURING ERROR RECOVERY - A data storage system includes a plurality of storage devices forming a storage array for storing data and associated error correction codes and a controller coupled to the plurality of storage devices. The controller is configured to, responsive to an error in a data element among the data, rebuild the data element from other data elements and an error correction code in the storage array and overwrite the error correction code with the rebuilt data element. | 11-19-2015 |
20150332777 | STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF - A read method of a nonvolatile memory device includes reading data from a selected memory area of the nonvolatile memory device according to a first read voltage; detecting and correcting an error of the read data; and deciding a second read voltage for reading the selected memory area when an error of the read data is uncorrectable. The second read voltage is decided according to either the number of logical 0s or 1s included in the read data, or a ratio of logical 1s to logical 0s in the read data. | 11-19-2015 |
20150333773 | SYSTEMS AND METHODS FOR ADAPTIVE ERROR-CORRECTION CODING - A storage module is configured to store data segments, such as error-correcting code (ECC) codewords, within an array comprising a plurality of columns. The ECC codewords may comprise ECC codeword symbols. The ECC symbols of a data segment may be arranged in a horizontal arrangement, a vertical arrangement, a hybrid channel arrangement, and/or vertical stripe arrangement within the array. The individual ECC symbols may be stored within respective columns of the array (e.g., may not cross column boundaries). Data of an unavailable ECC symbol may be reconstructed by use of other ECC symbols stored on other columns of the array. | 11-19-2015 |
20150333774 | STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION - The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer. | 11-19-2015 |
20150339189 | FIXED POINT CONVERSION OF LLR VALUES BASED ON CORRELATION - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory comprises a plurality of memory units each having a size less than a total size of the memory. The controller may be configured to perform error correction code decoding on the memory units. The controller may be configured to generate a plurality of original log likelihood ratios each comprising a real value. The controller may be configured to convert each of the original log likelihood ratios to a converted log likelihood ratio comprising a fixed point value. The conversion comprises (a) scaling down a magnitude of each of the original log likelihood ratios, and (b) rounding each of the original log likelihood ratios having a scaled down magnitude to the fixed point value. | 11-26-2015 |
20150347227 | Marker Programming in Non-Volatile Memories - A method for accessing a non-volatile memory is presented. The method comprises reading a first memory region of the non-volatile memory and ascertaining whether the first memory region contains a predetermined data pattern. The predetermined data pattern has no influence on resulting error correcting data determined for at least the first memory region. The method also comprises evaluating a data status for a second memory region of the non-volatile memory on the basis of a presence of the predetermined data pattern in the first memory region. A corresponding memory controller is also disclosed. | 12-03-2015 |
20150347229 | Method and System for Dynamic Word Line Based Configuration of a Three-Dimensional Memory Device - A memory controller configures a plurality of word lines associated with a respective block of a 3D memory device in a first configuration, where the first configuration includes a set of configuration parameters for each word line of the plurality of word lines determined at least in part on the vertical positions of each word line relative to a substrate of the 3D memory device and, while the plurality of word lines are configured in the first configuration, writes data to and reads data from the respective block. For the respective block, the memory controller: adjusts a first parameter in the respective set of configuration parameters corresponding to a respective word line of the plurality of word lines in response to detecting a first trigger condition as to the respective word line and, after adjusting the first parameter, writes data to and reads data from the respective word line. | 12-03-2015 |
20150347230 | HIGH-PERFORMANCE ECC DECODER - Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence. | 12-03-2015 |
20150347231 | TECHNIQUES TO EFFICIENTLY COMPUTE ERASURE CODES HAVING POSITIVE AND NEGATIVE COEFFICIENT EXPONENTS TO PERMIT DATA RECOVERY FROM MORE THAN TWO FAILED STORAGE UNITS - Erasure code syndrome computation based on Reed Solomon (RS) operations in a Galois field to permit reconstruction of data of more than 2 failed storage units. Syndrome computation may be performed with coefficient exponents that consist of −1, 0, and 1. A product xD of a syndrome is computed as a left-shift of data byte D, and selective compensation based on the most significant bit of D. A product x | 12-03-2015 |
20150348619 | DETERMINING SOFT DATA - The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell. | 12-03-2015 |
20150355858 | RECOVERY FROM PROGRAMMING FAILURE IN NON-VOLATILE MEMORY - A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed. | 12-10-2015 |
20150355964 | CONTROLLER DEVICE FOR USE WITH ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY CHIP WITH ERROR DETECTION AND RETRY MODES OF OPERATION - A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. | 12-10-2015 |
20150355967 | METHOD OF READING AND WRITING TO A SPIN TORQUEMAGNETIC RANDOM ACCESS MEMORY WITH ERROR CORRECTING CODE - A method includes destructively reading bits of a spin torque magnetic random access memory, using error correcting code (ECC) for error correction, and storing inverted or non-inverted data in data-store latches. When a subsequent write operation changes the state of data-store latches, parity calculation and majority detection of the bits are initiated. A majority bit detection and potential inversion of write data minimizes the number of write current pulses. A subsequent write operation received within a specified time or before an original write operation is commenced will cause the majority detection operation to abort. | 12-10-2015 |
20150363265 | METHOD FOR CONTROLLING MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS AND CONTROLLER THEREOF - A method for controlling a memory apparatus and the associated memory apparatus thereof and the associated controller thereof are provided, where the method includes: reading encoded data of a second set of error correction configuring parameters from a system block, and utilizing an LDPC engine to decode the encoded data to obtain the second set of error correction configuring parameters, where the LDPC engine stores a first set of error correction configuring parameters, and during decoding the encoded data, the LDPC engine performs decoding corresponding to a first LDPC characteristic matrix based on the first set of error correction configuring parameters; and controlling the LDPC engine to perform operations corresponding to a second LDPC characteristic matrix based on the second set of error correction configuring parameters in RAM, in order to make the LDPC engine be equipped with new encoding and decoding capabilities corresponding to the second LDPC characteristic matrix. | 12-17-2015 |
20150364199 | MEMORY SYSTEM HAVING OVERWRITE OPERATION CONTROL METHOD THEREOF - The memory system has an overwrite operation and an operation control method thereof. A nonvolatile memory device has a plurality of memory blocks including a plurality of memory cells stacked in a direction perpendicular to a substrate. When data of memory cells connected to a word line of a selected memory block is read, the need of reclaim is determined based on an error bit level of the read data. In the case that memory cells having an erase state among the memory cells connected to the word line become a soft program state, the read data is overwritten in the memory cells connected to the word line of the selected memory block. | 12-17-2015 |
20150370636 | CONSECUTIVE BIT ERROR DETECTION AND CORRECTION - Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome. | 12-24-2015 |
20150371676 | RECONSTRUCTIVE ERROR RECOVERY PROCEDURE (ERP) USING RESERVED BUFFER - In one embodiment, a tape drive includes a reserved data buffer and logic integrated with and/or executable by a processor. The logic is configured to read a data set from a medium and store a first portion of the data set to the reserved data buffer in response to a determination that the first portion of the data set is correctable using C2 error correction code (ECC). The logic is also configured to replace any stored row of a non-C2-correctable portion of the data set stored to the reserved data buffer with a corresponding row of the data set read from the medium in response to a determination that the stored row of the non-C2-correctable portion of the data set has an equal amount or more C1-correctable error therein than the corresponding row of the data set read from the medium. | 12-24-2015 |
20150378815 | NAND PRE-READ ERROR RECOVERY - Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method may include applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method may further include determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page. | 12-31-2015 |
20150378817 | Memory System With Error Detection And Retry Modes Of Operation - A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. | 12-31-2015 |
20150378818 | Memory Chip With Error Detection And Retry Modes Of Operation - A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. | 12-31-2015 |
20150378821 | EXTENDED LIFETIME MEMORY - A memory controller can include an error correction module for extended lifetime memory that tracks at least one sized block of non-fault consecutive bits within the disabled page as spare blocks and reuses the spare blocks from the disabled pages as an error correction resource for active blocks. The active blocks can store data, data and metadata, or metadata only (e.g., error correction metadata). A method for extended lifetime memory can include, for an active block of metadata containing at least one fault, using at least one spare block to correct the data of the active block. For an active block of data containing at least one fault, the data can be initially corrected via XOR correction with a first spare block and then ultimately corrected via XOR correction with a second spare block. | 12-31-2015 |
20150378823 | MEMORY DEVICE HAVING ERROR CORRECTION LOGIC - Data is read from memory cells in the memory device. The read data is transferred over a link to a memory controller that is external of the memory device. While the transferring of the read data is ongoing, error detection of the read data is performed inside the memory device using an error correction code. | 12-31-2015 |
20160004437 | STORAGE DEVICE AND READ METHODS THEREOF - A read method of a storage device includes performing a first read operation on a nonvolatile memory device based on a time stamp table storing a program time and a time-read level look-up table indicating a read level shift due to a program lapsed time. A determination is made whether to adjust the time-read level look-up table based on a result of the first read operation. As a consequence of determining to adjust the time-read level look-up table, adjusting the time-read level look-up table through a valley search operation and performing a second read operation on the nonvolatile memory device based on the time stamp table and the adjusted time-read level look-up table. | 01-07-2016 |
20160004595 | SHIFTING READ DATA - This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error. | 01-07-2016 |
20160004597 | Memory Controller With Error Detection And Retry Modes Of Operation - A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data. | 01-07-2016 |
20160005452 | SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING HAVING DIFFERENT REFRESH OPERATION PERIODS FOR DIFFERENT SETS OF MEMORY CELLS - Provided is a semiconductor memory device for controlling a refresh operation of redundancy memory cells. The semiconductor memory device may include normal memory cells and redundancy memory cells that are used to repair normal memory cell(s) to which a defective cell is connected, and an error-correction code (ECC) memory cell row that stores parity bits for controlling the defective cell. Memory cells on the normal memory cell rows are refreshed during a first refresh cycle. Other memory cells on, such as redundancy memory cell rows, an edge memory cell row that is adjacent to the redundancy memory cell row(s) from among the normal memory cell rows, and/or the ECC memory cell row may be refreshed during a second refresh cycle that is different from the first refresh cycle. | 01-07-2016 |
20160006459 | LOW BER HARD-DECISION LDPC DECODER - A non-volatile memory controller includes a hard-decision Low Density Parity Check (LDPC) decoder with a capability to dynamically select a voting method to improve the decoding in low bit error rate (BER) situations. The hard-decision LDPC decoder dynamically selects a voting method associated with a strength requirement for bit flipping decisions. In one implementation, the voting method is selected based on the degree of a variable node and previous syndrome values. | 01-07-2016 |
20160006462 | NON-VOLATILE MEMORY CONTROLLER WITH ERROR CORRECTION (ECC) TUNING VIA ERROR STATISTICS COLLECTION - A non-volatile memory controller for a solid state drive includes a soft-decision LDPC decoder. The soft-decision LDPC decoder includes a probability generation module. A processor reads collected statistics collated from decoded frames and tunes the performance of the soft-decision LDPC decoder performance. Additional parameters may also be taken into account, such as the scramble seed and the type of non-volatile memory. An asymmetry in errors may also be detected and provided to a hard-decision LDPC decoder to adjust its performance. | 01-07-2016 |
20160011934 | DECODING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE | 01-14-2016 |
20160011937 | SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND CONTROL METHOD OF MEMORY CONTROLLER | 01-14-2016 |
20160011939 | SYSTEMS AND METHODS FOR RELIABLY STORING DATA USING LIQUID DISTRIBUTED STORAGE | 01-14-2016 |
20160011940 | TIERED ECC SINGLE-CHIP AND DOUBLE-CHIP CHIPKILL SCHEME | 01-14-2016 |
20160011947 | RESISTANCE CHANGE MEMORY DEVICE | 01-14-2016 |
20160019113 | MEMORY SYSTEM - A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page. | 01-21-2016 |
20160019114 | METHODS AND SYSTEMS FOR STORING DATA IN A REDUNDANT MANNER ON A PLURALITY OF STORAGE UNITS OF A STORAGE SYSTEM - Described herein are techniques for storing data in a redundant manner on a plurality of storage units of a storage system. While all of the storage units are operating without failure, only error-correction blocks are stored on a first one of the storage units, while a combination of data blocks and error-correction blocks are stored on a second one of the storage units. Upon failure of the second storage unit, one or more data blocks and one or more error-correction blocks formerly stored on the second storage unit are reconstructed, and the one or more reconstructed data blocks and the one or more reconstructed error-correction blocks are stored on the first storage unit. | 01-21-2016 |
20160026524 | MEMORY DEVICE - A memory device includes memory elements and a controller. The memory controller executes a process including a first section and a second section in response to a refresh command, detects an error of data stored in the memory elements in the first section, and writes correct data in a memory element storing data with the detected error in a second section, the second section being variable in accordance with a time to write the correct data. | 01-28-2016 |
20160026526 | ENCODER BY-PASS WITH SCRAMBLER - A first physical location is read to obtain read data. Error correction decoding is performed on the read data to obtain error-corrected data where the error-corrected data includes first error-corrected metadata. Error correction encoding is performed on a first random sequence combined with a second random sequence, concatenated with second metadata. Error correction encoding is also performed on a sequence of zeros concatenated with the first error-corrected metadata to obtain second encoded data. The error-corrected data, the first encoded data, and the second encoded data are summed to obtain migrated data, which is stored at a second physical location. | 01-28-2016 |
20160026527 | SYSTEMS AND METHODS FOR ERROR CORRECTION CODING - Described are methods, systems, and apparatus, including computer program products for error correction coding and decoding procedures for data storage or transfer. A plurality of data blocks is received. A plurality of checksum blocks are generated by multiplying the plurality of data blocks by a coding matrix, where the coding matrix comprises values of at least one basic interpolation polynomial and the multiplying is according to a finite field arithmetic for a finite field comprising all possible values of the plurality of data blocks and the plurality of coding blocks. The plurality of data blocks and the plurality of checksum blocks are stored in a data storage medium. | 01-28-2016 |
20160027521 | METHOD OF FLASH CHANNEL CALIBRATION WITH MULTIPLE LUTS FOR ADAPTIVE MULTIPLE-READ - Error Correction Codes, which are able to take soft-decision information, work much better when compared with hard-decision decoding. It can achieve much better performance. However, due to lack of direct soft-decision information for the NAND flash, multiple-reads with different voltage thresholds are used to generate the soft-decision information. Another invention disclosure describes a method to perform the multiple-read adaptively with different voltage threshold for the NAND flash in order to minimize the number of total multiple-read. The invention disclosure described here is a method of flash channel calibration, which will generate multiple LUTs for adaptive multiple-read with different voltage threshold. | 01-28-2016 |
20160034344 | Error Repair Location Cache - A method for repairing a memory includes executing an Error Correction Code (ECC) for a page of the memory. The page includes a plurality of bits having an inherent number of failed bits equal to or greater than zero. The ECC is configured to correct a correctable number of failed bits from the plurality of bits. A location of a failure prone bit in the page is determined from a cache in response to the correctable number of failed bits being less than the inherent number of failed bits. A state of the failure prone bit is changed to a new state in response to determining the location of the failure prone bit. The ECC is executed in response to the state of the failure prone bit being changed to the new state. | 02-04-2016 |
20160034348 | SEMICONDUCTOR MEMORY DEVICE HAVING SELECTIVE ECC FUNCTION - A semiconductor memory device having a selective error correction code (ECC) function is provided. The semiconductor memory device divides a memory cell array into blocks according to data retention characteristics of memory cells. A block in which there are a plurality of fail cells generated at a refresh rate of a refresh cycle that is longer than a refresh cycle defined by the standards of the semiconductor device is selected from among the divided blocks. The selected block repairs the fail cells by performing the ECC function. The other blocks repair the fail cells by using redundancy cells. Accordingly, a refresh operation is performed on the memory cells of the memory cell array at the refresh rate of the refresh cycle that is longer than the refresh cycle by the standards of the semiconductor device. | 02-04-2016 |
20160034349 | OPERATING METHOD OF MEMORY CONTROLLER AND NONVOLATILE MEMORY DEVICE - A method of operating a nonvolatile memory device including a plurality of memory cells is provided. A default read operation is performed on a page using a default read voltage set to generate default raw data. If error bits of the default raw data are not corrected, a plurality of low-level read operations is performed on the page using a plurality of read voltage sets to generate a plurality of low-level raw data. Each read voltage set is different from the default voltage set. A read voltage set is selected from the plurality of read voltage sets as a starting voltage set, according to each low-level raw data. A high-level read operation using the selected starting voltage set is performed on the page to generate high-level raw data. | 02-04-2016 |
20160034350 | ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM - According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator. | 02-04-2016 |
20160034353 | Storage Module and Method for Improved Error Correction by Detection of Grown Bad Bit Lines - A storage module and method are provided for improved error correction by detection of grown bad bit lines. In one embodiment, a storage module is provided comprising a controller and a memory having a plurality of bit lines. The controller detects an uncorrectable error in a code word read from the memory, determines location(s) of grown bad bit line(s) that contributed to the error in the code word being uncorrectable, and uses the determined location(s) of the grown bad bit line(s) to attempt to correct the error in the code word. | 02-04-2016 |
20160034354 | GLOBAL ERROR RECOVERY SYSTEM - In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process. | 02-04-2016 |
20160036463 | DATA STORAGE DEVICE AND METHOD FOR PROTECTING A DATA ITEM AGAINST UNAUTHORIZED ACCESS - A method for protecting a data item against unauthorized access and a data processing device is disclosed comprising a memory unit and a memory control unit to protect data items stored in the memory unit against prohibited access. Upon a write access the memory control unit forms a first data word comprising a data item and a first key; computes a first error-detection code; and stores the data item along with the first error-detection code. Upon a read access the memory control unit reads the data item and the first error-detection code; forms a second data word comprising the data item and a second key; computes a second error-detection code to the second data word; and determines a syndrome on the basis of the first error-detection code and the second error-detection code, wherein the syndrome is indicative of whether or not the first and second data words are identical. | 02-04-2016 |
20160036466 | ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM - According to one aspect, a method for adaptive error correction in a memory system includes reading data from a memory array of a non-volatile memory device in the memory system. Error correcting logic checks the data for at least one error condition stored in the memory array. Based on determining that the at least one error condition exists, a write-back indicator is asserted by the error correcting logic to request correction of the at least one error condition. Based on determining that the at least one error condition does not exist, accesses of the memory array continue without asserting the write-back indicator. | 02-04-2016 |
20160041872 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a core block suitable for storing write data as normal data or a part of combined data according to a data masking signal, and masking information indicating data masking of the combined data; and an error correcting code (ECC) block suitable for performing an ECC decoding operation on the normal data, and bypassing the ECC decoding operation on the combined data according to the masking information, wherein the combined data further includes masked data. | 02-11-2016 |
20160041873 | DIE-LEVEL MONITORING IN A STORAGE CLUSTER - In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster. | 02-11-2016 |
20160041874 | SYSTEMS AND METHODS FOR ENHANCED DATA RECOVERY IN A SOLID STATE MEMORY SYSTEM - Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location. | 02-11-2016 |
20160041875 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code. | 02-11-2016 |
20160041876 | MEMORY MODULE, MEMORY SYSTEM HAVING THE SAME, AND METHODS OF READING THEREFROM AND WRITING THERETO - A method of reading from a memory module which includes a plurality of memories is provided. The method includes reading data corresponding to a plurality of burst length units from the plurality of memories; correcting an error of the read data using a storage error correction code; and outputting the error corrected data by a unit of data corresponding to one burst length unit. | 02-11-2016 |
20160042797 | METHOD OF DETERMINING DEFAULT READ VOLTAGE OF NON-VOLATILE MEMORY DEVICE AND METHOD OF READING DATA OF NON-VOLATILE MEMORY DEVICE - A method of determining a default read voltage of a non-volatile memory device which includes a plurality of first memory cells, each of which stores a plurality of data bits as one of a plurality of threshold voltages corresponding to a plurality of logic states, includes programming a first data to the first memory cells so that the logic states of the first memory cells are balanced or equally used. The method includes applying a first default read voltage included in default read voltages to word lines coupled to the first memory cells, and measuring a first ratio of first on-cells, each of which has a threshold voltage smaller than or equal to the first default read voltage, among the first memory cells, and modifying the first default read voltage based on the first ratio and a first reference value corresponding to the first default read voltage. | 02-11-2016 |
20160048422 | ERROR DETECTION DEVICE AND ERROR DETECTION METHOD - An error detection device includes: a writing portion configured to write, in an address of the storage, first data including a first error determination code in which a different error detection rule is applied in association with the address; a reading portion configured to read the first data from the storage as second data; and a detector configures to detect an error, using a second error determination code of the second data. | 02-18-2016 |
20160048424 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first and second banks, each of the first and second banks comprising a memory cell array; a data buffer a data buffer which is shared by the first and second banks, and stores write data which is to be written to the first and second banks and read data which is read from the first and second banks; a correcting circuit which is shared by the first and second banks, and corrects an error of the read data; and a multiplexer which switches a connection between the first bank and the data buffer and correcting circuit, and switches a connection between the second bank and the data buffer and correcting circuit. The multiplexer is disposed between the data buffer and the correcting circuit. | 02-18-2016 |
20160048425 | MEMORY DEVICE HAVING A SHAREABLE ERROR CORRECTION CODE CELL ARRAY - A memory device including: an error correction code (ECC) cell array; an ECC engine configured to receive write data to be written to a memory cell array and generate internal parity bits for the write data; and an ECC select unit configured to receive the internal parity bits and external parity bits and, in response to a first level of a control signal, store the internal parity bits in the ECC cell array and, in response to a second level of the control signal store the external parity bits in the ECC cell array. | 02-18-2016 |
20160049204 | MEMORY SYSTEM AND METHOD OF CONTROLLING NON-VOLATILE MEMORY - According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading. | 02-18-2016 |
20160054924 | MEMORY CONTROL DEVICE AND MEMORY CONTROL METHOD - A memory device is operative to reset write-in status or read-out status information data in accordance with a reset signal. In response to the reset signal, a memory control device refers to a power-on reset check region in a RAM and determines whether or not the received reset signal is a power-on reset signal that is the reset signal generated firstly after power on. If the reset signal is determined to be the power-on reset signal, a memory check process is executed on respective target pages in each block in the memory. A refresh process is also performed on a block in which the number of error bits detected in the memory check process is more than a threshold value. The memory check process is performed on a different page whenever power is supplied. | 02-25-2016 |
20160055055 | MEMORY SYSTEM AND ERROR CORRECTION DECODING METHOD - According to one embodiment, there is provided a memory system including a first generating unit, a buffer unit, a decoding unit, and an update unit. The first generating unit generates logarithm likelihood ratios for plural pieces of data read from a plurality of memory cells. The buffer unit stores the logarithm likelihood ratios. The decoding unit performs first error correction decoding process on the logarithm likelihood ratios, and estimates a logarithm likelihood ratio of data corresponding to an error memory cell among the plural pieces of read data. The update unit updates the logarithm likelihood ratios stored in the buffer unit using the estimated logarithm likelihood ratio. | 02-25-2016 |
20160055056 | MEMORY DEVICE HAVING ERROR NOTIFICATION FUNCTION - A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses. | 02-25-2016 |
20160055057 | STORAGE DEVICE INCLUDING ERROR CORRECTION DECODER AND OPERATING METHOD OF ERROR CORRECTION DECODER - An operating method of an error correction decoder includes receiving data, setting initial log-likelihood values of variable nodes, and decoding the received data by updating a log-likelihood value of a selected variable node by use of a minimum value and a minimum candidate value associated with the selected variable node. The minimum value indicates a minimum value of absolute values of log-likelihood values of first variable nodes sharing a check node with the selected variable node and including the selected variable node. The minimum candidate value indicates one, greater than the minimum value and smallest, from among absolute values of log-likelihood values of second variable nodes that are selected later than one, corresponding to the minimum value, from among the first variable nodes. | 02-25-2016 |
20160055058 | MEMORY SYSTEM ARCHITECTURE - An embodiment includes a system, comprising: a memory configured to store data, correct an error in data read from the stored data, and generate error information in response to the correcting of the error in the data read from the stored data; and a processor coupled to the memory through a first communication path and a second communication path and configured to: receive data from the memory through the first communication path; and receive the error information from the memory through the second communication path. | 02-25-2016 |
20160055059 | MEMORY DEVICES AND MODULES - An embodiment includes a memory device, comprising: a memory configured to store data; a data interface; an error interface; and a controller coupled to the data interface, the error interface, and the memory. The controller is configured to transmit data stored in the memory through the data interface; and the controller is configured to transmit error information generated in response to correcting an error in data read from memory through the error interface. | 02-25-2016 |
20160055060 | UTILIZING A LOCAL AREA NETWORK MEMORY AND A DISPERSED STORAGE NETWORK MEMORY TO ACCESS DATA - A method includes storing, by non-local DSN memory, redundancy encoded data slices of a set of encoded data slices. The method includes storing, by each DS processing module, a copy of the decode threshold number of encoded data slices in local memory. The method includes receiving, by the plurality of DS processing modules, read requests for the set of encoded data slices from user devices. The method includes, in response to a read request, determining, by a DS processing module, that at least one encoded data slice is unavailable; retrieving, by the DS processing module, at least one of the redundancy encoded data slices from the non-local DSN memory; and processing, by the DS processing module, the read request based on the retrieved at least one of the redundancy encoded data slice and available encoded data slices of the local copy of the decode threshold number of encoded data slices. | 02-25-2016 |
20160055061 | VIRTUAL MEMORY MAPPING IN A DISPERSED STORAGE NETWORK - A method for generating virtual dispersed storage network (DSN) addresses includes dispersed storage error encoding a data segment of a data object to produce a set of encoded data slices of a plurality of sets of encoded data slices of the pluralities of sets of encoded data slices. The method further includes generating, for each encoded data slice of the set of encoded data slices, a virtual DSN address having a slice name that includes a vault identifier, a slice index, a data object identifier, and a data segment identifier. The method further includes obtaining a mapping of a vault to a set of storage units of the DSN, wherein the mapping indicates how the set of encoded data slices are to be stored. The method further includes outputting the set of encoded data slices to the set of storage units in accordance with the mapping. | 02-25-2016 |
20160062435 | MEMORY SYSTEM - A memory system includes a nonvolatile memory, a thermoelectric device configured to generate power from heat, a main power supply for the nonvolatile memory, a backup power supply for the nonvolatile memory, the backup power supply including a capacitor, and a power supply controller configured to supply the power generated by the thermoelectric device to the capacitor to charge the capacitor. | 03-03-2016 |
20160062824 | METHOD AND SYSTEM FOR SCRUBBING DATA WITHIN A DATA STORAGE SUBSYSTEM - Various embodiments for scrubbing data within a data storage subsystem are disclosed. According to one embodiment, a method is provided for scrubbing data of a storage element within a data storage subsystem, the method comprising: selecting a storage element from the plurality of storage events; determining that a quantity of active data has reached a predetermined quantity threshold; and temporarily suspending data modifications on a portion of the selected storage element while maintaining read access to the selected storage element in response to the determination. | 03-03-2016 |
20160062827 | SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF - A semiconductor memory device is provided to keep data reliability while decreasing programming time. A NAND flash memory loads programming data from an external input/output terminal to a page buffer/sense circuit. A detecting circuit for monitoring the programming data detects whether the programming data is a specific bit string. If it is detected that the programming data is not a specific bit string, a transferring/writing circuit transfers the programming data kept by the page buffer/sense circuit to an error checking correction (ECC) circuit, and an ECC code generated by an ECC operation is written to the page buffer/sense circuit. If it is detected that the programming data is a specific bit string, transfer of the programming data kept by the page buffer/sense circuit is forbidden and a known ECC code corresponding to the specific bit string is written to the page buffer/sense circuit. | 03-03-2016 |
20160062830 | SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHOD OF CORRECTING ERRORS IN THE SAME - A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array. | 03-03-2016 |
20160062833 | REBUILDING A DATA OBJECT USING PORTIONS OF THE DATA OBJECT - Technology is disclosed for a data storage architecture for providing enhanced storage resiliency for a data object. The data storage architecture can be implemented in a single-tier configuration and/or a multi-tier configuration. In the single-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data fragments, which are stored across many storage devices. In the multi-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data segments, which are sent to one or more tiers of storage nodes. Each of the storage nodes further encodes the data segment to generate many data fragments representing the data segment, which are stored across many storage devices associated with the storage node. The I/O operations for rebuilding the data in case of device failures is spread across many storage devices, which minimizes the wear of a given storage device. | 03-03-2016 |
20160062835 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING SYSTEM, CONTROL METHOD FOR INFORMATION PROCESSING SYSTEM, AND MEDIUM - An apparatuses includes a processor, a storage unit, and a communication unit to access the storage unit without intermediary of the processor and to access a second apparatus of the plurality of information processing apparatuses via a communication unit of the second apparatus. The communication unit of a first apparatus of the plurality of information processing apparatuses executes at least one of a process of storing redundant data which is generated by making redundant data stored in the storage unit of the first apparatus in the storage unit of the second apparatus via the communication unit of the second apparatus, and a process of acquiring redundant data which is generated by making redundant data stored in the storage unit of the second apparatus via the communication unit of the second apparatus, and storing the acquired data in the storage unit of the first apparatus. | 03-03-2016 |
20160062896 | MEMORY SYSTEM - A memory system includes: a memory controller which executes a data access process with an external using an access unit; a first memory which is connected to the memory controller via a bus and has a first latency; and a second memory which is connected to the memory controller via a bus and has a second latency longer than the first latency. The access unit comprises a first access size assigned to the first memory and a second access size assigned to the second memory. The memory controller executes a data access process with the first memory using the first access size, and executes a data access process with the second memory using the second access size. | 03-03-2016 |
20160070498 | Memory System Configured to Avoid Memory Access Hazards for LDPC Decoding - Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests. | 03-10-2016 |
20160077912 | ENCODING SCHEME FOR 3D VERTICAL FLASH MEMORY - Techniques for encoding data for non-volatile memory storage systems are disclosed. In one particular embodiment, the techniques may be realized as a method including writing first data to the memory, reading the first data from the memory, analyzing the first read data such that the analyzing includes determining whether the read data includes an error, encoding second data based on the analyzing of the first data such that the second data is encoded to be written to a position adjacent to the error when it is determined that the read data includes the error, and writing the encoded second data to the memory at the position. | 03-17-2016 |
20160077913 | METHOD OF CONTROLLING NONVOLATILE MEMORY - According to an embodiment, The control method includes reading a plurality of first pages in parallel on the basis of respectively different operation parameters. each of the first pages is respectively included in a plurality of first blocks. Each of the operation parameters includes a read voltage. The control method includes performing error correction on each of read data, and selecting one operation parameter out of the plurality of different operation parameters based on a result of the error correction. | 03-17-2016 |
20160077914 | SOLID STATE STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF - An error correction method for a solid state storage device is provided. A controller of the solid state storage device issues plural slicing voltages to a flash memory. The flash memory issues a soft data to a soft decoder of the controller according to the plural slicing voltages. Firstly, the soft decoder receives the soft data, and performs an error correction process of the soft data according to a predetermined log-likelihood ratio (LLR) parameter set. If the error correction process of the soft data is not successfully completed according to the predetermined LLR parameter set, one LLR parameter set is selected from plural parameter sets of a LLR table and the error correction process of the soft data is performed according to the selected LLR parameter set. | 03-17-2016 |
20160077915 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory includes memory cells, a read circuit, (ECC) circuit, an address register, a flag register, a flag check circuit, and a write back circuit. The memory cells each include a magnetoresistive element. The address register stores the address at which the error has been detected by the ECC circuit. The data register stores corrected data in which the error has been corrected by the ECC circuit. The flag register sets an error flag in association with the address at which the error has been detected by the ECC circuit. The flag check circuit checks whether the error flag is set in the flag register. The write back circuit writes back the data to the memory cell designated by the address corresponding to the error flag. | 03-17-2016 |
20160078898 | Error Correction for Storage Devices - The present disclosure describes systems and techniques relating to storage devices, such as storage devices that employ Shingled Magnetic Recording (SMR). According to an aspect of the described systems and techniques, a device includes: circuitry configured to write stored data and parity data to discrete portions of a Shingled Magnetic Recording (SMR) track in a SMR storage device; and circuitry configured to recover stored data for one of the discrete portions of the SMR track using the parity data and the stored data read from remaining ones of the discrete portions of the SMR track. | 03-17-2016 |
20160080002 | ADAPTIVE ERROR CORRECTION CODES (ECCs) FOR ELECTRONIC MEMORIES - Systems and methods for adaptive error correction codes (ECCs) for electronic memories. In some embodiments, a memory device, may include a first memory having a plurality of address locations, each of the plurality of address locations having a number of storage bits configured to store data and one or more error correction bits corresponding to the data; and a second memory distinct from the first memory, the second memory having a plurality of entries, each of the plurality of entries configured to store one or more operation code bits relating to data stored at a corresponding address location in the first memory, the one or more operation code bits identifying an error correction scheme used to generate the one or more error correction bits at the corresponding address location in the first memory. | 03-17-2016 |
20160080003 | LOW-COMPLEXITY FLASH MEMORY DATA-ENCODING TECHNIQUES USING SIMPLIFIED BELIEF PROPAGATION - Technologies and implementations for encoding and storing data in a solid-state memory device with a reduced number of erasures using a simplified belief-propagation algorithm that includes a set of message-calculation rules that have a low computational complexity are generally disclosed. Additionally, technologies and implementations for decoding data and for error correction are generally disclosed. | 03-17-2016 |
20160080004 | MEMORY CONTROLLER AND DECODING METHOD - According to an embodiment, a memory controller controls a non-volatile memory that stores a codeword. The memory controller includes a SISO decoder that performs SISO decoding based on the codeword read out as a set of soft decision values from the non-volatile memory, and outputs a posteriori information; a hard decision processor that performs hard decision on the a posteriori information and calculates a set of hard decision values of the codeword; and a HIHO decoder that performs HIHO decoding by using the hard decision values. | 03-17-2016 |
20160085467 | INTELLIGENT DATA PLACEMENT - A method of mapping a volume of storage to a plurality of pools of storage devices specified by a host having a host identification. The volume of data storage has a volume identification and a plurality of extents. The method includes assigning a first pool of storage devices to the volume of storage based on the host identification, and determining a mapping value based on the host identification and the volume identification for the first pool of storage devices. The method also includes determining a storage device index based on the mapping value and one or more extents in the plurality of extents, and mapping a portion of the extents to the first pool of storage devices based on the storage device index. | 03-24-2016 |
20160085621 | RECOVERY ALGORITHM IN NON-VOLATILE MEMORY - Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a host device to read a line of data to the memory device, wherein the data is spread across a plurality (N) of dies and comprises an error correction code (ECC) spread across the plurality (N) of dies, retrieve the line of data from the memory device, perform an error correction code (ECC) check on the line of data retrieved from the memory device, and invoke a recovery algorithm in response to an error in the ECC check on the line of data retrieved from the memory device. Other embodiments are also disclosed and claimed. | 03-24-2016 |
20160085622 | EXPANDED ERROR CORRECTION CODES - In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on whether the majority of bits are set to a high state or a low state. For instance, the memory device may be configured to set each bit in the memory array to a low state when the data is read. The memory device may then be configured to store the data in the original state when a majority of the bits to be written to the array are in the low state and in the inverted state when the majority of the bits to be written to the array are in the high state. | 03-24-2016 |
20160085623 | SYSTEMS AND METHODS FOR SOFT DATA UTILIZATION IN A SOLID STATE MEMORY SYSTEM - Systems and methods relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. An example data processing system includes a first circuit operable to yield a modified soft data set from a data set accessed from a solid state memory device, and a second circuit operable to apply a data decoding algorithm to the modified soft data to yield a decoded output. | 03-24-2016 |
20160085626 | DECODING DEVICE, DECODING METHOD, AND MEMORY SYSTEM - According to an embodiment, a decoding device includes a check node processor, and a converter. The probability acquirer is configured to acquire. The check node processor is configured to perform check node processing during in a decoding operation of encoded data. A probability value for each bit of the encoded data is treated as an initial variable node in the check node processing. The converter is configured to convert, into bit values, updated values of the probability values based on the check node processing. The check node processor includes a check node circuit having a topology corresponding to a two-state trellis diagram representing the check node processing. The check node circuit includes conducting wires each corresponding to an edge of the two-state trellis diagram and includes switch units which are arranged on the conducting wires and switching of which is controlled according to a predetermined probability. | 03-24-2016 |
20160085627 | Memory System, Error Correction Device, and Error Correction Method - According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data. | 03-24-2016 |
20160085628 | STORAGE CLUSTER - A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided. | 03-24-2016 |
20160092129 | SYSTEM AND METHOD FOR FOLDING PARTIAL BLOCKS INTO MULTI-LEVEL CELL MEMORY BLOCKS - A method and system for folding only a portion of data from an SLC block to an MLC block is described. The method includes identifying word lines with only valid data and word lines with non-valid data in a selected SLC block, copying data only from word lines with valid data to a destination MLC block and copying data from word lines in the selected SLC block with non-valid data to a separate SLC compaction block. The system includes a first controller module configured to scan for word lines with only valid data and pass only a bitmap regarding valid and invalid word lines to a second controller module. The second controller module is configured to perform on-chip folding of data from valid word lines, and to copy data from invalid data word lines to an SLC compaction block. | 03-31-2016 |
20160092299 | METHOD AND SYSTEM FOR USING NAND PAGE BUFFERS TO IMPROVE THE TRANSFER BUFFER UTILIZATION OF A SOLID STATE DRIVE - A page data (e.g., upper page data) received from a host is stored in a transfer buffer of a controller of a solid state drive. Another page data (e.g., lower page data) is read from a non-volatile memory (e.g., a NAND memory) to store in the transfer buffer as an error corrected page data. The error corrected page data and the page data are written to the non-volatile memory. In additional embodiments, a controller loads a page data (e.g., upper page data) received from the host in one or more NAND page buffers. The controller reads another page data (e.g., lower page data) from a NAND memory to store in a transfer buffer as an error corrected page data. The error corrected page data stored in the transfer buffer is loaded to the one or more NAND page buffers. | 03-31-2016 |
20160092300 | USING RELIABILITY INFORMATION FROM MULTIPLE STORAGE UNITS AND A PARITY STORAGE UNIT TO RECOVER DATA FOR A FAILED ONE OF THE STORAGE UNITS - Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit. | 03-31-2016 |
20160092301 | CORRECTING SOFT RELIABILITY MEASURES OF STORAGE VALUES READ FROM MEMORY CELLS - A method for data storage includes reading storage values, which represent stored data, from a group of memory cells using read thresholds, and deriving respective soft reliability metrics for the storage values. The storage values are classified into two or more subgroups based on a predefined classification criterion. Independently within each subgroup, a subgroup-specific distribution of the storage values in the subgroup is estimated, and the soft reliability metrics of the storage values in the subgroup are corrected based on the subgroup-specific distribution. The stored data is decoded using the corrected soft reliability metrics. | 03-31-2016 |
20160092303 | METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY - A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences. | 03-31-2016 |
20160092305 | ECC WORD CONFIGURATION FOR SYSTEM-LEVEL ECC COMPATIBILITY - In some examples, a memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction may be performed on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device may be configured to provide only one bit of data per ECC word to an external source during an access from an external source. | 03-31-2016 |
20160092306 | PLATFORM ERROR CORRECTION - An example device in accordance with an aspect of the present disclosure includes a first error corrector to perform platform error correction based on a stride length. A memory includes a second error corrector that is to perform on-memory error correction that is to be disabled for platform error correction. | 03-31-2016 |
20160092307 | EXCHANGING ECC METADATA BETWEEN MEMORY AND HOST SYSTEM - Exposing internal error correction bits from a memory device for use as metadata bits by an external memory controller. In a first mode the memory device applies internal error correction bits for internal error correction at the memory device. In a second mode the memory device exposes the internal error correction bits to the memory controller to allow the memory controller to use the data. | 03-31-2016 |
20160093372 | READING RESISTIVE RANDOM ACCESS MEMORY BASED ON LEAKAGE CURRENT - A data storage device includes a resistive random access memory (ReRAM). The data storage device includes read circuitry coupled to a storage element of the ReRAM. The read circuitry is configured to read a data value from the storage element, during a read operation, based on a read current sensed during a first phase of the reading operation and a leakage current sensed during a second phase of the reading operation. The data storage device also includes a controller coupled to the read circuitry. The controller is configured to provide an input value to an error correction coding (ECC) decoder, where the input value includes a hard bit value and a soft bit value. The hard bit value corresponds to the data value, and the soft bit value is at least partially based on the leakage current. | 03-31-2016 |
20160093390 | Read With Look-Back Combined With Programming With Asymmetric Boosting In Memory - A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. The read operation occurs in connection with a programming operation which avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn−1) are read. The read operation for WLn uses multiple read voltages—one for each data state on WLn−1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell. | 03-31-2016 |
20160098316 | ERROR PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT - An error processing method for a rewritable non-volatile memory module, a memory storage device and a memory controlling circuit unit are provided. The rewritable non-volatile memory module includes a plurality of memory cells. The error processing method includes: sending a first read command sequence for reading a plurality of bits from the memory cells; performing a first decoding on the bits; determining whether each error belongs to a first type error or a second type error if the bits have at least one error; recording related information of a first error in the at least one error if the first error belongs to the first type error; and not recording the related information of the first error if the first error belongs to the second type error. Accordingly, errors with particular type may be processed suitably. | 04-07-2016 |
20160098317 | WRITE MAPPING TO MITIGATE HARD ERRORS VIA SOFT-DECISION DECODING - An apparatus having mapping and interface circuits. The mapping circuit (i) generates a coded item by mapping write unit bits using a modulation or recursion of past-seen bits, and (ii) calculates a particular state to program into a nonvolatile memory cell. The interface circuit programs the cell at the particular state. Two normal cell states are treated as at least four refined states. The particular state is one of the refined states. A mapping to the refined states mitigates programming write misplacement that shifts an analog voltage of the cell from the particular state to an erroneous state. The erroneous state corresponds to a readily observable illegal or atypical write sequence, and results in a modified soft decision from that calculated based on the normal states only. A voltage swing between the particular state and the erroneous state is less than between the normal states. | 04-07-2016 |
20160098318 | DYNAMIC PER-DECODER CONTROL OF LOG LIKELIHOOD RATIO AND DECODING PARAMETERS - An apparatus includes one or more error-correction decoders, a buffer, and at least one processor. The buffer may be configured to store data to be decoded by the one or more error-correction decoders. The at least one processor is generally enabled to send messages to the one or more error-correction decoders. The messages may contain datapath control information corresponding to data in the buffer to be decoded by the one or more error-correction decoders. The one or more error-correction decoders are generally enabled to decode the data read from the buffer according to the corresponding datapath control information. | 04-07-2016 |
20160103732 | Storage Module and Method for Datapath Bypass - A storage module and method for datapath bypass are disclosed. In one embodiment, a storage module begins to perform a read operation that reads a set of code words from the memory and attempts to perform an error detection and correction operation on one of the read code words. In response to determining that the code word has an uncorrectable error, the storage module reads the other code words in the set but bypasses the error detection and correction operation on those other code words. The code word that had the uncorrectable error and the other code words are re-read, wherein at least the code word with the uncorrectable error is re-read with a different read condition. The storage module then attempts to perform the error detection and correction operation on the re-read code words. Other embodiments are provided. | 04-14-2016 |
20160103734 | Data Storage Device and Data Maintenance Method Thereof - A data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of pages, the pages are arranged to assemble into a super block, the pages of the super block are numbered 0˜X from top to bottom of the super block, the pages with number 0˜Y−1 constitute a data area, and the pages with numbers Y˜X constitute a RAID parity area. The controller corrects data of the data area according to data of the RAID parity area when the data in the data area cannot be successfully read. | 04-14-2016 |
20160103735 | ERROR CORRECTION DECODER AND OPERATION METHOD OF THE ERROR CORRECTION DECODER - The inventive concepts relate to an operation method of an error correction decoder correcting an error of data read from a nonvolatile memory. The operation method may include receiving the data from the nonvolatile memory, performing a first error correction with respect to the received data in a simplified mode, and performing, when the first error correction fails in the simplified mode, a second error correction with respect to the received data in a full mode. When the first error correction of the simplified mode is performed, a part of operations of the second error correction of the full mode may be omitted. | 04-14-2016 |
20160103736 | PROCESSOR REGISTER ERROR CORRECTION MANAGEMENT - Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table. | 04-14-2016 |
20160110253 | SEMICONDUCTOR MEMORY DEVICE INCLUDING NON-VOLATILE MEMORY, CACHE MEMORY, AND COMPUTER SYSTEM - In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number. | 04-21-2016 |
20160110256 | COMBINED GROUP ECC PROTECTION AND SUBGROUP PARITY PROTECTION - A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P. | 04-21-2016 |
20160110257 | SETTING A DEFAULT READ SIGNAL BASED ON ERROR CORRECTION - The present disclosure includes apparatuses and methods related to setting a default read signal based on error correction. A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections. | 04-21-2016 |
20160111150 | DUAL POLARITY READ OPERATION - A data storage device includes a memory die and a controller coupled to the memory die. The memory die includes a resistive memory and read/write circuitry configured to determine a first hard bit value and a second hard bit value of a storage element of the resistive memory. The first hard bit value and the second hard bit value are determined using opposite polarity read voltages. The controller is configured to perform error correction with respect to data read from the resistive memory. | 04-21-2016 |
20160117220 | DATA STORAGE DEVICE AND ERROR CORRECTION METHOD CAPABLE OF ADJUSTING VOLTAGE DISTRIBUTION - The present invention provides a data storage device including a flash memory and a controller. The controller is configured to perform a first read operation to read a first page corresponding to a first word line of the flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment procedure. | 04-28-2016 |
20160117221 | ERROR DETECTION AND CORRECTION UTILIZING LOCALLY STORED PARITY INFORMATION - A processing system includes a memory coupled to a processor device. The memory stores data blocks, with each data block having a separate associated checksum value stored along with the data block in the memory. The processor device has a storage location that stores parity information for the data blocks, with the parity information having a plurality of parity blocks. Each parity block represents a parity of a corresponding set of data blocks. The parity blocks can be accessed for use in error detection and correction schemes used by the processing system. | 04-28-2016 |
20160117223 | METHOD FOR CONCURRENT SYSTEM MANAGEMENT AND ERROR DETECTION AND CORRECTION REQUESTS IN INTEGRATED CIRCUITS THROUGH LOCATION AWARE AVOIDANCE LOGIC - A method of incorporating active error correction inside a memory device is used, whereby memory scrub cycles can be completely hidden from an end user. The method simplifies the design of the memory interface and simplifies the data integrity management unit for the end user. An arbitration unit is implemented to allow concurrent processing of primary (user) and secondary (scrub) requests. The arbitration unit is location aware in context to the primary interface and is responsible for eliminating overlapping memory requests. | 04-28-2016 |
20160124806 | Data Storage Device and Flash Memory Control Method - A flash memory control method with high reliability. A control unit coupled between a host and a flash memory gathers statistics about commands performed on the flash memory. Based on the statistical result, the control unit is triggered to perform a sample check and correction procedure on the flash memory. The data within an endangered block failing to pass the sample check and correction procedure may be entirely moved to a spare block in the flash memory. | 05-05-2016 |
20160124807 | MULTI-CHIP DEVICE AND METHOD FOR STORING DATA - A multi-chip device and method for storing input data. The multi-chip device includes: a plurality of memory chips being adapted to store encoded input data, wherein each of the plurality of memory chips includes a detection unit that outputs detection information; an evaluation unit being adapted to perform an evaluation of the detection information from each of the plurality of memory chips, and to adapt the detection algorithm of any of the detection units depending on the performed evaluation; a combination unit being adapted to receive the detected bits and to combine the detected bits; and a decoding unit being adapted to output decoded data by decoding the combined detected bits. The present invention also provides a method and a computer program product for storing input data. | 05-05-2016 |
20160124808 | SYSTEMS AND METHODS FOR INTER-CELL INTERFERENCE MITIGATION IN A FLASH MEMORY - The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells. | 05-05-2016 |
20160124810 | 3D MEMORY WITH ERROR CHECKING AND CORRECTION FUNCTION - An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers. | 05-05-2016 |
20160132388 | SEMICONDUCTOR MEMORY DEVICE AND ECC METHOD THEREOF - A semiconductor memory device and ECC method thereof are provided which a first nonvolatile memory; a second nonvolatile memory having a type different from the first nonvolatile memory; a controller; a first error correction circuit configured to correct an error of first write data to be programmed at the first nonvolatile memory; and a second error correction circuit included in the controller and configured to correct an error of first write data or an error of second write data to be programmed at the second nonvolatile memory, based on an error correction algorithm different from that of the first error correction circuit. Error correction data for correcting an error of the first write data is generated using one of the first error correction circuit and the second error correction circuit according to an attribute of the first write data. | 05-12-2016 |
20160132389 | SOLID STATE DISK CONTROLLER APPARATUS - A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus. | 05-12-2016 |
20160132390 | USING ERROR CORRECTING CODES FOR PARITY PURPOSES - Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block. | 05-12-2016 |
20160132391 | SLEEP MODE OPERATION FOR VOLATILE MEMORY CIRCUITS - Aspects of the present disclosure are directed to circuits, apparatuses and methods for operating volatile memory circuits. According to an example embodiment, an apparatus includes a volatile memory circuit and a control circuit coupled to the volatile memory circuit. The control circuit is configured to generate and store parity data for data blocks written to the volatile memory circuit. The control circuit places the volatile memory circuit in a sleep mode in response to a first control signal. In response to a second control signal, the control circuit places the volatile memory into an active mode. In further response to the second control signal the control circuit detects and corrects errors in the data blocks stored in the volatile memory using the stored parity data. | 05-12-2016 |
20160139986 | DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF - A data reading method, applied to a data storage device that includes a flash memory capable of operating in a SLC mode and a multi-level cell mode. The data reading method includes reading a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host to obtain a first data segment, writing a predetermined data into a most-significant-bit page corresponding to the first word line in the multi-level cell mode when the first data segment has an error, and reading the page corresponding to the first word line in the SLC mode again to obtain a second data segment. | 05-19-2016 |
20160139987 | GENERATING SOFT READ VALUES USING MULTIPLE READS AND/OR BINS - A starting read threshold is received. A first offset and a second offset is determined. A first read is performed at the starting read threshold offset by the first offset to obtain a first hard read value and a second read is performed at the starting read threshold offset by the second offset to obtain a second hard read value. A soft read value is generated based at least in part on the first hard read value and the second hard read value. | 05-19-2016 |
20160139989 | GLOBAL ERROR CORRECTION - A method that includes evaluating, with a controller, local error detection (LED) information in response to a first memory access operation is disclosed. The LED information is evaluated per cache line segment of data associated with a rank of a memory. The method further includes determining an error in at least one of the cache line segments based on an error detection code and determining whether global error correction (GEC) data for a first cache line associated with the at least one cache line segment is stored in a GEC cache in the controller. The method also includes correcting the first cache line associated with the at least one cache line segment based on the GEC data retrieved from the GEC cache in the controller without accessing GEC data from a memory. | 05-19-2016 |
20160141037 | SEMICONDUCTOR MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory system includes: programming LSB data into a memory cell of a selected word line included in a memory block; storing MSB data to be programmed into the memory cell of the selected word line, from a controller into a page buffer; reading the programmed LSB data from the memory cell of the selected word line; performing an ECC operation on the read LSB data when a difference between a reference amount and an amount of bit line current, which flows through bit lines included in the memory block, does not fall in a predetermined range from a first current amount to a second current amount; and programming the MSB data stored in the page buffer into the memory cell of the selected word line based on the ECC-corrected LSB data. | 05-19-2016 |
20160147597 | DYNAMIC PARTIAL BLOCKING OF A CACHE ECC BYPASS - An aspect includes receiving a fetch request for a data block at a cache memory system that includes cache memory that is partitioned into a plurality of cache data ways including a cache data way that contains the data block. The data block is fetched and it is determined whether the in-line ECC checking and correcting should be bypassed. The determining is based on a bypass indicator corresponding to the cache data way. Based on determining that in-line ECC checking and correcting should be bypassed, returning the fetched data block to the requestor and performing an ECC process for the fetched data block subsequent to returning the fetched data block to the requestor. Based on determining that in-line ECC checking and correcting should not be bypassed, performing the ECC process for the fetched data block and returning the fetched data block to the requestor subsequent to performing the ECC process. | 05-26-2016 |
20160147599 | Memory Systems that Perform Rewrites of Resistive Memory Elements and Rewrite Methods for Memory Systems Including Resistive Memory Elements - A method of operating a nonvolatile memory device, such as a resistive memory device. The method includes performing error correction code (ECC) processing on data read from resistive memory cells to detect whether any of the resistive memories or soft error cell; checking completion of a read operation after storing an address of the soft error cell when the soft error cell is detected; and selectively rewriting error-corrected data into a soft error cell corresponding to the stored address in response to determining that the read operation is completed. | 05-26-2016 |
20160147600 | MEMORY ACCESS METHOD AND APPARATUS FOR MESSAGE-TYPE MEMORY MODULE - A memory access apparatus includes a read-write module and a processing module. The read-write module is configured to store an error detecting code in an (M+2) | 05-26-2016 |
20160162357 | APPROACH TO CORRECT ECC ERRORS USING DUPLICATE COPIES OF DATA - Devices and methods implemented therein in are disclosed for correcting errors in data. The method comprises determining that a first copy of data and a second copy of data include errors uncorrectable by an error correction code (ECC) engine. The ECC engine is modified based on determining that the first copy of data and the second copy of data include errors uncorrectable by the ECC engine and using the modified ECC engine, the first copy of data and the second copy of data are processed to correct the errors in the first and second copy of the data. | 06-09-2016 |
20160162358 | MICROCONTROLLER - A microcontroller includes a nonvolatile memory. The microcontroller executes an ECC error detection to detect an ECC error during a main process, which accesses the nonvolatile memory, and an interrupt process when the ECC error occurs. The interrupt process executes a change process that specifies an instruction causing the ECC error, which is detected by the ECC error detection, and changes a program counter to skip the specified instruction and to execute a next instruction. The microcontroller executes an abnormality value storage process that stores an abnormality value in a storage destination of a read value, and the read value is read in the main process after the change process. | 06-09-2016 |
20160162359 | SYSTEM AND METHOD FOR PERFORMING SIMULTANEOUS READ AND WRITE OPERATIONS IN A MEMORY - A memory comprises a set of content memory banks, a parity memory bank, and a register corresponding to the parity memory bank. A first memory interface device is configured to, in response to receiving a write request to write to the set of content memory banks, perform a write operation over multiple clock cycles including temporarily storing parity information corresponding to the write request in the register before the parity information is written to the parity memory bank. A second memory interface device is configured to: in response to i) receiving a read request to read data from a memory bank in the set of content memory banks, and ii) determining that information responsive to the read request is to be reconstructed using parity information, and selectively use information from either i) the register or ii) the parity memory bank, to reconstruct information responsive to the read request. | 06-09-2016 |
20160170831 | Response Control for Memory Modules That Include or Interface With Non-Compliant Memory Technologies | 06-16-2016 |
20160170832 | COMPUTING SYSTEM WITH SHIFT DATA PROTECTION MECHANISM AND METHOD OF OPERATION THEREOF | 06-16-2016 |
20160172029 | NONVOLITILE MEMORY REFRESH | 06-16-2016 |
20160179615 | OPERATING METHOD OF MEMORY SYSTEM | 06-23-2016 |
20160179618 | SELECTING STORAGE UNITS IN A DISPERSED STORAGE NETWORK | 06-23-2016 |
20160182088 | Method For File Updating And Version Control For Linear Erasure Coded And Network Coded Storage | 06-23-2016 |
20160188406 | INTRA-RACK AND INTER-RACK ERASURE CODE DISTRIBUTION - Methods, computing systems and computer program products implement embodiments of the present invention that include detecting multiple sets of storage objects stored in a data facility including multiple server racks, each of the server racks including a plurality of server computers, each of the storage objects in each set being stored in a separate one of the server racks and including one or more data objects and one or more protection objects. A specified number of the storage objects are identified in a given server rack, each of the identified storage objects being stored in a separate one of the server computers, and one or more server computers in the given server rack not storing any of the identified storage objects are identified. Finally, in the identified one or more server computers, an additional protection object is created and managed for the identified storage objects. | 06-30-2016 |
20160188407 | ARCHITECTURE FOR IMPLEMENTING ERASURE CODING - Disclosed is an improved approach to implement erasure coding, which can address multiple storage unit failures in an efficient manner. The approach can effectively address multiple failures of storage units by implementing diagonal parity sets. | 06-30-2016 |
20160188408 | PROTECTION OF MEMORIES, DATAPATH AND PIPELINE REGISTERS, AND OTHER STORAGE ELEMENTS BY DISTRIBUTED DELAYED DETECTION AND CORRECTION OF SOFT ERRORS - This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time. | 06-30-2016 |
20160188409 | REDUCED UNCORRECTABLE MEMORY ERRORS - Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively. | 06-30-2016 |
20160196179 | RECONFIGURABLE ECC FOR MEMORY | 07-07-2016 |
20160196180 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING THE DEVICE | 07-07-2016 |
20160197623 | READ THRESHOLD CALIBRATION FOR LDPC | 07-07-2016 |
20160203045 | SEMICONDUCTOR DEVICE HAVING ERROR CORRECTION CODE (ECC) CIRCUIT | 07-14-2016 |
20160203046 | MEMORY DEVICE, SERVER DEVICE, AND MEMORY CONTROL METHOD | 07-14-2016 |
20160203047 | OPERATION METHOD OF NONVOLATILE MEMORY SYSTEM | 07-14-2016 |
20160203048 | MEMORY CELL COUPLING COMPENSATION | 07-14-2016 |
20160253236 | MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM | 09-01-2016 |
20160253240 | REBUILDING ENCODED DATA SLICES IN A DISPERSED STORAGE NETWORK | 09-01-2016 |
20160254041 | NONVOLATILE LOGIC AND SECURITY CIRCUITS | 09-01-2016 |
20160378591 | ADAPTIVE ERROR CORRECTION IN MEMORY DEVICES - Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states. | 12-29-2016 |
20160378592 | CACHE MEMORY AND PROCESSOR SYSTEM - A cache memory has cache memory circuitry comprising a nonvolatile memory cell to store at least a portion of a data which is stored or is to be stored in a lower-level memory than the cache memory circuitry, a first redundancy code storage comprising a nonvolatile memory cell capable of storing a redundancy code of the data stored in the cache memory circuitry, and a second redundancy code storage comprising a volatile memory cell capable of storing the redundancy code. | 12-29-2016 |
20160378594 | METHOD AND APPARATUS TO DECODE LOW DENSITY PARITY CODES - Apparatus, systems, and methods for recovery algorithm in memory are described. In one embodiment a memory comprises a memory device and a controller coupled to the memory device and comprising logic, at least partially including hardware logic, to in response to a read request received from a host device, retrieve data from the memory device, perform an error correction code (ECC) check on the data retrieved from the memory device, invoke a recovery operation in response to an ECC error, wherein the recovery operation performs a non-binary, iterative symbol flipping procedure. Other embodiments are also disclosed and claimed. | 12-29-2016 |
20160378595 | CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF - An operating method of a controller includes: a first step of generating an internal codeword including an ECC unit data and an internal parity code by performing ECC decoding operation to an input data; a second step of updating an external parity code based on the ECC unit data, which is included in the internal codeword currently generated, and the ECC unit data, which is included in the internal codeword previously generated; and a third step of storing in a semiconductor memory device one or more internal codewords and the updated external parity code, which are generated through repetition of the first and second steps, by a unit of predetermined storage size. | 12-29-2016 |
20160378597 | CHARACTERIZATION OF IN-CHIP ERROR CORRECTION CIRCUITS AND RELATED SEMICONDUCTOR MEMORY DEVICES/MEMORY SYSTEMS - A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity. | 12-29-2016 |
20160378598 | SYSTEMS AND METHODS FOR LAST WRITTEN PAGE HANDLING IN A MEMORY DEVICE - Systems and method relating generally to solid state memory, and more particularly to systems and methods for recovering data from a solid state memory. In one embodiment, the systems and methods include providing a flash memory circuit including a superset of memory cells, accessing a data set from a group of memory cells using a standard reference value to distinguish bit values in the group of memory cells, and based at least in part on determining that the group of memory cells was a last written group of memory cells, re-accessing a data set from the group of memory cells using a last written reference value to distinguish bit values in the group of memory cells. | 12-29-2016 |
20160378599 | METHODS AND APPARATUS FOR EMBEDDING AN ERROR CORRECTION CODE IN STORAGE CIRCUITS - A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code. | 12-29-2016 |
20170235632 | ERROR MONITORING OF A MEMORY DEVICE CONTAINING EMBEDDED ERROR CORRECTION | 08-17-2017 |
20170235633 | DATA STORAGE DEVICE INCLUDING READ VOLTAGE SEARCH UNIT | 08-17-2017 |
20170235634 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME | 08-17-2017 |
20170235635 | SOLID STATE STORAGE DEVICE AND DATA PROCESSING METHOD THEREOF | 08-17-2017 |
20170235636 | Solid State Disk Storage Device and Method for Accessing Data in Solid State Disk Storage Device | 08-17-2017 |
20170235637 | HIGH PERFORMANCE MEMORY CONTROLLER | 08-17-2017 |
20170236593 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE | 08-17-2017 |
20180024878 | EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DYNAMIC RANDOM ACCESS MEMORY (DRAM) ERROR CORRECTION CODE (ECC) | 01-25-2018 |
20180024879 | DECODER USING LOW-DENSITY PARITY-CHECK CODE AND MEMORY CONTROLLER INCLUDING THE SAME | 01-25-2018 |
20180024881 | SYSTEM AND METHOD FOR ADAPTIVE MULTIPLE READ OF NAND FLASH | 01-25-2018 |
20180024882 | THROTTLING ACCESS REQUESTS AT DIFFERENT LAYERS OF A DSN MEMORY | 01-25-2018 |
20180024884 | PRIORITIZING REBUILDING BASED ON A LONGEVITY ESTIMATE OF THE REBUILT SLICE | 01-25-2018 |
20180024885 | ASSIGNING PRIORITIZED REBUILD RESOURCES OPTIMALLY | 01-25-2018 |
20180024886 | EFFICIENT METHOD FOR REBUILDING A SET OF ENCODED DATA SLICES | 01-25-2018 |
20180025776 | System and Method for Burst Programming Directly to MLC Memory | 01-25-2018 |
20180025777 | HIGH-RELIABILITY MEMORY READ TECHNIQUE | 01-25-2018 |
20180026659 | LOW-DENSITY PARITY CHECK DECODER, A STORAGE DEVICE INCLUDING THE SAME, AND A METHOD | 01-25-2018 |
20180026661 | CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF | 01-25-2018 |
20190146691 | Method and Apparatus for Flexible RAID in SSD | 05-16-2019 |
20190146703 | MEMORY DEVICE HAVING GLOBAL LINE GROUPS IN WHICH DATA INPUT AND OUTPUT UNITS ARE DIFFERENT FROM EACH OTHER | 05-16-2019 |
20190146711 | CONTENTION AVOIDANCE ON ASSOCIATIVE COMMUTATIVE UPDATES | 05-16-2019 |
20190146866 | UPDATING RELIABILITY DATA | 05-16-2019 |
20190146868 | REDUNDANT STORAGE OF ERROR CORRECTION CODE (ECC) CHECKBITS FOR VALIDATING PROPER OPERATION OF A STATIC RANDOM ACCESS MEMORY (SRAM) | 05-16-2019 |
20190146869 | SYSTEMS AND METHODS FOR PERFORMING A WRITE PATTERN IN MEMORY DEVICES | 05-16-2019 |
20190146871 | MEMORY CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF DRIVING THE SEMICONDUCTOR MEMORY SYSTEM | 05-16-2019 |
20190146873 | FAST SEARCH OF ERROR CORRECTION CODE (ECC) PROTECTED DATA IN A MEMORY | 05-16-2019 |
20190146874 | PROTECTING IN-MEMORY CONFIGURATION STATE REGISTERS | 05-16-2019 |
20190146876 | SLICE REBUILDING IN A DISPERSED STORAGE NETWORK | 05-16-2019 |
20190146877 | ALLOCATING REBUILDING QUEUE ENTRIES IN A DISPERSED STORAGE NETWORK | 05-16-2019 |
20190149175 | STOPPING CRITERIA FOR LAYERED ITERATIVE ERROR CORRECTION | 05-16-2019 |
20220137833 | METHOD, ELECTRONIC DEVICE, AND COMPUTER PROGRAM PRODUCT FOR MANAGING STORAGE SYSTEM - Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for managing a storage system. The method includes: if it is determined that a first storage unit of the storage system is faulty, writing a data block stored in the first storage unit into a hidden file of the storage system, wherein the hidden file is distributed across at least a second storage unit and a third storage unit of the storage system, and the second storage unit and the third storage unit are different from the first storage unit. The embodiments of the present disclosure can better protect data in the storage system and improve the performance of the storage system, and are particularly beneficial to improving the performance of a delay-sensitive workflow. | 05-05-2022 |