| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714759000 | Look-up table encoding or decoding | 23 |
| 20080215953 | THREE BIT ERROR DETECTION USING ECC CODES - An Error Correction Code (ECC) encoding module encodes an input data word by calculating parity bits according to an ECC index mapping. An ECC correction/detection module receives the encoded data word that may have become corrupted due to noise or distortion. The ECC correction/detection module executes a parity calculation on the encoded data word based on the ECC index mapping. Based on the parity calculation, the ECC correction/detection module can detect and correct a single bit error, detect if there is an error to an even number of bits, and detect the occurrence of a three consecutive bit burst error. | 09-04-2008 |
| 20080229175 | METHOD AND APPARATUS FOR PROVIDING HELP UPON USER'S WRONG BUTTON MANIPULATION - A method and apparatus for providing help upon a user's wrong button manipulation, the method including: obtaining information on a user's button manipulation; checking whether an error pattern is detected in the button manipulation, using the information on button manipulation; and if the error pattern is detected, providing help information corresponding to the detected error pattern. According to the present invention, information on a user's button manipulation in a device is obtained, an error or malfunction pattern due to the user's wrong button manipulation is detected, and help information is provided in order to allow the user to return to the right process or prevent the error next time. | 09-18-2008 |
| 20080307289 | Method for efficiently calculating syndromes in reed-solomon decoding, and machine-readable storage medium storing instructions for executing the method - A method for efficiently calculating syndromes in Reed-Solomon decoding is adapted to be implemented in a processor having a parallel processing instruction set. The method includes: (a) initializing a syndrome vector; (b) obtaining a symbol from a Reed-Solomon block code; (c) finding a lookup index based on the symbol; (d) using the parallel processing instruction set, obtaining a finite field product vector Corresponding to the lookup index from a finite field vector multiplication table that includes at least one finite field product vector; (e) using the parallel processing instruction set, performing vector finite field addition on the finite field product vector corresponding to the lookup index and the syndrome vector, thereby obtaining an updated syndrome vector; and (f) outputting the updated syndrome vector. | 12-11-2008 |
| 20090031193 | SYNDROME-ERROR MAPPING METHOD FOR DECODING LINEAR AND CYCLIC CODES - A decoding method is presented for error-correcting codes based on the syndrome decoding scheme, which means the set of all syndromes is one-to-one corresponding to the set of all correctable error patterns. The improvement in the high-speed error-correcting capability is achieved by searching a syndrome-error table, which is built upon the mathematical basis: there is a one-to-one correspondence between the set of all syndromes and the set of all correctable error patterns. | 01-29-2009 |
| 20090055712 | Data processing method and computer system medium thereof - A data processing method includes the steps of: initializing a syndrome vector to be an (n−1) | 02-26-2009 |
| 20090158121 | APPARATUS AND METHOD FOR DECODING LDPC CODE BASED ON PROTOTYPE PARITY CHECK MATRIXES - Provided is an apparatus and method for decoding a Low Density Parity Check (LDPC) code based on prototype parity check matrixes. The apparatus, includes: a parity check matrix selecting means for determining multiple prototype parity check matrixes according to a sub-matrix size and a parallelization figure for processing the parity check matrix; a bit input means for receiving a log likelihood probability value for input bit according to the sub-matrix size and the parallelization figure; a check matrix process means for sequentially performing a partial parallel process on the parity check matrix based on the received log likelihood probability value and the determined multiple prototype parity check matrixes; and a bit process means for determining a bit level based on the partial-parallel processed parity check matrix value and recovering the input bit according to the sub-matrix size and the parallelization figure. | 06-18-2009 |
| 20100180179 | PROTECTING AND MIGRATING MEMORY LINES - A data protection method is provided. The method includes receiving data; generating compressed data based on the data; determining a degree of compressibility based on the compressed data; determining an amount of free space based on the degree of compressibility; and setting one or more error bits based on the amount of free space. | 07-15-2010 |
| 20110145677 | METHOD AND SYSTEM FOR FAST TWO BIT ERROR CORRECTION - An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial. | 06-16-2011 |
| 20110179336 | MODE SELECTION FOR DATA TRANSMISSION IN WIRELESS COMMUNICATION CHANNELS BASED ON STATISTICAL PARAMETERS - A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a receive unit. The data is initially transmitted in an initial mode and the selection of the subsequent mode is based on a selection of first-order and second-order statistical parameters of short-term and long-term quality parameters. Suitable short-term quality parameters include signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR), power level and suitable long-term quality parameters include error rates such as bit error rate (BER) and packet error rate (PER). The method of the invention can be employed in Multiple Input Multiple Output (MIMO), Multiple Input Single Output (MISO), Single Input Single Output (SISO) and Single Input Multiple Output (SIMO) communication systems to make subsequent mode selection faster and more efficient. Furthermore the method can be used in communication systems employing various transmission protocols including OFDMA, FDMA, CDMA, TDMA. | 07-21-2011 |
| 20110246855 | Method and Apparatus of Generating a Soft Value for a Memory Device - A method and apparatus of generating the soft value for a memory device is disclosed. Memory read-related parameters are set, and data are read out of the memory device according to the set parameters. The data reading is performed for pre-determined plural iterations, thereby obtaining the soft value according to the read-out data and the set parameters. | 10-06-2011 |
| 20130080855 | METHODS AND APPARATUS FOR SEARCH SPHERE LINEAR BLOCK DECODING - A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors. | 03-28-2013 |
| 20130191700 | BIT ERROR RATE BASED WEAR LEVELING FOR SOLID STATE DRIVE MEMORY - According to exemplary embodiments, a system, method, and computer program product are provided for BER-based wear leveling in a SSD. A block-level BER value for a block in the SSD is determined. An adjusted PE cycle count for the block is incremented or decremented based on the block-level BER value. Wear leveling is then performed in the SSD based on the adjusted PE cycle count. | 07-25-2013 |
| 20140181617 | MANAGEMENT OF NON-VALID DECISION PATTERNS OF A SOFT READ RETRY OPERATION - An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry. | 06-26-2014 |
| 20140281800 | SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING - A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword. | 09-18-2014 |
| 20140325305 | CACHE FOR FILE-BASED DISPERSED STORAGE - A method obtains at least part of a file from a dispersed storage network (DSN) memory, and stores it in a data object cache. When the file is changed, a determination is made about where to store the changed file portions: in the data object cache or in the DSN. The changed file portions, for example a new copy of the part of the file obtained from the DSN, are encoded utilizing an error coding dispersal storage function, and stored in either the data object cache, or in the DSN memory. | 10-30-2014 |
| 20140344641 | MEMORY SYSTEM AND CACHE MANAGEMENT METHOD OF THE SAME - A memory system includes data lines, cache lines temporarily storing data of the data lines, an error correction circuit reading the data stored in each of the cache lines, detecting or correcting errors in the read data, calculating error rates according to each type of the detected errors, and accumulating the calculated error rates on previous error rates, an error rate table storing the accumulated error rates, and a line allocator allocating the cache lines corresponding to the data lines by using the error rate table, wherein cache lines whose accumulated error rates are greater than a predetermined value are not allocated. | 11-20-2014 |
| 20140344642 | MODULATION/DEMODULATION METHOD, DEMODULATION APPARATUS, AND CODE MODULATION METHOD - Patterns that might be generated due to a burst error are prepared beforehand. These patterns are formed by shifting all “1”s in an original channel word. A list of these patterns generated as described above is retrieved in parallel with a general conversion table during demodulation. When the demodulation is interrupted due to the burst error, the result of the retrieval of the previous pattern is referred to, and when there is a hit, the error is regarded as the burst error of the original channel word, and the demodulation is continued. | 11-20-2014 |
| 20150067441 | COMPUTING DEVICE STORING LOOK-UP TABLES FOR COMPUTATION OF A FUNCTION - A computing device is provide, configured to compute a function of one or more inputs, the device comprising a storage device storing one or more look-up tables used in the computation of said function, the look-up tables mapping input values to output values, the look-up table being constructed with respect to the first error correcting code, a second error correcting code, a first error threshold and a second error threshold, such that any two input values ( | 03-05-2015 |
| 20150074488 | DYNAMIC DISTRIBUTION OF CODE WORDS AMONG MULTIPLE DECODERS - A device comprising a data transfer channel is configured to transfer data between multiple memory devices and a host device. The channel includes multiple decoders and a buffer coupled between the multiple memory devices and the multiple decoders. The buffer is configured to store code words received from the memory devices. Channel control logic is configured to determine availability of one or more of the multiple decoders and to distribute the code words to the one or more decoders based on decoder availability. | 03-12-2015 |
| 20150095739 | METHOD & IMPLEMENTATION FOR NETWORK COEFFICENTS SELECTION - A method and apparatus that improves the performance of TCP (and other protocols) in a data network by implementing segmenting the TCP path and implementing a proprietary protocol (DPR™) over the network. The DPR™ protocol provides a multiplexed tunnel for a multiplicity of TCP sessions from a client to a cloud proxy. DPR™ implements congestion management, flow control, reliability, and link monitoring. Other network protocols (such as UDP) are supported with a reliability protocol based upon network coding that improves the transmission reliability. A network and a method for transmitting processes in a network are disclosed, using deterministic coefficients for encoding packets based on network coding principles. Disclosed is a method and implementation for using deterministic coefficients for encoding packets based on network coding principles. The use of deterministic coefficients reduces the need for extra information to be transmitted to recover the lost packets and results in significantly reduced overhead and increased performance, security and reliability. | 04-02-2015 |
| 20150149856 | DECODING WITH LOG LIKELIHOOD RATIOS STORED IN A CONTROLLER - An apparatus having one or more lookup tables and a decoder is disclosed. The lookup tables are configured to store a plurality of sets of values of log likelihood ratios. The decoder is configured to (i) receive a codeword read from a memory, (ii) receive an initial one of the sets from the lookup tables and (iii) generate read data by decoding the codeword based on the values. | 05-28-2015 |
| 20150365107 | DATA TRANSMISSION METHOD AND APPARATUS - A data transmission method and apparatus, which can improve transmission efficiency and securely perform communication without increasing the bandwidth of encrypted data in an environment in which a transmission success rate for encrypted data is changeable depending on the quality of a network. In the method, a network quality of a channel is measured, and a lossy compression scheme or a lossless compression scheme is selected depending on results of measurement. Original data to be transmitted is compressed so that the original data is compressed using the selected compression scheme. Compressed data is encrypted. ECC encoding is performed on encrypted data, and ECC-encoded data is interleaved. | 12-17-2015 |
| 20160182086 | SYSTEMS AND METHODS FOR SOFT DECISION GENERATION IN A SOLID STATE MEMORY SYSTEM | 06-23-2016 |
