| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714754000 | Error correction during refresh cycle | 11 |
| 20080222483 | Method, system, and apparatus for distributed decoding during prolonged refresh - Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode. | 09-11-2008 |
| 20080235555 | METHOD, APPARATUS, AND SYSTEM FOR RETENTION-TIME CONTROL AND ERROR MANAGEMENT IN A CACHE SYSTEM COMPRISING DYNAMIC STORAGE - Methods, systems, and apparatuses are provided for operating a cache comprising dynamic storage having an array of cells. At a refresh interval, the array of cells of the cache is refreshed. A determination is made whether an error is found in the cache at the refresh interval. If no error is found in the cache, the refresh interval is repeatedly increased by a predetermined amount until an error is found. If an error is found, the error is recovered from. A determination is made if a number of line deletions for the cache is a maximum number of line deletions for the cache. If the maximum number of line deletions is not attained, a line having the error is deleted, and the number of line deletions for the cache is increased. If the maximum number of line deletions for the cache is attained, the refresh interval is decreased by the predetermined amount. | 09-25-2008 |
| 20110060961 | MEMORY CONTROLLER METHOD AND SYSTEM COMPENSATING FOR MEMORY CELL DATA LOSSES - A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh. | 03-10-2011 |
| 20120036411 | METHOD, SYSTEM, AND APPARATUS FOR DISTRIBUTED DECODING DURING PROLONGED REFRESH - Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode. | 02-09-2012 |
| 20120159280 | METHOD FOR CONTROLLING NONVOLATILE MEMORY APPARATUS - There is provided a method for controlling a nonvolatile memory apparatus in a nonvolatile memory system including a host interface, a memory controller, and a memory area. The method includes: checking a number of ECC fail bits, determining whether or not to replace a corresponding block, and replacing the block, while a read command provided from the host interface is performed; and replacing a block, which was not replaced during the read operation, with a block to be used as a replacement target during a write operation. | 06-21-2012 |
| 20130139029 | MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA - A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells. | 05-30-2013 |
| 20140181613 | MEMORY CONTROLLER METHOD AND SYSTEM COMPENSATING FOR MEMORY CELL DATA LOSSES - A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal refresh of the memory cells. Upon power-up, the data from the non-volatile memory are transferred to a comparator in the memory controller. The comparator compares the row addresses to row addresses from a refresh shadow counter that identify the rows in the DRAMs being refreshed. When a row of memory cells is being refreshed that is located one-half of the rows away from a row that is likely to loose data, the memory controller causes the row that is likely to loose data to be refreshed. The memory controller also includes error checking circuitry for identifying the rows of memory cells that are likely to lose data during refresh. | 06-26-2014 |
| 20140359391 | MEMORY SYSTEM AND METHOD USING PARTIAL ECC TO ACHIEVE LOW POWER REFRESH AND FAST ACCESS TO DATA - A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells. | 12-04-2014 |
| 20140372827 | PULSED-LATCH BASED RAZOR WITH 1-CYCLE ERROR RECOVERY SCHEME - Systems and methods for error recovery include determining an error in at least one stage of a plurality of stages during a first cycle on a hardware circuit, each of the plurality of stages having a main latch and a shadow latch. A first signal is transmitted to an output stage of the at least one stage to stall the main latch and the shadow latch of the output stage during a second cycle. A second signal is transmitted to an input stage of the at least one stage to stall the main latch of the input stage during the second cycle and to stall the main latch and the shadow latch of the input stage during a third cycle. Data is restored from the shadow latch to the main latch for the at least one stage and the input stage to recover from the error. | 12-18-2014 |
| 20150121163 | MEMORY SYSTEM DATA MANAGEMENT - The present disclosure includes apparatuses and methods for memory system data management. A number of embodiments include writing data from a host to a buffer in the memory system, receiving, at the buffer, a notification from a memory device in the memory system that the memory device is ready to receive data, sending at least a portion of the data from the buffer to the memory device, and writing the portion of the data to the memory device. | 04-30-2015 |
| 20190147936 | MEMORY DEVICE AND OPERATING METHOD THEREOF | 05-16-2019 |
