| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714736000 | Device response compared to expected fault-free response | 22 |
| 20080282124 | Predictive run testing - A test object can be selectively included in a test run based on predicting the behavior of the test object. In one embodiment, the present invention includes predicting how likely the test object is to produce a failure in a test run and deciding whether to include the test object in the test run based on the predicted likelihood. This likelihood of producing a failure may be based on any number of circumstances. For example, these circumstances may include the history of prior failures and/or the length of time since the test object was last included in a test run. | 11-13-2008 |
| 20080301512 | SEMICONDUCTOR TEST SYSTEM - A semiconductor test system includes: pin electronics (“PE”) cards each being operable to: a) apply a test pattern to device under tests (“DUTs”) each connected to the PE cards; b) capture patterns outputted in response to the test pattern from the DUTs; c) compare the patterns with an expected value pattern; and d) determine whether or not the patterns correspond with the expected value pattern, and a fail control card being operable to: e) aggregate fail information about the DUTs inputted through the PE cards every the DUTs; and f) transfer the fail information to the PE cards. | 12-04-2008 |
| 20080307282 | System and Method for Electronic Device Development - A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT. | 12-11-2008 |
| 20090024890 | CIRCUIT ARRANGEMENT, DATA PROCESSING DEVICE COMPRISING SUCH CIRCUIT ARRANGEMENT AS WELL AS METHOD FOR IDENTIFYING AN ATTACK ON SUCH CIRCUIT ARRANGEMENT - In order to further develop a circuit arrangement ( | 01-22-2009 |
| 20090292964 | Method and System for Testing an Electronic Circuit to Identify Multiple Defects - A method for testing an electronic circuit comprises selecting a plurality of test patterns arranged in an order. The method tests an electronic circuit by applying to the electronic circuit a first subset range of the plurality of test patterns sequentially in the order, from a first test pattern to a first log interval after the first test pattern, thereby generating a first associated output. The method compares the first associated output with a first known output of the plurality of known outputs. In the event the first associated output does not match the first known output, the method stores indicia of the first mismatch; causes the electronic circuit to appear to assume the first known output state; and proceeds with additional test procedures. | 11-26-2009 |
| 20100153800 | LOGIC TESTER AND METHOD FOR SIMULTANEOUSLY MEASURING DELAY PERIODS OF MULTIPLE TESTED DEVICES - The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the tested devices to fix output signals of the tested devices to a first value, and then generates a functional code sequence as the input signal of the tested devices to trigger the output signals of the tested devices to change from the first value to a second value. The pattern comparator converts the output signals of the tested devices to a plurality of bitstreams after the functional code sequence is generated, calculates numbers of bits corresponding to the first value in the bitstreams, estimates delay periods of the tested devices according to the numbers of bits, and outputs the delay periods of the tested devices. | 06-17-2010 |
| 20100281320 | METHOD FOR ACCURACY IMPROVEMENT ALLOWING CHIP-BY-CHIP MEASUREMENT CORRECTION - A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circuit chip. The error correction values are stored within an error correction table within a nonvolatile memory of the integrated circuit chip. | 11-04-2010 |
| 20100306608 | Circuit States - Systems and methods for deriving a net equation representing a net state of an analog circuit net, wherein the net equation is derived from at least one other net state, determining a truthfulness of the net equation, reporting the truthfulness. | 12-02-2010 |
| 20110138242 | METHOD AND APPARATUS FOR SELECTIVELY COMPACTING TEST RESPONSES - A method and apparatus to compact test responses containing unknown values or multiple fault effects in a deterministic test environment. The proposed selective compactor employs a linear compactor with selection circuitry for selectively passing test responses to the compactor. In one embodiment, gating logic is controlled by a control register, a decoder, and flag registers. This circuitry, in conjunction with any conventional parallel test-response compaction scheme, allows control circuitry to selectively enable serial outputs of desired scan chains to be fed into a parallel compactor at a particular clock rate. A first flag register determines whether all, or only some, scan chain outputs are enabled and fed through the compactor. A second flag register determines if the scan chain selected by the selector register is enabled and all other scan chains are disabled, or the selected scan chain is disabled and all other scan chains are enabled. Other embodiments allow selective masking of a variable number of scan chain outputs. | 06-09-2011 |
| 20110264973 | METHODS AND SYSTEMS FOR TESTING ELECTRONIC CIRCUITS - A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion to be tested, a comparator and a comparison result recorder. The circuit portion to be tested receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. Then, the comparator outputs a comparison result according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The comparison result recorder may record comparison results within a period of test time. The test instrument can obtain a record of the comparison results from the comparison result recorder. | 10-27-2011 |
| 20110271161 | On-Chip Non-Volatile Storage of a Test-Time Profile for Efficiency and Performance Control - Mechanisms for controlling an operation of one or more cores on an integrated circuit chip are provided. The mechanisms retrieve, from an on-chip non-volatile memory of the integrated circuit chip, baseline chip characteristics data representing operational characteristics of the one or more cores prior to the integrated circuit chip being operational in the data processing system. Current operational characteristics data of the one or more cores are compared with the baseline chip characteristics data. Deviations of the current operational characteristics data from the baseline chip characteristics data are determined and used to determine modifications to an operation of the one or more cores. Control signals are sent to one or more on-chip management units based on the determined modifications to cause the operation of the one or more cores to be modified. | 11-03-2011 |
| 20130073918 | CIRCUITRY TESTING MODULE AND CIRCUITRY TESTING DEVICE - A circuitry testing module for testing an external circuit of a Light-Emitting Diode (LED) includes at least one logic unit and a latch circuit. Two input terminals of the at least one logic unit are connected to a first end and a second of the LED correspondingly. The output terminal of the at least one logic unit is connected to the latch circuit. If the external circuit works normally, the logic unit outputs a first logic operating signal to the latch unit, and the latch circuit outputs a first latch signal. If the external circuit does not work normally, the logic unit outputs a second logic operating signal to the latch unit, and the latch circuit outputs a second latch signal. | 03-21-2013 |
| 20140040692 | ERROR PREDICTION IN LOGIC AND MEMORY DEVICES - Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example. | 02-06-2014 |
| 20140164862 | ELECTRONIC DEVICE TESTING SYSTEM AND METHOD - An electronic device testing system is configured to test an electronic device which generates a plurality of signals while running. The electronic device testing system includes a programmable logic device (PLD) configured to monitor and control the electronic device and a computer connected to the PLD. The PLD includes a read/write control module connected to the electronic device and a controller connected to the read/write control module. The read/write control module reads the plurality of signals generated by the electronic device. The controller determines whether the plurality of signals has errors and sends error signals to the computer. The computer analyzes the error signals and displays problems associated with the error signals. The present disclosure further discloses an electronic device testing method based upon the above testing system. | 06-12-2014 |
| 20140258800 | SYSTEMS AND METHODS FOR DETECTING ABNORMALITIES WITHIN A CIRCUIT OF AN ELECTROSURGICAL GENERATOR - An electrosurgical generator includes primary and test sources. The primary source supplies a primary signal and the test source supplies a test signal. The electrosurgical generator includes an output circuit and an abnormality detection circuit. The output circuit is electrically coupled to the primary and test sources. The output circuit receives the primary and test signals from the primary and test sources, respectively. The output circuit is electrically coupled to a load to supply the primary signal thereto. The abnormality detection circuit is electrically coupled to the output circuit to detect an abnormality therein as a function of the test signal. The abnormality detection circuit can also determine a location of the abnormality within the output circuit. | 09-11-2014 |
| 20150095734 | DETECTING HIDDEN FAULT USING FAULT DETECTION CIRCUIT - Embodiments of the present invention disclose a hidden fault detection circuit and a method of detecting a hidden fault using the hidden fault detection circuit. The hidden fault detection circuit comprises a function module for indicating a working state of an integrated circuit board to which the hidden fault detection circuit belongs; and a hidden fault detection module for detecting a hidden fault existing in the function module according to output of the function module. The hidden fault may be detected and eliminated according to embodiments of the present invention. | 04-02-2015 |
| 20160018463 | SIGNAL PROCESSING APPARATUS - A signal processing apparatus includes a recording unit, an operation unit, a processing unit and an abnormality detector. The recording unit records configuration data therein. The operation unit performs arithmetic and logical operations on an input signal and outputs an operation signal indicative of the result of the operations. The operation unit has a circuit configuration defined by the configuration data recorded in the recording unit. The processing unit acquires the operation signal outputted from the operation unit, produces an output signal based on the acquired operation signal and outputs the produced output signal. The abnormality detector detects an abnormality of the circuit configuration of the operation unit. Moreover, in the signal processing apparatus, the processing unit is configured to further acquire an abnormality detection result from the abnormality detector after the acquisition of the operation signal and output the output signal depending on the abnormality detection result. | 01-21-2016 |
| 20160054388 | DEBUGGING CIRCUIT, DEBUGGER DEVICE, AND DEBUGGING METHOD - A debugging circuit including: a storage configured to store a first code value which is calculated by an encoding method in which a value is changed according to a sequence of a signal in a debugging target circuit, and indicates a stop condition of the debugging target circuit; a code value calculator configured to calculate a second code value by the encoding method based on the signal each time when the signal is changed; and an operation stopper configured to stop an operation of the debugging target circuit when the first code value and the second code value are identical to each other. | 02-25-2016 |
| 20160097810 | SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor device and a method for testing the same are provided. The semiconductor device includes a plurality of semiconductor dies staked, a plurality of through-electrodes disposed between the semiconductor dies, a first calculation unit calculating a first output value from input signals inputted into the through-electrodes by a logical operation, a second calculation unit calculating a second output value from output signals outputted from the through-electrodes by a logical operation, and a comparator comparing the first output value with the second output value. | 04-07-2016 |
| 20160169970 | CYCLE ACCURATE AND CYCLE REPRODUCIBLE MEMORY FOR AN FPGA BASED HARDWARE ACCELERATOR | 06-16-2016 |
| 20160179647 | TEST LOGIC FOR A SERIAL INTERCONNECT | 06-23-2016 |
| 20160377680 | EFFICIENCY OF CYCLE-REPRODUCIBLE DEBUG PROCESSES IN A MULTI-CORE ENVIRONMENT - An approach for improving efficiency of cycle-reproducible debug in a multi-core environment is provided. The approach executes an exerciser image on one or more cores, wherein the exerciser image includes one or more different seeds. The approach determines a seed from the one or more different seeds that locates a fail-condition. Responsive to determining a seed from the one or more different seeds that locates the fail condition, the approach determines an upper bound and a lower bound of the fail-condition. The approach determines an exact cycle where the fail-condition occurs. The approach constructs a multi-cycle trace for the fail-condition. | 12-29-2016 |
