| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714735000 | Device response compared to input pattern | 24 |
| 20080209294 | BUILT-IN SELF TESTING OF A FLASH MEMORY - The present invention relates to a built-in self test of a flash memory device in a data processing device, particularly a mobile terminal, comprising a flash-memory having a plurality of data blocks, a data block memory for temporarily storing a data block of said data blocks, a CPU and a test memory comprising a stored test program executable by the CPU, wherein the method comprises:
| 08-28-2008 |
| 20080229166 | Accelerating Test, Debug and Failure Analysis of a Multiprocessor Device - A mechanism for accelerating test, debug and failure analysis of a multiprocessor device is provided. With the mechanism, on-chip trace logic is utilized to receive internal signals from logic provided in modules of the multiprocessor device. The modules are preferably copies of one another such that, given the same inputs, each module should operate in the same manner and generate the same output as long as the modules are operating properly. The modules are provided with the same inputs and the internal signals of the modules are traced using an on-chip trace bus and on-chip trace logic analyzer to perform the trace. The internal signals from one module are compared against another module so as to determine if there is any discrepancy which would indicate a fault. Additional pairs of modules may be compared to pinpoint a faulty module that is the source of the fault. | 09-18-2008 |
| 20080270864 | DIFFERENCE SIGNAL PATH TEST AND CHARACTERIZATION CIRCUIT - A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points. | 10-30-2008 |
| 20090077440 | Apparatus and method for verifying target cicuit - A circuit verifying method is provided for a logic circuit of a first sequential circuit which outputs a first data based on an input data in synchronization with a first clock signal, and a second sequential circuit which outputs a second data based on the first data in synchronization with a second clock signal with a period longer than that of a first clock signal. The circuit verifying method includes detecting a change of the input data in synchronization with the first clock signal; outputting a data indicating a meta stable state during a period longer than one period of the first clock signal based on the change of the input data as the first data; storing the changed input data in a storage unit based on the change of the input data; and outputting the changed input data which has been stored in the storage unit as the first data after stop the output of the data indicating the meta stable state. | 03-19-2009 |
| 20090094497 | DATA INVERSION REGISTER TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY TESTING - A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester. | 04-09-2009 |
| 20090172489 | CIRCUIT ARRANGEMENT AND METHOD FOR CHECKING THE FUNCTION OF A LOGIC CIRCUIT IN A CIRCUIT ARRANGEMENT - A circuit arrangement comprising a logic circuit to be tested and a test circuit is provided. The logic circuit is designed to provide output data from input data, said output data being generated from the input data by logic-circuit-internal combinations, such that the output data are in a predetermined relationship with the input data. The logic circuit is designed to detect whether the relationship is fulfilled and to provide an error signal if the relationship is not fulfilled. The test circuit is designed to alter logic-circuit-internal combinations. The test circuit is designed to detect the error signal, and is furthermore designed to output an alarm signal if the error signal is not detected upon alteration of the logic-circuit-internal combinations. | 07-02-2009 |
| 20100011266 | PROGRAM VERIFY METHOD FOR OTP MEMORIES - A method for executing a program verify operation in a non-volatile memory. A data register having master and slave latching circuits is used for concurrently storing two different words of data. In a program operation, the master latch stores program data which is used for programming selected memory cells. In a program verify operation, the data programmed to the memory cells are read out and stored in the slave latches. In each data register stage, the logic states of both latches are compared to each other, and a status signal corresponding to a program pass condition is generated if opposite logic states are stored in both latches. The master latch in each stage is inverted if programming was successful, in order to prevent re-programming of that bit of data. | 01-14-2010 |
| 20100153799 | METHOD AND APPARATUS FOR LOOPBACK SELF TESTING - A system and method for loopback self testing. A system includes a host device and an endpoint device. The host device transmits unencoded test symbols. The endpoint device loops back the unencoded test symbols to the host device. The host device drives at least some bits of each unencoded test symbol onto host device data signals and drives at least some bits of each unencoded test symbol onto host device control signals. | 06-17-2010 |
| 20100162063 | Control of clock gating - Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock signal from a clock signal generator and for outputting said clock signal to synchronous circuitry that is to be clocked by said clock signal. It comprises: an input for receiving mode switching signals indicating said synchronous circuitry is to switch between modes, said mode switching signals comprising a clock gating request signal indicating said synchronous circuitry is to enter a sleep mode during which said circuitry is not clocked and a wake up request signal indicating said synchronous circuitry is to enter an operational mode during which said circuitry is clocked; and is responsive to said clock gating request signal to gate said clock signal such that no clock signal is output to said synchronous circuitry and being responsive to said wake up request signal to output said clock signal to said synchronous circuitry. The clock signal control circuitry further comprises: a data store for storing a delay value; and delay circuitry for delaying switching of said clock signal between modes in response to at least one of said mode switching signals, said delay circuitry delaying said switching by an amount dependent upon said stored delay value. | 06-24-2010 |
| 20100235699 | FAULT DIAGNOSIS APPARATUS AND FAULT DIAGNOSIS METHOD OF MULTI-CHANNEL ANALOG INPUT/OUTPUT CIRCUIT - A fault diagnosis apparatus and method capable of simultaneously detecting the fault of a multiplexer and the fault of an A/D converter and isolating and identifying causes of these faults, the multiplexer and the A/D converter being used in a multi-channel analog input/output circuit. Test-voltage values are inputted from a diagnosis-voltage input unit into the multiplexer and the A/D converter constituting an analog-signal conversion unit, the multiplexer having plural channels, the A/D converter converting outputs from the multiplexer into digital signals, the test-voltage values being different from each other for each channel of the multiplexer. Comparisons are made between the digital voltage values and the test-voltage values inputted, the digital voltage values being outputted for each channel of the multiplexer. From this comparison result, it is judged whether the multiplexer is at fault or the A/D converter is at fault. | 09-16-2010 |
| 20120124441 | EMBEDDED TESTING MODULE AND TESTING METHOD THEREOF - The present invention discloses an embedded testing module and testing method thereof which encodes one or more test commands to reduce the storage space required by a testing memory. In addition, most functions of automatic test equipment can be replaced by the present invention, in which, through the testing memory according to the present invention, if errors are found during testing, the error information will be transmitted to the external automatic test equipment and the error information can be optionally recorded in a memory. A test operator can get detailed descriptions from the error information stored in the memory, so the test operator can save time for subsequent debugging and tracking operations concerning the errors. | 05-17-2012 |
| 20130227366 | SEMI-AUTOMATIC CONVERSION AND EXECUTION OF FUNCTIONAL MANUAL TESTS - Embodiments of the invention relate to the conversion and execution of functional tests. In one embodiment, a current test step of a manual functional test is executed. The test includes a set of test steps each including at least one action and one target of the action. The test is associated with an application that includes a plurality of objects to be tested. At least two of the objects are determined to be associated with the target of the test step. A user is prompted to provide a selection of one of the at least objects for association with the target of the test step. A new test step is generated. The new test step associates the object selected by the user with the target of the current test step. The new test step is designated for automatic execution in place of the current test step for subsequent executions thereof. | 08-29-2013 |
| 20130227367 | Test IP-Based A.T.E. Instrument Architecture - A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus. The test program stored on the controller, and the controller, instantiates interfaces and protocols, and certain process transactions to support the protocols, into FPGAs, to match device interfaces for each DUT, to execute test sequences. | 08-29-2013 |
| 20130326299 | TESTER HARDWARE - A server stores multiple configuration data. A tester hardware is configured to be capable of changing at least a part of its functions according to configuration data stored in rewritable nonvolatile memory, to supply a power supply voltage to a DUT, to transmit a signal to the DUT, and to receive a signal from the DUT. An information technology equipment is configured such that, (i) when the test system is set up, the information technology equipment acquires the configuration data from the server according to the user's input, and writes the configuration data to the nonvolatile memory. Furthermore, the information technology equipment is configured such that, (ii) when the DUT is tested, the information technology equipment executes a test program so as to control the tester hardware, and to process data acquired by the tester hardware. | 12-05-2013 |
| 20130326300 | TERMINATION CIRCUIT, SEMICONDUCTOR DEVICE, AND TEST SYSTEM - A termination circuit includes a pMOS transistor configured to have a source connected with a signal terminal outputting or inputting a transmission signal, a drain connected with a grounding line, and a gate receiving a control signal, the pMOS transistor being turned on when enabling a characteristic impedance matching function and being turned off when disabling the matching function; and an inductor and a capacitor configured to be connected with the signal terminal for matching characteristic impedance. | 12-05-2013 |
| 20140195870 | METHODS AND SYSTEMS FOR TESTING ELECTRONIC CIRCUITS - A system for testing electronic circuits is configured to receive a test signal and an ideal response signal and output a test result signal. The system for testing electronic circuits includes a circuit portion under test, a comparator and a comparison result recorder. The circuit portion under test receives a test signal from a test instrument, and outputs a system response signal. The comparator receives the system response signal from the circuit portion to be tested and receives an ideal response signal from the test instrument. The comparator outputs comparison results according to the system response signal and the ideal response signal. The comparison result recorder receives and records the comparison result. The system receives at least a portion of test signals and at least a portion of ideal response signals in a dynamically configurable time-interleaved manner via one or more physical channels from a test equipment. | 07-10-2014 |
| 20150121159 | SEMICONDUCTOR INTEGRATED CIRCUIT - There is provided a semiconductor integrated circuit, including a test circuit, a plurality of signal cells, a power supply cell, and a control circuit. The test circuit performs a predetermined test on a test target circuit. A plurality of signal cells input an input signal into the test circuit and the test target circuit. The power supply cell supplies power to some of the plurality of signal cells in the test. The control circuit controls a value of the input signal from signal cells that include signal cells to which the power is not supplied and that are not used in the test, to be a predetermined value. | 04-30-2015 |
| 20150135030 | SPEEDING UP DEFECT DIAGNOSIS TECHNIQUES - Fault diagnosis techniques (e.g., effect-cause diagnosis techniques) can be speeded up by, for example, using a relatively small dictionary. Examples described herein exhibit a speed up of effect-cause diagnosis by up to about 160 times. The technologies can be used to diagnose defects using compacted fail data produced by test response compactors. A dictionary of small size can be used to reduce the size of a fault candidate list and also to facilitate procedures to select a subset of passing patterns for simulation. Critical path tracing can be used to handle failing patterns with a larger number of failing bits, and a pre-computed small dictionary can be used to quickly find the initial candidates for failing patterns with a smaller number of failing bits. Also described herein are exemplary techniques for selecting passing patterns for fault simulation to identify faults in an electronic circuit. | 05-14-2015 |
| 20150369862 | EFFICIENT METHOD OF RETESTING INTEGRATED CIRCUITS - Efficient production testing of integrated circuits. A first production test is implemented on a group of integrated circuits and failures among the test group are assessed. Specifically, the results of the first test are analyzed such that integrated circuits having a recoverable fail and integrated circuits having a non-recoverable fail are differentiated. The integrated circuits are integrated based on the analyzed results and a second production test is implemented. The second production test tests the integrated circuits responsive to the segregation, such that the second production test is limited only to integrated circuits with a recoverable fail. The next succeeding production test will then use the new test program in the second production test with the handler bin designated as having integrated circuits not to be re-tested. | 12-24-2015 |
| 20160084906 | DEBUG CIRCUIT, SEMICONDUCTOR DEVICE, AND DEBUG METHOD - A debug circuit, includes: a controller to start a debugging of a circuit based on first and second code values, the first code value obtained by encoding a first sequence included in a processing sequence indicating a condition for a process of the circuit, the second code value obtained by encoding a second sequence subsequent to the first sequence, wherein the controller performs to: calculate a third code value as a current code value based on signals input and output to the circuit; output, as a fourth code value, a previous third code value that is earlier than the current code value; detect the first sequence by comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value; and perform the process when the third code value and the first expected value match. | 03-24-2016 |
| 20160139202 | TESTBENCH BUILDER, SYSTEM, DEVICE AND METHOD INCLUDING LATENCY DETECTION - A testbench for testing a device under test (DUT), wherein the testbench has a verification environment including a reference model, a scoreboard and a customized agent for each interface that the DUT needs to receive input from and/or transmit output on. The testbench system is able to be generated by a testbench builder that automatically creates a scoreboard, a reference model, a dispatcher and generic agents including generic drivers, loopback ports, sequencers and/or generic monitors for each interface and then automatically customize the generic agents based on their corresponding interface such that the agents meet the requirements of the interface for the DUT. | 05-19-2016 |
| 20160139203 | TEST SETTING CIRCUIT, SEMICONDUCTOR DEVICE, AND TEST SETTING METHOD - A test setting circuit includes a first detection unit suitable for detecting whether a first code is sequentially inputted based on a first sequence, at each of first to Nth steps, where N is a natural number; a second detection unit suitable for sequentially receiving a second code through the first to Nth steps, and detecting whether the second code that is sequentially inputted through the first to Nth steps has a value corresponding to a second sequence; and a test setting unit suitable for setting a test mode when it is detected that the first code and the second code are inputted to satisfy the first sequence and the second sequence. | 05-19-2016 |
| 20160377679 | INTERCONNECT RETIMER ENHANCEMENTS - A test mode signal is generated to include a test pattern and an error reporting sequence. The test mode signal is sent on link that includes one or more extension devices and two or more sublinks. The test mode signal is to be sent on a particular one of the sublinks and is to be used by a receiving device to identify errors on the particular sublink. The error reporting sequence is to be encoded with error information to describe error status of sublinks in the plurality of sublinks. | 12-29-2016 |
| 20220137125 | METHOD AND DEVICE FOR TESTING SYSTEM-ON-CHIP, ELECTRONIC DEVICE USING METHOD, AND COMPUTER READABLE STORAGE MEDIUM - A method for testing systems on a chip during manufacture obtains basic function information of intellectual property cores and relevant information of network on chip and generates one or more test names according to the basic function information, and the relevant information of the network on chip. The method invokes a pre-prepared integral script to construct a running environment configured to invoke basic function scripts of to-be-tested intellectual property cores one by one, according to each of the test names which are generated. The method also generates the results of testing. A related electronic device and a non-transitory storage medium are also disclosed. | 05-05-2022 |
