| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714734000 | Structural (in-circuit test) | 39 |
| 20080256408 | TEST APPARATUS AND PERFORMANCE BOARD FOR DIAGNOSIS - A test apparatus being capable of replacing a test module with the other kind of test module that tests device under tests by using the test module is provided. The test apparatus includes a plurality of test modules that transmit/receive signals to/from the device under tests to test the device under test; and a performance board for diagnosis that diagnose the plurality of test modules. The performance board for diagnosis including: a motherboard provided common to the plurality of test, modules; a circuit for diagnosis that transmits/receives a signal to/from each test module to diagnose the test module; a plurality of inter-board to module connectors that connect between the corresponding test module and the circuit for diagnosis; and
| 10-16-2008 |
| 20080282123 | System and Method of Multi-Frequency Integrated Circuit Testing - A system and method of multi-frequency integrated circuit testing with a method for testing a clocked logic type integrated circuit including creating exerciser code on the integrated circuit when the integrated circuit is operating at a first frequency, switching the integrated circuit to operating at a second frequency greater than the first frequency, and running the exerciser code on the integrated circuit when the integrated circuit is operating at the second frequency. | 11-13-2008 |
| 20090083599 | Hierarchical test response compaction for a plurality of logic blocks - In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed. | 03-26-2009 |
| 20090100306 | ELECTRONIC UNIT | 04-16-2009 |
| 20090150733 | TEST APPARATUS AND CALIBRATION METHOD - A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section. | 06-11-2009 |
| 20090150734 | TRI-STATE I/O PORT - The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block. | 06-11-2009 |
| 20090158107 | SYSTEM-ON-CHIP WITH MASTER/SLAVE DEBUG INTERFACE - A System-on-Chip (SOC) integrated circuit (IC) debugging system includes a plurality of SOC ICs connected to a shared debug bus. One of the plurality of SOC ICs is a master SOC IC having a master/slave debug interface and a user interface. The master/slave debug interface on the master SOC IC is a bidirectional debug interface operable to send and receive debug data between the SOC ICs and an external host system. The host system is connected to the at least one of the plurality of SOC ICs via the user interface. | 06-18-2009 |
| 20100011265 | INTEGRATED CIRCUIT CHIP AND CIRCUIT NETWORK - An integrated circuit chip includes a plurality of two-way transceivers capable of simultaneously transmitting and receiving signals, a switch circuit coupled to the plurality of two-way transceivers and to a given node to provide switchable couplings between the plurality of two-way transceivers and the given node, an interconnection information storage unit to store interconnection information, and a control circuit to set the couplings of the switch circuit in response to the interconnection information. | 01-14-2010 |
| 20100077270 | Concurrent Testing of Multiple Communication Devices - Testing a plurality of communication devices. A plurality of signals may be received from the plurality of communication devices. The plurality of signals may include a signal from each of the plurality of communication devices, where a first subset of the plurality of signals has a different frequency than a second subset of the plurality of signals. The received signals may be combined into a combined signal. The combined signal may be downconverted to a combined signal, e.g., by mixing the combined signal with an output from at least one local oscillator. The downconverting may generate a plurality of lower frequency signals, each corresponding to one of the plurality of received signals. Testing may be performed on each of the plurality of lower frequency signals. | 03-25-2010 |
| 20100088564 | SEMICONDUCTOR IC INCORPORATING A CO-DEBUGGING FUNCTION AND TEST SYSTEM - A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series. | 04-08-2010 |
| 20100095178 | OPTIMIZED JTAG INTERFACE - An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations. | 04-15-2010 |
| 20100100785 | INTEGRATED CIRCUIT WITH JTAG PORT, TAP LINKING MODULE, AND OFF-CHIP TAP INTERFACE PORT - An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC. | 04-22-2010 |
| 20100153797 | Apparatus and method of authenticating Joint Test Action Group (JTAG) - In an apparatus including a joint test action group (JTAG) authentication device, and a JTAG authentication method using the apparatus, the apparatus includes a joint test action group (JTAG) authentication device, the apparatus comprising a JTAG access circuit that determines whether to access a JTAG-compliant device according to a predetermined protocol that governs the JTAG-compliant device and the apparatus, wherein the JTAG access circuit at least one of inactivates at least one of inner bus lines and inner units and activates the at least one of the inner bus lines and the inner units according to whether the JTAG-compliant device is accessed. | 06-17-2010 |
| 20100153798 | SERIAL I/O USING JTAG TCK AND TMS SIGNALS - The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. | 06-17-2010 |
| 20100287431 | REDUCED SIGNALING INTERFACE METHOD AND APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 11-11-2010 |
| 20110010596 | TESTABLE CIRCUIT WITH INPUT/OUTPUT CELL FOR STANDARD CELL LIBRARY - A testable circuit includes a first function logic, an input output cell including an input/output unit and a first control multiplexer; and a first testing block is provided, wherein the input/output unit has at least a connection terminal. The first control multiplexer has an output port coupled to the connection terminal, a first input port coupled to the first functional logic, and a second input port. The first testing block is coupled between the first functional logic and the second input port, wherein when the testable circuit is under a testing mode, the first control multiplexer couples the second input port to the output port; and when the testable circuit is under a normal mode, the first control multiplexer couples the first input port to the output port. | 01-13-2011 |
| 20110029830 | INTEGRATED CIRCUIT (IC) WITH PRIMARY AND SECONDARY NETWORKS AND DEVICE CONTAINING SUCH AN IC - Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC. | 02-03-2011 |
| 20110107163 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 05-05-2011 |
| 20110119544 | User Guided Short Correction And Schematic Fix Visualization - Techniques for assisting a designer in correcting discrepancies identified in layout design data. A user interface may be provided listing identified shorts and relevant information related to those shorts. Still further, the user interface may allow a designer to selectively choose a subset of the identified shorts, and to designate or otherwise provide correction data for use to correct the shorts before performing a short isolation process on the selected shorts. Alternately or additionally a user interface may provide a designer with graphical images showing the correction that should be made by a designer to address an identified discrepancy in layout design data. | 05-19-2011 |
| 20110161762 | DOUBLE DATA RATE TEST INTERFACE AND ARCHITECTURE - A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. Additional features and embodiments of the device test architecture and reduced test interface are also disclosed. | 06-30-2011 |
| 20110258506 | REDUCED SIGNALING INTERFACE METHOD & APPARATUS - This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. | 10-20-2011 |
| 20120005547 | SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING - A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more programmable embedded debug circuits each receiving a first group of selected signals from the logic circuit under verification and providing control signals for (1) selecting a portion of the first group of selected signals, or (2) affecting the values of a second group of selected signals in the logic circuit under verification based on a portion of the first group of selected signals satisfying a predetermined triggering condition, wherein the programmable embedded debug circuits each including a built-in memory for storing signal vectors, the programmable embedded debug circuits each being configured according to a trigger specification defining one or more trigger states and triggering conditions; and (iii) a local debugging controller that controls programmable embedded debug circuits and transfers signal vectors between the built-in memories of the programmable embedded debug circuits and the vector processor interface bus; and (c) a vector processor which controls transferring of signal vectors between the host processor and the vector processor interface bus. | 01-05-2012 |
| 20120023382 | Data processing system and method for regulating a voltage supply to functional circuitry of the data processing system - A data processing system and method for regulating a voltage supply to functional circuitry of the data processing system is provided. The functional circuitry is configured to operate from a voltage supply whose voltage level is variable, the functional circuitry having at least one error correction circuit configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Voltage regulator circuitry provides the voltage supply to the functional circuitry, and modifies the voltage level of the voltage supply based on a feedback control signal. Error rate history circuitry receives error indications from the error correction circuit during operation of the functional circuitry and generates error rate history information therefrom. An adaptive controller then generates the feedback control signal in dependence on the error rate history information such that the adaptive controller adjusts the feedback control signal over time having regard to the error rate history information in order to obtain a predetermined target non-zero error rate within the functional circuitry. Such an approach enables a significant reduction in power consumption of the data processing system to be achieved. | 01-26-2012 |
| 20120036408 | Test Chain Testability In a System for Testing Tri-State Functionality - An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed. | 02-09-2012 |
| 20120159276 | AUTOMATED DETECTION OF AND COMPENSATION FOR GUARDBAND DEGRADATION DURING OPERATION OF CLOCKED DATA PROCESSING CIRCUIT - An automated guardband compensation system may automatically compensate for degradation in the guardband of a clocked data processing circuit while that circuit is connected within a data processing system. A control circuit may automatically and repeatedly request: a switching circuit to switch a critical path within the clocked data processing circuit out of a data processing pathway within the data processing system while the clocked data processing circuit is connected within the data processing system; a guardband test circuit to test the guardband of the critical path while the critical path is switched out of the data processing pathway; a guardband compensation circuit to increase the guardband when the results of the test indicate a material degradation in the guardband; and a switching circuit to switch the critical path back into the data processing pathway after the test. | 06-21-2012 |
| 20120173944 | SERVER AND METHOD FOR TESTING INTER-INTEGRATED CIRCUIT DEVICES - A server includes a baseboard management controller (BMC). More than one inter-integrated circuit (I2C) device may be connected to the BMC via a multiplexing switch. The server sets a first identifier for indicating which channels of I2C device are open, and a second identifier for indicating which channels of the I2C devices are closed, and sends the set information to the BMC. To test a selected I2C device, the server opens a channel to the selected I2C device and assigns the first identifier to the channel of the selected I2C device. During testing of the selected I2C device, if the BMC intends to access a different I2C device, the BMC waits for the identifier of the selected I2C device to change from the first identifier to the second identifier, and then opens a channel to the different I2C device. | 07-05-2012 |
| 20120233514 | FUNCTIONAL FABRIC BASED TEST WRAPPER FOR CIRCUIT TESTING OF IP BLOCKS - A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition. | 09-13-2012 |
| 20130166979 | Methods and Systems for an Automated Test Configuration to Identify Logic Device Defects - Provided is an apparatus configured for testing a logic device. The apparatus includes a testing mechanism configured to output test patterns representative of logical structures within the logic device and a testable logic device having (i) input ports coupled to output ports of the automated testing mechanism and (ii) output ports coupled to input ports of the automated testing mechanism. The apparatus also includes a fusing mechanism configured to compensate for defects within the logic device responsive to a segregation of the type of defects identified. | 06-27-2013 |
| 20130318415 | Test System Having a Sub-System to Sub-System Bridge - A test system having a sub-system to sub-system bridge may be provided that utilizes the useful attributes of a plurality of circuit testing techniques, while reducing deficiencies associated with certain types of circuit testing. A bridged test system structure is utilized to facilitate circuit testing that is more effective and time efficient. The method analyzes performance data acquired by a first component for one or more circuits, and sends that performance data to a second test component. The second test component provides test signals to the circuits, using the performance date to enhance the use of the test signals, and also provides test response data for the circuits in response to the provided test signals. | 11-28-2013 |
| 20140053036 | DEBUGGING MULTIPLE EXCLUSIVE SEQUENCES USING DSM CONTEXT SWITCHES - A system and method for efficiently debugging an integrated circuit with on-die hardware. A processor core includes an on-die debug state machine (DSM). The DSM includes multiple programmable storage elements for storing parameter values corresponding to multiple contexts. Each context is associated with a given one of multiple instruction sequences, such as at least threads and power-performance states. The DSM detects a sequence identifier (ID) and selects a context based on the sequence ID. The corresponding parameter values are used by transition conditions (triggers) and taken debug actions in a finite state machine (FSM) within the DSM. Each state and transition in the FSM is used by each one of the multiple contexts. The programmable DSM shares many resources, rather than replicating them, while being used for multiple sequences. | 02-20-2014 |
| 20140143624 | CONVERSION CIRCUIT AND CHIP - The present invention provides a conversion circuit including: an inputting unit, a DAC connected to the inputting unit, an ADC connected to an output end of the DAC, and a comparing unit connected to an output end of the ADC. The comparing unit compares a test code set output by the ADC with a second standard test code set, and if the comparison result is in a preset error range, notify a test data collecting unit; otherwise, output the comparison result to a correcting unit. The correcting unit obtains a complementary code set according to the comparison result, and output the complementary code set to the inputting unit, so that the inputting unit updates the standard test code set according to the complementary code set and obtains the updated first standard test code set. The test data collecting unit obtains a voltage value of an input end of the ADC. | 05-22-2014 |
| 20140365841 | SIGNAL PROCESSING SYSTEM WITH BIST FUNCTION, TESTING METHOD THEREOF AND TESTING SIGNAL GENERATOR - A signal processing system includes a module under test, an oscillation signal generator, a translational filter, and a testing module. The module under test has a signal input end. The oscillation signal generator generates an oscillation signal. The translational filter includes a mixer controlled by the oscillation signals. The mixer has a high-frequency side and a low-frequency side. The high-frequency side is coupled to the signal input end of the module under test. The testing module is coupled to the low-frequency side of the mixer. When the signal processing system is in a testing mode, the testing module provides a testing signal to the low-frequency side, so as to generate a high-frequency testing signal at the high-frequency side of the mixer. | 12-11-2014 |
| 20150058691 | METHOD FOR TESTING DATA PACKET SIGNAL TRANSCEIVER USING COORDINATED TRANSMITTED DATA PACKET SIGNAL POWER - A method for testing a data packet signal transceiver device under test (DUT) that minimizes time lost due to waiting for respective power levels of data packets transmitted by the DUT to settle at the desired nominal value for transmit signal testing. In accordance with exemplary embodiments, signals transmitted by the DUT during receive signal testing, e.g., as acknowledgement data packets, are transmitted at the nominal value for transmit signal testing, thereby allowing sufficient time for individual data packet signal power levels to settle and remain consistent at the nominal value by the time receive signal testing is completed and transmit signal testing is to begin. | 02-26-2015 |
| 20150067429 | WAFER-LEVEL GATE STRESS TESTING - A method of testing a semiconductor device includes forming a test circuit over a semiconductor substrate. The test circuit includes a plurality of interconnects electrically connected to a set of device structures supported by the semiconductor substrate. A test, such as a gate stress or leakage current test, of each device structure is conducted with the test circuit. The plurality of interconnects are removed after conducting the test. | 03-05-2015 |
| 20150067430 | SEMICONDUCTOR INTEGTRATED CIRCUIT INCLUDING TEST PADS - A The semiconductor integrated circuit includes a test input/output port including test pads; an internal input interface configured to generate an internal clock, an internal address, an internal command, internal data and temporary storage data in response to external signals through the test input/output port; and an error detection block configured to determine whether the internal data and the temporary storage data are the same, and output a result through one test pad of the port. The internal input interface includes a data input/output block which generates the internal data and the data input/output block includes a temporary storage part which stores the internal data as the temporary storage data, a data output part which receives the temporary storage data, and a data input part which receives an output of the data output part and outputs it as the internal data. | 03-05-2015 |
| 20150095733 | Method and Apparatus for Testing Surface Mounted Devices - An apparatus comprising a plurality of devices connected in series with one another, each of the devices comprising a test enable pin for receiving a test enable signal that indicates enablement of a test mode, and a test output pin for outputting a test output signal in the test mode, and a controller coupled to the devices and comprising an additional test output pin for outputting a test channel output signal, wherein a failure of at least one of the test output signals and the test channel output signal indicates the existence of one or more potential defects associated with the plurality of devices and the controller. | 04-02-2015 |
| 20160047859 | SIGNAL TRACING USING ON-CHIP MEMORY FOR IN-SYSTEM POST-FABRICATION DEBUG - A post-fabrication debug and on-line error checking framework for 2D- and 3D-ICs with integrated memories is described. A design-for-debug (DfD) architecture can include, for an IC with on-chip memory, a debug module connected to a functional bus of the IC. The debug module receives trace data for an interval, generates compact signatures based on the received data, and compares these signatures to expected signatures. Intervals containing erroneous trace data can be identified by the debug module and stored in on-chip memory. A single iteration of signal tracing for debug testing between automated test equipment and the IC is possible. | 02-18-2016 |
| 20160146888 | ON-CHIP FIELD TESTING METHODS AND APPARATUS - On-chip field testing methods and apparatus are disclosed. Example on-chip testers disclosed herein include a decoder having a test data input and a test stimuli interface. Disclosed example on-chip testers also include a multiplexer having a first multiplexer interface coupled to the test stimuli interface, a second multiplexer interface coupled to an automatic test equipment interface, a third multiplexer interface coupled to a design-for-testing subsystem interface and an interface selection input. Disclosed example on-chip testers further include a memory having a memory interface coupled to the test data input. | 05-26-2016 |
| 20180024193 | CORE TESTING MACHINE | 01-25-2018 |
