Entries |
Document | Title | Date |
20080229164 | MEMORY CARD AND MEMORY CONTROLLER - A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card. | 09-18-2008 |
20080235541 | METHOD FOR TESTING A WORD LINE FAILURE - A method for testing a word line failure of a memory device is provided. The memory device comprises a memory cell with a transistor connecting to a word line and a bit line. The method comprises driving the word line to a predetermined voltage level by a word line driver so as to turn off or on the transistor of the memory cell; and reducing the driving ability of the word line drive. | 09-25-2008 |
20080263415 | Integrated Circuit, Memory Module, Method of Operating an Integrated Circuit, Method of Fabricating an Integrated Circuit, Computer Program Product, and Computing System - According to one embodiment of the present invention, an integrated circuit includes a plurality of memory cells, the integrated circuit being operable in a memory cell testing mode in which testing signals are applied to the memory cells, wherein the strengths and durations of the testing signals at least partly differ from the strengths and durations of programming signals or sensing signals used for programming and sensing memory states of the memory cells. | 10-23-2008 |
20080320346 | SYSTEMS FOR READING NONVOLATILE MEMORY - In a nonvolatile memory system, first raw data is obtained from stored data using a first set of reading parameters. Subsequently, the first raw data is transferred to an ECC circuit where it is decoded. While the first raw data is being transferred and decoded, second raw data is obtained from the same stored data using a second set of reading parameters. | 12-25-2008 |
20090063918 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines. | 03-05-2009 |
20090089633 | Semiconductor Testing Apparatus and Method - The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened. | 04-02-2009 |
20090113259 | MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state. | 04-30-2009 |
20090125764 | DATA PRESERVING METHOD AND DATA ACCESSING METHOD FOR NON-VOLATILE MEMORY - A data preserving method and a data accessing method for a non-volatile memory are provided. In the data preserving method, a data is checked according to an error correcting code (ECC) to obtain an error bit number of the data. When the error bit number is greater than a threshold, the data is moved from a first memory unit to a second memory unit and is corrected according to the ECC. Thereby, the data stability of the non-volatile memory is improved. | 05-14-2009 |
20090132875 | METHOD OF CORRECTING ERROR OF FLASH MEMORY DEVICE, AND, FLASH MEMORY DEVICE AND STORAGE SYSTEM USING THE SAME - According to this invention, a highly reliable memory device that uses up a life of a flash memory can be provided. The memory device is a nonvolatile memory device including a plurality of memory cells, in which: each of the plurality of memory cells is an FET which includes a floating gate; the plurality of memory cells are divided into a plurality of deletion blocks; and the nonvolatile memory device reads data stored in a first deletion block, detects and corrects an error contained in the read data, stores, when the number of bits of the detected error exceeds a threshold, the corrected data in a second deletion block, sets a smaller value as the threshold as an error frequency detected in the first deletion block is higher, and sets a smaller value as the threshold as the number of deletion times executed in the first deletion block is larger. | 05-21-2009 |
20090150730 | Test apparatus for data storage device and test method for data storage device - In a test apparatus for a data storage device, embodiments of the present invention help to support data storage devices with different specifications using a single processor. According to one embodiment, a test apparatus comprises a processor card and adapter cards. The adapter cards comprise power supply circuits to generate power supply voltages to be supplied to the hard disk drives (HDDs). Implementing power supply circuits in the adapter card accomplishes flexible support for HDDs with various specifications with a single processor cards. Since a plurality of HDDs are concurrently tested with a single processor card, it is not necessary to mount a plurality of power supply circuits on the processor card so that the processor card can be decreased in size. | 06-11-2009 |
20090172481 | Partial Voltage Read of Memory - A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices. | 07-02-2009 |
20090313513 | APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device for performing a reliability test includes a write driving block for generating a predetermined test voltage in a test mode and delivering a data inputted from an external circuit into the local I/O line pair during a data access operation in a normal mode, a local I/O line pair coupled to the write driving block for receiving the predetermined test voltage in the test mode, and a cell array having a plurality of unit cells and a plurality of bit line pairs respectively having first and second bit lines and coupled to at least one unit cell for receiving the predetermined test voltage from each local I/O line pair to thereby check a result of the reliability test in the test mode. | 12-17-2009 |
20100037110 | AUTOMATIC MULTICABLE ELECTRICAL CONTINUITY TESTER - An automatic multi-cable continuity tester. The multi-conductor electrical continuity tester includes a controller that is configured to generate a first serial stream of input test signals. The first serial stream of input test signals includes a plurality of signals equal in number to a plurality of conductors in a cable. A data input module is configured to convert the first serial stream of input test signals into a first parallel stream of test signals. A data output module is configured to receive and convert the first parallel stream of test signals to a first serial stream of output test signals. The controller is further configured to receive the first serial stream of output signals, store the first serial stream of output signals to a memory, generate subsequent serial streams of input test signals corresponding to each possible combination and permutation of conductors, determine whether each possible combination and permutation of conductors includes an open circuit condition and/or a short circuit condition, and determine whether at least one predefined relationship between input and output test signals includes an open circuit condition and/or a short circuit condition, wherein the predefined relationship defines a stream of output test signals that are different than a stream of input test signals. | 02-11-2010 |
20100122131 | SEMICONDUCTOR MEMORY DEVICE AND TESTING METHOD THEREFOR - A semiconductor memory device comprises a plate voltage generating circuit that generates a plate voltage supplied to a memory cell array and a plate voltage supply terminal that supplies a plate voltage from the outside. A first switching circuit is provided to switch the supply of the plate voltage between the supply from the plate voltage generating circuit and the supply from the outside through the plate voltage supply terminal. | 05-13-2010 |
20100131811 | Semiconductor device and verify method for semiconductor device - A semiconductor device includes a memory module provided with a plurality of memory cells, a verify determination unit that performs quality determination of read data that have been read from the memory cells on the basis of the read data and an expected value prepared in advance, and a power source monitoring circuit that detects fluctuations equal to or greater than a predetermined variation rate in a power source voltage supplied to the memory module and outputs a power source abnormality detection signal. Furthermore, the verify determination unit invalidates a result of the quality determination when the power source abnormality detection signal indicates an abnormal state of the power source voltage. | 05-27-2010 |
20100211836 | FAILURE ANALYSIS METHOD, FAILURE ANALYSIS SYSTEM, AND MEMORY MACRO SYSTEM - Configuration information including number of normal cell areas and number of spare cell areas arranged in a memory macro and a size of each cell area is extracted from circuit design information, and electrical test results of the normal cell areas and the spare cell areas arranged in the memory macro are collected. Arrangement information corresponding to a collection order of the electrical test results is converted to a two-dimensional coordinate value for two-dimensionally displaying the arrangement information corresponding to a collection order of the electrical test results in a unit of cell area in association with a physical layout of a memory cell in the memory macro based on the configuration information. The collected electrical test results are displayed based on the two-dimensional coordinate value so that the normal cell areas and the spare cell areas can be distinguished. | 08-19-2010 |
20100287427 | Flash Memory Device and Flash Memory Programming Method Equalizing Wear-Level - Disclosed are a flash memory device and flash memory programming method that equalizes a wear-level. The flash memory device includes a memory cell array, an inversion determining unit to generate a programming page through inverting or not inverting a data page based on a number of ‘1’s and ‘0’s in the data page, a programming unit to store the generated programming page in the memory cell array; and a data verifying unit to read the programming page stored in the memory cell array, to restore the data page from the programming page according to whether an error exists in the read programming page, and to output the restored data page, and thereby can equalize a wear-level of a memory cell. | 11-11-2010 |
20100306604 | METHOD AND CIRCUIT FOR BROWNOUT DETECTION IN A MEMORY SYSTEM - Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout. | 12-02-2010 |
20110022905 | Test Circuit and Method for Multilevel Cell Flash Memory - A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system. | 01-27-2011 |
20110035637 | SYSTEMS AND DEVICES INCLUDING MEMORY WITH BUILT-IN SELF TEST AND METHODS OF MAKING AND USING THE SAME - Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing circuit may include an analog-to-digital converter, a switch coupled to the memory element and a feedback signal path coupled to the output of the analog-to-digital converter and to the switch. | 02-10-2011 |
20110066902 | SYSTEM AND METHOD OF READING DATA USING A RELIABILITY MEASURE - In a particular embodiment, a data storage device includes a memory array including a target memory cell and one or more other memory cells. The data storage device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array. | 03-17-2011 |
20110083050 | MEMORY CELL PROGRAMMING - Embodiments of the present disclosure provide methods, devices, and systems for performing a programming operation on an array of non-volatile memory cells. One method includes programming a number of cells to a number of final data states. The method includes performing, prior to completion of, e.g., finishing, the programming operation, an erase state check on a subset of the number of cells, which were to be programmed to an erased state. | 04-07-2011 |
20110099438 | Methods of Cell Population Distribution Assisted Read Margining - A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored. | 04-28-2011 |
20110107161 | THRESHOLD VOLTAGE TECHNIQUES FOR DETECTING AN IMMINENT READ FAILURE IN A MEMORY ARRAY - A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level. | 05-05-2011 |
20110131458 | METHOD AND SYSTEM FOR EVALUATING EFFECTS OF SIGNAL PHASE DIFFERENCE ON A MEMORY SYSTEM - In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another. | 06-02-2011 |
20110246841 | STORING APPARATUS - A storing apparatus, equipped with a control unit configured to control the writing of data into a memory and to communicate a notice to an external device with a communication unit if the remaining amount of substitute blocks becomes equal to or less than a threshold value specified by stored threshold value information, includes the control unit configured to change the threshold value information, used for the notice communicated by the control unit, by the use of threshold value information received from the external device with the communication unit. | 10-06-2011 |
20120047411 | DETERMINING DATA VALID WINDOWS IN A SYSTEM AND METHOD FOR TESTING AN INTEGRATED CIRCUIT DEVICE - Embodiments of a system and method for testing an integrated circuit device are described herein. Testing is complemented by a determination of characteristics of a data valid window that identifies components of a response data signal from a device under test where the data signal can always be expected to be stable. In at least one embodiment, the method comprises: for each individual data bit region of one or more data bit regions of a second data signal, sampling the second data signal at a plurality of points of the individual data bit region to produce a plurality of sampled values for the second data signal; for each sampled value of the plurality of sampled values, determining whether the sampled value matches an expected bit pattern value corresponding to the sampled value; determining one or more characteristics of the data valid window that defines conditions under which a valid sample can be expected to be taken; and outputting a test outcome based on one or more characteristics of the data valid window. In some embodiments, the second data signal may be sampled at the plurality of points of the individual data bit region concurrently. In some embodiments, the determination of whether each sampled value of the plurality of sampled values matches the expected bit pattern value may be performed concurrently for all of the plurality of sampled values. | 02-23-2012 |
20120072794 | NON-VOLATILE MEMORY (NVM) WITH IMMINENT ERROR PREDICTION - A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value. | 03-22-2012 |
20120072795 | SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD - According to one embodiment, a semiconductor memory device includes a plurality of semiconductor memory chips configured to store therein information depending on an amount of accumulated charge; a plurality of parameter storage units that are provided in correspondence with the semiconductor memory chips, each of the plurality of parameter storage units being configured to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and writes the parameters changed into the parameter storage units, respectively. | 03-22-2012 |
20120110401 | SYSTEM AND METHOD OF SENSING DATA IN A SEMICONDUCTOR DEVICE - A semiconductor memory apparatus includes: a first data counting unit configured to count respective programming levels of a plurality of input data and output a plurality of first data counting codes having a code value corresponding to the number of respective programming levels; a data read unit configured to sense data stored in a memory block having the plurality of input data programmed therein, based on a voltage level of a plurality of read bias signals, and output the sensed result as a plurality of output data; a second data counting unit configured to count respective programming levels of the plurality of output data and output a plurality of second data counting codes having a code value corresponding to the number of respective programming levels; a read bias control unit configured to compare the plurality of first data counting codes with the plurality of second data counting codes and output a bias control code having a code value corresponding to the comparison result; and a read bias generating unit configured to generate the plurality of read bias signals whose voltage levels are adjusted based on the code value of the bias control code. | 05-03-2012 |
20120166897 | Data management in flash memory using probability of charge disturbances - A Flash memory system and a method for data management using the system's sensitivity to charge-disturbing operations and the history of charge-disturbing operations executed by the system are described. In an embodiment of the invention, the sensitivity to charge-disturbing operations is embodied in a disturb-strength matrix in which selected operations have an associated numerical value that is an estimate of the relative strength of that operation to cause disturbances in charge that result in data errors. The disturb-strength matrix can also include the direction of the error which indicates either a gain or loss of charge. The disturb-strength matrix can be determined by the device conducting a self-test in which charge-disturb errors are provoked by executing a selected operation until a detectable error occurs. In alternative embodiments the disturb-strength matrix is determined by testing selected units from a homogeneous population. | 06-28-2012 |
20120179943 | METHOD FOR INFORMATION TRANSFER IN A VOLTAGE-DRIVEN INTELLIGENT CHARACTERIZATION BENCH FOR SEMICONDUCTOR - A method for transmitting data from test device to a storage device via a parallel bus. The methods comprising the steps of setting a flag to indicate that data is available, reading the data, setting a flag to indicate the data was read. In addition test parameters are sent to the test device from the storage device, the method comprises the steps of checking to see if a test device is ready to receive data, transferring the test parameters, identifying the next channel to update. | 07-12-2012 |
20120216086 | TEST APPARATUS - A test apparatus comprising a first buffer section and a second buffer section that each buffers fail data and address data; an address fail memory section that writes the fail data buffered in the first buffer section to an address of an internal memory indicated by the address data corresponding to the fail data, using an RMW process; and a control section that, in a state in which the fail data and address data output from the testing section are supplied to the first buffer section, when unused capacity of the first buffer section becomes less than or equal to a predetermined first threshold value, supplies the fail data and address data output from the testing section to the second buffer section instead of to the first buffer section. | 08-23-2012 |
20120260137 | MEMORY BUFFER FOR BUFFER-ON-BOARD APPLICATIONS - Disclosed in a method of optimizing a voltage reference signal. The method includes: assigning a first value to the voltage reference signal; executing a test pattern while using the voltage reference signal having the first value; observing whether a failure occurs in response to the executing and thereafter recording a pass/fail result; incrementing the voltage reference signal by a second value; repeating the executing, the observing, and the incrementing a plurality of times until the voltage reference signal exceeds a third value; and determining an optimized value for the voltage reference signal based on the pass/fail results obtained through the repeating the executing, the observing, and the incrementing the plurality of times. | 10-11-2012 |
20130019132 | DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORYAANM AMIRKHANYAN; KarenAACI YerevanAACO AMAAGP AMIRKHANYAN; Karen Yerevan AMAANM Grigoryan; HaykAACI YerevanAACO AMAAGP Grigoryan; Hayk Yerevan AMAANM Harutyunyan; GurgenAACI AbovyanAACO AMAAGP Harutyunyan; Gurgen Abovyan AMAANM Melkumyan; TatevikAACI YerevanAACO AMAAGP Melkumyan; Tatevik Yerevan AMAANM Shoukourian; SamvelAACI YerevanAACO AMAAGP Shoukourian; Samvel Yerevan AMAANM Shubat; AlexAACI Los Altos HillsAAST CAAACO USAAGP Shubat; Alex Los Altos Hills CA USAANM Vardanian; ValeryAACI YerevanAACO AMAAGP Vardanian; Valery Yerevan AMAANM Zorian; YervantAACI Santa ClaraAAST CAAACO USAAGP Zorian; Yervant Santa Clara CA US - A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory. | 01-17-2013 |
20130019133 | METHODS FOR TESTING A MEMORY EMBEDDED IN AN INTEGRATED CIRCUIT - A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array. | 01-17-2013 |
20130159798 | NON-VOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A non-volatile memory device and an operating method thereof are provided. The non-volatile memory device includes a memory unit including a plurality of memory blocks and a cam block, a peripheral circuit unit configured to program memory cells included in the plurality of memory blocks and the cam block or read programmed data, and a processor configured to control the peripheral circuit unit to measure an offset voltage by memory cell group in the plurality of memory blocks to set a read voltage during a test read operation and control the peripheral circuit unit to perform a read operation by memory cell group by using a new read voltage during a read operation. | 06-20-2013 |
20130326296 | NONVOLATILE MEMORY DEVICE AND ERROR CORRECTION METHODS THEREOF - A data processing method is provided for processing data read from a nonvolatile memory. The data processing method includes receiving first bit data from the nonvolatile memory at a memory controller, and performing erasure decoding based on the first bit data and second bit data stored in the memory controller. The first bit data indicates a memory cell that is erasure, and the second bit data is read using a read voltage during previous error correction decoding. | 12-05-2013 |
20140013170 | SCALABLE PREDICTION FAILURE ANALYSIS FOR MEMORY USED IN MODERN COMPUTERS - One embodiment provides a method for scalable predictive failure analysis. Embodiments of the method may include gathering memory information for memory on a user computer system having at least one processor. Further, the method includes selecting one or more memory-related parameters. Further still, the method includes calculating based on the gathering and the selecting, a single bit error value for the scalable predictive failure analysis through calculations for each of the one or more memory-related parameters that utilize the memory information. Yet further, the method includes setting, based on the calculating, the single bit error value for the user computer system. | 01-09-2014 |
20140053033 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL - Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels. | 02-20-2014 |
20140059398 | ADAPTIVE ERROR CORRECTION FOR NON-VOLATILE MEMORIES - Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry uses error correction code (ECC) routines to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry then dynamically adjusts sense amplifier read detection windows to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories. | 02-27-2014 |
20140075252 | Erased Page Confirmation in Multilevel Memory - In a multi-level cell memory array, a flag that indicates that a logical page is unwritten is subject to a two-step verification. In a first verification step, the logical page is read, and ECC decoding is applied. If the first verification step indicates that the logical page is unwritten, then a second verification step counts the number of cells that are not in an unwritten condition. | 03-13-2014 |
20140082440 | METHOD AND APPARATUS OF MEASURING ERROR CORRECTION DATA FOR MEMORY - Multiple measurements are made with one memory sense operation having a first word line sensing voltage on a memory cell. The multiple measurements include a first measurement, of whether the memory cell stores either: (a) data corresponding to a first set of one or more threshold voltage ranges below the first word line sensing voltage of the one memory sense operation, or (b) data corresponding to a second set of one or more threshold voltage ranges above the first word line sensing voltage of the one memory sense operation. The multiple measurements include a second measurement, of error correction data of the memory cell indicating relative position within a particular threshold voltage range of a stored threshold voltage in the memory cell. | 03-20-2014 |
20140129884 | REGISTER FILE WRITE RING OSCILLATOR - Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell. | 05-08-2014 |
20140157068 | PROGRAMMING NONVOLATILE MEMORY BASED ON STATISTICAL ANALYSIS OF CHARGE LEVEL DISTRIBUTIONS OF MEMORY CELLS - A system includes a read module, a statistical data generating module, and a storing module. The read module reads charge levels of nonvolatile memory cells and generates read signals. The statistical data generating module generates statistical data based on the read signals. The storing module stores the statistical data. The read module generates the read signals based on the charge levels of the nonvolatile memory cells and the statistical data. | 06-05-2014 |
20140189451 | Addressing, Command Protocol, and Electrical Interface for Non-volatile Memories Utilized in Recording Usage Counts - A memory module, including a plurality of memory cells and a plurality of signal lines for communicating with a processing device. The memory module is configured such that following reception of a command and upon encountering a first condition while processing the command, the memory module limits a voltage on a first signal line of the plurality of signal lines to be no more than an intermediate voltage greater than voltage levels corresponding to a binary zero state and less than voltage levels corresponding to a binary one state for a period of time for indicating an occurrence of the first condition. | 07-03-2014 |
20140201580 | SYSTEMS AND METHODS TO UPDATE REFERENCE VOLTAGES IN RESPONSE TO DATA RETENTION IN NON-VOLATILE MEMORY - A data storage device includes non-volatile memory and a controller. The controller is configured to, at a first time, determine a first count of storage elements having threshold voltages within a voltage range that corresponds to a first reference voltage. The controller is further configured to, at a second time, determine a second count of storage elements having threshold voltages within the voltage range. The controller is further configured to calculate an updated first reference voltage at least partially based on the first reference voltage, the first count, and the second count. | 07-17-2014 |
20140208174 | STORAGE CONTROL SYSTEM WITH DATA MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of a storage control system includes: determining a bit error rate of a page; calculating a slope based on the bit error rate; and adjusting a threshold voltage for the page based on the slope for reading a memory device. | 07-24-2014 |
20140245089 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory cells each given one of threshold voltages to store data, and a controller configured to use read voltages to determine threshold voltages of the memory cells. The controller is configured to use voltages over a window to read data from the memory cells to determine distribution of the threshold voltages of the memory cells to estimate a read voltage. The controller is further configured to execute the estimation of a read voltage for each of the read voltages. The controller is further configured to use an estimated value of a first read voltage of the read voltages to determine a window for estimation of a second read voltage of the read voltages. | 08-28-2014 |
20140281766 | PROBABILITY-BASED REMEDIAL ACTION FOR READ DISTURB EFFECTS - A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line. | 09-18-2014 |
20140281767 | RECOVERY STRATEGY THAT REDUCES ERRORS MISIDENTIFIED AS RELIABLE - A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window; and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window. | 09-18-2014 |
20140281768 | RETENTION LOGIC FOR NON-VOLATILE MEMORY - An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state characterized by a minimum threshold exceeding a selected read bias. A controller includes a stand-by mode, a write mode and a read mode. Retention check logic executes on power-up, or during the stand-by mode, to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells. | 09-18-2014 |
20140281769 | MEMORY SYSTEM AND MEMORY CONTROLLER - According to one embodiment, a memory system includes a non-volatile memory and a memory controller that controls the non-volatile memory. The non-volatile memory includes a memory cell array and an access control unit. The access control unit performs a program operation for changing threshold voltages of memory cells and a read operation for reading data from the memory cells. The memory controller includes a read/write control unit having a first program parameter set and a second program parameter set. The read/write control unit causes the access control unit to perform a program operation based on the first program parameter set, and when a predetermined condition is satisfied, performs switching from the first program parameter set to the second program parameter set and causes the access control unit to perform a program operation based on the second program parameter set. | 09-18-2014 |
20140281770 | METHOD OF READING DATA FROM A NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY DEVICE, AND METHOD OF OPERATING A MEMORY SYSTEM - In a method of reading data from a nonvolatile memory device, a first read operation for memory cells coupled to a first word line is performed by applying a first read voltage to the first word line, a first read retry is performed to obtain an optimal read level regardless or independent of whether data read by the first read operation is error-correctable, and the optimal read level is stored to perform a subsequent second read operation using the optimal read level. Related methods and devices are also discussed. | 09-18-2014 |
20140281771 | METHOD AND DEVICE FOR OPTIMIZING LOG LIKELIHOOD RATIO (LLR) USED FOR NONVOLATILE MEMORY DEVICE AND FOR CORRECTING ERRORS IN NONVOLATILE MEMORY DEVICE - In a method of optimizing a log likelihood ratio (LLR) used to correct errors related to data stored in a nonvolatile memory device, variation of threshold voltage distribution for a plurality of memory cells included in the nonvolatile memory device is monitored, and the LLR for the memory cells is updated based on a monitoring result. Although the characteristics of the memory cells are deteriorated, the LLR is continuously maintained to the optimal value. | 09-18-2014 |
20140281772 | DETECTING EFFECT OF CORRUPTING EVENT ON PRELOADED DATA IN NON-VOLATILE MEMORY - A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event. | 09-18-2014 |
20140298121 | ANALYSIS SUPPORT APPARATUS, ANALYSIS SUPPORT METHOD, AND COMPUTER PRODUCT - An analysis support apparatus includes a processor that is configured to acquire circuit data that indicates plural elements within a circuit and a node to which at least two elements are connected among the elements, and determine, based on the acquired circuit data and by referring to a memory unit that correlates and stores for each of the elements, the type of the element and information that indicates whether the phase of a signal is reversed when the signal passes through the element, whether the phase of the signal is reversed when the signal that passed through a given node among a plurality of nodes within the circuit returns to the given node; and an output unit that outputs information that indicates the given node when the processor determines that the phase of the signal is not reversed. | 10-02-2014 |
20140351663 | SINGLE CHECK MEMORY DEVICES AND METHODS - Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells. | 11-27-2014 |
20140365836 | Device and Method for Resolving an LM Flag Issue - The reliability with which data can be read from a storage medium, such as flash memory storage medium, is enhanced by updating an upper limit of a reading threshold voltage window for a respective portion of the storage medium. For each memory cell in the respective portion of the storage medium, a memory controller is configured to perform a plurality of sensing operations and obtain results from the plurality of sensing operations, where the plurality of sensing operations includes sensing operations using a predefined range of offsets from a previously established reading threshold voltage. The memory controller is further configured to determine the updated upper limit of the reading threshold voltage window based on the-results from the plurality of sensing operations, and store the updated upper limit of the reading threshold voltage window for the respective portion of the storage medium. | 12-11-2014 |
20140372815 | APPARATUS AND METHOD TO REDUCE POWER DELIVERY NOISE FOR PARTIAL WRITES - Apparatus, systems, and methods to reduce power delivery noise for partial writes are described. In one embodiment, an apparatus comprises a processor and a memory control logic to insert one or more dummy unit intervals into data in a write operation when a number of state transitions between adjacent unit intervals exceeds a threshold. Other embodiments are also disclosed and claimed. | 12-18-2014 |
20140380108 | METHOD AND SYSTEM TO OBTAIN STATE CONFIDENCE DATA USING MULTISTROBE READ OF A NON-VOLATILE MEMORY - An apparatus may include a processor circuit a processor circuit to retrieve data from a non-volatile memory, and a multistrobe read module operable on the processor circuit to set a read operation to read a memory cell over a multiplicity of sense operations, where each sense operation is performed under a different sense condition. The multistrobe read module may be further operable to schedule a new sense operation to succeed a prior sense operation of the multiplicity of sense operations without recharge of the wordline when a value of one or more read condition is within a preset range. Other embodiments are disclosed and claimed. | 12-25-2014 |
20140380109 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits. | 12-25-2014 |
20150012787 | TESTING OF NON-VOLATILE MEMORY ARRAYS - A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for V | 01-08-2015 |
20150046762 | Data Storage Device and Method for Restricting Access Thereof - A data storage device including a flash memory, a temperature sensor and a controller. The flash memory has a plurality of blocks, and each of the blocks has a plurality of pages. The temperature sensor detects surrounding ambient temperature and to produce a temperature parameter accordingly. The controller is arranged to perform a first maintenance procedure after a predetermined period since the data storage device is powered on. The controller reads the temperature sensor to obtain a first temperature parameter in the first maintenance procedure and determines a first time span according to a first predetermined condition for performing a second maintenance procedure, wherein the first predetermined condition includes the first temperature parameter, and the controller is further arranged to perform the second maintenance procedure after the first time span since the first maintenance procedure has finished. | 02-12-2015 |
20150067419 | Bad Block Reconfiguration in Nonvolatile Memory - When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors. | 03-05-2015 |
20150082105 | ERROR PREDICTION IN LOGIC AND MEMORY DEVICES - Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example. | 03-19-2015 |
20150095728 | TESTING METHOD FOR REDUCING NUMBER OF OVERKILLS BY REPEATEDLY WRITING DATA TO ADDRESSES IN A NON-VOLATILE MEMORY - A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number. | 04-02-2015 |
20150106671 | MEMORY DEVICE RETENTION MODE BASED ON ERROR INFORMATION - A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter. | 04-16-2015 |
20150113342 | NONVOLATILE MEMORY DEVICE INCLUDING DUMMY WORDLINE, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY SYSTEM - A method of operating a memory system includes reading data of first memory cells, the first memory cells being connected to a first wordline from among a plurality of wordlines, the plurality of wordlines including one or more dummy wordlines and one or more normal wordlines; determining whether the first wordline is one of the one or more dummy wordlines by determining, based on the read data, a number of the first memory cells having a first threshold voltage state, the one or more dummy wordlines being wordlines the memory cells of which have been programmed with dummy data, the one or more normal wordlines being wordlines that are not dummy wordlines; and performing a repair algorithm for correcting an error in the read data, selectively according to a result of the determination. | 04-23-2015 |
20150127999 | System and Method for Adjusting Trip Points within a Storage Device - The embodiments described herein include a method and device for adjusting trip points within a storage device. The method includes: obtaining one or more configuration parameters; and based on the one or more configuration parameters, determining a trip voltage. The method also includes comparing the trip voltage with an input voltage. The method further includes triggering a power fail condition in accordance with a determination that the input voltage is less than the trip voltage. | 05-07-2015 |
20150135027 | DETERMINING AN AGE OF DATA STORED IN MEMORY - The present disclosure includes apparatuses and methods for determining an age of data stored in memory. A number of embodiments include determining a sensing voltage that results in a particular error rate being associated with a sense operation performed on a memory using the sensing voltage, determining a difference between the determined sensing voltage and a program verify voltage associated with the memory, and determining an age of data stored in the memory based on the determined difference. | 05-14-2015 |
20150149841 | SYSTEMS AND METHODS FOR LOW VOLTAGE SECURE DIGITAL (SD) INTERFACES - Systems and methods for low voltage secure digital (SD) interfaces are disclosed. Embodiments of the present disclosure relate to systems and voltage for a lower voltage SD or SD Input/Output (SDIO) interface such as two integrated circuits. In particular, a SD or SDIO interface may be established between two SD compliant devices. While the SD compliant devices may otherwise comply with the SD standard, the voltage levels for signals passed between the SD compliant devices may be below 1.8 volts that the standard mandates. This reduced voltage is possible because the distances involved for interchip communication or the short distances involved for mobile terminal to peripheral connection are short enough that the reduced voltage is sufficient to still provide the desired signal strength at the receiver. | 05-28-2015 |
20150294739 | ONLINE HISTOGRAM AND SOFT INFORMATION LEARNING - A system includes a processor configured to read information from a plurality of memory cells. The processor initiates a first read of raw data from a group of memory cells using a first reference voltage. The processor also initiates a second read of raw data from the group of memory cells using a second reference voltage different from the first reference voltage. The processor further compares the first read to the second read to identify memory cells read with a bit value that changes between the first and second reads. The processor also assigns the memory cells read with a bit value that changes between the first and second reads to a region associated with the second reference voltage. The processor further counts the number of cells read with a bit value that changes to generate a histogram corresponding to soft information for the group of memory cells. | 10-15-2015 |
20150309870 | MEMORY DEVICE WITH INTERNAL SIGNAL PROCESSING UNIT - A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data. | 10-29-2015 |
20150310934 | SEMICONDUCTOR DEVICE - A semiconductor device is packaged in a module and includes an interface arranged to perform data communication with outside of the device, and a detector arranged to detect whether or not a module output terminal is in a non-normal state. The module has a module power source terminal and a module output terminal, but has no data communication dedicated terminal. When the module output terminal is in the non-normal state, the interface uses the module output terminal or the module power source terminal so as to proceed to a module data communication mode for data communication with outside. | 10-29-2015 |
20150310938 | Temperature Tracking to Manage Threshold Voltages in a Memory - Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, a first data access operation is conducted on a memory cell and a first temperature associated with the memory cell and associated with the first data access operation is measured. A second temperature associated with the memory cell is measured. At least one operational parameter is adjusted responsive to the first and second temperatures associated with the memory cell. A second data access operation is conducted on the memory cell using the adjusted operational parameter. | 10-29-2015 |
20150357046 | TESTING OF NON-VOLATILE MEMORY ARRAYS - A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for V | 12-10-2015 |
20150363261 | RAM REFRESH RATE - A refresh rate of a random-access memory (RAM) is increased if a number of errors is greater than an error threshold and the refresh rate has not reached a maximum rate. The refresh rate of the RAM is set to a normal rate if the number of errors is less than or equal to the error threshold. | 12-17-2015 |
20150363330 | Flash NAND device bad page replacement - Where one or more flash NAND devices are in an array where bit error recovery resolution is available, the controller can log what pages have had what degree of fails, and program a Replace Bad Page function to replace the bad page with a new page from another new die as needed. The Replace Bad Page function with logic blocks, content addressable memory and RAM, once programmed, provides the means to know when a bad page is being accessed and displaces this access with access to the new page, with no change in overall page access function or performance. | 12-17-2015 |
20150370629 | STORAGE DEVICE INCLUDING NONVOLATILE MEMORY AND MEMORY CONTROLLER AND OPERATING METHOD OF STORAGE DEVICE - An operating method of a storage device includes reading data from a nonvolatile memory using first read parameters and second read parameters and collecting read histories associated with a plurality of read operations. First histories and second histories are determined from the collected read histories. The second read parameters are adjusted according to the first histories, and the first read parameters are adjusted according to the second histories. The read histories include information on read voltages used to perform the read operations, and the first histories and the second histories are determined from the collected read histories according to the number of read voltages having the same level. | 12-24-2015 |
20160012913 | AC Stress Mode to Screen Out Word Line to Word Line Shorts | 01-14-2016 |
20160034342 | OPERATIONAL VIBRATION COMPENSATION THROUGH MEDIA CACHE MANAGEMENT - Apparatus and method for managing a media cache through the monitoring of operational vibration of a data storage device. In some embodiments, a non-volatile media cache of the data storage device is partitioned into at least first and second zones having different data recording characteristics. Input data are received for storage in a non-volatile main memory of the data storage device. An amount of operational vibration associated with the data storage device is measured. The input data are stored in a selected one of the first or second zones of the media cache prior to transfer to the main memory responsive to a comparison of the measured amount of operational vibration to a predetermined operational vibration threshold. | 02-04-2016 |
20160049209 | THRESHOLD VOLTAGE EXPANSION - Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed. | 02-18-2016 |
20160118143 | THRESHOLD VOLTAGE MARGIN ANALYSIS - The present disclosure is related to a threshold voltage margin analysis. An example embodiment apparatus can include a memory and a controller coupled to the memory. The controller is configured to determine a previous power loss of a memory to be an asynchronous power loss, and identify a portion of the memory last subject to programming operations during the determined asynchronous power loss. The controller is further configured to perform a threshold voltage (Vt) margin analysis on the portion of the memory responsive to the determined asynchronous power loss. | 04-28-2016 |
20160125958 | TESTING STORAGE DEVICE POWER CIRCUITRY - The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails. | 05-05-2016 |
20160132408 | MIRRORING IN THREE-DIMENSIONAL STACKED MEMORY - A method for mirroring in three-dimensional-stacked memory includes receiving a plurality of thermal profiles from a plurality of memory chips. The method also includes ranking the plurality of memory chips in a first ranked list of memory chips as a function of the plurality of thermal profiles and forming a first group of memory chips from the plurality of memory chips based on the first ranked list of memory chips. The method also includes forming a second group of memory chips from the plurality of memory chips distinct from the first group of memory chips based on the first ranked list of memory chips. The method also includes pairing a first memory chip from the first group of memory chips and a second memory chip from the second group of memory chips, and mirroring the pairing of memory chips. | 05-12-2016 |
20160155516 | READ LEVELING METHOD AND MEMORY DEVICE USING THE SAME | 06-02-2016 |
20160180968 | MEMORY DEVICE, STORAGE APPARATUS AND METHOD FOR DIAGNOSING STORAGE APPARATUS | 06-23-2016 |
20160203049 | PROGRAM AND OPERATING METHODS OF NONVOLATILE MEMORY DEVICE | 07-14-2016 |
20160253238 | DATA ENCODING ON SINGLE-LEVEL AND VARIABLE MULTI-LEVEL CELL STORAGE | 09-01-2016 |
20160254063 | DYNAMIC APPROXIMATE STORAGE FOR CUSTOM APPLICATIONS | 09-01-2016 |
20170236592 | ESTABLISHING PARAMETERS OF SUBSEQUENT READ RETRY OPERATIONS BASED ON SYNDROME WEIGHTS OF PRIOR FAILED DECODINGS | 08-17-2017 |
20170236598 | NOISE DETECTION CIRCUIT AND SEMICONDUCTOR SYSTEM USING THE SAME | 08-17-2017 |