| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 714011000 | Concurrent, redundantly operating processors | 62 |
| 20080215913 | Information Processing System and Information Processing Method - An anomaly detector detects anomaly of a first device. A second device reset part, in case that anomaly has been detected by the anomaly detector, resets a second device. A first device reset part, in case that anomaly has been detected by the anomaly detector, resets a first device. Further, a collating part collates data generated by the first device with data generated by the second device, and judges anomaly when these data are in disagreement with each other. A reset part, in case that the anomaly has been judged by the collating part, resets the second device. | 09-04-2008 |
| 20080215914 | Self-reparable semiconductor and method thereof - A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a defect in a sub-functional unit is detected, then that sub-functional unit is switched out and replaced with a sub-functional unit in the full or partial spare functional unit. The reconfiguration is realized with switching devices that are associated with the sub-functional units. Defective functional or sub-functional units can be detected after assembly, during power up, periodically during operation, and/or manually. | 09-04-2008 |
| 20080270827 | RECOVERING DIAGNOSTIC DATA AFTER OUT-OF-BAND DATA CAPTURE FAILURE - Embodiments of the present invention address deficiencies of the art in respect to out-of-band management of system fault handling and provide a novel and non-obvious method, system and computer program product for recovering diagnostic data after out-of-band data capture failure. In an embodiment of the invention, a method for recovering diagnostic data after out-of-band data capture failure can include detecting an uncorrectable error in a coupled CPU. Thereafter, the coupled CPU can be placed in a quiesced state and the CPU can be warm reset. Error data can be retrieved from the CPU registers for the CPU and the CPU can be rebooted. Finally, the quiesced state of the CPU can be removed. | 10-30-2008 |
| 20090006891 | Apparatus, System, and Method for Hard Disk Drive Redundancy - An apparatus, system, and method are disclosed for hard disk drive redundancy. A demarcation module demarks a parity data block in each set of a specified number of data blocks on a hard disk drive. An association module associates a PBA of each un-demarked data block with a LBA. A write module writes the data to the un-demarked data blocks. A parity module calculates parity data for the data written to the un-demarked data blocks and the write module writes the parity data to the parity data block. | 01-01-2009 |
| 20090044048 | Method and device for generating a signal in a computer system having a plurality of components - A method and device for generating a signal in a computer system having a plurality of components, at least two execution units being provided as two components, and a switchover means being provided as an additional component, in the computer system, switchover operations being carried out between at least two operating modes, and a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, wherein, in one component of the computer system, a mode signal, indicative of the current operating mode, and/or changes in a mode signal are generated, and at least the changes in the mode signal and/or the mode signal itself are made available outside of the component. | 02-12-2009 |
| 20090044049 | Multiple Parallel Pipeline Processor Having Self-Repairing Capability - A multiple parallel pipeline digital processing apparatus has the capability to substitute a second pipeline for a first in the event that a failure is detected in the first pipeline. Preferably, a redundant pipeline is shared by multiple primary pipelines. Preferably, the pipelines are located physically adjacent one another in an array. Preferably, a pipeline failure causes data to be shifted one position within the array of pipelines, to by-pass the failing pipeline, so that each pipeline has only two sources of data, a primary and an alternate. Preferably, selection logic controlling the selection between a primary and alternate source of pipeline data is integrated with other pipeline operand selection logic. | 02-12-2009 |
| 20090094481 | Enhancing Reliability of a Many-Core Processor - In one embodiment, the present invention includes a method for identifying available cores of a many-core processor, allocating a first subset of the cores to an enabled state and a second subset of the cores to a spare state, and storing information regarding the allocation in a storage. The allocation of cores to the enables state may be based on a temperature-aware algorithm, in certain embodiments. Other embodiments are described and claimed. | 04-09-2009 |
| 20090138757 | FAILURE RECOVERY METHOD IN CLUSTER SYSTEM - There is provided a method executed in a cluster system comprising a first computer and at least one second computer that stores the data transmitted from the first computer. The method comprising the steps of: judging whether the failure-occurred processing is restarted by the first computer or the failure-occurred processing is switched over by the second computer based on the system information; receiving the stored data from the second computer and re-executing the processing in which the failure has occurred by the first computer, in the case of which it is judged that the processing in which the failure has occurred is restarted by the first computer; and executing, by the second computer, the processing in which the failure has occurred, in the case of which it is judged that the processing in which the failure has occurred is switched over by the at least one second computer. | 05-28-2009 |
| 20090138758 | METHOD AND SYSTEM TO EXECUTE RECOVERY IN NON-HOMOGENEOUS MULTI PROCESSOR ENVIRONMENTS - Disclosed are a method and system for parallel execution of recovery in a non-homogeneous multi-processor environment. The method defines criteria how to decide which recovery actions are to be performed, and on which processor. If multiple recovery actions are pending, the goal is to execute them in parallel on multiple processors. This is much more efficient than the traditional approach of one processor doing all the required recovery. In addition, in large, non-homogeneous systems such a single processor capable of doing the complete recovery might not be existing at all due to technical limitations. The method of this invention also defines rules and mechanisms how multiple processors executing recovery in parallel can access shared resources while avoiding deadlock situations. This includes accessing resources that are currently owned by another processor. | 05-28-2009 |
| 20090158088 | Self-Correcting Computer - The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached. The milestone may be a predetermined time interval or any other event that may be defined by a user. | 06-18-2009 |
| 20090240979 | DETERMINING A SET OF PROCESSOR CORES TO BOOT - Techniques that determine a strict subset of multiple processor cores from a set of multiple functional processor cores integrated within a single integrated circuit package. The determined strict subset of multiple processor cores differs from a previously determined strict subset of multiple processor cores from the set of multiple functional processor cores used to initiate an immediately previous core booting. In response to a processor reset, booting of the strict subset of multiple processor cores is initiated. Also, support for selecting multiple modes of operations, either supporting fault tolerance or extended life. | 09-24-2009 |
| 20090240980 | INFORMATION PROCESSING DEVICE AND FAILURE CONCEALING METHOD THEREFOR - An information processing device comprises a plurality of processing units on which OSs and execution environments operate, and shared peripheral devices shared by the plurality of processing units. The information processing device is provided with a failure concealing device for concealing a failure which has occurred in a processing unit. The failure concealing device determines a substitutional processing unit that will act as a substitute for a failed processing unit so that the OS and execution environment which have operated on the failed processing unit will operate on the substitutional processing unit, switches the OS and execution environment which have operated on the failed processing unit so that they will operate on the substitutional processing unit, and switches a shared resource used by the failed processing unit such that it is available to the substitutional processing unit. | 09-24-2009 |
| 20090259883 | ROBUST SYNCHRONIZATION OF DIAGNOSTIC INFORMATION AMONG POWERTRAIN CONTROL MODULES - An automotive system has a primary control module, such as an engine control module (ECM) configured for connection to a malfunction indicator lamp (MIL), and a secondary control module, such as a transmission control module (TCM), each in communication with each other over a bus. Each control module includes a respective diagnostic data status record. Each record includes a pending fault field, a confirmed fault field and an MIL control status field. An improved method for synchronizing the diagnostic data contained in the respective status records includes an extended status signal set that is used to communicate over the bus. The set includes a diagnostic testing complete signal, a fault present signal and a MIL request signal indicative of a request to illuminate the MIL. Logic in the receiving control module (ECM) interprets the extended status signal set to properly synchronize its diagnostic data status record with the TCM's, including both pending and confirmed faults. | 10-15-2009 |
| 20090259884 | COST-REDUCED REDUNDANT SERVICE PROCESSOR CONFIGURATION - A redundant service processor configuration is provided. A first processor in a first node operates elements in the first node. A first control line connects the first processor to a first multiplexer in the first node. A second processor in a second node operates elements in the second node. A second control line connects the second processor to a second multiplexer in the second node. The first control line from the first processor connects to the second multiplexer. The second control line from the second processor connects to the first multiplexer. In response to a failure of the second processor, the first processor operates the first multiplexer to initialize the elements of the first node, the second processor is switched off, and the first processor operates the second multiplexer to initialize the elements of the second node. Analogous operations occur in response to a failure of the first processor. | 10-15-2009 |
| 20090300414 | METHOD AND COMPUTER SYSTEM FOR MAKING A COMPUTER HAVE HIGH AVAILABILITY - A method and a computer system for making a computer achieve high availability. The method includes running a host virtual machine on a host virtual machine container; running a servant virtual machine on the servant virtual machine container; and synchronizing the host virtual machine and the servant virtual machine by using an I/O instruction. The system includes at least two computers including a host computer and a servant computer, each computer including a virtual machine container; a virtual machine running on the virtual machine container; and a communication channel making the virtual machine container execute a virtual machine synchronization operation. The virtual machine synchronization operation of the virtual machine container is triggered by the virtual machine executing I/O instructions. | 12-03-2009 |
| 20090313500 | CONTAINMENT AND RECOVERY OF SOFTWARE EXCEPTIONS IN INTERACTING, REPLICATED-STATE-MACHINE-BASED FAULT-TOLERANT COMPONENTS - A method, system and article of manufacture are disclosed for error recovery in a replicated state machine. A batch of inputs is input to the machine, and the machine uses a multitude of components for processing those inputs. Also, during this processing, one of said components generates an exception. The method comprises the steps of after the exception, rolling the state machine back to a defined point in the operation of the machine; preemptively failing said one of the components; re-executing the input batch in the state machine; and handling any failure, during the re-executing step, of the one of the components using a defined error handling procedure. The rolling, preemptively failing, re-executing and handling steps are repeated until the input batch runs to completion without generating any exception in any of the components that are not preemptively failed. | 12-17-2009 |
| 20100011242 | Failover method and system for a computer system having clustering configuration - A failover method for a computer system having a clustering configuration, in which among a plurality of computers having the clustering configuration, any one of computers, when detecting a malfunction of a system including a certain computer, transmits a detection of the system malfunction to computers configuring the other systems, and the any one of computers, when detecting the malfunction of the system including the certain computer and receiving malfunction notifications of the system including the certain computer from the computers configuring the other systems, issues a reset request to the certain computer. | 01-14-2010 |
| 20100017652 | APPARATUS WITH REDUNDANT CIRCUITRY AND METHOD THEREFOR - An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry. | 01-21-2010 |
| 20100042871 | System with Configurable Functional Units and Method - A method and a system is provided for the processing of data or signals with a number of functional units which are each adapted to apply one or several functions to the data or signals, and which are connected with each other via a connection matrix for the exchange of data or signals between the functional units. At least one functional unit of the system is programmable and/or configurable such that it performs a particular function out of a number of different functions. The connection matrix is programmed and/or configured such that the functional units are connected with each other in a particular configuration out of a number of different configurations. | 02-18-2010 |
| 20100162042 | MULTIPROCESSOR SYSTEM AND CONTROL METHOD THEREOF - A multiprocessor system is disclosed. The multiprocessor system includes plural processor cores to which control to be performed is allocated. The multiprocessor system includes a monitoring processor which detects an abnormal operation that has occurred in a specific processor core to which control having a higher priority order than control to be allocated to processor cores other than the specific processor core is allocated. When the monitoring processor detects the abnormal operation in the specific processor core, the monitoring processor allocates the control having the higher priority order to one of the processor cores other than the specific processor core. | 06-24-2010 |
| 20110004787 | SELF-REPAIRING ELECTRONIC DATA SYSTEM - An array of logic devices capable of self-determining the program, inputs and outputs from configuration information provided by its nearest neighbours. The rules used by each device to self-determine its behaviour are identical to those of every other device in the array. This facilitates the development of robust array configurations and robust behaviour of the device as a whole. This system's logic devices utilize three shift-registers, two are programmed before operation, the third is programmed on-the-fly by the other two. This facilitates a fast response to changes in the performance of the array in the event of partial dynamic or static failures of the array. An iterative design algorithm for the array ensures optimum use of the resources of the array. | 01-06-2011 |
| 20110010581 | CONVERGENT MEDIATION SYSTEM WITH DYNAMIC RESOURCE ALLOCATION - An object is to create a convergent mediation system ( | 01-13-2011 |
| 20110047412 | PARALLEL PROGRAMMING ERROR CONSTRUCTS - A system receives a program, allocates the program to a first software unit of execution (UE) and a second software UE, executes a first portion of the program with the first and second software UEs in parallel, and determines whether an error is detected during execution of the first portion of the program by the first and second software UEs. The system also sends a signal, between the first and second software UEs, to execute a second portion of the program when the error is detected in the first portion of the program, executes the second portion of the program with the first and second software UEs when the error is detected, and provides for display information associated with execution of the first portion and the second portion of the program by the first and second software UEs. | 02-24-2011 |
| 20110214012 | SECURED COPROCESSOR COMPRISING AN EVENT DETECTION CIRCUIT - A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of the command so as to detect any execution error, putting the coprocessor into an error mode by default as soon as the execution of the command begins, and lifting the error mode at the end of the execution of the command if no error has been detected, an event detection circuit for monitoring the appearance of at least one event to be detected, and a masking circuit for masking the error mode while the event to be detected does not happen, and declaring the error mode to the outside of the coprocessor if the event to be detected happens while the coprocessor is in the error mode. Application in particular but not exclusively to coprocessors embedded in integrated circuits for smart cards. | 09-01-2011 |
| 20120047397 | CONTROLLING APPARATUS, METHOD FOR CONTROLLING APPARATUS AND INFORMATION PROCESSING APPARATUS - A controlling apparatus for controlling an information processing apparatus, the controlling apparatus includes a first controller including a first data transfer unit that communicates data between the information processing apparatus, and a first processing unit that generates a command to instruct the first data transfer unit to communicate data between the information processing apparatus, and a second controller including a second data transfer unit that communicates data between the information processing apparatus, and a second processing unit that generates a command to instruct the second data transfer unit to communicate data between the information processing apparatus. | 02-23-2012 |
| 20120124417 | DISPLAY APPARATUS AND METHOD FOR UPDATING MICOM CODE THEREOF - A display apparatus and a method for updating a micom code thereof are provided. According to the display apparatus, if an error occurs while a CPU is updating a micom code, a micom may drive the CPU using a system code. Accordingly, even if an error occurs in the process of updating the micom code, the display apparatus may be restored automatically without a jig apparatus. | 05-17-2012 |
| 20120159241 | INFORMATION PROCESSING SYSTEM - An information processing system may not degrade a processor, if the system is designed so as to satisfy connection restrictions between processors and chipsets. In the system a route switching function is provided to control the connection between a CPU and a BIOS ROM among a plurality of CPUs and the BIOS ROM. When a fault occurs in a particular CPU, a route connecting the BIOS ROM and another CPU in which a fault does not occur is determined, and then the route switching is performed on the basis of the determined route information. | 06-21-2012 |
| 20120185726 | Saving Power in Computing Systems with Redundant Service Processors - A mechanism is provided for saving power in redundant service processors of the data processing system. A redundant service processor places a plurality of components into a low power state in response to receiving a primary control signal from a primary service processor within a first predetermined time period. The redundant service processor monitors for a signal within a second predetermined time period from the primary service processor. The redundant service processor determines whether the signal is a heartbeat signal or an activate signal in response to receiving the signal from the primary service processor within the second predetermined time period. Responsive to receiving the activate signal, the redundant service processor wakes-up the plurality of components that are in the low-power state in order for the redundant service processor to collect data and recover the data processing system in an event of a failure. | 07-19-2012 |
| 20120246512 | PARALLEL COMPUTER SYSTEM, CONTROL DEVICE, AND CONTROLLING METHOD - The control device detects a failed node in which a failure has occurred from a plurality of computation nodes included in a plurality of computation units included in the parallel computer. The control device chooses execution nodes for executing the program from the computation nodes of the parallel computer except the detected failed nodes based on the number of computation nodes needed to execute the program. The control device selects a paths to connect the computation nodes from a plurality of links each connecting two computation units adjacent to each other through a plurality of paths configured to connect computation nodes included in two computation units adjacent to each other in a one-to-one manner included in the links connecting two computation units adjacent to each other in the plurality of computation units including the choosed execution nodes except the path connected to the detected failed node. | 09-27-2012 |
| 20130007514 | REDUNDANT SYSTEM - The reliability of output data is enhanced, and the frequency of stopping arithmetic devices is reduced. A redundant system includes an input device; a plurality of arithmetic devices that receive input data from the input device; and an output device that receives output data output from the arithmetic devices, the redundant system causing the arithmetic devices to perform the same processing. Each of the arithmetic devices includes: a first communication unit that acquires the input data from the input device; and a second communication unit that sends the input data acquired by the first communication unit to other arithmetic device and receives the input data acquired by the other arithmetic device from the other arithmetic device. | 01-03-2013 |
| 20130091380 | Dynamically Reconfiguring A Primary Processor Identity Within A Multi-Processor Socket Server - Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server. | 04-11-2013 |
| 20130111264 | PROCESSOR DEVICE AND PROGRAM | 05-02-2013 |
| 20130145210 | FLEXIBLE REPLICATION WITH SKEWED MAPPING IN MULTI-CORE CHIPS - For a flexible replication with skewed mapping in a multi-core chip, a request for a cache line is received, at a receiver core in the multi-core chip from a requester core in the multi-core chip. The receiver and requester cores comprise electronic circuits. The multi-core chip comprises a set of cores including the receiver and the requester cores. A target core is identified from the request to which the request is targeted. A determination is made whether the target core includes the requester core in a neighborhood of the target core, the neighborhood including a first subset of cores mapped to the target core according to a skewed mapping. The cache line is replicated, responsive to the determining being negative, from the target core to a replication core. The cache line is provided from the replication core to the requester core. | 06-06-2013 |
| 20130179727 | Reliable compute engine, method and apparatus - A redundant controller engine (RCE) of a system includes a first, second and at least a third redundant processing unit (RPU). The RCE includes an arbitrator in communication with the first, second and third RPUs which sends a message for a corresponding time requiring a decision to the first, second and third RPUs, and receives the decisions made by the first, second and third RPUs. The arbitrator accepts a first two matching decisions for the corresponding time received from the first, second and third RPUs, and sending the matching decision for the corresponding time to the system. The arbitrator has a first message processing unit (MPU) and a second MPU. The first MPU sends the message for the corresponding time to and receives the decisions for the corresponding time from the first, second and third RPUs. A method for processing data from a system. An apparatus for conferencing. | 07-11-2013 |
| 20130205169 | MULTIPLE PROCESSING ELEMENTS - A first processing element can run within a first operating range. A second processing element can run within a second operating range. A third processing element can be activated if the second processing element fails or can be refrained from being run unless the first or second processing element fails. | 08-08-2013 |
| 20140053019 | REDUCED-IMPACT ERROR RECOVERY IN MULTI-CORE STORAGE-SYSTEM COMPONENTS - A method for recovering from an error in a multi-core storage-system component is disclosed. In one embodiment, such a method includes detecting an error in a first core of a multi-core component. The method determines whether the error was one of (1) detected by the first core; and (2) detected by a core other than the first core. In the event the error was detected by the first core and the error is recoverable, the first core recovers from the error without substantially impacting operation of other cores in the multi-core component. In the event the error was detected by a core other than the first core and the error is recoverable, a core other than the first core recovers from the error without substantially impacting operation of other cores in the multi-core component. A corresponding apparatus and computer program product are also disclosed. | 02-20-2014 |
| 20140089732 | THREAD SPARING BETWEEN CORES IN A MULTI-THREADED PROCESSOR - Embodiments relate to thread sparing between cores in a processor. An aspect includes determining that a number of recovery attempts made by a first thread on the first core has exceeded a recovery attempt threshold, and sending a request to transfer the first thread. Another aspect includes, selecting a second core from a plurality of cores to receive the first thread from the first core, wherein the second core is selected based on the second core having an idle thread. Another aspect includes transferring a last good architected state of the first thread from the first core to the second core. Another aspect includes loading the last good architected state of the first thread by the idle thread on the second core. Yet another aspect includes resuming execution of the first thread on the second core from the last good architected state of the first thread by the idle thread. | 03-27-2014 |
| 20140108861 | SYSTEMS AND METHODS FOR FAULT TOLERANT, ADAPTIVE EXECUTION OF ARBITRARY QUERIES AT LOW LATENCY - A system and method for performing distributed execution of database queries includes a query server that receives a query to be executed on a database, forms a query plan based on the query, assigns tasks to task slots on a plurality of worker nodes in a cluster, and, upon receipt of a notification that a task has completed on a worker node, immediately assigns an unassigned task to a free task slot on that worker node, such that the task may begin executing on that worker node substantially immediately thereafter. The task slots on worker nodes include pools of resources that run tasks without start-up overhead. | 04-17-2014 |
| 20140237289 | HANDLING FAULTS IN A CONTINUOUS EVENT PROCESSING (CEP) SYSTEM - The concept of faults and fault handling are added to the execution of continuous event processing (CEP) queries. By introducing fault handling techniques to the processing of CEP queries, users are enabled to instruct a CEP query processor to respond to faults in a customized manner that does not necessarily involve the halting of the CEP query relative to which the faults occurred. For example, a fault might be due to a temporary problem. Under such circumstances, the CEP query processor can be instructed to ignore the fault and allow the execution of the CEP query to continue relative to the remainder of the event stream. Alternatively, if the fault is due to a problem with the CEP query itself, then the CEP query processor can be instructed to propagate the fault through the query processing system until the fault ultimately causes the problematic CEP query to be halted. | 08-21-2014 |
| 20140258776 | SYSTEM ON CHIP FAULT DETECTION - The invention relates to a method for fault identification in a System-on-Chip (SoC) consisting of a number of IP cores, wherein each IP core is a fault containment unit, and where the IP cores communicate with one another by means of messages via a Network-on-Chip, and wherein an excellent IP core provides a TRM (Trusted Resource Monitor), wherein a faulty control message which is sent from one non-privileged IP core to another non-privileged IP core is identified and projected by an (independent) fault container unit, as a result of which this faulty control message cannot cause any failure of the message receiver. | 09-11-2014 |
| 20140344619 | PROCESSOR CAPABLE OF DETECTING FAULT AND METHOD OF DETECTING FAULT OF PROCESSOR CORE USING THE SAME - A processor capable of detecting fault and a method of detecting the fault of processor core using the same are disclosed. The processor includes a first processor core, a second processor core, and a fault manager. The first processor core includes one or more pipeline registers. The second processor core has a same structure as the first processor core, and is included in a single chip along with the first processor core. The comparator compares the value of the pipeline register of the first processor core with the value of the pipeline register of the second processor core. The fault manager performs a fault management operation if, as a result of the comparison of the comparator, it is determined that a fault has occurred. | 11-20-2014 |
| 20150052389 | MANAGEABILITY REDUNDANCY FOR MICRO SERVER AND CLUSTERED SYSTEM-ON-A-CHIP DEPLOYMENTS - Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks. | 02-19-2015 |
| 20150082083 | INFORMATION PROCESSING SYSTEM AND INFORMATION PROCESSING METHOD - An information processing system includes two or more processors each of which can execute one or more instructions, an executability information storage unit in which executability information, which includes information specifying instructions as being executable or not executable by each of the two or more processors, can be stored for each of the two or more processors, and a control unit that, at the time of execution of a program, selects at least one processor for execution of one or more instructions necessary to execute the program, from among the two or more processors, with reference to the executability information, and causes the selected at least one processor to execute the instructions. | 03-19-2015 |
| 20160003910 | SEMICONDUCTOR DEVICE - The disclosed invention provides a semiconductor device that enables early discovery of a sign of aged deterioration that occurs locally. An LSI has a plurality of modules and a delay monitor cluster including a plurality of delay monitors. Each delay monitor inducts a ring oscillator having a plurality of gate elements. Each delay monitor measures a delay time of the gate elements. A CPU #0 determines if a module proximate to a delay monitor suffers from aged deterioration, based on the delay time measured by the delay monitor. | 01-07-2016 |
| 20160011948 | Run-To-Completion Thread Model for Software Bypass Fail Open for an Inline Intrusion Protection System | 01-14-2016 |
| 20160019126 | FAILURE RECOVERY APPARATUS OF DIGITAL LOGIC CIRCUIT AND METHOD THEREOF - Exemplary embodiments of the present invention relate to a failure recovery apparatus of digital logic circuit and method thereof when a fault occurs in the digital logic circuit. A failure recovery apparatus according to an embodiment of the present invention comprises: a fault detection block configured to determine fault occurrence by comparing output results of a plurality of digital logic circuit which perform the same operation using a clock having a first cycle; and a failure recovery block configured to perform a failure recovery operation of the plurality of digital logic circuit by using a clock having a second cycle which is longer than the first cycle when it is determined as that a fault occurs. According to exemplary embodiments of the present invention, when a fault occurs in digital logic circuits due to external factors, it provides high reliability in failure recovery of the digital logic circuits. | 01-21-2016 |
| 20160019130 | TRACKING CORE-LEVEL INSTRUCTION SET CAPABILITIES IN A CHIP MULTIPROCESSOR - Techniques described herein generally relate to a task management system for a chip multiprocessor having multiple processor cores. The task management system tracks the changing instruction set capabilities of each processor core and selects processor cores for use based on the tracked capabilities. In this way, a processor core with one or more failed processing elements can still be used effectively, since the processor core may be selected to process instruction sets that do not use the failed processing elements. | 01-21-2016 |
| 20160034367 | METHOD FOR LIMITING THE RISK OF ERRORS IN A REDUNDANT, SAFETY-RELATED CONTROL SYSTEM FOR A MOTOR VEHICLE - The invention relates to a method and a device for limiting the risk of faults in a control system, in particular a safety-relevant control system, wherein a preferably intelligent actuator controller (AST), by means of the application of a weighted mean value algorithm, calculates a new control value from the two control values determined by means of diverse redundancy by two independent fault-containment units (FCUs), which new control value, in spite of the occurrence of a fault in one of the two FCUs, causes an object to be controlled by the control system to be guided into a safe state, preferably quickly. | 02-04-2016 |
| 20160034368 | SEMICONDUCTOR DEVICE - Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core | 02-04-2016 |
| 20160170849 | LEVERAGE OFFLOAD PROGRAMMING MODEL FOR LOCAL CHECKPOINTS | 06-16-2016 |
| 714012000 | Synchronization maintenance of processors | 12 |
| 20080270828 | Memory Redundancy Method and Apparatus - Redundancy is provided in a memory device having a configurable data bus organization by associating a redundant memory location with a defective memory location and configuring a size of the redundant memory location based on the current data bus organization of the memory device. | 10-30-2008 |
| 20090063898 | Processor Instruction Retry Recovery - Recovery circuits react to errors in a processor core by waiting for an error-free completion of any pending store-conditional instruction or a cache-inhibited load before ceasing to checkpoint or backup progress of a processor core. Recovery circuits remove the processor core from the logical configuration of the symmetric multiprocessor system, potentially reducing propagation of errors to other parts of the system. The processor core is reset and the checkpointed values may be restored to registers of the processor core. The core processor is allowed not just to resume execution just prior to the instructions that failed to execute correctly the first time, but is allowed to operate in a reduced execution mode for a preprogrammed number of groups. If the preprogrammed number of instruction groups execute without error, the processor core is allowed to resume normal execution. | 03-05-2009 |
| 20090089613 | REDUNDANCY SYSTEM HAVING SYNCRONIZATION FUNCTION AND SYNCRONIZATION METHOD FOR REDUNDANCY SYSTEM - A redundancy system that can perform synchronization even if a failure occurs to an application. According to the redundancy system of the present invention, a synchronization data memory area, a management bit map table having a flag created for each segment of the synchronization data memory area, and a management memory area for storing the starting address of the segment are set in each device. In the service application process, a service is performed using one or more segments, a flag corresponding to the segment is set, and synchronization information is written to the management memory each time the segment is written or overwritten. In the read process, each flag in the management bit map table is checked, and if a flag being set exists, the synchronization data is read from the segment corresponding to the synchronization information stored in the management memory, and the flag is reset. | 04-02-2009 |
| 20090259885 | Systems and methods for redundancy management in fault tolerant computing - Systems and methods for redundancy management in fault tolerant computing are provided. The systems and methods generally relate to enabling the use of non-custom, off-the-shelf components and tools to provide redundant fault tolerant computing. The various embodiments described herein, generally speaking, use a decrementer register in a general purpose processor for synchronizing identical operations across redundant general purpose processors, execute redundancy management services in the kernels of commercial off-the-shelf real-time operating systems (RTOS) running on the general purpose processors, and use soft coded tables to schedule operations and assign redundancy management parameters across the general purpose processors. | 10-15-2009 |
| 20120005525 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD FOR INFORMATION PROCESSING APPARATUS, AND COMPUTER-READABLE MEDIUM FOR STORING CONTROL PROGRAM FOR DIRECTING INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a degeneration control unit and a re-synchronization processing instructing unit. The degeneration control unit degenerates, of a first controller group including a first controller and a second controller group including a second controller, the second control device group when the first and second controller performing a synchronization operation with each other detect occurrence of errors. The re-synchronization processing instructing unit instructs a controller included in the first controller group to execute re-synchronization processing. When another controller different from the first controller receives the instruction for the execution of the re-synchronization processing, the another controller performs interrupt mask setting. When the first controller receives the instruction for the execution of the re-synchronization processing, the first controller withholds the execution of the re-synchronization processing, starts error processing, and instructs the controller that performs the interrupt mask setting to release the interrupt mask. | 01-05-2012 |
| 20120117419 | SYSTEM, METHOD AND APPARATUS FOR ERROR CORRECTION IN MULTI-PROCESSOR SYSTEMS - This disclosure provides apparatus, methods and systems for error correction in multi processor systems. Some implementations include a plurality of computing modules, each computing module including a processor. Each processor may include processing state. In some other implementations, each computing module may also include a memory. Upon receiving a signal to perform a partial re-synchronization, a hash of each processor's state data may be performed. In some embodiments, a hash of at least a portion of each computing module's memory data may also be performed. The hashes for each processor are then compared to determine majority hashes and possible minority hashes. Upon identifying a minority hash, the computing module that produced the minority hash may receive new processing state data from one of the computing modules that produced a majority hash. | 05-10-2012 |
| 20120221889 | SYSTEM AND METHOD FOR DUPLEXED REPLICATED COMPUTING - Systems and methods are disclosed herein for a replicated duplex computer system. The system includes a triplet of network elements, which each maintain a clock signal, and a monitor at each network element for monitoring incoming clock signals. Each network element interfaces with a fault containment region (FCR). The system provides the ability to transition to a duplex system if one of the fault containment regions fails. The three network elements are able to send their clock signals to the other network elements and receive their own clock signal and clock signals from the other elements. The monitors are configured to detect discrepancies in the clock signals of the network elements. If a monitor determines that an FCR has failed, each network element is reconfigured so that the FTPP system operates in a duplex mode without the faulty FCR by replacing the clock signal from the faulty element with its own clock signal. | 08-30-2012 |
| 20140082413 | SYSTEM AND METHOD FOR USING REDUNDANCY OF CONTROLLER OPERATION - Exemplary embodiments are directed to a system and method for maintaining continuous operation applications in spite of hardware faults, maintenance, or replacement. The system having at least two physically redundant controllers, each controller being configured to achieve at least one of high availability and functional safety and having at least one control unit which actively participates in a control loop, and n redundant units that are kept synchronized in a stand-by mode. The at least two controllers are configured such that software code recorded on a first of the at least two controllers is replicated among others of the at least two controllers. Moreover, each of the at least two controllers include central processing units (CPUs) has a plurality of cores arranged within a single piece of silicon. | 03-20-2014 |
| 20140143595 | MICROCOMPUTER RUNAWAY MONITORING DEVICE - The invention provides a control device for mutually monitoring two microcomputers at a low cost while reducing a parts number and doubly monitoring abnormality in each of the microcomputers. The control device transmits a reset signal to a main microcomputer and resets the main microcomputer when a frequency of a first pulse signal deviates from a normal frequency range determined by a frequency calculating means, in which the first pulse signal is output from the main microcomputer, and the frequency calculating means calculates a frequency of the first pulse signal by an input of the first pulse signal to a sub microcomputer. The control device transmits a reset signal to the sub microcomputer and resets the sub microcomputer when a frequency of a second pulse signal deflects from a normal frequency range, by an input of the second pulse signal to the main microcomputer from the sub microcomputer. | 05-22-2014 |
| 20150095699 | CONTROL DEVICE, CONTROL METHOD AND RECORDING MEDIUM STORING PROGRAM THEREOF - A control device according to an exemplary aspect of the present invention, which is included in a sub-system of a plurality of sub-systems included in a fault tolerant system, includes: a packet reception unit that receives data from a processor unit included in the plurality of sub systems each including: the processor unit; an input-output unit; and a signal transmission path, the control device being connected between the processor unit and the input-output unit; and a first transmission unit that transmits error detection data being generated from the data of accessing from the processor unit to the input-output unit in an own sub-system to an companion sub-system when the processor unit is in the lockstep synchronous state, and transmits the data of accessing from a processor unit to the input-output unit in the own sub-system to the companion sub-system when the processor is in a lockstep asynchronous state. | 04-02-2015 |
| 20150363283 | MULTI-THREADED SERVER CONTROL AUTOMATION FOR DISASTER RECOVERY - Systems and methods for multi-threaded server control automation for disaster recovery are described. A method may include initiating a disaster recovery sequence on two or more processors, wherein the disaster recovery sequence comprises a plurality of subsequences. The method may also include implementing the disaster recovery sequence on the two or more processors in parallel, wherein one or more subsequences of the disaster recovery sequence are implemented on the two or more processors in parallel. Upon completion of the disaster recovery sequence, at least one server partition is repurposed from a first configuration, such as a test configuration, to a second configuration, such as a production configuration. | 12-17-2015 |
| 20180024896 | INFORMATION PROCESSING SYSTEM, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING METHOD | 01-25-2018 |
