Entries |
Document | Title | Date |
20080229145 | Method and system for soft error recovery during processor execution - A system for soft error recovery used during processor execution. The system may include a microprocessor, processor, controller, or the like. The system may also include a pipeline to reduce the cycle time of the processor, and a write-back stage within the pipeline. The system may further include an error-correcting code stage before the write-back stage that checks a value to be written by the processor for any error. The error-correcting code stage may correct any error in the value, and the pipeline may lack a recovery unit pipeline. | 09-18-2008 |
20080235535 | WRITING DATA PROCESSING CONTROL APPARATUS, WRITING METHOD, AND WRITING APPARATUS - A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus. | 09-25-2008 |
20080288815 | Firmware assisted error handling scheme - A firmware assisted error handling scheme in a computer system has been disclosed. In one embodiment, firmware is used to access one or more hardware-specific error registers within the computer system in response to a system management interrupt (SMI) trap. Using the firmware, an error record in a common error record format is constructed. The error record is made available to an operating system (OS) within the computer system. | 11-20-2008 |
20080288816 | System module and data relay method - A system module includes a plurality of processors, and a system controller that is connected to the processors via a first transmission line and relays a packet from each of the processors to another system module via a second transmission line in a multiprocessor system. The system controller includes a data transmission controller that, when part of packets constituting a series of data is not received normally from a processor due to a fault in the processor or the first transmission line, generates a supplement packet for a packet that has not been received normally and outputs the supplement packet to the second transmission line. | 11-20-2008 |
20080307254 | INFORMATION-PROCESSING EQUIPMENT AND SYSTEM THEREFOR - In cases where the system which performs service provision includes plural kinds of OS, the plural kinds of OS are operated simultaneously on one standby server provided with the virtual control unit. When a failure etc. occurred in the operation system server necessitates the system switchover from the operation system server to the standby server, the virtual control unit of the standby server distinguishes an operation system server in which the failure has occurred, and takes over the processing to the switching control unit on a suitable OS on the standby server. | 12-11-2008 |
20090049336 | PROCESSOR CONTROLLER, PROCESSOR CONTROL METHOD, STORAGE MEDIUM, AND EXTERNAL CONTROLLER - A processor having a plurality of hardware resources can perform separate controls within a proper range according to the dependent relations of hardware resources troubled. In case a notification is made of the failure of the hardware resources constituting the processor, a processor control method decides the range of the hardware resources, which cannot be used because of that failure, as a failure range, on the basis of the dependencies of the individual hardware resources predetermined, and stops the use of the hardware resources of the failure range on the basis of that decision result. When the use of the hardware resources indicated by the failure range is stopped, the hardware is not stopped before a predetermined operation is performed not to affect the instruction processing procedure outside of the failure range. | 02-19-2009 |
20090063897 | METHOD OF INCREASING SYSTEM AVAILABILITY BY ASSIGNING PROCESS PAIRS TO PROCESSOR PAIRS - A method is provided of assigning processors in a multiprocessor environment to a plurality of processes that are executed in the multiprocessor environment. Each process has a process pair defined by a primary process that executes on a first processor, and a backup process that executes on a second processor. There are a plurality of process pairs. The processors are in communication with one another via a communication network. The processors are associated with a plurality of predefined processor pairs. First, a plurality of process pairs are provided that are initially assigned to a respective plurality of pairs of processors, wherein at least one of the processors in the plurality of pairs of processors is initially assigned to more than one processor pair. Each processor is then assigned to only one of the predefined processor pairs so that no processor belongs to more than one processor pair. Then, each of the plurality of process pairs are assigned to a respective one of the predefined processor pairs. This assigning process results in a configuration that reduces the number of failure modes from the number of failure modes that exists in the initial configuration. | 03-05-2009 |
20090119540 | Device and method for performing switchover operations in a computer system having at least two execution units - A device and method for performing switchover operations in a computer system having at least two execution units, a changeover switch being provided which switches between at least two operating modes, a first operating mode corresponding to a comparison mode, and a second operating mode corresponding to a performance mode, in addition, a comparator being provided which is activated in the comparison mode, in which an arrangement provides desired switchover detection, the arrangement for desired switchover detection controlling the changeover switch in order to switch from one operating mode to another. | 05-07-2009 |
20090119541 | Information Processing Device, Recovery Device, Program and Recovery Method - The information processing device which recovers a domain developing a fault caused by added application and device driver while maintaining security and reliability includes a plurality of processors, wherein the plurality of processors form a plurality of domains according to processing contents to be executed, and the processors in different domains communicate with each other through a communication unit, and which further includes a recovery unit for executing, for a domain developing a fault, failure recovery processing based on a failure recovery request notified by the domain and a recovery condition set in advance for each domain. | 05-07-2009 |
20090177919 | DYNAMIC REDUNDANCY FOR MICROPROCESSOR COMPONENTS AND CIRCUITS PLACED IN NONOPERATIONAL MODES - An apparatus for implementing dynamic redundancy for a microprocessor system includes a plurality of microprocessor components, each of which is capable of being selectively placed in a non-operational mode while one or more other of the microprocessor components remain in an operational mode, and then subsequently restored from the non-operational mode back to the operational mode, the spare microprocessor component configured to be switched from the non-operational mode to the operational mode whenever one of the plurality of the microprocessor components is placed in the non-operational mode, and wherein the spare microprocessor component is configured to be switched back to the non-operational mode whenever each of the microprocessor components are in the operational mode; and multiplexing circuitry configured to map the use of the microprocessor components and the spare microprocessor component with respect to the operational mode and the non-operational mode. | 07-09-2009 |
20090193291 | Equipment controlling system and controlling method thereof - An equipment controlling system and a controlling method thereof are disclosed. The system includes a first controller connected to equipments of a first group to monitor and control operations of the equipments; and a second controller connected to equipments of a second group to monitor and control operations of the equipments; the first controller emergently controlling the equipments of the second group when the second controller malfunctions, and the second controller emergently controlling the equipments of the second group when the first controller malfunctions. When control problem of equipments such as indoor and outdoor unit due to malfunction of a controller is solved, a systemic and consistent control are enabled by consistently controlling the equipments so that control efficiency is enhanced and the equipments are kept in operating to provide a comfortable condition and an improved convenience to a user. | 07-30-2009 |
20090307526 | MULTI-CPU FAILURE DETECTION/RECOVERY SYSTEM AND METHOD FOR THE SAME - A multi-CPU system including plural CPUs, comprising a failure state detection unit for detecting a failure in an operating program, and a recovery unit for determining, when the failure state detection unit has detected a failure, whether or not recovery of data involved in the failure is possible on the basis of content of the detected failure, and for recovering the data when recovery is determined to be possible. | 12-10-2009 |
20100005338 | Programmable Logic Configuration for Instruction Extensions - A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory. | 01-07-2010 |
20100011240 | DEVICE AND METHOD FOR SYNCHRONIZING THE STATES OF A PLURALITY OF SEQUENTIAL PROCESSING UNITS - A device for providing a plurality of clock signals from a common clock signal. The device includes an input for receiving the common clock signal, a first clock signal path for providing a first output clock signal on the basis of the common clock signal and a second clock signal path for providing a second output clock signal. The second clock signal path includes a clock processing device for changing a phase of the common clock signal to provide the second clock signal. | 01-14-2010 |
20100011241 | Information processing apparatus and domain dynamic reconfiguration processing method - An information processing apparatus includes a domain configured by plural system boards, and a pair of service processors, wherein when one of the pair of service processors fails during the execution of domain dynamic reconfiguration processing for the domain, the other of the pair of service processors takes over and executes the domain dynamic reconfiguration processing under execution. | 01-14-2010 |
20100031083 | INFORMATION PROCESSOR - In the event of occurrence of an error in a memory in an information processor, a first processor that is one of a number of processors executes an error handler program stored in a first memory that is one of a number of memories. If the first processor fails in correctly operating the error handler program, a second processor different from the first processor executes an error handler program stored in a second memory different from the first memory. | 02-04-2010 |
20100042870 | MULTICORE PROCESSOR AND METHOD OF CONTROLLING MULTICORE PROCESSOR - A multicore processor has a plurality of processor cores each of which is configured to execute a computation, a plurality of reconfigurable devices dynamically reconfigurable in circuit configuration on the basis of circuit information, and a lock state storage section configured to store lock information indicating whether or not each of the reconfigurable devices is locked. The multicore processor also has a plurality of reconfigurable control sections each of which is configured to load circuit information for a computation to be executed into one of the reconfigurable devices not locked, by referring to the lock information, performs execution of the computation with the reconfigurable device and execution of the computation with the one of the processor cores in parallel with each other, and perform control so that results of execution of the computation completed faster are adopted. | 02-18-2010 |
20100088542 | LOCKUP RECOVERY FOR PROCESSORS - A system comprises processing logic configured to assert a lockup signal upon detection of a fault condition and a module coupled to the processing logic and configured to activate a counter upon receiving the lockup signal. After the module activates the counter and before the counter reaches a predetermined threshold, the processing logic attempts to correct the fault condition and the module prevents the processing logic from being reset. | 04-08-2010 |
20100107005 | PROCESSOR OPERATION INSPECTION SYSTEM AND OPERATION INSPECTION CIRCUIT - A processor operation inspection system includes a processor and an operation inspection circuit that inspects an operation of the processor. When a program under execution changes from one predefined state to another state, the processor outputs a state switching signal indicating a transition of its state, a state signal indicating a current state to the inspection circuit. The inspection circuit includes a state register that stores the state of the processor, a combinational logic circuit that calculates, according to the stored state of the processor and the state switching signal, a new state to be taken by the processor, and a comparison circuit that inspects the operation of the processor by comparing the calculated new state to the state of the processor inputted as the state signal. | 04-29-2010 |
20100162041 | FETCH OPERATION SCHEDULING - Fetch operations are assigned to different threads in a multithreaded environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a sub-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. Two-level priority scheme is used to combine both priorities. The judgement of satisfactory performance is preferably based on the difference between a desired number of fetch operations attributed per sub-context switch interval to each thread and a real number of fetch operations attributed per sub-context switch interval to each thread. | 06-24-2010 |
20100229034 | CLOCK SUPPLY METHOD AND INFORMATION PROCESSING APPARATUS - A clock supply method for supplying a clock to a plurality of processing units includes supplying a clock from a first clock supply unit to processing units forming a first group as a primary clock and to processing units forming a second group as a standby clock; supplying a clock from a second clock supply unit including a clock source different from that of the first clock supply unit to the processing units forming the second group as a primary clock and to the processing units forming the first group as a standby clock; and when a processing unit in the first or second group detects an abnormality of the primary clock, switching the standby clock into use in place of the primary clock being supplied to the processing units that has detected the abnormality belongs; wherein the first and second clock supply units supply clocks with the same frequency. | 09-09-2010 |
20100241899 | Debugging for multiple errors in a microprocessor environment - A new method and apparatus have been taught for storing error information used for debugging as generated by the initial and subsequent error occurrences. In this invention, a register with several bit ranges is used to store error information. The first bit-range is allocated to the initial error information. If the total number of the errors exceeds the capacity of the register, the last error is kept in a last bit-range. This way, precious initial error information (as well as the last error information) will be available for debugging. | 09-23-2010 |
20100268986 | MULTI-NODE CONFIGURATION OF PROCESSOR CARDS CONNECTED VIA PROCESSOR FABRICS - Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes. | 10-21-2010 |
20100281298 | Monitoring Device - The invention relates to a monitoring device for a processor comprising a means for monitoring the power consumption of the processor and a means for analysing the power consumption to detect abnormal operation of the processor. | 11-04-2010 |
20100293411 | IMAGE FORMING APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM - An image forming apparatus that can be used even when an access error occurs due to replacement of component elements. When replacement of a component element of the image forming apparatus is detected, it is determined whether or not a predetermined process has been normally carried out on the component element. When it is determined that the predetermined process has not been normally carried out, another process different from the predetermined process is carried out. When the other process has been normally carried out, the predetermined process for the component element is changed to the other process. | 11-18-2010 |
20100299557 | Providing tuning limits for operational parameters in data processing apparatus - The application discloses a means of setting tuning limits for operational parameters in a processing stage within a data processing apparatus for processing a signal. The processing stage comprises: an input for receiving the signal, processing circuitry for processing the signal and an output for outputting the processed signal at an output time; an error detecting circuit for determining if a signal output by the processing stage between the output time and a predetermined time later does not have a stable value, the predetermined time later being before a next output time, and for signaling an error if the signal is not stable; a tuning circuit for adjusting at least one operational parameter of the processing stage; a tuning limiting circuit for providing at least one tuning limit for the tuning circuit, such that the at least one operational parameter is not adjusted beyond the corresponding at least one tuning limit, a tuning limiting circuit for providing at least one tuning limit for said tuning circuit, such that said at least one operational parameter is not adjusted beyond said corresponding at least one tuning limit, the tuning limiting circuit being configured to provide the at least one tuning limit such that a signal passing along a critical path of the processing stage tuned to the tuning limit is estimated to reach the output of the processing stage at a preset time later than the output time, the preset time being less than the predetermined time. | 11-25-2010 |
20100325481 | DEVICE HAVING REDUNDANT CORE AND A METHOD FOR PROVIDING CORE REDUNDANCY - A device and a method for providing core redundancy, the device includes: multiple cores; a core operability unit adapted to indicate an operability of each core out of the multiple cores; and a core control signal unit adapted to provide mapping signals that comprise virtual core to physical core mapping signals and physical core to virtual core mapping signals; wherein each core out of the multiple cores comprises at least one interrupt interface, and a crossbar interface which are responsive to at least one mapping signal. | 12-23-2010 |
20100325482 | METHOD AND APPARATUS FOR BOOTING TO DEBUG IN PORTABLE TERMINAL - A booting method and an apparatus thereof for debugging in a portable terminal are provided. The method includes, when a booting event occurs; stacking a boot loader in a preset boot loader region of a Random Access Memory (RAM), and executing, and stacking an Operating System (OS) in a preset OS region of the RAM, wherein the boot loader region and the OS region of the RAM are set such that they do not overlap each other. | 12-23-2010 |
20100325483 | NON-FAULTING AND FIRST-FAULTING INSTRUCTIONS FOR PROCESSING VECTORS - The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation). | 12-23-2010 |
20110041006 | DISTRIBUTED TRANSACTION PROCESSING - A system and method for processing a distributed transaction for an application are disclosed. Conventionally transactions on critical data (e.g. financial information) are processed using a database architecture whereby a persistent database (typically a redundant disk array) comprises the master record. In cases where large amounts of data need to be accessed but absolute data integrity is less critical, for example search engines, processing is conducted on live in-memory data without all the data being backed up, which can be much faster but data can be lost when processors fail. There have been attempts to use data grid architectures with some backup to persistent stores for more important data but these have either introduced disk access bottlenecks or required manual intervention in the event of failure. Aspects of the invention provide committal of distributed transactions independently of persistent storage which can make the speed advantages of data grid computing available for high volume distributed transactions, without losing the reliability of conventional database systems. The methods, systems and architecture are independent of the nature of the application or data. | 02-17-2011 |
20110072303 | DATA PROCESSING WITH PROTECTION AGAINST SOFT ERRORS - A processing circuit has functional units ( | 03-24-2011 |
20110099421 | RADIATION-HARDENED HYBRID PROCESSOR - A processing system having a small form factor and configured to connect to an external platform. The processing system includes input interfaces configured to receive an input signal to be processed; a radiation tolerant field programmable gate array including processors configured to process the input signal; memory containing reconfigurable instructions for the processors that, when the reconfigurable instructions are executed, process the input signal and obtain the output signal; output interfaces configured to send the output signal to the external platform; and a reset logic element configured to selectively reset the field programmable gate array and at least one of the processors in response to a reset command. The input interfaces include at least one gigabit Ethernet interface and at least one space-rated balanced voltage digital interface circuit. The output interfaces include at least one serial advanced technology attachment interface and at least one space-rated balanced voltage digital interface circuit. | 04-28-2011 |
20110138223 | PREVENTING INFORMATION LEAKAGE BETWEEN COMPONENTS ON A PROGRAMMABLE CHIP IN THE PRESENCE OF FAULTS - Mechanisms are provided to prevent information leakage between components implemented on a programmable chip such as a Field Programmable Gate Array (FPGA). An automated routing algorithm is effective at enforcing security restrictions with minimal input form the user while providing efficient utilization of the device. Compatible sets of signals are identified and locked, and reservations of routing resources are generated. Remaining signals are rerouted until all signal constraints are met. Specified security constraints with one or more security levels and one or more secure regions may be applied through iterations of the automated routing mechanism. | 06-09-2011 |
20110145634 | APPARATUS, A RECOVERY METHOD AND A PROGRAM THEREOF - An apparatus and method for automatically recovering a hardware when the hardware is not accessible from the processing unit. The hardware is recovered via a path different from a path which the processing unit uses when the processing unit fails to access to the hardware via the path initially used. | 06-16-2011 |
20110154106 | DMI REDUNDANCY IN MULTIPLE PROCESSOR COMPUTER SYSTEMS - In accordance with various aspects of the disclosure, a method and apparatus are disclosed that includes aspects of monitoring a first processor of a computer by a monitoring module for a first processor instability; determining if the first processor is stable based on the monitored first processor instability; routing operational priority to a second processor of the computer through a multiplexer module if the first processor is determined not to be stable, wherein a first desktop management interface of the first processor and a second desktop management interface of the second processor are in communication with the multiplexer module and wherein the first processor and the second processor are in communication by a processor interconnect; and operating the computer using the second processor. | 06-23-2011 |
20110154107 | TRIGGERING WORKAROUND CAPABILITIES BASED ON EVENTS ACTIVE IN A PROCESSOR PIPELINE - A method, information processing system, and processor work around a processing flaw in a processor. At least one instruction is fetched from a memory location. The at least one instruction is decoded. An opcode compare operation is compared with the at least one instruction and a set of values within at least one opcode compare register in response to the decoding. The instruction is marked with a pattern based on the opcode compare operation. The pattern indicates that the instruction is associated with a processing flaw. | 06-23-2011 |
20110173494 | Data processing system and data processing method - A data processing system for performing stuck-at control includes system boards that process data, a crossbar unit having control units to control communication between each system board, and a system controller without causing an availability ratio of a computer system to fall. When a control unit fails, the crossbar unit sends, among IDs uniquely attached to each system board, the ID of each system board under the control of the failed control unit to the system controller. The system controller determines to which of partitions that logically divide a system each system board corresponding to the ID received from the crossbar unit belongs and sends a stop command to stop driving of each system board belonging to the determined partition. | 07-14-2011 |
20110208997 | Radiation hard and fault tolerant multicore processor and method for ionizing radiation environment - A redundancy system in a fault tolerant computer comprises a multiple core processor which may support a real time operating system. The multiple core machine may be actual or virtual. Multiple identical instructions, e.g., three instructions, are executed redundantly so that the redundancy system can detect and recover from a single event upset (SEU). The instructions are also displaced in time. In one form, two non-consecutive instructions are run on one core which is virtualized into two cores. Alternatively, a second actual core may provide symmetric processing. The system prevents single event functional interrupts (SEFIs) from hanging up the processor. Each core may run a separate operating system. When a first core hangs up a first operating system, the second operating system takes over operation and the processor recovers. Embedded routines may store selected data variables in memory for later recovery and perform an SEFI “self-test” routine. | 08-25-2011 |
20110246820 | MICROCOMPUTER MUTUAL MONITORING SYSTEM AND A MICROCOMPUTER MUTUAL MONITORING METHOD - The present invention is related to a microcomputer mutual monitoring system in which mutual monitoring is performed between a first microcomputer | 10-06-2011 |
20110271142 | METHOD AND SYSTEM FOR HANDLING A MANAGEMENT INTERRUPT EVENT IN A MULTI-PROCESSOR COMPUTING DEVICE - A method and system for handling a management interrupt, such as a system management interrupt (SMI) and/or a platform management interrupt (PMI), includes allocating two or more processor cores from a plurality of processor cores to form a group of management interrupt handling processor cores. Generated management interrupts are directed to this first group of processor cores and not to remaining processor cores, which forma second group. At least one of the processor cores in the first group handles the management interrupt without disrupting the current operation of the processor cores in the second group. | 11-03-2011 |
20120124416 | DMI REDUNDANCY IN MULTIPLE PROCESSOR COMPUTER SYSTEMS - In accordance with various aspects of the disclosure, a method and apparatus are disclosed that includes aspects of monitoring a first processor of a computer by a monitoring module for a first processor instability; determining if the first processor is stable based on the monitored first processor instability; routing operational priority to a second processor of the computer through a multiplexer module if the first processor is determined not to be stable, wherein a first interface of the first processor and a second interface of the second processor are in communication with the multiplexer module and wherein the first processor and the second processor are in communication by a processor interconnect; and operating the computer using the second processor. | 05-17-2012 |
20120137171 | ENHANCED SCALABLE CPU FOR CODED EXECUTION OF SW IN HIGH-DEPENDABLE SAFETY RELEVANT APPLICATIONS - Some embodiments of the invention relate to a single processor configured to comprise configurable hardware extensions, disposed within a data path configured to selectively provide either encoded data or original data, that allow for two modes of operation. In a high performance mode, the hardware extensions allow for increased processing bandwidth by using the hardware extensions for processing extended data (i.e., additional original data). In a safety integrity mode the hardware extensions allow for parallel processing of encoded data concurrent with the processor executing a SBST by processing a self-test program and self-test data. Therefore, the single channel processor provides a single core system that can selectively achieve either high safety integrity levels (e.g., SIL3) for safety relevant applications or high performance for non-safety relevant applications. | 05-31-2012 |
20120204059 | DISTRIBUTED VEHICLE CONTROL SYSTEM - A distributed vehicle control system comprising a secure real-time executive running as a distributed abstraction of both the application and the operating system, where the SRE comprises a message manager, security manager, critical data manager, configuration manager, and multi-processor task control manager and is configured to control how the processors communicate with each other, how the processors are initiated, how the processors start tasks, and how priorities are set for messages. | 08-09-2012 |
20120210164 | SCHEDULER FOR MULTIPROCESSOR SYSTEM SWITCH WITH SELECTIVE PAIRING - System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience. | 08-16-2012 |
20120284560 | READ XF INSTRUCTION FOR PROCESSING VECTORS - The described embodiments include a processor that handles faults. The processor first receives a first input vector, a control vector, and a predicate vector, each vector comprising a plurality of elements. For each element in the first input vector for which a corresponding element in the control vector and the predicate vector are active, the processor then performs a read operation using an address from the element of the first input vector. When a fault condition is encountered while performing the read operation, the processor determines if the element is a first element where a corresponding element of the control vector is active. If so, the processor handles/processes the fault. Otherwise, the processor masks the fault for the element. | 11-08-2012 |
20120311382 | ERROR DETECTION AND/OR CORRECTION THROUGH COORDINATED COMPUTATIONS - Techniques are generally described for addressing computation errors via coordinated computation on two computing platforms are disclosed. In some embodiments, one or more cuts may be taken of a computation to observe variables, and the observations may be analyzed to detect errors. Corrections may be created for the detected errors. The disclosed techniques may be employed in power and/or energy minimization/reduction, and debugging, among other goals. Other embodiments may be disclosed and/or claimed. | 12-06-2012 |
20130007512 | MANAGING STORAGE PROVIDERS IN A CLUSTERED APPLIANCE ENVIRONMENT - Via a processor, receiving a power off alert indicating a power off condition of a first processing system on which a first storage provider is installed, the first storage provider managing at least one storage controller. The method further can include, responsive to the power off alert, issuing a first command to a second storage provider installed on a second processing system, the first command indicating to the second storage provider to assume management of the storage controller. | 01-03-2013 |
20130007513 | REDUNDANT TWO-PROCESSOR CONTROLLER AND CONTROL METHOD - A redundant two-processor controller having a first processor ( | 01-03-2013 |
20130024724 | PROCESSOR AND METHOD OF CONTROLLING EXECUTION OF PROCESSES - A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section. | 01-24-2013 |
20130055014 | Analytical and Combinatorial Fault Restoration - Embodiments of the invention can provide systems and methods for combining analytical and combinatorial processes to compute fault restoration of a dead load area. According to one embodiment of the invention, a system can be provided. The system can be operable to receive location and switch information associated with an area of a power grid that has lost power, identify a switch within an area of the power grid that has lost power, compute an alternative source capacity (ASC) value for the identified switch, identify and open at least one second switch, compute combinations of the switch with each second switch that satisfies a rule, eliminate redundant switch open or close operations prior to the computation of the dead load area restoration plan, and compute a restoration plan based at least in part on the computed combinations. | 02-28-2013 |
20130151891 | LIMITING CERTAIN PROCESSING ACTIVITIES AS ERROR RATE PROBABILITY RISES - A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change. The data processing apparatus further comprises performance control circuitry configured to determine when the data processing apparatus is operating close to the operating region limits where an error rate is raised and in response to determining operation close to the operating region limits to modify a behaviour of the data processing apparatus by at least one of: limiting speculative processing, and selecting timing insensitive processing paths and circuitry. | 06-13-2013 |
20130191684 | HARDWARE RECOVERY IN MULTI-THREADED PROCESSOR - A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state. | 07-25-2013 |
20130254592 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM USING THE SAME - The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided. | 09-26-2013 |
20130268804 | SYNCHRONOUS SOFTWARE INTERFACE FOR AN ACCELERATED COMPUTE ENGINE - Some implementations disclosed herein provide techniques and arrangements for a synchronous software interface for a specialized logic engine. The synchronous software interface may receive, from a first core of a plurality of cores, a control block including a transaction for execution by the specialized logic engine. The synchronous software interface may send the control block to the specialized logic engine and wait to receive a confirmation from the specialized logic engine that the transaction was successfully executed. | 10-10-2013 |
20130290776 | Redundant Automation System and Method for Operating the Redundant Automation System - A redundant automation system and a method for operating the redundant automation system which is provided with a first subsystem and a second subsystem that each process a control program while controlling a technical process, one of these subsystems operating as a master and the other subsystem operating as a slave, and the slave assuming the function of the master if the master fails such that it becomes possible to dispense with temporally synchronous communication between the participants with regard to the synchronization of the program processing in the two subsystems, thus reducing the communication load. | 10-31-2013 |
20130297967 | HYBRID TRANSACTIONAL MEMORY (HYBRID TM) - Embodiments related to a hardware transactional memory (HTM). An aspect includes setting a mode register of a processor core of a computer to indicate a HTM mode. Another aspect includes executing a plurality of transactions by the processor core in the HTM mode based on the mode register. Another aspect includes determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode. Yet another aspect includes, based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode. | 11-07-2013 |
20140006852 | 3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS TO ENABLE RELIABLE OPERATION OF PROCESSORS AT SPEEDS ABOVE SPECIFIED LIMITS | 01-02-2014 |
20140025991 | CORE DIAGNOSTICS AND REPAIR - Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core. | 01-23-2014 |
20140040663 | INFORMATION PROCESSING APPARATUS, COMPUTER READABLE STORAGE MEDIUM, AND COLLECTING METHOD - An information processing apparatus includes a processor, and a memory connected to the processor, that stores a piece of identification information allocated to a physical partition in the information processing apparatus. The processor executes a process including collecting pieces of the identification information that are stored by other information processing apparatuses included in an information processing system. The process includes notifying an operating system of the pieces of the identification information collected at the collecting. | 02-06-2014 |
20140089731 | OPERATING METHOD OF SOFTWARE FAULT-TOLERANT HANDLING SYSTEM - An exemplary embodiment provides an operating method of a software fault-tolerant handling system, and more particularly, to an operating method of a fault-tolerant handling system in which a fault recovery is easy in a fault-tolerant technology of copying with various faults which can occur in a computing device. | 03-27-2014 |
20140108859 | CORE DIAGNOSTICS AND REPAIR - Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core. | 04-17-2014 |
20140108860 | SYSTEM AND METHOD FOR AVOIDING SYNCHRONIZATION BUGS THROUGH VIRTUALIZATION - A system and method for reducing the likelihood of concurrency errors by identifying vulnerable segments of computer code and stalling other virtual machine threads of execution. According to one embodiment of the present invention, the vulnerable segment is identified at runtime, for example in a dynamic translator. According to another embodiment of the present invention, the vulnerable segment is identified ahead of time, for example in a static translator. According to yet another embodiment of the present invention, the vulnerable segment is identified in the binary translator of a virtual machine monitor. | 04-17-2014 |
20140136888 | CORE FILE LIMITER FOR ABNORMALLY TERMINATING PROCESSES - Computer program product and system to limit core file generation in a massively parallel computing system comprising a plurality of compute nodes each executing at least one task, of a plurality of tasks, by: upon determining that a first task executing on a first compute node has failed, performing an atomic load and increment operation on a core file count; generating a first core file upon determining that the core file count is below a predefined threshold; and not generating the first core file upon determining that the core file count is not below the predefined threshold. | 05-15-2014 |
20140164826 | In-Vehicle Electronic Control Device - An in-vehicle electronic control device for diagnosing the details of an abnormality of a microcomputer appropriately is provided. A monitoring function for detecting a malfunction by monitoring input/output of a main function of a hardware part and a monitoring function for detecting an abnormality by monitoring the calculating result of a main function in a software part are provided in a microcomputer. The main function to be monitored is implemented with a different structure than the malfunction/abnormality monitoring function. Furthermore, a malfunction processing circuit for monitoring an abnormality of the microcomputer is provided outside the microcomputer. | 06-12-2014 |
20140164827 | METHOD AND DEVICE FOR MANAGING HARDWARE ERRORS IN A MULTI-CORE ENVIRONMENT - A method and device for managing hardware errors in a multi-core environment includes allocating processor cores to a main set and a spare set of processor cores. The main set of processor cores are used by an operating system, and the spare set of processor cores are dedicated to software applications. Should a processor core error occur, a processor core swap may be performed to swap a spare processor core for a failing main processor core without interrupting the execution of the operating system. | 06-12-2014 |
20140223224 | SYSTEMS AND METHODS FOR ERROR CORRECTION IN QUANTUM COMPUTATION - The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described. | 08-07-2014 |
20140237288 | INFORMATION PROCESSING APPARATUS, METHOD OF INFORMATION PROCESSING, AND RECORDING MEDIUM HAVING STORED THEREIN PROGRAM FOR INFORMATION PROCESSING - An information processing apparatus includes: processors each having a memories and a memory controller that controls the memories; a normality checker that checks whether the processors operate normally when started; a failure detector that finds any failed processor from a result of the check; a fallback unit that falls back a failed processor if any; a redundancy determiner that determines whether the memories are used in a redundancy configuration; a redundancy cancellation determiner that determines, when the memories are determined to be used in the redundant configuration, whether the redundancy configuration of the memories is to be cancelled; and a redundancy canceller that cancels, when the redundancy configuration of the memories is to be cancelled, the redundancy configuration of the memories in at least one processor operating normally. | 08-21-2014 |
20140281695 | PROCESSOR HANG DETECTION AND RECOVERY - Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction. | 09-18-2014 |
20140281696 | DETERMINE VOLTAGE SUPPLIED TO A CORE - Techniques for determining the voltage to be supplied to a core of a central processing unit are provided. A core of a central processing unit is monitored for errors. The voltage to be supplied to the core is determined based on the monitored errors. The voltage supplied to the core is altered based on the determined voltage. | 09-18-2014 |
20140344618 | METHOD OF IMPROVING FAULT TOLERANCE IN A COMPUTING SYSTEM ARRANGED TO FIND A COMPUTATIONAL SOLUTION - A method of improving fault tolerance in a computing system arranged to find a computational solution, the method comprising: computing at least two versions of the solution by using a hierarchy of at least two different solvers in parallel; and if there is a fault during execution of a solver resulting in a missing value, substituting a value from a solver that is lower in the hierarchy to replace the missing value. | 11-20-2014 |
20140359350 | WEAR-LEVELING CORES OF A MULTI-CORE PROCESSOR - Techniques that relate to wear-leveling cores of a multi-core processor are described in various implementations. The techniques may include determining, for a plurality of cores of a multi-core processor, usage information that is indicative of past wear on the plurality of cores. The techniques may also include selectively activating a subset of the plurality of cores based on the usage information such that cores that exhibit less wear relative to other cores are preferentially selected for activation. | 12-04-2014 |
20150019907 | DYNAMIC ACCESSING OF EXECUTION ELEMENTS THROUGH MODIFICATION OF ISSUE RULES - Embodiments of the invention relate to dynamically routing instructions to execution units based on detected errors in the execution units. An aspect of the invention includes a computer system including a processor having an instruction issue unit and a plurality of execution units. The processor is configured to detect an error in a first execution unit among the plurality of execution units and adjust instruction dispatch rules of the instruction issue unit based on detecting the error in the first execution unit to restrict access to the first execution unit while leaving un-restricted access to the remaining execution units of the plurality of execution units. | 01-15-2015 |
20150026515 | MOBILE DATA CENTER - A portable and mobile deployable data center (DDC) is disclosed, which includes various components that enables the DDC to have multiple functions including, computing, data storage and retrieval, communications and routing. A DDC includes a rugged case that suitable for harsh environments, an interconnection mechanism, a plurality of hot swappable readers, a plurality of hot swappable portable computing devices, and a plurality of hot swappable power supplies. | 01-22-2015 |
20150033071 | ROBUST HARDWARE/SOFTWARE ERROR RECOVERY SYSTEM - A method for error detection and recovery is provided in which a host controller and host software collaborate together. The host controller may: detect an error condition, set an error interrupt or register, and/or halt task execution or processing at the host controller. The host software may: detect an error condition as a result of the host controller having set the error interrupt or register; performs error handling, and clears the error condition. The host controller then resumes execution or processing of tasks upon detecting that error condition has been cleared by the host software. | 01-29-2015 |
20150039937 | IMAGE FORMING APPARATUS, IMAGE FORMING APPARATUS CONTROL METHOD, AND RECORDING MEDIUM - An image forming apparatus configured to operate in a first power state and a second power state that uses less power than the first power state, in which error information for identifying processing that resolves an error detected during initialization processing is associated and registered in a storage unit, and processing for resolving the detected error is executed based on the error information registered in the storage unit. | 02-05-2015 |
20150058665 | ERROR CORRECTING SYSTEM AND METHOD FOR SERVER - An error correcting system applied to a server, the server comprising a central processing unit, the central processing unit configured to send a warning signal when the central processing unit generates error. The error correcting system includes a programmable logic device, a baseboard management controller coupled to the programmable logic device, and a basic input output system coupled to the baseboard management controller. The programmable logic device is configured to detect the warning signal and send an interrupt signal to the baseboard management controller after the warning signal is detected. The baseboard management controller is configured to send a notification signal to the basic input output system after receiving the interrupt signal. The basic input output system is configured to retrieve the error and correct the error after receiving the notification signal. | 02-26-2015 |
20150058666 | SYSTEM AND METHOD FOR TREATING SERVER ERRORS - An error handling system as applied to a server, the server comprising a central processing unit, the central processing unit configured to send a warning signal when the central processing unit generates an error. The error handling system includes a programmable logic device, a baseboard management controller coupled to a southbridge chip, and a basic input-output system coupled to the baseboard management controller. The southbridge chip is configured to detect the warning signal and send a notification signal to the baseboard management controller upon detection. The basic input-output system is configured to identify the error and correct the error upon receiving the notification signal. | 02-26-2015 |
20150058667 | Method And Apparatus For A Zero Voltage Processor - Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory. | 02-26-2015 |
20150067389 | Programmable Substitutions for Microcode - The apparatuses, systems, and methods in accordance with the embodiments disclosed herein may facilitate modifying post silicon instruction behavior. Embodiments herein may provide registers in predetermined locations in an integrated circuit. These registers may be mapped to generic instructions, which can modify an operation of the integrated circuit. In some embodiments, these registers may be used to implement a patch routine to change the behavior of at least a portion of the integrated circuit. In this manner, the original design of the integrated circuit may be altered. | 03-05-2015 |
20150082082 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM STORING PROGRAM FOR EXECUTING INFORMATION PROCESSING METHOD - An information processing device includes: a plurality of processing units configured to execute software components each having a priority level; an abnormality determination unit configured to determine whether any one of the plurality of processing units has an abnormality; and a changing unit configured to, when the abnormality determination unit has determined that any one of the processing units has an abnormality, execute control such that the processing unit not determined to have an abnormality processes the software component supposed to be executed by the processing unit determined to have an abnormality. The changing unit is configured to process the software component having the priority level higher than or equal to a reference level among the software components supposed to be executed by the processing unit determined to have an abnormality. | 03-19-2015 |
20150089284 | APPROACH TO REDUCING VOLTAGE NOISE IN A STALLED DATA PIPELINE - Computer and graphics processing elements, connected generally in series, form a pipeline. Circuit elements known as di/dt throttles are inserted within the pipeline at strategic locations where the potential exists for data flow to transition from an idle state to a maximum data processing rate. The di/dt throttles gently ramp the rate of data flow from idle to a typical level. Disproportionate current draw and the consequent voltage droop are thus avoided, allowing an increased frequency of operation to be realized. | 03-26-2015 |
20150095698 | INFORMATION PROCESSING DEVICE, FAULT AVOIDANCE METHOD, AND PROGRAM STORAGE MEDIUM - An information processing device includes a detection unit and an avoidance unit. The detection unit monitors one or both of a utilization rate of memory capacity allocated to a process, and a processing time to take to process a request. The detection unit detects a state where a fault is likely to occur in the information processing device, based on the monitoring result. The avoidance unit executes fault avoidance processing when the state where the fault is likely to occur is detected. The fault avoidance processing is processing that to lowers an upper limit number of threads from a standard value to a limit value that is less than the standard value, and extends a waiting time of a thread from a standard time to an extended time that is longer than the standard time. | 04-02-2015 |
20150135007 | System and Method for an Integrated Open Network Switch - A device includes a first processing unit and a second processing unit. The first processing unit is configured to execute a performance test on the device. The second processing unit is in communication with the first processing unit, and is configured to migrate an application from the second processing unit to the first processing unit. The second processing unit is further configured to detect a failure of the first processing unit, to migrate the application to a third processing unit in response to the failure of the first processing unit, and to assign a first plurality of ports to the third processing unit in rexponse to the failure of the first processing unit. | 05-14-2015 |
20150309897 | ERROR RECOVERY CIRCUIT FACING CPU ASSEMBLY LINE - Disclosed is an error recovery circuit facing a CPU assembly line, comprising: on-chip monitoring circuits ( | 10-29-2015 |
20150355973 | LOAD CONTROL BACKUP SIGNAL GENERATING CIRCUIT - A load control backup signal generating circuit for supplying a backup control signal to a switch of a load connected to an output of a control processor in a case that abnormality occurs in the control processor, includes a first input terminal that receives a constant period signal that is output periodically from the control processor when the control processor is normal, a constant period signal monitoring section that monitors a state of the constant period signal for identifying whether a length of the time during which a high or low level state of the constant period signal continues is longer than a predetermined time, and that outputs the signal corresponding to a result of the identification, and a backup signal output section that outputs the backup control signal when the output of the constant period signal monitoring section satisfies a predetermined condition. | 12-10-2015 |
20150378810 | MANAGEMENT APPARATUS, METHOD AND PROGRAM - A disclosed management apparatus monitors hardware faults in an information processing apparatus. And the management apparatus includes a first processing unit that determines whether a first notification representing that a fault occurred includes identification information of hardware in which the fault occurred, upon receiving the first notification from the information processing apparatus; a second processing unit that transmits an execution request to execute a module for obtaining the identification information of the hardware to the information processing apparatus, upon determining that the first notification does not include the identification information of the hardware; and a third processing unit that transmits a stop request to stop executing the module to the information processing apparatus, upon receiving the identification information of the hardware from the information processing apparatus. | 12-31-2015 |
20150382498 | MOBILE DATA CENTER - A portable and mobile deployable data center (DDC) is disclosed, which includes various components that enables the DDC to have multiple functions including, computing, data storage and retrieval, communications and routing. A DDC includes a rugged case that suitable for harsh environments, an interconnection mechanism, a plurality of hot swappable readers, a plurality of hot swappable portable computing devices, and a plurality of hot swappable power supplies. | 12-31-2015 |
20160124800 | MICROCONTROLLER UNIT AND METHOD OF OPERATING A MICROCONTROLLER UNIT - A microcontroller unit (MCU) having a functional state, a reset state, and one or more assertable fault sources is described. Each fault source has its own fault source assertion count and its own fault source assertion limit; the MCU is arranged to perform the following sequence of operations in a cyclic manner: if one or more of the fault sources are asserted, pass from the functional state to the reset state and increase the respective fault source assertion counts by one increment; if one or more of the fault source assertion counts exceeds the respective fault source assertion limit, disable the respective fault source; and pass from the reset state to the functional state. A method of operating an MCU is also disclosed. | 05-05-2016 |
20160196184 | STORAGE SYSTEM AND STORAGE SYSTEM FAILURE MANAGEMENT METHOD | 07-07-2016 |