| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 712240000 | History table | 87 |
| 20080209190 | PARALLEL PREDICTION OF MULTIPLE BRANCHES - A branch history value associated with a first branch instruction of a first set of instructions is determined. The branch history value represents a branch history of a program flow prior to the first branch instruction. A first branch prediction of the first branch instruction is determined based on the branch history value of the first branch instruction and a first identifier associated with first branch instruction. A second branch prediction of a second branch instruction of the first set of instructions based on the branch history value associated with the first branch instruction and a second identifier associated with the second branch instruction. The second branch instruction occurs subsequent to the first branch instruction in the program flow. A second set of instructions is fetched at the processing device based on at least one of the first branch prediction and the second branch prediction. | 08-28-2008 |
| 20080215866 | BRANCH PREDICTION APPARATUS, SYSTEMS, AND METHODS - An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system context, using a second strategy. In some embodiments, apparatus and systems may comprise one or more first storage locations to store branch history information associated with a first operating context, and one ore more second storage locations to store branch history information associated with a second operating context. | 09-04-2008 |
| 20080256347 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR PATH-CORRELATED INDIRECT ADDRESS PREDICTIONS - A method, system, and computer program product are provided, for maintaining a path history register of register indirect branches. A set of bits is generated based on a set of target address bits using a hit selection and/or a hash function operation, and the generated set of bits is inserted into a path history register by shifting bits in the path history register and/or applying a hash operation, information corresponding to prior history is removed from the path history register, using a shift out operation and/or a hash operation. The path, history register is used to maintain a recent target, table and generate register-indirect branch target address predictions based on path history correlation between register-indirect branches captured by the path history register. | 10-16-2008 |
| 20080276081 | COMPACT REPRESENTATION OF INSTRUCTION EXECUTION PATH HISTORY - A method of representing instruction execution path history is provided. The method in one aspect may include gathering information associated with a current instruction, the information including at least a target address. Previously computed bits representing execution path history is modified and hashed based on the target address, to compute current execution path history. | 11-06-2008 |
| 20080288761 | METHOD AND SYSTEM FOR EFFICIENT TENTATIVE TRACING OF SOFTWARE IN MULTIPROCESSORS - A method of tentative tracing execution events in a multiprocessor system. Each processor stores tentative events in a corresponding buffer. The processor sets pointers in an array to a head and tail of a thread. When a condition triggers a tentative thread to be committed, the processor marks the first event as committed and sets the pointers to a null value. When a condition triggers the thread to be discarded, the processor marks the first event as discarded and sets the pointers to a null value. The processor makes the buffer available to a consumer process, which extracts the first event. If the first event is marked as committed, the consumer process follows a link to a second event of the thread and marks the second event as committed. If the first event is marked as discarded, the second event is marked as discarded and the first event is skipped. | 11-20-2008 |
| 20080301420 | Branch prediction control device having return address stack and method of branch prediction - A branch prediction control device, in an information processing unit which performs a pipeline process, generates a branch prediction address used for verification of an instruction being speculatively executed. The branch prediction control device includes a first return address storage unit storing the prediction return address, a second return address storage unit storing a return address to be generated depending on an execution result of the call instruction, and a branch prediction address storage unit sending a stored prediction return address as a branch prediction address and storing the sent branch prediction address. When the branch prediction address differs from a return address, which is generated after executing a branch instruction or a return instruction, contents stored in the second return address storage unit are copied to the first return address storage unit. | 12-04-2008 |
| 20080307210 | System and Method for Optimizing Branch Logic for Handling Hard to Predict Indirect Branches - A system and method for optimizing the branch logic of a processor to improve handling of hard to predict indirect branches are provided. The system and method leverage the observation that there will generally be only one move to the count register (mtctr) instruction that will be executed while a branch on count register (bcctr) instruction has been fetched and not executed. With the mechanisms of the illustrative embodiments, fetch logic detects that it has encountered a bcctr instruction that is hard to predict and, in response to this detection, blocks the target fetch from entering the instruction buffer of the processor. At this point, the fetch logic has fetched all the instructions up to and including the bcctr instruction but no target instructions. When the next mtctr instruction is executed, the branch logic of the processor grabs the data and starts fetching using that target address. Since there are no other target instructions that were fetched, no flush is needed if that target address is the correct address, i.e. the branch prediction is correct. | 12-11-2008 |
| 20080320288 | BRANCH PREDICTION APPARATUS OF COMPUTER - One aspect of the embodiments utilizes a branch instruction predicting unit includes a history memory to store a branch address as history information, a selecting unit to select a storing place with reference to selection information for selecting either one of storing places when the branch address of the branch instruction is stored as the history information, In the case that there are a plurality of branch addresses to be stored at a storing place, when a first branch address is stored at a storing place, a second branch address is stored at a storing place in accordance with selection information updated by the updating unit. | 12-25-2008 |
| 20090037709 | BRANCH PREDICTION DEVICE, HYBRID BRANCH PREDICTION DEVICE, PROCESSOR, BRANCH PREDICTION METHOD, AND BRANCH PREDICTION CONTROL PROGRAM - A branch prediction device capable of preventing degradation of branch prediction accuracy and a delay in processing speed is provided. The branch prediction device includes a branch prediction information accumulation processing section which stores branch prediction groups in which a plurality of pieces of branch prediction information are grouped, and performs accumulation-processing of the branch prediction information. The branch prediction device further includes a pipeline access control section which performs processing, upon request, by pipeline processing, including first selection control processing for selection-controlling at least one branch prediction group from the branch prediction groups, and second selection control processing for selection-controlling one or a plurality of pieces of branch prediction information from the branch prediction group, and controls an access to the branch prediction information accumulation processing section. | 02-05-2009 |
| 20090125707 | System and method for speculative global history prediction updating - A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR. | 05-14-2009 |
| 20090158017 | TARGET-FREQUENCY BASED INDIRECT JUMP PREDICTION FOR HIGH-PERFORMANCE PROCESSORS - A frequency-based prediction of indirect jumps executing in a computing environment is provided. Illustratively, a computing environment comprises a prediction engine that processes data representative of indirect jumps performed by the exemplary computing environment according to a selected frequency-based prediction paradigm. Operatively, the exemplary prediction engine can keep track of targets, in a table, taken for each indirect jump and program context (e.g., branch history and/or path information) of an exemplary computing program. Further, the prediction engine can also store a frequency counter associated with each target in the exemplary table. Illustratively, the frequency counter can record the number of times a target was taken in the recent past executions of an observed one or more indirect jump. The prediction engine can supply the target address of an indirect jump based on the values of the frequency counters of each stored target address. | 06-18-2009 |
| 20090164766 | BRANCH HISTORY WITH POLYMORPHIC INDIRECT BRANCH INFORMATION - A system and method for efficient improvement of branch prediction in a microprocessor with negligible impact on die-area, power consumption, and clock cycle period. It is determined if a program counter (PC) register contains a polymorphic indirect unconditional branch (PIUB) instruction. One determination may be searching a table with a portion or all of a PC of past PIUB instructions. If a hit occurs in this table, the global shift register (GSR) is updated by shifting a portion of the branch target address into the GSR, rather than updating the GSR with a taken/not-taken prediction bit. The stored value in the GSR is input into a hashing function along with the PC in order to index prediction tables such as a pattern history table (PHT), a branch target buffer (BTB), an indirect target array, or other. The updated value due to the PIUB instruction improves the accuracy of the prediction tables. | 06-25-2009 |
| 20090172371 | FEEDBACK MECHANISM FOR DYNAMIC PREDICATION OF INDIRECT JUMPS - Systems and methods are provided to detect instances where dynamic predication of indirect jumps (DIP) is considered to be ineffective utilizing data collected on the recent effectiveness of dynamic predication on recently executed indirect jump instructions. Illustratively, a computing environment comprises a DIP monitoring engine cooperating with a DIP monitoring table that aggregates and processes data representative of the effectiveness of DIP on recently executed jump instructions. Illustratively, the exemplary DIP monitoring engine collects and processes historical data on DIP instances, where, illustratively, a monitored instance can be categorized according to one or more selected classifications. A comparison can be performed for currently monitored indirect jump instructions using the collected historical data (and classifications) to determine whether DIP should be invoked by the computing environment or whether to invoke other indirect jump prediction paradigms. | 07-02-2009 |
| 20090198983 | GLOBAL HISTORY FOLDING TECHNIQUE OPTIMIZED FOR TIMING - A global history vector (GHV) mechanism maintains a folded GHV with higher order entries an an unfolded GHV with lower order entries. When a new entry arrives at the GHV, the GHV mechanism performs an XOR of the oldest unfolded entry in the unfolded GHV with the new entry. The XOR result is then shifted into the folded GHV as the newest folded entry. The oldest folded entry is discarded during the shift in of the newest folded entry. The GHV mechanism thus provides a resulting folded GHV that is current and can be utilized for XORing with an IFAR by performing an XOR operation. Only a single XOR logic is required to perform a single bit XOR operation between the oldest entry and the youngest entry, resulting in reducing the cycle time required to complete the folding operation on a GHV. | 08-06-2009 |
| 20090198984 | Global History Branch Prediction Updating Responsive to Taken Branches - A system and method are provided for updating a global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts a microprocessor instruction of consecutive operations, including a conditional branch operation with an associated branch address, at a first stage in a pipelined microprocessor execution process. A global history record (GHR) of conditional branch resolutions and predictions is accessed and hashed with the branch address, creating a first hash result. The first hash result is used to access an indexed branch history table (BHT) of branch direction counts and the BHT is used to make a branch prediction. If the branch prediction being “taken”, the current GHR value is left-shifted and hashed with the branch address, creating a second hash result which is used in creating an updated GHR. | 08-06-2009 |
| 20090198985 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE WITH HASHED INDICES - In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including a branch target address cache (BTAC) including a plurality of entries for storing branch target address predictions. The BTAC includes index logic that selects an entry to access utilizing a BTAC index based upon at least a set of higher order bits of an instruction address and a set of lower order bits of the instruction address. | 08-06-2009 |
| 20090204798 | Simplified Implementation of Branch Target Preloading - A system for using complex branch execution hardware and a hardware based Multiplex (MUX) to multiplex a fetch address of a future branch and a branch fetch address to one index hash value used to index a branch target prediction table for execution by a processor core, to reduce branch mis-prediction by preloading. | 08-13-2009 |
| 20090204799 | METHOD AND SYSTEM FOR REDUCING BRANCH PREDICTION LATENCY USING A BRANCH TARGET BUFFER WITH MOST RECENTLY USED COLUMN PREDICTION - System and method for reducing branch prediction latency using a branch target buffer with most recently used column prediction. An exemplary embodiment includes a method for reducing branch prediction latency, the method including reading most-recently-used information from a most-recently-used table associated with the branch target buffer where each most-recently-used entry corresponds to one or more branch target buffer rows and specifies the ordering from least-recently-used to most-recently-used of the associated branch target buffer columns, selecting a row from the branch target buffer and simultaneously selecting the associated entry from the most-recently-used table and speculating that there is a prediction in the most recently used column of the plurality of columns from the selected row from the branch target buffer while determining whether there is a prediction and which column contains the prediction. | 08-13-2009 |
| 20090210686 | METHOD AND SYSTEM FOR PURGING PATTERN HISTORY TABLES AS A FUNCTION OF GLOBAL ACCURACY IN A STATE MACHINE-BASED FILTERED GSHARE BRANCH PREDICTOR - A method, system and computer product for purging pattern history tables as a function of global accuracy in a state machine-based filter gshare branch predictor. An exemplary embodiment includes a method including storing a plurality of encountered branch instructions in the branch history table, indexing the branch history table by a branch instruction address, modifying an entry of the branch history table, indexing the pattern history table, selecting at least one of a branch history entry and a pattern history table entry as a prediction for the branch instruction, wherein the pattern history table entry is selected as the prediction for the branch instruction in response to the branch history entry being in a state specifying to use the pattern history table entry, comparing a pattern history table accuracy to an accuracy threshold, and in response to the pattern history table accuracy falling below the accuracy threshold, purging the PHT. | 08-20-2009 |
| 20090217016 | SYSTEM AND METHOD FOR SEARCH AREA CONFINED BRANCH PREDICTION - A system and method for performing search area confined branch prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information for branch prediction, where the branch information includes a branch address. The system also includes search logic for searching the BTB to locate a branch address. The system additionally includes throttle logic to stop searching the BTB in response to reaching a predefined search limit. | 08-27-2009 |
| 20090271597 | Branch Prediction In A Computer Processor - Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results. | 10-29-2009 |
| 20090276611 | Ram Block Branch History Table in a Global History Branch Prediction System - Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of conditional branch resolutions and predictions for a fetched conditional branch instruction. An associated instruction address is hashed with a left-shifted GHR value. The result is used to access a word in an indexed BHT stored in a single-port random access memory (RAM). The word comprises a branch direction count for the plurality of fetched conditional branch instructions. In a second clock cycle a conditional branch instruction is executed at an execute stage and the BHT is written with an updated branch direction count in response to a resolution of the executed conditional branch instruction. | 11-05-2009 |
| 20090287912 | SYSTEM AND METHOD FOR BRANCH MISPREDICTION USING COMPLEMENTARY BRANCH PREDICTIONS - A system is disclosed for providing branch misprediction prediction in a microprocessor. The system includes a mispredicted branch table that includes address, distance, and true/not true fields, and an index to the mispredicted branch table that is formed responsive to 1) a current mispredicted branch, 2) a global history, 3) a global misprediction history, and 4) a branch misprediction distance. | 11-19-2009 |
| 20090313462 | METHODS INVOLVING BRANCH PREDICTION - A method for branch prediction, the method comprising, receiving a load instruction including a first data location in a first memory area, retrieving data including a branch address and a target address from the first data location data location, and saving the data in a branch prediction memory. | 12-17-2009 |
| 20090327673 | ESTIMATOR, TABLE MANAGING DEVICE, SELECTING DEVICE, TABLE MANAGING METHOD, PROGRAM FOR ALLOWING COMPUTER TO EXECUTE THE TABLE MANAGING METHOD, AND RECORDING MEDIUM WHERE THE PROGRAM IS RECORDED - An estimator suitable for hot-path detection conducted while managing the history of the executed instructions is provided. A hot-path estimator ( | 12-31-2009 |
| 20100031011 | METHOD AND APPARATUS FOR OPTIMIZED METHOD OF BHT BANKING AND MULTIPLE UPDATES - The invention relates to a method and apparatus for controlling the instruction flow in a computer system and more particularly to the predicting of outcome of branch instructions using branch prediction arrays, such as BHTs. In an embodiment, the invention allows concurrent BHT read and write accesses without the need for a multi-ported BHT design, while still providing comparable performance to that of a multi-ported BHT design. | 02-04-2010 |
| 20100049957 | RECOVERING A SUBORDINATE STRAND FROM A BRANCH MISPREDICTION USING STATE INFORMATION FROM A PRIMARY STRAND - Embodiments of the present invention provide a system that executes program code in a processor. The system starts by executing the program code in a normal mode using a primary strand while concurrently executing the program code ahead of the primary strand using a subordinate strand in a scout mode. Upon resolving a branch using the subordinate strand, the system records a resolution for the branch in a speculative branch resolution table. Upon subsequently encountering the branch using the primary strand, the system uses the recorded resolution from the speculative branch resolution table to predict a resolution for the branch for the primary strand. Upon determining that the resolution of the branch was mispredicted for the primary strand, the system determines that the subordinate strand mispredicted the branch. The system then recovers the subordinate strand to the branch and restarts the subordinate strand executing the program code. | 02-25-2010 |
| 20100161951 | PROCESSOR AND METHOD FOR RECOVERING GLOBAL HISTORY SHIFT REGISTER AND RETURN ADDRESS STACK THEREOF - A method for recovering global history shift register (GHSR) and return address stack (RAS) is provided, which is applicable to an instruction pipeline of a processor and includes the following steps. First, provide a branch recovery table (BRT) and a backup stack. Whenever a branch instruction enters a predetermined stage of the instruction pipeline, add a record in the BRT according to the branch instruction. Whenever a return address is popped from the RAS of the instruction pipeline, push the return address into the backup stack. When flushing the instruction pipeline, determine a removal range of the BRT according to the condition which triggers the pipeline flush. Recover the RAS according to the records in the removal range and the backup stack. Remove all records in the removal range. Recover the GHSR of the instruction pipeline according to the removed records. | 06-24-2010 |
| 20100169627 | System and method for repairing a speculative global history record - A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor instructions with consecutive operations, including a conditional branch operation with an associated first branch address. A speculative global history record (SGHR) of conditional branch resolutions and predictions is accessed and hashed with the first branch address, creating a first hash result. The first hash result is used to index a branch history table (BHT) of previous first branch resolutions. As a result, a first branch prediction is made, and the SGHR is updated with the first branch prediction. A non-speculative global history record (NSGHR) of branch resolutions is updated with the resolution of the first branch operation, and if the first branch prediction is incorrect, the SGHR is corrected using the NSGHR. | 07-01-2010 |
| 20100262813 | Detecting and Handling Short Forward Branch Conversion Candidates - Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions. | 10-14-2010 |
| 20100306514 | Correlating Instruction Sequences with CPU Performance Events to Improve Software Performance - A system and method are disclosed for correlating instruction sequences. A plurality of instructions is processed to parse a first sequence of instructions comprising a first area of interest. A first instruction sequence pattern is then generated from the first sequence of instructions. Pattern matching operations are performed with the first instruction sequence pattern. A second sequence of instructions are parsed, comprising a second instruction sequence pattern and a second address of interest that is a substantially equivalent match to the first instruction sequence pattern. | 12-02-2010 |
| 20100306515 | Predictors with Adaptive Prediction Threshold - An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine for a PHT entry is obtained. Count values in a set of counters allocated to the entry in the PHT are changed based on the count value of the entry's prediction state counter. The prediction threshold of the prediction state machine for the entry may then be adjusted based on the changed count values in the set of counters, wherein the prediction threshold is adjusted by changing a count value in a prediction threshold counter in the entry, and wherein adjusting the prediction threshold redefines predictions provided by the prediction state machine. | 12-02-2010 |
| 20100306516 | INFORMATION PROCESSING APPARATUS AND BRANCH PREDICTION METHOD - An information processor includes a first recording unit which stores first information indicating correspondence between an instruction address and a branch destination address of a most recent branch instruction, a computation of the most recent branch instruction having been completed and a branch for the most recent branch prediction having been taken, a second recording unit which stores a second information indicating correspondence between an instruction address and a branch destination address of each of past branch instructions including the most recent branch instruction, computations of the past branch instructions having been completed and branches for the past branch instructions having been taken, and a control unit which makes a branch prediction based on the first information or the second information, and stops supply of a clock to the second recording unit and makes a branch prediction based on the first information when an instruction sequence enters a loop. | 12-02-2010 |
| 20110022825 | CREATING AND MANAGING LINKS TO DEDUPLICATION INFORMATION - In a method of linking to information in a deduplication data sequence, a branching point is identified. The branching point is a place where a branch data sequence diverges from a parent data sequence that has been previously stored in a data deduplication process. A signature value associated with a subsequence of the information represented in the branch data sequence is determined. A branch location where the information of the branch data sequence begins is identified. Link information is stored in association with the branching point. The link information is stored in a computer memory. The link information comprises a link to the branch location and also comprises a portion of the signature value. | 01-27-2011 |
| 20110113224 | EXECUTION TIME ESTIMATION METHOD, EXECUTION TIME ESTIMATION PROGRAM, AND EXECUTION TIME ESTIMATION DEVICE - An execution time estimation device includes a program partitioning section that extracts partial programs partitioned by a conditional branch instruction or a function call instruction from a target program, a partial program execution time estimation calculating section that calculates the execution time of each of the partial programs to associate the leading instruction and the end instruction of each of the partial programs, and the calculated execution time with one another, a branch history information generating section that generates a branch history bit sequence which is a sequence of the true-false of the conditional branch instruction of when the target program is executed, an execution trace reproducing section that generates the execution sequences of the partial programs based on the branch history bit sequence, and an execution time estimation calculating section that adds the execution time of the partial programs based on the execution sequences of the partial programs. | 05-12-2011 |
| 20110167247 | System for efficiently tracing data in a data processing system - A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program instruction; tracing circuitry for tracing operation of the data processing apparatus for outputting a prediction indicator indicating whether or not the predicted response is correct; a data store configured to store information relating to the predicted response of said data processing circuitry at the given execution point for use by at least one of said prediction logic and said tracing circuitry a later execution point; and a history buffer configured to store historical information with regard to one or more entries of the data store at a corresponding execution point previous to the given execution point to enable restoration of said data store to a state corresponding to said previous execution point. | 07-07-2011 |
| 20110225401 | PREFETCHING BRANCH PREDICTION MECHANISMS - A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch associated with the branch action was taken, and saving an identifier of the branch instruction and in indicator that the branch action was taken in a prefetch history table responsive to determining that the branch associated with the branch action was taken. | 09-15-2011 |
| 20110320791 | Method and Apparatus to Limit Millicode Routine End Branch Prediction - A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines. | 12-29-2011 |
| 20110320792 | STATE MACHINE-BASED FILTERING OF PATTERN HISTORY TABLES BASED ON DISTINGUISHABLE PATTERN DETECTION - Machine-based filtering of a pattern history table includes identifying a matching previous occurrence of a current branch instruction in an address history vector (AHV), the AHV storing addresses, or partial addresses, of most recently occurring branch instructions. In response to determining a direction history of the previous occurrence matches a direction history of the current branch, the machine-based filtering includes comparing the outcome of the previous occurrence with the outcome of the current branch instruction, and preventing the pattern history table from being updated with the outcome of the current branch instruction when the outcome of the previous occurrence does not match the outcome of the current branch instruction. | 12-29-2011 |
| 20110320793 | OPERATING SYSTEM AWARE BRANCH PREDICTOR USING A DYNAMICALLY RECONFIGURABLE BRANCH HISTORY TABLE - A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions. | 12-29-2011 |
| 20120005463 | BRANCH TRACE HISTORY COMPRESSION - The disclosure provides a method, data processing system, and computer program product for managing a branch trace environment. In response to a branch being taken for a first branch instruction that is conditional and direct in the branch instructions, a performance monitoring unit stores an effective address of the first branch instruction into a first entry in a set of entries in a memory. The performance monitoring unit counts each branch not taken in processing the branch instructions occurring after the first branch instruction to form a branch count. In response to a branch being taken during processing of subsequent branch instructions in the branch instructions after the first branch instruction, the performance monitoring unit determines whether to create a second entry in the set of entries in the memory using the branch count with a set of rules identifying when the second entry is to be made. | 01-05-2012 |
| 20120072708 | HISTORY BASED PIPELINED BRANCH PREDICTION - Systems and methods for history based pipelined branch prediction. In one embodiment, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded. | 03-22-2012 |
| 20120124348 | BRANCH PREDICTOR ACCURACY BY FORWARDING TABLE UPDATES TO PENDING BRANCH PREDICTIONS - A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value. | 05-17-2012 |
| 20120124349 | POWER EFFICIENT PATTERN HISTORY TABLE FETCH IN BRANCH PREDICTOR - A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a queue. If a branch prediction is requested, the queue is accessed to obtain a prediction value. The queue may include any number of entries and the queue maintains the oldest prediction value at the head of the queue. The prediction value at the head of the queue is used when a branch prediction is needed. | 05-17-2012 |
| 20120166776 | METHOD, SYSTEM, AND COMPUTER PROGRAM FOR ANALYZING PROGRAM - Upon start of a program, a plurality of flags, each corresponding to an instruction of the program, are initialized to a disabled state and an initial state of a BHT is stored. Upon execution of a branch instruction, if a branch has not been taken, a value of history information of a corresponding entry of the BHT is decremented. If the branch has been taken, the value of the history information of the corresponding entry is incremented and whether a corresponding flag is enabled or disabled is determined. If the corresponding flag is disabled, the flag is enabled. Upon termination of the program, a differential history information value of each entry is obtained from the stored initial state and a final state of the BHT. A final state of each flag is obtained. | 06-28-2012 |
| 20120290821 | LOW-LATENCY BRANCH TARGET CACHE - Techniques and structures are disclosed relating to a branch target cache (BTC) in a processor. In one embodiment, the BTC is usable to predict whether a control transfer instruction is to be taken, and, if applicable, a target address for the instruction. The BTC may operate in conjunction with a delayed branch predictor (DBP) that is more accurate but slower than the BTC. If the BTC indicates that a control transfer instruction is predicted to be taken, the processor begins to fetch instructions at the target address indicated by the BTC, but may discard those instructions if the DBP subsequently determines that the control transfer instruction was predicted incorrectly. Branch prediction information output from the BTC and the DBP may be used to update the branch target cache for subsequent predictions. In various embodiments, the BTC may simultaneously store entries for multiple processor threads, and may be fully associative. | 11-15-2012 |
| 20120303938 | PERFORMANCE IN PREDICTING BRANCHES - A method, data processing system, and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table. | 11-29-2012 |
| 20130007425 | PROCESSOR AND DATA PROCESSING METHOD INCORPORATING AN INSTRUCTION PIPELINE WITH CONDITIONAL BRANCH DIRECTION PREDICTION FOR FAST ACCESS TO BRANCH TARGET INSTRUCTIONS - Disclosed are a processor and a processing method incorporating an instruction pipeline with direction prediction (i.e., taken or not taken) for conditional branch instructions. In the embodiments, reading of a branch instruction history table (BHT) and a branch instruction target address cache (BTAC) for branch direction prediction occurs in parallel with the current instruction fetch in order to minimize delay in the next instruction fetch. Additionally, direction prediction is performed in the very next clock cycle based either on an initial direction prediction for the specific instruction, as stored in the BHT, or, if applicable, on a prior entry for the specific instruction in the BTAC. An override bit associated with each entry in the BTAC is the determining factor for whether or the BTAC or BHT is controlling. Override bits in the BTAC can be pre-established based on the branch instruction type in order to ensure prediction accuracy. | 01-03-2013 |
| 20130036297 | META PREDICTOR RESTORATION UPON DETECTING MISPREDICTION - Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed. | 02-07-2013 |
| 20130080749 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor includes: first selectors that select instruction addresses of instructions of a plurality of threads or a branch target address of a branch instruction to be predicted and that output addresses of the plurality of threads; a second selector that selects one of the addresses of the plurality of threads output by the first selectors; a branch prediction circuit that predicts and outputs a branch direction, which indicates whether the branch instruction of the address selected by the second selector is branched, based on the selected address in a first cycle stage and that predicts and outputs the branch target address of the branch instruction to be predicted based on the selected address in a second cycle stage later than the first cycle stage; and a thread arbitration circuit that controls selection of the addresses of the threads by the first selectors and the second selector. | 03-28-2013 |
| 20130080750 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor includes: first selectors that select instruction addresses of instructions of a plurality of threads or a branch target address of a branch instruction to be predicted and that output addresses of the plurality of threads; a second selector that selects one of the addresses of the plurality of threads output by the first selectors; a branch prediction circuit that predicts and outputs a branch direction, which indicates whether the branch instruction of the address selected by the second selector is branched, based on the selected address in a first cycle stage and that predicts and outputs the branch target address of the branch instruction to be predicted based on the selected address in a second cycle stage later than the first cycle stage; and a thread arbitration circuit that controls selection of the addresses of the threads by the first selectors and the second selector. | 03-28-2013 |
| 20130151823 | NEXT FETCH PREDICTOR TRAINING WITH HYSTERESIS - A system and method for efficient branch prediction. A processor includes two branch predictors. A first branch predictor generates branch prediction data, such as a branch direction and a branch target address. The second branch predictor generates branch prediction data at a later time and with higher prediction accuracy. Control logic may determine whether the branch prediction data from each of the first and the second branch predictors match. If a mismatch occurs, the first predictor may be trained with the branch prediction data generated by the second branch predictor. A stored indication of hysteresis may indicate a given branch instruction exhibits a frequently alternating pattern regarding its branch direction. Such behavior may lead to consistent branch mispredictions due to the training is unable to keep up with the changing branch direction. When such a condition is determined to occur, the control logic may prevent training of the first predictor. | 06-13-2013 |
| 20130283023 | Bimodal Compare Predictor Encoded In Each Compare Instruction - Systems and methods for branch prediction, including predicting evaluation of a producer instruction such as a compare instruction, by encoding a prediction field in the producer instruction, and predicting evaluation of the producer instruction by using the encoded prediction field. A consumer instruction such as a conditional branch instruction predicated on the producer instruction can be speculatively executed based on the predicted evaluation of the producer instruction. The producer instruction is executed in an execution pipeline to determine an actual evaluation of the producer instruction, and the prediction field is updated, if necessary, based on the actual evaluation and the predicted evaluation. The producer instruction can be updated in memory with the updated prediction field. | 10-24-2013 |
| 20130311760 | Multi Level Indirect Predictor using Confidence Counter and Program Counter Address Filter Scheme - The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor. | 11-21-2013 |
| 20130332715 | GLOBAL WEAK PATTERN HISTORY TABLE FILTERING - Embodiments relate to global weak pattern history table (PHT) filtering. An aspect includes receiving a search address associated with a branch prediction, and receiving a prediction strength indicator and a tag from a PHT. Based on determining that the tag matches the search address and the prediction strength indicator is weak, an accuracy counter is compared to a comparison threshold to determine whether a PHT direction prediction from the PHT is more likely accurate than a branch history table (BHT) direction prediction from a BHT. The PHT direction prediction is selected as a direction prediction based on determining that the accuracy counter indicates that the PHT direction prediction is more likely accurate than the BHT direction prediction. The BHT direction prediction is selected as the direction prediction based on determining that the accuracy counter indicates that the BHT direction prediction is more likely accurate than the PHT direction prediction. | 12-12-2013 |
| 20130332716 | BRANCH TARGET BUFFER PRELOAD TABLE - Embodiments relate to using a branch target buffer preload table. An aspect includes receiving a search request to locate branch prediction information associated with a branch instruction. Searching is performed for an entry corresponding to the search request in a branch target buffer and a branch target buffer preload table in parallel. Based on locating a matching entry in the branch target buffer preload table corresponding to the search request and failing to locate the matching entry in the branch target buffer, a victim entry is selected to overwrite in the branch target buffer. Branch prediction information of the matching entry is received from the branch target buffer preload table at the branch target buffer. The victim entry in the branch target buffer is overwritten with the branch prediction information of the matching entry. | 12-12-2013 |
| 20140019738 | MULTICORE PROCESSOR SYSTEM AND BRANCH PREDICTING METHOD - A multicore processor system includes plural CPUs; branch prediction memories respectively disposed for the CPUs; and a shared branch prediction memory that stores branch prediction information records respectively corresponding to threads executed by the CPUs. A first CPU among the CPUs is configured to set the branch prediction information record corresponding to a first thread among the threads executed by the first CPU, from the shared branch prediction memory to the branch prediction memory corresponding to the first CPU. | 01-16-2014 |
| 20140052972 | META PREDICTOR RESTORATION UPON DETECTING MISPREDICTION - Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed. | 02-20-2014 |
| 20140075166 | Swapping Branch Direction History(ies) in Response to a Branch Prediction Table Swap Instruction(s), and Related Systems and Methods - Swapping branch direction history(ies) in response to a branch prediction table swap instruction(s), and related systems and methods are disclosed. In one embodiment, a branch history management circuit is configured to process a branch prediction table swap instruction. In response to the branch prediction table swap instruction, the branch history management circuit is configured to swap a prior branch direction history set assigned to a current software code region from cache memory, into a branch prediction table (BPT) for use in branch prediction. The current branch direction history set is swapped out of the BPT and stored in cache memory to avoid being overwritten. In this manner, branch direction history sets assigned to particular software code regions are used for branch prediction when processing the particular software code regions. Therefore, branch prediction accuracy and instruction processing throughput of an instruction processing system are increased. | 03-13-2014 |
| 20140075167 | BRANCH HISTORY CACHE AND METHOD - A branch history table cache is a write cache that stores values of branch history counters written to a branch history table. An update to a branch history table counter is reflected in both the branch history table cache and the branch history table. Before a branch history table counter is updated, a check is made to see if the branch history table counter is in the cache. If not, the branch history table counter is updated based on a value of the branch history table counter that was saved during fetch of the branch history table counter. If, however, the branch history table counter value is in the cache, the value in the cache is used to update the branch history table counter. All branches that use the branch history table counter update the correct counter value, improving processor performance by providing more accurate predictions of branches taken. | 03-13-2014 |
| 20140075168 | INSTRUCTION SEQUENCE BUFFER TO STORE BRANCHES HAVING RELIABLY PREDICTABLE INSTRUCTION SEQUENCES - A method for outputting reliably predictable instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor, and out of that set, identifying a branch instruction having a series of subsequent frequently executed branch instructions that form a reliably predictable instruction sequence. The reliably predictable instruction sequence is stored into a buffer. On a subsequent hit to the branch instruction, the reliably predictable instruction sequence is output from the buffer. | 03-13-2014 |
| 20140082339 | GLOBAL WEAK PATTERN HISTORY TABLE FILTERING - Embodiments relate to global weak pattern history table (PHT) filtering. An aspect includes receiving a search address associated with a branch prediction, and receiving a prediction strength indicator and a tag from a PHT. Based on determining that the tag matches the search address and the prediction strength indicator is weak, an accuracy counter is compared to a comparison threshold to determine whether a PHT direction prediction from the PHT is more likely accurate than a branch history table (BHT) direction prediction from a BHT. The PHT direction prediction is selected as a direction prediction based on determining that the accuracy counter indicates that the PHT direction prediction is more likely accurate than the BHT direction prediction. The BHT direction prediction is selected as the direction prediction based on determining that the accuracy counter indicates that the BHT direction prediction is more likely accurate than the PHT direction prediction. | 03-20-2014 |
| 20140089647 | Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch - In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch. | 03-27-2014 |
| 20140156978 | Detecting and Filtering Biased Branches in Global Branch History - A processor includes an instruction pipeline for executing instructions including a branching instruction, a counter for counting times that the branching instruction is taken, a register for storing a global branch history as a function of a value of the counter, and a branch prediction unit for predicting branching based on the global branch history. | 06-05-2014 |
| 20140156979 | Performance in Predicting Branches - A method for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table. | 06-05-2014 |
| 20140250289 | Branch Target Buffer With Efficient Return Prediction Capability - Improved branch target buffers (BTBs) and methods of processing data in a microprocessor with a pipeline are provided. According to various embodiments, a BTB is provided that includes a non-return buffer, a return buffer, and a multiplexer. The non-return buffer is designed to store a multiple of non-return entries. Each non-return entry corresponds to a non-return type instruction. The return buffer is designed to store a plurality of return entries that each correspond to a return type instruction. Additionally, the return buffer may generate a control signal. The multiplexer also generates a control signal and outputs either data from the non-return buffer or data from a return prediction stack (RPS). Whether the multiplexer returns data from the non-return buffer or the RPS depends on the control signal. | 09-04-2014 |
| 20140380027 | ELAPSED CYCLE TIMER IN LAST BRANCH RECORDS - A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created. | 12-25-2014 |
| 20150046691 | GLOBAL BRANCH PREDICTION USING BRANCH AND FETCH GROUP HISTORY - This disclosure includes a method for performing branch prediction by a processor having an instruction pipeline. The processor speculatively updates a global history register having fetch group history and branch history, fetches a fetch group of instructions, and assigns a global history vector to the instructions. The processor predicts any branches in the fetch group using the global history vector and a predictor, and evaluates whether the fetch group contains a predicted taken branch. If the fetch group contains a predicted taken branch, the processor flushes subsequently fetched instructions in the pipeline following the predicted taken branch, repairs the global history register to the global history vector, and updates the global history register based on branch prediction information. If the fetch group does not contain a predicted taken branch, the processor updates the global history register with a branch history value for each branch in the fetch group. | 02-12-2015 |
| 20150052338 | ARITHMETIC PROCESSING DEVICE AND CONTROL METHOD OF ARITHMETIC PROCESSING DEVICE - An arithmetic processing device includes: first prediction units which output branch prediction information of a fetched conditional branch instruction based on past branch history information of conditional branch instructions; a second prediction unit which stores a branch taken consecutive number of times and a branch not-taken consecutive number of times to a pattern information storage unit, and outputs branch prediction information of a fetched conditional branch instruction based on the past branch taken consecutive number of times or branch not-taken consecutive number of times stored; selecting units which selectively output the branch prediction information output from the first prediction units or the second prediction unit; and a selector which outputs a next instruction address of the conditional branch instruction or a branch target address of the conditional branch instruction to an instruction fetch unit in accordance with the branch prediction information output by the selecting units. | 02-19-2015 |
| 20150052339 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - When predicting that branch is established as a result of performing branch prediction of a branch instruction based on pieces of branch information on branch instructions included in entries read from branch histories stored in a storing unit which stores, in each way, the branch history including a first index being part of an instruction address and a second index being a value obtained by an arithmetic operation using part of the instruction address, a branch predicting unit outputs a predicted branch destination address, and when a prediction failure of the predicted branch destination address obtained is detected, a branch history updating unit sets updated information of the branch information to update the branch history, and when the prediction failure is detected and the updated information is set in the branch information, registers the branch information in the branch history stored in the storing unit, by using the second index. | 02-19-2015 |
| 20150309794 | BRANCH PREDICTION - A method and system for branch prediction are provided herein. The method includes executing a program, wherein the program comprising multiple procedures, and setting bits in a taken branch history register to indicate whether a branch is taken or not taken during execution of instructions in the program. The method further includes the steps of calling a procedure in the program and overwriting, responsive to calling the procedure, the contents of the taken branch history register to a start address for the procedure. | 10-29-2015 |
| 20150331691 | BRANCH PREDICTION USING MULTIPLE VERSIONS OF HISTORY DATA - Branch prediction is provided by generating a first index from a previous instruction address and from a first branch history vector having a first length. A second index is generated from the previous instruction address and from a second branch history vector that is longer than the first vector. Using the first index, a first branch prediction is retrieved from a first branch prediction table. Using the second index, a second branch prediction is retrieved from a second branch prediction table. Based upon additional branch history data, the first branch history vector and the second branch history vector are updated. A first hash value is generated from a current instruction address and the updated first branch history vector. A second hash value is generated from the current instruction address and the updated second branch history vector. One of the branch predictions are selected based upon the hash values. | 11-19-2015 |
| 20150363202 | BRANCH PREDICTION BASED ON CORRELATING EVENTS - Branch prediction using a correlating event, such as an unconditional branch that calls a routine including the branch, instead of the branch itself, to predict the behavior of the branch. The circumstances in which the branch is employed, and not the actual branch itself, is used to predict how strongly taken or not taken the branch is to behave. A correlating value associated with the branch (e.g., an address of the instruction calling a routine that includes the branch), an address of the branch, and a value that represents the number of selected branch instructions between the anchor point and the branch are used to select information to be used to predict the direction of the branch. | 12-17-2015 |
| 20150363203 | Apparatus and Method for Bias-Free Branch Prediction - Aspects of the present invention provide an apparatus and method for filtering biased conditional branches in a branch predictor in favor of non-biased conditional branches. Biased conditional branches, which are consistently skewed toward one direction or outcome, are filtered such that an increased number of non-biased conditional branches which resolve in both directions may be considered. As a result, more useful branches may be captured over larger distances, thereby providing correlations deeper in a global history to provide greater prediction accuracy. In addition, by tracking only the latest occurrences of non-biased conditional branches using a recency stack structure, even more distant branch correlations may be made. | 12-17-2015 |
| 20150363204 | BRANCH PREDICTION BASED ON CORRELATING EVENTS - Branch prediction using a correlating event, such as an unconditional branch that calls a routine including the branch, instead of the branch itself, to predict the behavior of the branch. The circumstances in which the branch is employed, and not the actual branch itself, is used to predict how strongly taken or not taken the branch is to behave. A correlating value associated with the branch (e.g., an address of the instruction calling a routine that includes the branch), an address of the branch, and a value that represents the number of selected branch instructions between the anchor point and the branch are used to select information to be used to predict the direction of the branch. | 12-17-2015 |
| 20150378727 | CONDITIONAL BRANCH INSTRUCTION COMPACTION FOR REGIONAL CODE SIZE REDUCTION - In an approach for decreasing an execution time of a computer code, one or more processors receive a computer code and identify a frequently executed region of the computer code. One or more processors identify a long-form conditional branch in the frequently executed region of the computer code that is infrequently taken. One or more processors generate a long-form unconditional branch with a target that is a target of the long-form conditional branch. One or more processors modify the long-form conditional branch to be a short-form conditional branch. One or more processors insert the long-form unconditional branch in the computer code within a branch distance of the short-form conditional branch. One or more processors modify a target of the short-form conditional branch to be a location of the long-form unconditional branch in the computer code. | 12-31-2015 |
| 20160026470 | Conditional Branch Prediction Using a Long History - Methods and conditional branch predictors for predicting an outcome of a conditional branch instruction in a program executed by a processor using a long conditional branch history include generating a first index from a first portion of the conditional branch history and a second index from a second portion of the conditional branch history. The first index is then used to identify an entry in a first pattern history table including first prediction information; and the second index is used to identify an entry in a second pattern history table including second prediction information. The outcome of the conditional branch is predicted based on the first and second prediction information. | 01-28-2016 |
| 20160034279 | BRANCH PREDICTION USING MULTI-WAY PATTERN HISTORY TABLE (PHT) AND GLOBAL PATH VECTOR (GPV) - Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction. | 02-04-2016 |
| 20160034280 | BRANCH PREDICTION USING MULTI-WAY PATTERN HISTORY TABLE (PHT) AND GLOBAL PATH VECTOR (GPV) - Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction. | 02-04-2016 |
| 20160034281 | INSTRUCTION PROCESSING SYSTEM AND METHOD - An instruction processing system is provided. The system includes a central processing unit (CPU), a memory system and an instruction control unit. The CPU is configured to execute one or more instructions of the executable instructions. The memory system is configured to store the instructions. The instruction control unit is configured to, based on location of a branch instruction stored in a track table, control the memory system to provide the instructions to be executed for the CPU. Further, the instruction control unit is also configured to, based on branch prediction of the branch instruction stored in the track table, control the memory system to output one of a fall-through instruction and a target instruction of the branch instruction. | 02-04-2016 |
| 20160048395 | Branch Predictor for Wide Issue, Arbitrarily Aligned Fetch - In an embodiment, a processor may be configured to fetch N instruction bytes from an instruction cache (a “fetch group”), even if the fetch group crosses a cache line boundary. A branch predictor may be configured to produce branch predictions for up to M branches in the fetch group, where M is a maximum number of branches that may be included in the fetch group. In an embodiment, a branch direction predictor may be updated responsive to a misprediction and also responsive to the branch prediction being within a threshold of transitioning between predictions. To avoid a lookup to determine if the threshold update is to be performed, the branch predictor may detect the threshold update during prediction, and may transmit an indication with the branch. | 02-18-2016 |
| 20160110202 | BRANCH PREDICTION SUPPRESSION - A data processing apparatus | 04-21-2016 |
| 20160139932 | MANAGING HISTORY INFORMATION FOR BRANCH PREDICTION - Branch history information characterizes results of branch instructions previously executed by a processor. A count is stored of a number of consecutive branch instructions previously executed by the processor whose results all indicate a not taken branch. In a first pipeline stage, a predicted branch result is provided based on at least a portion of the branch history information, and one or more of the branch history information, and the count, is updated based on the predicted branch result. In a second pipeline stage an actual branch result is provided based on an executed branch instruction, and the branch history information is updated based on the actual branch result. If the predicted branch result indicates a taken branch, the branch history information is updated based on the count, and if the predicted branch result indicates a not taken branch, the count is updated but not the branch history information. | 05-19-2016 |
| 20160139933 | PROVIDING LOOP-INVARIANT VALUE PREDICTION USING A PREDICTED VALUES TABLE, AND RELATED APPARATUSES, METHODS, AND COMPUTER-READABLE MEDIA - Providing loop-invariant value prediction using a predicted values table, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, an apparatus comprising an instruction processing circuit is provided. The instruction processing circuit is configured to detect a loop body in an instruction stream, and to detect a value-generating instruction within the loop body. The instruction processing circuit determines whether an attribute of the value-generating instruction matches an entry of a predicted values table. If the attribute of the value-generating instruction is determined to be present in the entry of the predicted values table, the instruction processing circuit further determines whether a counter of the entry exceeds an iteration threshold. Responsive to determining that the counter of the entry exceeds the iteration threshold, the instruction processing circuit provides a predicted value in the entry of the predicted values table for execution of at least one dependent instruction. | 05-19-2016 |
| 20160179546 | TECHNIQUES FOR ENFORCING CONTROL FLOW INTEGRITY USING BINARY TRANSLATION | 06-23-2016 |
| 20160253177 | Universal History Buffer to Support Multiple Register Types | 09-01-2016 |
| 20160253180 | History Buffer with Hybrid Entry Support for Multiple-Field Registers | 09-01-2016 |
