Entries |
Document | Title | Date |
20080201565 | CONTEXT SWITCH DATA PREFETCHING IN MULTITHREADED COMPUTER - An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching. | 08-21-2008 |
20080215865 | DATA PROCESSOR AND MEMORY READ ACTIVE CONTROL METHOD - Instruction cache memory having a plurality of memory (for example, cache WAY), means | 09-04-2008 |
20080235500 | STRUCTURE FOR INSTRUCTION CACHE TRACE FORMATION - A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC). | 09-25-2008 |
20080256345 | Method and Apparatus for Conserving Power by Throttling Instruction Fetching When a Processor Encounters Low Confidence Branches in an Information Handling System - An information handling system includes a processor that throttles the instruction fetcher whenever the inaccuracy, or lack of confidence, in branch predictions for branch instructions stored in a branch instruction queue exceeds a predetermined threshold confidence level of inaccuracy or error. In this manner, fetch operations slow down to conserve processor power when it is likely that the processor will mispredict the outcome of branch instructions. Fetch operations return to full speed when it is likely that the processor will correctly predict the outcome of branch instructions. | 10-16-2008 |
20080256346 | CENTRAL PROCESSING UNIT HAVING BRANCH INSTRUCTION VERIFICATION UNIT FOR SECURE PROGRAM EXECUTION - Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to a computer virus and a hacker is provided. The CPU includes: a branch instruction verification unit which verifies whether a branch instruction is valid; and a branch instruction execution unit which executes the branch instruction when the branch instruction is valid. The method includes: verifying whether the branch instruction is valid; and not executing the branch instruction when the branch instruction is invalid. | 10-16-2008 |
20080263341 | Data processing apparatus and method for generating prediction data - A data processing apparatus and method are provided for generating prediction data. The data processing apparatus has processing circuitry for performing processing operations including high priority operations and low priority operations, events occurring during performance of those processing operations. Prediction circuitry is responsive to a received event to generate prediction data used by the processing circuitry. The prediction circuitry includes a history storage having a plurality of counter entries for storing count values, and index circuitry for identifying, dependent on the received event, at least one counter entry and for causing the history storage to output the count value stored in that at least one counter entry, with the prediction data being derived from the output count value. Further update control circuitry is provided for modifying at least one count value stored in the history storage in response to update data generated by the processing circuitry. The update control circuitry has a priority dependent modification mechanism such that the modification to the at least one count value is dependent on the priority of the processing operation with which that update data is associated. As a result, the prediction data output for a received event associated with a high priority operation is more accurate than the prediction data output for a received event associated with a low priority operation. | 10-23-2008 |
20080270774 | Universal branch identifier for invalidation of speculative instructions - A system for speculative branch predictions. An embodiment of the system includes branch prediction logic, fetch logic, and branch identification logic. The branch prediction logic is configured to predict a branch path for a branch in an instruction stream. The fetch logic is coupled to the branch prediction logic. The fetch logic is configured to speculatively fetch an instruction corresponding to the predicted branch path. The branch identification logic is coupled to the branch prediction logic and the fetch logic. The branch identification logic is configured to mark the speculatively fetched instruction with a branch identifier using a universal branch identification format. The universal branch identification format includes a bit value at a bit position corresponding to the predicted branch path. | 10-30-2008 |
20080276080 | METHODS FOR STORING BRANCH INFORMATION IN AN ADDRESS TABLE OF A PROCESSOR - Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information. | 11-06-2008 |
20080307209 | METHODS AND APPARATUS FOR IMPLEMENTING POLYMORPHIC BRANCH PREDICTORS - A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to select one or more of the branch prediction methods in accordance with a dynamic setting to optimize performance of the branch predictor during operation in accordance with a current task. | 12-11-2008 |
20080313445 | METHOD AND SYSTEM FOR PREVENTING LIVELOCK DUE TO COMPETING UPDATES OF PREDICTION INFORMATION - A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of the event is mispredicted to form an appended instruction. A prediction override bit is set on the appended instruction. Then, the appended instruction is executed with the real event outcome. | 12-18-2008 |
20080313446 | PROCESSOR PREDICTING BRANCH FROM COMPRESSED ADDRESS INFORMATION - Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and lower-order bit parts included in an instruction address, and a restoring section to restore the higher-order bit part from the higher-order address information. Branch instruction predicting section includes a history memory section that stores the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction at either one of a plurality of storing places determined from the higher-order bit part and the lower-order bit part corresponding to a branch address of a processed branch instruction. | 12-18-2008 |
20090006826 | BRANCH PREDICTION METHODS AND DEVICES CAPABLE OF PREDICTING FIRST TAKEN BRANCH INSTRUCTION WITHIN PLURALITY OF FETCHED INSTRUCTIONS - A branch prediction method, capable of predicting a first taken branch instruction within a plurality of fetched instructions, includes: determining whether one of the fetched instructions is the first taken branch instruction to be predicted according to hint instruction(s) or according to latest statistics of whether respective fetched instructions have been taken. The branch prediction method further includes: if one of the fetched instructions is determined to be the first taken branch instruction, performing branch prediction on the first taken branch instruction. | 01-01-2009 |
20090063831 | BRANCH PREDICTOR FOR BRANCHES WITH ASYMMETRIC PENALTIES - A mechanism is disclosed for enabling a plurality of nodes on a network to collaboratively exchange sets of rendering information respecting a file. In one implementation, each node maintains its own copy of the file, and each node may access its copy of the file. Whenever a node does access the locations of the file, that node sends out a rendering information message. The rendering information message comprises the set of rendering information for the file that has been updated. The rendering information message is forwarded to each of the other nodes. When each of the other nodes receives the rendering information message, it stores the set of rendering information contained therein to a rendering history associated with a user. In this manner, histories of access in the file by all users are exchanged among the nodes, and the user on each node is able to see rendering information generated by users on the other nodes. Collaboration among the users is thus achieved. | 03-05-2009 |
20090070569 | BRANCH PREDICTION DEVICE,BRANCH PREDICTION METHOD, AND MICROPROCESSOR - A branch prediction device predicts a branching probability in which a branch condition of a conditional branch instruction read out from an instruction memory storing an instruction is satisfied. A branch prediction entry part included in the branch prediction device stores prediction information as to whether or not the branch condition of the conditional branch instruction is satisfied. An entry update part included in the branch prediction device predicts the branching probability when the conditional branch instruction is executed next time based on a branch direction and updates the prediction information when the branch condition is satisfied by executing the conditional branch instruction. | 03-12-2009 |
20090089564 | Protecting a Branch Instruction from Side Channel Vulnerabilities - Embodiments of an invention to protection a branch instruction from side channel vulnerabilities are described. In one embodiment, a method includes receiving a request to modify the operation of a processor to protect against side channel attacks, and modifying branch prediction operation in response to the request. | 04-02-2009 |
20090106541 | PROCESSORS WITH BRANCH INSTRUCTION, CIRCUITS, SYSTEMS AND PROCESSES OF MANUFACTURE AND OPERATION - An electronic processor is provided for use with a memory ( | 04-23-2009 |
20090119494 | DESIGN STRUCTURE FOR PREDICTIVE DECODING - A design structure embodied in a machine readable medium used in a design process includes an apparatus for predictive decoding, the apparatus including register logic for fetching an instruction; predictor logic containing predictor information including prior instruction execution characteristics; logic for obtaining predictor information for the fetched instruction from the predictor; and decode logic for generating a selected one of a plurality of decode operation streams corresponding to the fetched instruction, wherein the decode operation stream is selected based on the predictor information. | 05-07-2009 |
20090138690 | LOCAL AND GLOBAL BRANCH PREDICTION INFORMATION STORAGE - Embodiments of the invention provide an apparatus of storing branch prediction information. In one embodiment, an integrated circuit device includes a first table for storing local branch prediction information, a second table for storing global branch prediction information, and circuitry. The circuitry is configured to receive a branch instruction and store local branch prediction information for the branch instruction in the first table. The local branch prediction information includes a local predictability value for the local branch prediction information. The circuitry is further configured to store global branch prediction information for the branch instruction in the second table only if the local predictability value is below a threshold value of predictability. | 05-28-2009 |
20090150657 | Method and Apparatus for Inhibiting Fetch Throttling When a Processor Encounters a Low Confidence Branch Instruction in an Information Handling System - An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less than a first predetermined threshold confidence threshold. In one embodiment, the processor includes a fetch throttle controller that inhibits fetch throttling by the instruction fetcher when confidence in the accuracy of a branch prediction for a particular currently issued branch instruction exhibits less than a second predetermined threshold confidence threshold. | 06-11-2009 |
20090193240 | METHOD AND APPARATUS FOR INCREASING THREAD PRIORITY IN RESPONSE TO FLUSH INFORMATION IN A MULTI-THREADED PROCESSOR OF AN INFORMATION HANDLING SYSTEM - An information handling system employs a processor that includes a thread priority controller. The processor includes a memory array that stores instruction threads including branch instructions. A branch unit in the processor sends flush information to the thread priority controller when a particular branch instruction in a particular instruction thread requires a flush operation. The flush information may indicate the correctness of incorrectness of a branch prediction for the particular branch instruction and thus the necessity of a flush operation. The flush information may also include a thread ID of the particular thread. If the flush information for the particular branch instruction of the particular thread indicates that a flush operation is necessary, the thread priority controller in response speculatively increases or boosts the priority of the particular instruction thread including the particular branch instruction. In this manner, a fetcher in the processor obtains ready access to the particular thread in the memory array. | 07-30-2009 |
20090198982 | DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING HAVING BRANCH TARGET ADDRESS CACHE SELECTIVELY APPLYING A DELAYED HIT - In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one execution unit. The instruction sequencing logic including branch target address prediction circuitry that stores a branch target address prediction associating a first instruction fetch address with a branch target address to be used as a second instruction fetch address. The branch target address prediction circuitry includes delay logic that, in response to at least a tag portion of a third instruction fetch address matching the first instruction fetch address, delays access to the memory system utilizing the second instruction fetch address if no branch target address prediction was made in an immediately previous cycle of operation. | 08-06-2009 |
20090204797 | METHOD AND SYSTEM FOR MITIGATING LOOKAHEAD BRANCH PREDICTION LATENCY WITH BRANCH PRESENCE PREDICTION AT THE TIME OF INSTRUCTION FETCHING - System and method for mitigating lookahead branch prediction latency with branch presence prediction at the time of instruction fetching. An exemplary embodiment includes a method for mitigating lookahead branch prediction latency, the method including receiving an instruction address in an instruction cache for fetching instructions in the microprocessor pipeline, receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline, and releasing instructions extracted from the instruction cache after determining that a branch prediction is available or unlikely to occur for instructions identified as potential predictable branches by the branch presence prediction. | 08-13-2009 |
20090210683 | METHOD AND APPARATUS FOR RECOVERING FROM BRANCH MISPREDICTION - Embodiments of the present invention provide a system that executes a branch instruction. When executing the branch instruction, the system obtains a stored prediction of a resolution of the branch instruction and fetches subsequent instructions for execution based on the predicted resolution of the branch instruction. If an actual resolution of the branch instruction is different from the predicted resolution (i.e., if the branch is mispredicted), the system updates the stored prediction of the resolution of the branch instruction to the actual resolution of the branch instruction. The system then re-executes the branch instruction. When re-executing the branch instruction, the system obtains the stored prediction of the resolution of the branch instruction and fetches subsequent instructions for execution based on the predicted resolution of the branch instruction. | 08-20-2009 |
20090210684 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR RECOVERING FROM BRANCH PREDICTION LATENCY - A branch prediction algorithm is used to generate a prediction of whether or not a branch will be taken. One or more instructions are fetched such that, for each of the fetched instructions, the prediction initiates a fetch of an instruction at a predicted target of the branch. A test is performed to ascertain whether or not the prediction was generated late relative to the fetched instructions, so that if the branch is later detected as mispredicted, that detection can be correlated to the late prediction. When the prediction is generated late relative to the fetched instructions, a latent prediction is selected by utilizing a fetching initiated by the latent prediction such that a new fetch is not started. | 08-20-2009 |
20090210685 | Identification and correction of cyclically recurring errors in one or more branch predictors - A data processing apparatus | 08-20-2009 |
20090217015 | SYSTEM AND METHOD FOR CONTROLLING RESTARTING OF INSTRUCTION FETCHING USING SPECULATIVE ADDRESS COMPUTATIONS - A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target. | 08-27-2009 |
20090265533 | Branch Prediction Mechanisms Using Multiple Hash Functions - In one embodiment, the branch prediction mechanism includes a first storage including a first plurality of locations for storing a first set of partial prediction information. The branch prediction mechanism also includes a second storage including a second plurality of locations for storing a second set of partial prediction information. Further, the branch prediction mechanism includes a control unit that performs a first hash function on input branch information to generate a first index for accessing a selected location within the first storage. The control unit also performs a second hash function on the input branch information to generate a second index for accessing a selected location within the second storage. Lastly, the control unit further provides a prediction value based on corresponding partial prediction information in the selected locations of the first and the second storages. | 10-22-2009 |
20100064123 | HYBRID BRANCH PREDICTION DEVICE WITH SPARSE AND DENSE PREDICTION CACHES - A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache. | 03-11-2010 |
20100082953 | RECOVERY APPARATUS FOR SOLVING BRANCH MIS-PREDICTION AND METHOD AND CENTRAL PROCESSING UNIT THEREOF - A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one circular instruction buffer, and a decoding and pairing circuit. The decoding and pairing circuit is coupled to the instruction buffer and the circular instruction buffer. The instruction buffer stores a plurality of instructions, and the circular instruction buffer stores a recovery instruction queue corresponding to the instructions, wherein the recovery instruction queue includes a plurality of recovery instructions. The decoding and pairing circuit decodes and pairs the instructions and the recovery instructions. When the branch mis-prediction occurs, the decoding and pairing circuit outputs the recovery instructions to an instruction execution and processing circuit which is externally connected to the decoding and pairing circuit. | 04-01-2010 |
20100146249 | Control-Flow Prediction Using Multiple Independent Predictors - The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a single and complete flow of program instructions associated therewith and to be performed on at least one processor core of the computing system. Overall processor performance and physical scalability may be improved by the described methods. | 06-10-2010 |
20100169625 | REDUCING BRANCH CHECKING FOR NON CONTROL FLOW INSTRUCTIONS - Some microprocessors check branch prediction information in a branch history table and/or a branch target buffer. To check for branch prediction information, a microprocessor can identify which instructions are control flow instructions and which instructions are non control flow instructions. To reduce power consumption in the branch history table and/or branch target buffer, the branch history table and/or branch target buffer can check for branch prediction information corresponding to the control flow instructions and not the non control flow instructions. | 07-01-2010 |
20100169626 | SYSTEM AND METHOD FOR A MULTI-SCHEMA BRANCH PREDICTOR - A system and method for predicting the execution of a branch of computer-executable instructions. In an embodiment, a branch predictor may include a program-counter register operable to store a program-counter value and a branch-history register operable to store a branch-history value. Additionally, the branch predictor may include a prediction hash table having a plurality of prediction values each uniquely corresponding to a plurality of memory locations. With these components, the branch predictor may generate a first prediction value that corresponds to the program-counter value and may generate a second prediction value that corresponds to a logical combination of the program-counter value and the branch-history value. With these two prediction values obtained from two different prediction schemas, the branch predictor is better suited to generate an overall prediction value based on the first and second prediction values that is more accurate than a single prediction value based upon a single prediction schema. | 07-01-2010 |
20100217962 | PREDICTING A CONDITIONAL BIT VALUE FOR CONTINUING EXECUTION OF AN INSTRUCTION - Methods and microprocessors are provided for continuing execution of an instruction, even though execution of the instruction depends on a value of a conditional bit (e.g., a flag bit or a predicated bit) that has not been determined. Rather than stalling execution of the instruction, a predicted value of the conditional bit is predicted and execution of the instruction is continued based on the predicted value of the conditional bit. If the predicted value matches a determined value of the conditional bit, a result from continuing execution of the instruction is committed. An existing branching prediction block of a microprocessor might be extended to support this mechanism. | 08-26-2010 |
20100332812 | METHOD, SYSTEM AND COMPUTER-ACCESSIBLE MEDIUM FOR LOW-POWER BRANCH PREDICTION - Examples of a method, system, and computer-accessible medium are provided which can utilize a neural branch predictor on, e.g., an analog circuit. For example, a current summation can be used instead of the digital dot-product generally used in traditional neural predictor designs. A scaling factor may also be used to increase prediction accuracy. | 12-30-2010 |
20110078425 | BRANCH PREDICTION MECHANISM FOR PREDICTING INDIRECT BRANCH TARGETS - A multithreaded microprocessor includes an instruction fetch unit that may fetch and maintain a plurality of instructions belonging to one or more threads and one or more execution units that may concurrently execute the one or more threads. The instruction fetch unit includes a target branch prediction unit that may provide a predicted branch target address in response to receiving an instruction fetch address of a current indirect branch instruction. The branch prediction unit includes a primary storage and a control unit. The storage includes a plurality of entries, and each entry may store a predicted branch target address corresponding to a previous indirect branch instruction. The control unit may generate an index value for accessing the storage using a portion of the instruction fetch address of the current indirect branch instruction, and branch direction history information associated with a currently executing thread of the one or more threads. | 03-31-2011 |
20110087866 | PERCEPTRON-BASED BRANCH PREDICTION MECHANISM FOR PREDICTING CONDITIONAL BRANCH INSTRUCTIONS ON A MULTITHREADED PROCESSOR - A multithreaded microprocessor includes an instruction fetch unit including a perceptron-based conditional branch prediction unit configured to provide, for each of one or more concurrently executing threads, a direction branch prediction. The conditional branch prediction unit includes a plurality of storages each including a plurality of entries. Each entry may be configured to store one or more prediction values. Each prediction value of a given storage may correspond to at least one conditional branch instruction in a cache line. The conditional branch prediction unit may generate a separate index value for accessing each storage by generating a first index value for accessing a first storage by combining one or more portions of a received instruction fetch address, and generating each other index value for accessing the other storages by combining the first index value with a different portion of direction branch history information. | 04-14-2011 |
20110119472 | BRANCH PREDICTING DEVICE, BRANCH PREDICTING METHOD THEREOF, COMPILER, COMPILING METHOD THEREOF, AND MEDIUM FOR STORING BRANCH PREDICTING PROGRAM - A branch prediction mechanism | 05-19-2011 |
20110238965 | BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT PERFORMING THE METHOD - A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit. | 09-29-2011 |
20110238966 | BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT FOR EXECUTING THE SAME - A branch prediction method executed in a branch prediction circuit executes the branch instruction, the branch prediction method includes: a branch information storing process for storing the information in the first storage unit or the second storage unit; a process for determining on the basis of a branch condition set by the branch instruction and a realized branch whether the branch prediction is realized; a rewriting process for performing a rewrite of the information in one of the first storage unit and the second storage unit in accordance with the determination and the degree of likelihood that a branch indicated by the branch prediction occurs; and a process for performing branch prediction in response to the branch information when the branch instruction is executed in the processor. | 09-29-2011 |
20110320790 | Link Stack Repair of Erroneous Speculative Update - Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer. | 12-29-2011 |
20120005462 | Hardware Assist for Optimizing Code During Processing - A method, data processing system, and computer program product for obtaining information about instructions. Instructions are processed. In response to processing a branch instruction in the instructions, a determination is made as to whether a result from processing the branch instruction follows a prediction of whether a branch is predicted to occur for the branch instruction. In response to the result following the prediction, the branch instruction is added to a current segment in a trace. In response to an absence of the result following the prediction, the branch instruction is added to the current segment in the trace and a first new segment and a second new segment are created. The first new segment includes a first branch instruction reached in the instructions from following the prediction. The second new segment includes a second branch instruction in the instructions reached from not following the prediction. | 01-05-2012 |
20120079255 | INDIRECT BRANCH PREDICTION BASED ON BRANCH TARGET BUFFER HYSTERESIS - Methods and apparatus to perform efficient indirect branch prediction operations are described. In one embodiment, a branch target buffer (BTB) stored a target address and a bimodal hysteresis counter for an indirect branch that has been encountered by a front-end of the processor during a time period. An indirect branch prediction logic then generates a prediction for an instruction corresponding to a indirect branch based on the stored bimodal hysteresis counter of the BTB. Other embodiments are also claimed and disclosed. | 03-29-2012 |
20120089823 | PROCESSING APPARATUS, COMPILING APPARATUS, AND DYNAMIC CONDITIONAL BRANCH PROCESSING METHOD - A technology for reducing pipeline a control hazard is provided. A conditional branch is processed through a conditional branch prediction, and a predetermined conditional branch prediction, which is determined as incorrect, may be modified through a following test for the conditional branch prediction, thereby reducing the pipeline control hazard quickly without additional hardware. | 04-12-2012 |
20120089824 | PROCESSOR AND VECTOR LOAD INSTRUCTION EXECUTION METHOD - Provided is a processor including an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch instruction, a data acquisition unit that starts issue of a plurality of acquisition requests for acquiring a plurality of vector data based on the issued vector load instruction from the main memory, a determination unit that determines a success or a failure of the branch target prediction after the branch target is determined, and a vector load management unit that, when the branch target prediction is determined to be a success, acquires all vector data based on the plurality of acquisition requests and then transfers all the vector data to a vector register, and, when the branch target prediction is determined to be a failure, discards the vector data acquired by the issued acquisition requests. | 04-12-2012 |
20120117362 | REPLAY OF DETECTED PATTERNS IN PREDICTED INSTRUCTIONS - Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued. | 05-10-2012 |
20120124346 | Decoding conditional program instructions - A processor | 05-17-2012 |
20120124347 | BRANCH PREDICTION SCHEME UTILIZING PARTIAL-SIZED TARGETS - A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type. | 05-17-2012 |
20120151194 | BYTECODE BRANCH PROCESSOR AND METHOD - A bytecode interpreter in a computing system is provided. The interpreter assists in branch prediction by a host processor that processes a virtual machine such as JAVA® and DALVIK®, thereby reducing branch misprediction and achieving high performance. | 06-14-2012 |
20120166775 | COMBINED LEVEL 1 AND LEVEL 2 BRANCH PREDICTOR - A branch predictor for use in a processor includes a Level 1 branch predictor, a Level 2 branch predictor, a match determining circuit, and an override determining circuit. The Level 1 branch predictor generates a Level 1 branch prediction. The Level 2 branch predictor generates a Level 2 branch prediction. The match determining circuit determines whether the Level 1 and Level 2 branch predictions match. The override determining circuit determines whether to override the Level 1 branch prediction with the Level 2 branch prediction. The Level 1 branch prediction is used when the Level 1 and Level 2 branch predictions match or when the Level 1 and Level 2 branch predictions do not match and the Level 1 branch prediction is not overridden. The Level 2 branch prediction is used when the Level 1 and Level 2 branch predictions do not match and the Level 1 branch prediction is overridden. | 06-28-2012 |
20120311308 | Branch Predictor with Jump Ahead Logic to Jump Over Portions of Program Code Lacking Branches - A processor of an aspect includes front end logic to process parcels of program code. Each of the parcels has multiple instructions. A branch predictor of the processor is coupled with the front end logic. The branch predictor is to predict directions of branch instructions of the program code. The processor includes jump ahead logic to cause the branch predictor to jump over at least one parcel of the program code that does not have a branch instruction between parcels of the program code that each have at least one branch instruction. | 12-06-2012 |
20130007423 | PREDICTING OUT-OF-ORDER INSTRUCTION LEVEL PARALLELISM OF THREADS IN A MULTI-THREADED PROCESSOR - Systems and methods for predicting out-of-order instruction-level parallelism (ILP) of threads being executed in a multi-threaded processor and prioritizing scheduling thereof are described herein. One aspect provides for tracking completion of instructions using a global completion table having a head segment and a tail segment; storing prediction values for each instruction in a prediction table indexed via instruction identifiers associated with each instruction, a prediction value being configured to indicate an instruction is predicted to issue from one of: the head segment and the tail segment; and predicting threads with more instructions issuing from the tail segment have a higher degree of out-of-order instruction-level parallelism. Other embodiments and aspects are also described herein. | 01-03-2013 |
20130007424 | CASCADING INDIRECT BRANCH INSTRUCTIONS - Techniques are disclosed relating to improving misprediction rates of indirect branch instructions. In one embodiment, a computer system determines misprediction information for an indirect branch instruction included in a sequence of instructions. The misprediction information is indicative of a processor not correctly predicting an actual target address of the indirect branch instruction. In some embodiments, the misprediction information includes a misprediction rate for the target address). Based on the misprediction information, the computer system inserts before the indirect branch instruction a conditional branch instruction that specifies the target address. | 01-03-2013 |
20130086370 | COMBINED BRANCH TARGET AND PREDICATE PREDICTION - Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed. | 04-04-2013 |
20130145135 | PERFORMANCE OF PROCESSORS IS IMPROVED BY LIMITING NUMBER OF BRANCH PREDICTION LEVELS - A method utilizes information provided by performance monitoring hardware to dynamically adjust the number of levels of speculative branch predictions allowed (typically 3 or 4 per thread). for a processor core. The information includes cycles-per-instruction (CPI) for the processor core and number of memory accesses per unit time. If the CPI is below a CPI threshold; and the number of memory accesses (NMA) per unit time is above a prescribe threshold, the number of levels of speculative branch predictions is reduced per thread for the processor core. Likewise, the number of levels of speculative branch predictions could be increased, from a low level to maximum allowed, if the CPI threshold is exceeded or the number of memory accesses per unit time is below the prescribed threshold. | 06-06-2013 |
20130198499 | System and Method for Mitigating the Impact of Branch Misprediction When Exiting Spin Loops - A computer system may recognize a busy-wait loop in program instructions at compile time and/or may recognize busy-wait looping behavior during execution of program instructions. The system may recognize that an exit condition for a busy-wait loop is specified by a conditional branch type instruction in the program instructions. In response to identifying the loop and the conditional branch type instruction that specifies its exit condition, the system may influence or override a prediction made by a dynamic branch predictor, resulting in a prediction that the exit condition will be met and that the loop will be exited regardless of any observed branch behavior for the conditional branch type instruction. The looping instructions may implement waiting for an inter-thread communication event to occur or for a lock to become available. When the exit condition is met, the loop may be exited without incurring a misprediction delay. | 08-01-2013 |
20130297918 | Apparatus for Predicate Calculation in Processor Instruction Set - An apparatus and method for calculating flag bits is disclosed. The flag bits may be used in a processor utilizing branch predication. More particularly, the apparatus and method may be used to calculate a predicate that can be used by a branch unit to evaluate whether a branch is to be taken. In one embodiment, the apparatus is coupled to receive a condition code associated with an instruction, and flag bits generated responsive to execution of the instruction. The condition code is indicative of a condition to be checked resulting from execution of the instruction. The apparatus may then provide an indication of whether the condition is true. | 11-07-2013 |
20130311759 | INSTRUCTION SEQUENCE BUFFER TO ENHANCE BRANCH PREDICTION EFFICIENCY - A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer. | 11-21-2013 |
20130318332 | BRANCH MISPREDICTION BEHAVIOR SUPPRESSION USING A BRANCH OPTIONAL INSTRUCTION - A method for suppressing branch misprediction behavior is contemplated in which a branch-optional instruction that would cause the flow of control to branch around instructions in response to a determination that a predicate vector is null is predicted not taken. However, in response to detecting that the prediction is incorrect, misprediction behavior is inhibited. | 11-28-2013 |
20130332713 | FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION - Embodiments relate to using a fast index tree for accelerated branch prediction. A system includes a branch target buffer, a FIT structure, and a processing circuit configured to perform a method. The method includes determining that searching of the branch target buffer is to be performed under FIT control. A current search address for searching of the branch target buffer is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from the FIT structure. The searching of the branch target buffer is re-indexed based on the FIT next-search address. It is determined whether the searching at the saved current search address located the branch prediction. | 12-12-2013 |
20130332714 | FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION - Embodiments relate to using a fast index tree for accelerated branch prediction. A computer-implemented method includes determining, by a computer, that searching of a branch target buffer is to be performed under FIT control. A current search address is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from a FIT structure. The searching is re-indexed based on the FIT next-search address. Based on locating the branch prediction, the searching is continued under FIT control with the current search address set based on the FIT next-search address. Based on failing to locate the branch prediction, the searching is re-indexed with the saved current search address, and the searching is performed without FIT control. | 12-12-2013 |
20130339695 | ASYNCHRONOUS LOOKAHEAD SECOND LEVEL BRANCH TARGET BUFFER - Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer. | 12-19-2013 |
20130339696 | SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION - Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction. | 12-19-2013 |
20130339697 | BRANCH PREDICTION PRELOADING - Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field. Based on executing the branch prediction preload instruction, a branch target buffer is preloaded with the address of the predicted branch instruction, the branch instruction length, and the predicted target address associated with the predicted branch instruction. | 12-19-2013 |
20130339698 | SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION - Embodiments relate to selectively blocking branch instruction predictions. An aspect includes computer implemented method for performing selective branch prediction. The method includes detecting, by a processor, a branch-prediction blocking instruction in a stream of instructions and blocking, by the processor, branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction. | 12-19-2013 |
20140019737 | Branch Prediction For Indirect Jumps - Branch prediction for indirect jumps, including: receiving, by a branch prediction module, a branch address for each of a plurality of executed branch instructions; receiving, by the branch prediction module, an instruction address of a current branch instruction; creating, by the branch prediction module, an execution path identifier in dependence upon the branch address for each of the plurality of executed branch instructions and the instruction address of the current branch instruction; and searching, by the branch prediction module, a branch prediction table for an entry that matches the execution path identifier. | 01-16-2014 |
20140025938 | PREDICTION OPTIMIZATIONS FOR MACROSCALAR VECTOR PARTITIONING LOOPS - A method of predicting a backward conditional branch instruction used in a vector partitioning loop includes detecting the first conditional branch instruction that occurs after consumption of a dependency index vector by a predicate generating instruction. The dependency index vector includes information indicative of a number of iterations of the vector partitioning loop, and the conditional branch instruction may branch backwards when taken. The conditional branch instruction may then be predicted to be taken a number of times that is determined by the dependency index vector. | 01-23-2014 |
20140082338 | INSTRUCTION FILTERING - Embodiments relate to instruction filtering. An aspect includes a computer-implemented method for instruction filtering. The method includes detecting, by a processor, a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in a tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. The method further includes marking, by the processor, instruction text of the subsequently fetched instruction to indicate that the subsequently fetched instruction is a previously executed tracked instruction based on the indication of the tracked instruction from the tracking array. The method additionally includes preventing an action of a tracked instruction logic block based on detecting the marked instruction text. | 03-20-2014 |
20140095849 | INSTRUCTION AND LOGIC FOR OPTIMIZATION LEVEL AWARE BRANCH PREDICTION - A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level. | 04-03-2014 |
20140101418 | MITIGATING INSTRUCTION PREDICTION LATENCY WITH INDEPENDENTLY FILTERED PRESENCE PREDICTORS - Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters. The stall determination logic is configured to generate a combined indication that will stall instruction delivery, allowing potentially latent instruction predictions to be accounted for, based upon one or more non-blocked indications received from the plurality of dynamic filters. | 04-10-2014 |
20140143526 | Branch Prediction Gating - In one embodiment, a processor includes at least one execution unit. The processor also includes prediction gating logic coupled to the at least one execution unit. The prediction gating logic may be to, in response to a first prediction that a first branch is taken, obtain a distance value to a second branch using a target array, and gate a branch prediction unit for a number of instruction blocks equal to the distance value to the second branch. Other embodiments are described and claimed. | 05-22-2014 |
20140149726 | ESTABLISHING A BRANCH TARGET INSTRUCTION CACHE (BTIC) ENTRY FOR SUBROUTINE RETURNS TO REDUCE EXECUTION PIPELINE BUBBLES, AND RELATED SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA - Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations. | 05-29-2014 |
20140156977 | ENABLING AND DISABLING A SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION - Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific. | 06-05-2014 |
20140173262 | Energy-Focused Compiler-Assisted Branch Prediction - A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency. | 06-19-2014 |
20140189330 | OPTIONAL BRANCHES - Branch instructions are provided for improved execution performance. The branch instruction includes one or more paths that are marked as a safe path for execution. If a marked path is executed based on a branch prediction, the execution continues until completion after it is determined that the other path is the correct path. | 07-03-2014 |
20140195789 | Usefulness Indication For Indirect Branch Prediction Training - A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries. | 07-10-2014 |
20140195790 | PROCESSOR WITH SECOND JUMP EXECUTION UNIT FOR BRANCH MISPREDICTION - A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances. | 07-10-2014 |
20140201507 | THREAD SELECTION AT A PROCESSOR BASED ON BRANCH PREDICTION CONFIDENCE - A processor employs one or more branch predictors to issue branch predictions for each thread executing at an instruction pipeline. Based on the branch predictions, the processor determines a branch prediction confidence for each of the executing threads, whereby a lower confidence level indicates a smaller likelihood that the corresponding thread will actually take the predicted branch. Because speculative execution of an untaken branch wastes resources of the instruction pipeline, the processor prioritizes threads associated with a higher confidence level for selection at the stages of the instruction pipeline. | 07-17-2014 |
20140201508 | CONFIDENCE THRESHOLD-BASED OPPOSING BRANCH PATH EXECUTION FOR BRANCH PREDICTION - Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread. | 07-17-2014 |
20140201509 | SWITCH STATEMENT PREDICTION - Methods and branch predictors for predicting a target location of a jump table switch statement in a program. The method includes continuously monitoring instructions at the branch predictor to determine if they write to registers used to store an input variable to a jump table switch statement. Any update to a monitored register is stored in a register table maintained by the branch predictor. Then when it comes time to make a prediction for a jump table switch statement instruction the branch predictor uses the register value stored in the table is used to predict where the jump table switch statement will branch to. | 07-17-2014 |
20140258696 | STRIDED TARGET ADDRESS PREDICTOR (STAP) FOR INDIRECT BRANCHES - Systems and methods for predicting an indirect branch target address. A strided target address predictor (STAP) system can observe a striding pattern from a previous indirect branch target. The system can predict a target address based on the observed striding pattern. The system can initialize a confidence counter. The system can determine a previous indirect branch target address. The system can determine a predicted target address. The system can determine an actual target address, determine if the predicted target has the same address as the actual target, determine if a confidence counter is less than a prediction threshold if the predicted target has the same address as the actual target, and if the confidence counter is less than a prediction threshold, increase the value of the confidence counter, reinitialize the confidence counter, assign the value of the difference between the actual target and the previous indirect branch target to the stride length, and assign the address of the actual target to the previous indirect branch target value. | 09-11-2014 |
20140281439 | HARDWARE OPTIMIZATION OF HARD-TO-PREDICT SHORT FORWARD BRANCHES - Methods and apparatuses for optimizing hard-to-predict short forward branches. A method detects a forward conditional branch with at least one instruction between the forward conditional branch and forward conditional branch target. The method determines whether a first of the at least one instruction includes at least one of a conditional branch or a condition-code setter. If the first instruction does not have the at least one of a conditional branch or a condition-code setter, the first instruction is dynamically assigned an inverted condition to optimize a code path. The method determines if there is a next instruction between the forward conditional branch and its target. If there is, the method analyzes the next instruction. If there is no next instruction, the method executes the optimized code path. If the instruction includes the conditional branch or condition-code setter, it discards dynamic assignments and executes the detected forward conditional branch. | 09-18-2014 |
20140281440 | PRECALCULATING THE DIRECT BRANCH PARTIAL TARGET ADDRESS DURING MISSPREDICTION CORRECTION PROCESS - An example method of storing a partial target address in an instruction cache includes receiving a branch instruction. The method also includes predicting a direction of the branch instruction as being not taken. The method further includes calculating a destination address based on executing the branch instruction. The method also includes determining a partial target address using the destination address. The method further includes in response to the predicted direction of the branch instruction changing from not taken to taken, replacing an offset in an instruction cache with the partial target address. | 09-18-2014 |
20140281441 | INDIRECT BRANCH PREDICTION - Methods and indirect branch predictor logic units to predict the target addresses of indirect branch instructions. The method comprises storing in a table predicted target addresses for indirect branch instructions indexed by a combination of the indirect path history for previous indirect branch instructions and the taken/not-taken history for previous conditional branch instructions. When a new indirect branch instruction is received for prediction, the indirect path history and the taken/not-taken history are combined to generate an index for the indirect branch instruction. The generated index is then used to identify a predicted target address in the table. If the identified predicted target address is valid, then the target address of the indirect branch instruction is predicted to be the predicted target address. | 09-18-2014 |
20140297996 | MULTIPLE HASH TABLE INDEXING - A processor includes storage elements to store a first and second value, as well as a plurality of hash units coupled to the storage elements. Each hash unit performs a hash operation using the first value and the second value to generate a corresponding hash result value. The processor further includes selection logic to select a hash result value from the hash result values generated by the plurality of hash units responsive to a selection input generated from another hash operation performed using the first value and the second value. A method includes predicting whether a branch instruction is taken based on a prediction value stored at an entry of a branch prediction table indexed by an index value selected from a plurality of values concurrently generated from an address value of the branch instruction and a branch history value representing a history of branch directions at the processor. | 10-02-2014 |
20140317390 | RETURN ADDRESS PREDICTION - A data processing apparatus executes call instructions, and after a sequence of instructions executed in response to a call instruction a return instruction causes the program flow to return to a point in the program sequence associated with that call instruction. The data processing apparatus is configured to speculatively execute instructions in dependence on a predicted outcome of earlier instructions and a return address prediction unit is configured to store return addresses associated with unresolved call instructions. The return address prediction unit comprises: a stack portion onto which return addresses associated with unresolved call instructions are pushed, and from which a return address is popped when a return instruction is speculatively executed; and a buffer portion which stores an entry for each unresolved call instruction executed and for each return instruction which is speculatively executed. | 10-23-2014 |
20140337605 | Mechanism for Reducing Cache Power Consumption Using Cache Way Prediction - A mechanism for reducing power consumption of a cache memory of a processor includes a processor with a cache memory that stores instruction information for one or more instruction fetch groups fetched from a system memory. The cache memory may include a number of ways that are each independently controllable. The processor also includes a way prediction unit. The way prediction unit may enable, in a next execution cycle, a given way within which instruction information corresponding to a target of a next branch instruction is stored in response to a branch taken prediction for the next branch instruction. The way prediction unit may also, in response to the branch taken prediction for the next branch instruction, enable, one at a time, each corresponding way within which instruction information corresponding to respective sequential instruction fetch groups that follow the next branch instruction are stored. | 11-13-2014 |
20140344558 | NEXT FETCH PREDICTOR RETURN ADDRESS STACK - A system and method for efficient branch prediction. A processor includes a next fetch predictor to generate a fast branch prediction for branch instructions at an early pipeline stage. The processor also includes a main return address stack (RAS) at a later pipeline stage for predicting the target of return instructions. When a return instruction is encountered, the prediction from the next fetch predictor is replaced by the top of the main RAS. If there are any recent call or return instructions in flight toward the main RAS, then a separate prediction is generated by a mini-RAS. | 11-20-2014 |
20140351568 | OPPORTUNISTIC MULTI-THREAD METHOD AND PROCESSOR - Disclosed are an opportunistic multi-thread method and processor, the method comprising the following steps: if a zeroth thread, a first thread, a second thread and a third thread all have instructions ready to be executed, then a zeroth clock period, a first clock period, a second clock period and a third clock period are respectively allocated to the zeroth thread, the first thread, the second thread and the third thread; if one of the threads cannot issue an instruction within a specified clock period because the instruction is not ready, and the previous thread still has an instruction ready to be executed after issuing certain instructions in the previous specified clock period, then the previous thread will take the specified clock period. The processor comprises an instruction cache, an instruction decoder, an instruction pipeline controller and an arithmetic logic unit; the opportunistic multi-thread processor adds for each stage of production line a prediction circuit for an effective thread instruction and a set of two-dimensional thread identity registers. | 11-27-2014 |
20140365753 | SELECTIVE ACCUMULATION AND USE OF PREDICTING UNIT HISTORY - A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler. | 12-11-2014 |
20140372736 | DATA PROCESSING APPARATUS AND METHOD FOR HANDLING RETRIEVAL OF INSTRUCTIONS FROM AN INSTRUCTION CACHE - A data processing apparatus and method are provided for handling retrieval of instructions from an instruction cache. Fetch circuitry retrieves instructions from the instruction cache into a temporary buffer, and execution circuitry executes a sequence of instructions retrieved from the temporary buffer, that sequence including branch instructions. Branch prediction circuitry is configured to predict, for each identified branch instruction in the sequence, if that branch instruction will result in a taken branch when that branch instruction is subsequently executed by the execution circuitry. In a normal operating mode, the fetch circuitry retrieves one or more speculative instructions from the instruction cache between the time that a source branch instruction is retrieved from the instruction cache and the branch prediction circuitry predicts if that source branch instruction will result in the taken branch. In the event that that source branch instruction is predicted as taken, the one or more speculative instructions are discarded. In the event that a source branch instruction is predicted as taken, throttle prediction circuitry maintains a count value indicative of a number of instructions appearing in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction, that is predicted as taken, the throttle prediction circuitry operates the fetch circuitry in a throttled mode where the number of instructions subsequently retrieved by the fetch circuitry from the instruction cache is limited dependent on the count value, and then the fetch circuitry is prevented from retrieving any further instructions from the instruction cache for a predetermined number of clock cycles. This serves to reduce the power consumption consumed in accessing the instruction cache to retrieve speculative instructions which later need to be discarded. | 12-18-2014 |
20150046690 | Techinques for selecting a predicted indirect branch address from global and local caches - A technique for branch target prediction includes storing, based on an instruction fetch address for a group of fetched instructions, first predicted targets for first indirect branch instructions in respective entries of a local count cache. Second predicted targets for second indirect branch instructions are stored in respective entries of a global count cache, based on the instruction fetch address and a global history vector for the instruction fetch address. One of the local count cache and the global count cache is selected to provide a selected predicted target for an indirect branch instruction in the group of fetched instructions. | 02-12-2015 |
20150058607 | CONFIDENCE THRESHOLD-BASED OPPOSING BRANCH PATH EXECUTION FOR BRANCH PREDICTION - Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread. | 02-26-2015 |
20150100769 | PROCESSOR BRANCH CACHE WITH SECONDARY BRANCHES - A processor uses a prediction unit to predict subsequent instructions of a program to be executed by the processor. Many implementations or combinations of implementations may be used to predict the subsequent instruction of the program. In one embodiment, a branch cache is used to store branch information. A prediction table is used to store prediction information based on the branch. A prediction logic module determines whether a branch is taken or not taken based on the branch information stored in the branch cache and the prediction information stored in the prediction table. | 04-09-2015 |
20150339126 | DYNAMIC THREAD SHARING IN BRANCH PREDICTION STRUCTURES - Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state. | 11-26-2015 |
20150347133 | Suspending Branch Prediction in Transactional Memory Instruction Execution - In a computer supporting Transactional Memory (TM) Transaction Execution (TX), use of speculative branch prediction is programmably suspended during TX, and programmably resumed. The branch prediction suspension may cause the execution of the branch instruction to stall in the pipeline until branch conditions and branch target addresses are resolved. | 12-03-2015 |
20150347134 | Delaying Branch Prediction Updates Until After a Transaction is Completed - In a branch predictor in a processor capable of executing transactional memory transactions, the branch predictor for speculatively prediction outcome of branch instructions, such as taken/not-taken, target address and target instruction. Branch prediction information is buffered during a transaction, and is only loaded into the branch predictor when the transaction is completed, but discarded if the transaction aborts. | 12-03-2015 |
20150347135 | Suppressing Branch Prediction Updates on a Repeated Execution of an Aborted Transaction - Aspects of branch prediction are suppressed for branch instructions executing in a transaction of a transactional memory (TM) environment in transactions that are re-executions of previously aborted transactions. | 12-03-2015 |
20150347136 | Branch Predictor Performing Distinct Non-Transaction Branch Prediction Functions and Transaction Branch Prediction Functions - A branch predictor for predicting branch instructions performs different branch prediction operations for branches executing in a transaction than those not-executing in a transaction, including suppressing branch prediction functions based on progress of a re-execution of a previously aborted transaction, the transaction buffering data and committing the buffered data to memory when the transaction completes, but discarding the buffered data when the transaction aborts. | 12-03-2015 |
20150347137 | Suppressing Branch Prediction on a Repeated Execution of an Aborted Transaction - Branch prediction is suppressed for branch instructions executing in a transaction of a transactional memory (TM) environment in transactions that are re-executions of previously aborted transactions. | 12-03-2015 |
20150347138 | Branch Predictor Suppressing Branch Prediction of Previously Executed Branch Instructions in a Transactional Execution Environment - Branch prediction is suppressed for specific branch instructions executing in a transaction of a transactional memory (TM) environment, when the specific branch instruction was previously executed in the transaction, in one embodiment the specific branch instruction is suppressed after a predetermined number of executions of the specific instruction in a transaction. | 12-03-2015 |
20150363201 | PREDICTING INDIRECT BRANCHES USING PROBLEM BRANCH FILTERING AND PATTERN CACHE - Predicting indirect branch instructions may comprise predicting a target address for a fetched branch instruction. Accuracy of the target address may be tracked. The fetched branch instruction may be flagged as a problematic branch instruction based on the tracking. A pattern cache may be trained for predicting more accurate target address for the fetched branch instruction, and the next time the fetched branch instruction is again fetched, a target address may be predicted from the pattern cache. | 12-17-2015 |
20150378728 | BRANCH SYNTHETIC GENERATION ACROSS MULTIPLE MICROARCHITECTURE GENERATIONS - Branch sequences for branch prediction performance test are generated by performing the following steps: (i) generating a branch node graph, by a branch node graph generator machine logic set, based, at least in part, upon a set of branch traces of a workload or benchmark code; (ii) generating a first assembly pattern file, for use with a first instruction set architecture (ISA)/microarchitecture set, by an assembly pattern generator machine logic set, based, at least in part, upon the branch node graph so as to mimic the control-flow pattern of the workload or benchmark code; and (iii) running the assembly pattern file on the first ISA/microarchitecture set to obtain first execution results. | 12-31-2015 |
20160092221 | DEPENDENCY-PREDICTION OF INSTRUCTIONS - Systems and methods for dependency-prediction include executing instructions in an instruction pipeline of a processor and detecting a conditionality-imposing control instruction, such as an If-Then (IT) instruction, which imposes dependent behavior on a conditionality block size of one or more dependent instructions. Prior to executing a first instruction, a dependency-prediction is made to determine if the first instruction is a dependent instruction of the conditionality-imposing control instruction, based on the conditionality block size and one or more parameters of the instruction pipeline. The first instruction is executed based on the dependency-prediction. When the first instruction is dependency-mispredicted, an associated dependency-misprediction penalty is mitigated. If the first instruction is a branch instruction, the mitigation involves training a branch prediction tracking mechanism to correctly dependency-predict future occurrences of the first instruction. | 03-31-2016 |
20160098279 | METHOD AND APPARATUS FOR SEGMENTED SEQUENTIAL STORAGE - Various embodiments are described relating to processors, hierarchical processors, branch predictors, branch prediction systems, and computing systems. Some or all of a hierarchical instruction scheduler, hierarchical register file, or a hierarchical store buffer may be included in a hierarchical microprocessor. Some or all aspects of the hierarchical microprocessor may be implemented, partially or fully, using a method for sequential data storage. | 04-07-2016 |
20160103683 | COMPILE METHOD AND COMPILER APPARATUS - A compiler apparatus copies a branch instruction included in first code to produce a plurality of branch instructions. The compiler apparatus generates a control instruction to cause different threads running on a processor, which is able to execute a plurality of threads that share storage space for storing information to be used for branch prediction, to execute different ones of the plurality of branch instructions. The compiler apparatus generates second code including the plurality of branch instructions and the control instruction. | 04-14-2016 |
20160170750 | BRANCH SYNTHETIC GENERATION ACROSS MULTIPLE MICROARCHITECTURE GENERATIONS | 06-16-2016 |
20160179547 | Binary Translation Mechanism | 06-23-2016 |
20160188338 | BRANCH TARGET BUFFER FOR EMULATION ENVIRONMENTS - Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction. | 06-30-2016 |
20220137972 | PROCESSING DEVICE WITH A MICROBRANCH TARGET BUFFER FOR BRANCH PREDICTION USING LOOP ITERATION COUNT - An integrated circuit comprising instruction processing circuitry for processing a plurality of program instructions and instruction prediction circuitry. The instruction prediction circuitry comprises circuitry for detecting successive occurrences of a same program loop sequence of program instructions. The instruction prediction circuitry also comprises circuitry for predicting a number of iterations of the same program loop sequence of program instructions, in response to detecting, by the circuitry for detecting, that a second occurrence of the same program loop sequence of program instructions comprises a same number of iterations as a first occurrence of the same program loop sequence of program instructions. | 05-05-2022 |