| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 711168000 | Concurrent accessing | 35 |
| 20080244209 | METHODS AND DEVICES FOR DETERMINING QUALITY OF SERVICES OF STORAGE SYSTEMS - Methods and systems for allowing access to computer storage systems. Multiple requests from multiple applications can be received and processed efficiently to allow traffic from multiple customers to access the storage system concurrently. | 10-02-2008 |
| 20080263303 | LINEAR COMBINER WEIGHT MEMORY - A linear combiner weight memory. Various embodiments of the weight memory provide a weight bank and control logic. The weight bank is operable to couple with a data stream and may include four registers. The first register is operable to store a first in-phase weight value. The second register is operable to store a second in-phase weight value and be written with the second in-phase weight value while the first in-phase weight value is read from the first register. The third register is operable to store a first quadrature weight value. The fourth register is operable to store a second quadrature weight value and be written with the second quadrature weight value while the first quadrature weight value is read from the third register. | 10-23-2008 |
| 20080270727 | Data transfer in cluster storage systems - Embodiments include methods, apparatus, and systems for data transfer in storage systems. One embodiment includes a method that transmits a state of cached write data and mapping metadata associated with a disk group from a first array to a second array and then transfers access to the disk group from the first array to the second array while host applications continue to access data in the disk group. | 10-30-2008 |
| 20080301392 | SYSTEM AND DEVICE HAVING ALTERNATIVE BIT ORGANIZATION - A system is disclosed that includes a first memory device operable according to either a first bit organization or a second bit organization, a second memory device operable according to only the first bit organization, and a central processing unit (CPU). The CPU is commonly connected to the first and second memory devices via a command/address bus, and is connected to the first memory device via a data bus separate from the command/address bus and having an upper half and a lower half. However, the CPU is connected to the second memory device via only the upper half of the data bus. | 12-04-2008 |
| 20090013144 | INTEGRATED CIRCUIT, AND INTEGRATED CIRCUIT SYSTEM - A main LSI includes a plurality of master circuits that transmit access requests to an SDRAM, an input interface that receives an access request from a master circuit in a sub LSI, an arbitration circuit that receives the access requests from the internal master circuits and from the input interface, sequentially selects, in accordance with a predetermined arbitration rule, a master circuit to be allowed to access the SDRAM, and determines output timings for addresses pertaining to the data transfers from the sequentially selected master circuits, and an access signal generation circuit that causes the sequentially selected master circuits to access the SDRAM in accordance with the corresponding output timings. | 01-08-2009 |
| 20090077337 | DATA READING METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - The present invention provides a data reading method suitable for use in a semiconductor memory device equipped with a plurality of semiconductor memory chips, which is capable of suppressing an increase in layout area as compared with a required storage capacity, and a semiconductor memory device. Two memory chips are sequentially selected in the way of combinations different from each other from within a plurality of memory chips each having a first storage area and a second storage area. Data are simultaneously read from the first storage area of one of the selected two memory chips and the second storage area of the other thereof. | 03-19-2009 |
| 20090157994 | MEMORY MODULE WITH REDUCED ACCESS GRANULARITY - A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands. | 06-18-2009 |
| 20090204780 | DATA STORAGE UNIT, DATA STORAGE CONTROLLING APPARATUS AND METHOD, AND DATA STORAGE CONTROLLING PROGRAM - A data storage unit is provided in which all data are stored into a memory including a plurality of memory banks and a plurality of desired data is read simultaneously, without any load to the hardware. It includes a memory controlling means including a data storage controller ( | 08-13-2009 |
| 20100088484 | SYNCHRONOUS FLASH MEMORY WITH STATUS BURST OUTPUT - A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification. | 04-08-2010 |
| 20100180096 | LICENSE DATA FOR CONTROLLING PARTIAL AVOIDANCE OR SIMULTANEOUS ACCESS TO MULTIMEDIA CONTENTS, AND APPARATUS AND METHOD FOR CONSUMING MULTIMEDIA CONTENTS USING THIS LICENSE DATA - Provided is a technology for controlling partial avoidance or simultaneous access to multimedia contents. This research provides a multimedia contents consuming apparatus, which includes: a receiver for receiving a multimedia content and license data representing a condition for prohibiting partial avoidance of the multimedia content; a license analyzer for receiving the license data from the receiver, analyzes the license condition for the multimedia content, and creating a control signal for partial avoidance; and a controller for controlling avoidance for a predetermined part of the multimedia content according to the control signal. | 07-15-2010 |
| 20100199057 | INDEPENDENT LINK AND BANK SELECTION - Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller. | 08-05-2010 |
| 20100223443 | MULTI-PROTOCOL ACCESS TO FILES AND DIRECTORIES - An operating system is provided. The system includes an agent component to monitor computer activities between one or more single-item access components and one or more set-based access components. A protocol component is employed by the agent component to mitigate data access between the single-item access components and the set-based access components. | 09-02-2010 |
| 20100228939 | Parallel Read Functional Unit for Microprocessors - A functional unit for a microprocessor is provided, which allows for fast, parallel data read, write, and manipulation operations in the microprocessor that are useful for a number of software applications, such as cryptography. The functional unit includes first and second source registers for receiving first and second data items to be processed by the functional unit, first and second banks of memory tables, a combinational logic circuit, and a decoder. The first and second banks of memory tables are in communication with the first source register, and each of the tables is indexed by an index comprising a portion of the first data item received by the first source register. Each index points to a lookup result in a respective one of the memory tables. The combinational logic circuit is in communication with the first and second banks of memory tables and the second source register, receives the lookup results, and processes the lookup results and the second data item in the second source register to produce a result data item. The decoder circuit is in communication with the combinational logic circuit, and extracts an operational code from an instruction supplied to the functional unit, decodes the operational code, and controls the combinational logic circuit in accordance with the operational code. | 09-09-2010 |
| 20110167238 | METHOD AND SYSTEM FOR CONTROLLING MEMORY ACCESSES TO MEMORY MODULES HAVING A MEMORY HUB ARCHITECTURE - A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules. | 07-07-2011 |
| 20110179245 | INDEPENDENT LINK AND BANK SELECTION - Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller. | 07-21-2011 |
| 20120124317 | CONCURRENT READ AND WRITE MEMORY OPERATIONS IN A SERIAL INTERFACE MEMORY - Subject matter disclosed herein relates to read and write processes of a memory device. | 05-17-2012 |
| 20130073827 | MEMORY MANAGEMENT UNIT (MMU) HAVING REGION DESCRIPTOR GLOBALIZATION CONTROLS AND METHOD OF OPERATION - Embodiments of computer processing systems and methods are provided that include a memory protection unit (MPU), and a plurality of region descriptors associated with the MPU. The region descriptors include address range and translation identifier values for a respective region of memory. Control logic determines whether a translation identifier control indicator is in a first state, and if the translation identifier control indicator is in the first state, the control logic allows a first process being executed by the processing system to access a memory region allocated to a second process being executed by the processing system. | 03-21-2013 |
| 20130086350 | METHOD AND SYSTEM FOR ENHANCED PERFORMANCE IN SERIAL PERIPHERAL INTERFACE - A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed. | 04-04-2013 |
| 20130132697 | THREE-STAGE MEMORY ARRANGEMENT - An electronic memory arrangement having at least three memory areas, a memory control unit, and a writing memory-accessing unit configured to carry out write access. A reading memory-accessing unit is configured to carry out read accesses. The memory control unit determines read and write access to the at least three memory areas, and the memory control unit is configured such that after the writing of a first data packet to one of the three memory areas, a following second data packet to be written is written to one on the three memory area to which read access does not place simultaneously during the write access of the second data packet. | 05-23-2013 |
| 20130219145 | Method and Apparatus for Ensuring Data Cache Coherency - A multithreaded processor can concurrently execute a plurality of threads in a processor core. The threads can access a shared main memory through a memory interface; the threads can generate read and write transactions that cause shared main memory access. An incoherency detection module prevents incoherency by maintaining a record of outstanding global writes, and detecting a conflicting global read. A barrier is sequenced with the conflicting global write. The conflicting global read is allowed to proceed after the sequence of the conflicting global write and the barrier are cleared. The sequence can be maintained by a separate queue for each thread of the plurality. | 08-22-2013 |
| 20130275710 | SCHEDULING OF I/O WRITES IN A STORAGE ENVIRONMENT - A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency. | 10-17-2013 |
| 20140089621 | INPUT/OUTPUT TRAFFIC BACKPRESSURE PREDICTION - According to one aspect of the present disclosure a system and technique for input/output traffic backpressure prediction is disclosed. The system includes a processor unit and logic executable by the processor unit to: determine, for each of a plurality of memory transactions, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determine a median value based on the determined traffic values; determine whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicate a prediction of a backpressure condition. | 03-27-2014 |
| 20140089622 | MEMORY LOCATION DETERMINING DEVICE, MEMORY LOCATION DETERMINING METHOD, DATA STRUCTURE, MEMORY, ACCESS DEVICE, AND MEMORY ACCESS METHOD - A memory location determining device determines memory locations for storing M pieces of compressed data each of which is compressed from one of M pieces of N-bit data. For each piece of compressed data, the memory location determining device performs a first arithmetic operation on an address value of a corresponding piece of N-bit data, and determines to store X bits of the piece of compressed data and a flag indicating whether or not the piece of compressed data exceeds X bits at a location indicated by the result value of the first arithmetic operation. When the piece of compressed data exceeds X bits, the memory location determining device further performs a second arithmetic operation on the address value of the corresponding piece of N-bit data and determines to store one or more bits of the piece of compressed data other than the X bits. | 03-27-2014 |
| 20140136808 | SCHEDULING OF I/O WRITES IN A STORAGE ENVIRONMENT - A system and method for effectively scheduling read and write operations among a plurality of solid-state storage devices. A computer system comprises client computers and data storage arrays coupled to one another via a network. A data storage array utilizes solid-state drives and Flash memory cells for data storage. A storage controller within a data storage array comprises an I/O scheduler. The data storage controller is configured to receive requests targeted to the data storage medium, said requests including a first type of operation and a second type of operation. The controller is further configured to schedule requests of the first type for immediate processing by said plurality of storage devices, and queue requests of the second type for later processing by the plurality of storage devices. Operations of the first type may correspond to operations with an expected relatively low latency, and operations of the second type may correspond to operations with an expected relatively high latency. | 05-15-2014 |
| 20140195765 | IMPLEMENTING USER MODE FOREIGN DEVICE ATTACHMENT TO MEMORY CHANNEL - A method, system and computer program product are provided for implementing attachment of a user mode foreign device to a memory channel in a computer system. A user mode foreign device is attached to the memory channel using memory mapping of device registers and device buffers to the processor address space. The storage capacity on the device is doubly mapped in the address space creating separate control and data address spaces to allow user mode processes to control the device therefore eliminating the need for software system calls. A processor Memory Management Unit (MMU) coordinates multiple user processes accessing the device registers and buffers providing address space protection of each of interfaces, shifting device protection to the processor MMU from system software. | 07-10-2014 |
| 20140310496 | Parallel Memories for Multidimensional Data Access - The subject disclosure is directed towards loading parallel memories (e.g., in one or more FPGAs) with multidimensional data in an interleaved manner such that a multidimensional patch/window may be filled with corresponding data in a single parallel read of the memories. Depending on the position of the patch, the data may be rotated horizontally and/or vertically, for example, so that the data in each patch is consistently arranged in the patch regardless of from which memory each piece of data was read. Also described is leveraging dual ported memory for multiple line reads and/or loading one part of a buffer while reading from another. | 10-16-2014 |
| 20140344545 | PARALLEL ATOMIC INCREMENT - Certain example embodiments of the present disclosure can provide a parallelized atomic increment. A vgather instruction returns to a plurality of processing elements the value of a memory location. A vgather_hit instruction returns to a function of the number of “hits” to the memory location. In one embodiment, the function is unity. In another embodiment, the function is the number of hits having an ordinal designation less than or equal to the processing element receiving the return value. | 11-20-2014 |
| 20140344546 | Memory Controller For Micro-Threaded Memory Operations - A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval. | 11-20-2014 |
| 20140365744 | Programmable Latency Count to Achieve Higher Memory Bandwidth - Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device. | 12-11-2014 |
| 20150095606 | SYSTEM AND METHOD FOR PREDICTING MEMORY PERFORMANCE - A method, computer program product, and computing system for defining an optimal execution time (t) for a concurrent memory operation to be performed on a transactional memory system. An abort probability (p) is associated with the optimal execution time (t) based, at least in part, upon a probability curve. The probability curve is empirically derived and based upon the performance of the transactional memory system. A probable execution time (T | 04-02-2015 |
| 20150113244 | CONCURRENTLY ACCESSING MEMORY - When a first transaction needs to conduct a writing operation to first data, after there is a determination that there exists a second transaction that has conducted a reading operation of the first data or is to conduct a reading operation of the first data, a record that indicates a conflict between the writing operation of the first transaction and the reading operation of the second transaction is generated. A processing of the second transaction is performed. After the processing is completed, the second transaction is submitted and the first transaction is notified according to the record. A processing of the first transaction is performed. After the processing is completed and a notification of the second transaction is received, the first transaction is submitted. The present techniques improve concurrently visiting transaction memory at a multi-core system, avoid rollbacks incurred by conflicts, and improve overall system performance. | 04-23-2015 |
| 20150347055 | System and Method for Parallelized Performance Data Collection in a Computing System - A system and method for of prioritizing accumulation of time-dependent data is disclosed. In an embodiment, a plurality of data elements are identified to be retrieved. The data elements include a high-priority data element and a low-priority data element. A first data retrieval operation is performed to retrieve the high-priority data element, to store a copy of the high-priority data element in a memory structure, and to reserve a memory space in the memory structure for the low-priority data element based on the low-priority data element corresponding to the high-priority data element. In parallel with the first data retrieval operation, a second data retrieval operation is performed to analyze the memory structure to detect the reserved memory space, upon detecting the reserved memory space, to retrieve the low-priority data element, and to store a copy of the low-priority data element in the reserved memory space. | 12-03-2015 |
| 20160117258 | SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY - A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component. | 04-28-2016 |
| 20160162401 | ALIGNMENT BASED BLOCK CONCURRENCY FOR ACCESSING MEMORY - Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory reference instruction for accessing data of a first size at an address in the memory. The method determines an alignment size of the address in the memory. The method accesses the data of the first size in one or more groups of data by accessing each group of data block concurrently. The groups of data have sizes that are multiples of the alignment size. | 06-09-2016 |
| 20160205079 | User Authentication System and Method for Encryption and Decryption | 07-14-2016 |
