| Entries |
| Document | Title | Date |
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| 20080209151 | Storage device and control method of the storage device - A storage device includes a storage medium, a nonvolatile memory, a head, a driving unit, and a processor. The driving unit drives the storage medium. The processor controls the storage device according to a process. The process includes receiving the data transmitted from the host, storing the data received into the nonvolatile memory, estimating a period of time from a time point of the reception of the data to a time point at which a usage rate of the nonvolatile memory becomes 100%, controlling the driving unit on the basis of comparison of the estimated period of time with a period of time before the storage medium is accessible, and writing the data stored in the nonvolatile memory to the storage medium by controlling the head in accordance with the control of the driving unit. | 08-28-2008 |
| 20080215842 | DISTANCE-PRESERVING ANONYMIZATION OF DATA - An embodiment includes a system with a processing unit and a communication unit. The processing unit is configured: to compute a first reference point of a data point that represents a private data item and has a first distance value to the data point, wherein the first distance value is less than a threshold value, to compute a second reference point of the data point different from the first reference point with a second distance value to the data point, wherein the second distance value is less than the threshold value, and to generate hidden reference points from the reference points. The communication unit is configured to send the hidden reference points and distance values to a system. | 09-04-2008 |
| 20080222378 | MEMORY MODULE AND MEMORY MODULE SYSTEM - A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed. | 09-11-2008 |
| 20080222379 | System and method for memory hub-based expansion bus - A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit. | 09-11-2008 |
| 20080235480 | Systems for storing memory operations in a queue - A non-volatile memory storage system is provided. The non-volatile memory storage system is configured to store a queue. Here, the queue is configured to store memory operations associated with two or more types of memory operations. The memory operations are associated with maintenance of the non-volatile memory storage system. The non-volatile memory storage system further comprises a processor in communication with the non-volatile memory cell array. The processor is configured to schedule a memory operation for execution in response to an event and store the memory operation in the queue. | 09-25-2008 |
| 20080263302 | Non-volatile memory circuit, system, and method - A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command. | 10-23-2008 |
| 20080294862 | ARBITRATION SYSTEM HAVING A PACKET MEMORY AND METHOD FOR MEMORY RESPONSES IN A HUB-BASED MEMORY SYSTEM - A memory hub module includes a decoder that receives memory requests determines a memory request identifier associated with each memory request. A packet memory receives memory request identifiers and stores the memory request identifiers. A packet tracker receives remote memory responses and associates each remote memory response with a memory request identifier and removes the memory request identifier from the packet memory. A multiplexor receives remote memory responses and local memory responses. The multiplexor selects an output responsive to a control signal. Arbitration control logic is coupled to the multiplexor and the packet memory and develops the control signal to select a memory response for output. | 11-27-2008 |
| 20080301391 | METHOD AND APPARATUS FOR MODIFYING A BURST LENGTH FOR SEMICONDUCTOR MEMORY - A method and apparatus for performing a burst access operation for a memory device. The method includes receiving a burst access command for the burst access operation and receiving a burst length modifying value for the burst access operation. A modified burst length is generated from a pre-programmed burst length using the burst length modifying value. The modified burst length is used for the burst access operation without changing the pre-programmed burst length. The burst access operation is performed with the modified burst length. | 12-04-2008 |
| 20080307183 | AUTOMATIC MEMORY MANAGEMENT (AMM) - The present invention manages the execution of multiple AMM cycles to reduce or eliminate any overlap. Specifically, the present invention provides an external supervisory process to monitor the AMM behavior of VMs on one or more nodes, and intervene when coincident AMM activity appears to be imminent. If AMM patterns suggest that two VMs are likely to perform a (e.g., a major) AMM cycle simultaneously (or with significant overlap) in the near future, the supervisory process can trigger one of the VMs to AMM immediately, or at the first ‘safe’ interval prior to the predicted AMM collision. This will have the effect of desynchronizing the AMM behavior of the VMs and maintaining AMM latency for both VMs within the expected bounds for their independent operation, without any inter-VM effects. | 12-11-2008 |
| 20080307184 | MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK - The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access. | 12-11-2008 |
| 20080307185 | APPARATUS AND METHOD TO SET SIGNAL COMPENSATION SETTINGS FOR A DATA STORAGE DEVICE - A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length. | 12-11-2008 |
| 20080320265 | SYSTEM FOR PROVIDING A SLOW COMMAND DECODE OVER AN UNTRAINED HIGH-SPEED INTERFACE - A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates slow commands and transmits the slow commands to the memory interface device via the untrained high-speed interface. The slow commands operate at a first data rate that is slower than a second data rate utilized by the high-speed interface after it has been trained. The memory interface device receives the slow commands via the untrained high-speed interface, decodes the slow commands, and executes the slow commands. | 12-25-2008 |
| 20090006798 | Structure for Memory Chip for High Capacity Memory Subsystem Supporting Replication of Command Data - A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining | 01-01-2009 |
| 20090013143 | SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing. | 01-08-2009 |
| 20090024816 | Non-Linear Stochastic Processing Storage Device - A storage device includes an interface for receiving and outputting messages for processing data units, wherein each data unit includes message input field parameters, message output field parameters, and content field parameters, a non-volatile memory for storing data units, a volatile memory, and a processor coupled to the interface, the non-volatile memory and the volatile memory, for manipulation of the parameter values in the data units, and storing the data units in at least one of the non-volatile memory and the volatile memory. | 01-22-2009 |
| 20090037683 | Semiconductor Memory Arrangement - A semiconductor memory arrangement includes a substrate, a first control device disposed on the substrate and adapted to receive command and address signals, a second control device, and a plurality of memory units. The second control device is adapted to receive the command and address signals from the first control device and to transmit the command and address signals to the memory units of the plurality of memory units. | 02-05-2009 |
| 20090043981 | MEMORY CONTROL CIRCUIT CAPABLE OF DYNAMICALLY ADJUSTING DEGLITCH WINDOWS, AND RELATED METHOD - A memory control method for adjusting deglitch windows utilized by a memory control circuit receiving an original data strobe signal of a memory includes: deglitching according to the original data strobe signal by utilizing a plurality of deglitch windows that are set by delaying an original deglitch window signal in order to derive a plurality of deglitch results, where the deglitch windows have different beginning time points; and utilizing the deglitch results to dynamically determine a delay amount for delaying the original deglitch window signal, where the beginning time point of one of the deglitch windows is kept centered at a middle time point of a preamble of the original data strobe signal. | 02-12-2009 |
| 20090055614 | Information processing program and information processing apparatus - A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a first memory writing processing to write a first command element having a specific attitude out of the command elements corresponding to the accepted operation in a first memory and a second memory writing processing to write a second command element having an attitude different from the attitude in a second memory, determines whether or not a command element array stored over the first memory and the second memory satisfies an execution allowable condition every execution of the writing processing, and processes information according to the command element array when the satisfaction is determined. | 02-26-2009 |
| 20090089530 | APPARATUS AND METHOD FOR ACCESSING A SYNCHRONOUS SERIAL MEMORY HAVING UNKNOWN ADDRESS BIT FIELD SIZE - An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set to a first predetermined logic state in response to a read command being provided to the serial memory. The data out control circuit has an output terminal for providing the read command and a first predetermined number of address bits to the output terminal. The transition detector is coupled to an input terminal for detecting if the input terminal transitions from the first predetermined logic state to a second predetermined logic state in response to the first predetermined number of address bits. The transition detector will detect a transition of the input terminal when a correct number of address bits have been provided. | 04-02-2009 |
| 20090094432 | MEMORY ACCESS CONTROL DEVICE, COMMAND ISSUING DEVICE, AND METHOD - A memory access control device for controlling access to a plurality of memory devices with differing latency, controls, when performing a first access and then a second access, the timing of performing the second access, according to a memory device accessed in the first access and a memory device accessed in the second access. | 04-09-2009 |
| 20090106519 | Storage Device and Method of Accessing a Status Thereof - A storage device and a method of accessing a status thereof are provided. The storage device is disposed in a host. The device data structure field of the storage device is adapted to record the status of the non-volatile memory. The control module is adapted to access the status according to a control signal from the host. Therefore, the operating system or the application of the host is capable of getting the status of the non-volatile memory to ensure the safety of the stored data. | 04-23-2009 |
| 20090106520 | DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY - A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made. The timing circuit varies the position of the acceptance time points within the validity duration intervals, so that the position is delayed to make room for previously accepting an access request from another processor. The position is subsequently moved back toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit. | 04-23-2009 |
| 20090113158 | METHOD AND APPARATUS FOR SYNCHRONIZING MEMORY ENABLED SYSTEMS WITH MASTER-SLAVE ARCHITECTURE - Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew. | 04-30-2009 |
| 20090113159 | Data processing with time-based memory access - Memory access in data processing is provided using a time-based technique in which memory locations are mapped to respectively corresponding periods of time during which they are made available for access. | 04-30-2009 |
| 20090119470 | Probabilistic Method for Performing Memory Prefetching - A method for preforming memory prefetching is disclosed. A stream length histogram (SLH) is initially generated based on a stream of Read and Write requests intended for a system memory. A determination is then made whether or not to issue a prefetch command after a Read request based on information within the generated SLH. In a determination that a prefetch command should be issued, prefetch command to be sent to the system memory is issued along with other commands. | 05-07-2009 |
| 20090119471 | Priority-Based Memory Prefetcher - A method for preforming memory prefetching and scheduling prefetch commands inside the memory controller is disclosed. A set of prefetch commands is generated based on a stream of Read requests intended for a system memory, and the prefetch commands are stored in a low priority queue (LPQ). A set of regular commands is generated based on a stream of Read and Write requests intended for the system memory, and the regular commands are stored in a centralized arbiter queue. One of the prefetch commands is issued from the LPQ depending on the status of the other queues in the memory controller. | 05-07-2009 |
| 20090119472 | CONTROL CIRCUIT IN A MEMORY CHIP - Embodiments of the invention relate to a control circuit comprising a clock signal connection for receiving a system clock signal, a write signal connection for receiving a write signal, and a write control circuit for executing write commands, wherein the write control circuit is designed to start executing a write command when a write signal is applied to the write signal connection during an edge of the system clock signal. | 05-07-2009 |
| 20090132778 | SYSTEM, METHOD AND A COMPUTER PROGRAM PRODUCT FOR WRITING DATA TO DIFFERENT STORAGE DEVICES BASED ON WRITE FREQUENCY - A system, method, and computer program product are provided for writing data to different storage devices based on write frequency. In operation, a frequency in which data is written is identified. Additionally, a plurality of storage devices of different types is selected from to write the data, based on the frequency. | 05-21-2009 |
| 20090132779 | STORAGE SYSTEM AND REMOTE COPY CONTROL METHOD - A plurality of second groups respectively including one or more second volumes are configured in correspondence with each of the first groups of a remote copy source in a remote copy destination, journals are acquired from the first storage apparatus periodically and in the order the journals were created for each of the configured second groups, and the acquired journals are reflected in the corresponding second volume in the corresponding second group. In addition, the latest time stamp of each of the second groups containing the journals retained in the second volume in an unreflected state is compared, the time difference of the latest and oldest time stamps is detected, and prescribed control processing is executed for acquiring the journals regarding the second group with the oldest time stamp in preference to the journals regarding other second groups when the time difference exceeds a preset threshold value. | 05-21-2009 |
| 20090138670 | SOFTWARE-CONFIGURABLE AND STALL-TIME FAIR MEMORY ACCESS SCHEDULING MECHANISM FOR SHARED MEMORY SYSTEMS - Systems and methodologies for stall-time fair memory access scheduling for shared memory systems are provided herein. A stall-time fairness policy can be applied in accordance with various aspects described herein to schedule memory requests from threads sharing a memory system. To this end, a Stall-Time Fair Memory scheduler (STFM) algorithm can be utilized, wherein memory-related slowdown experienced by a group of threads due to interference from other threads is equalized. Additionally and/or alternatively, a traditional scheduling policy such as first-ready first-come-first-serve (FR-FCFS) can be utilized in combination with a cap on column-over-row reordering of memory requests, thereby reducing the amount of stall-time unfairness imposed by such traditional scheduling policies. Further, various aspects described herein can perform memory scheduling based on thread weights and/or other parameters, which can be configured in hardware and/or software. | 05-28-2009 |
| 20090144517 | DATA PROCESSING APPARATUS AND DATA PROCESSING SYSTEM - Decrease in throughput performance called a “jamming” in a memory device is prevented. There is provided a timing generation part which gives, based on a request signal outputted for each unit of the data processing from a data processing part, an output timing for a burst transfer request to a burst transfer request generation part. Based on the relationship in size between a lapsed time from the output of the burst transfer request to the activation of the request signal and a time specified by a set threshold value of a threshold value register, the timing generation part controls output timing for a burst transfer request. When the lapsed time exceeds the time specified by a maximum threshold value, the burst transfer request generation part is given an output timing for the burst transfer request without waiting for the activation of the request signal. As a result, when the issuance of the request signal is delayed, a next burst transfer request can be given to the memory device without waiting for the issuance but preceding it. | 06-04-2009 |
| 20090150635 | COMMAND CONTROL FOR SYNCHRONOUS MEMORY DEVICE - Systems, methods, and circuits for command control for synchronous memory device are disclosed. In one embodiment, a memory device comprises a first synchronous memory controlled by a second group of commands which includes a first command receiving section for receiving a first group of commands, and a second command receiving section for receiving a command that is unique to the first synchronous memory and different from the first group of commands during execution of the first group of commands received by the first command receiving section. The synchronous memory further comprises a second synchronous memory controlled by the first group of commands, where the first synchronous memory and the second synchronous memory are coupled to a same data bus, and where the second group of commands is different from the first group of commands. | 06-11-2009 |
| 20090150636 | MEMORY SUBSYSTEM WITH POSITIONAL READ DATA LATENCY - A memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or more memory busses is provided. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected via the memory busses. | 06-11-2009 |
| 20090157992 | Docbase management system and implementing method thereof - The present invention discloses a docbase management system, including a first module, adapted to parse a received invocation from an application and generate an execution plan which comprises operations on physical storage; a second module, adapted to execute the execution plan to schedule a third module to execute the operations on physical storage in the execution plan; and the third module, adapted to execute the operations on physical storage in the execution plan under the scheduling of the second module. Since the implementation of the docbase management system is divided into hierarchies, and the hierarchies are independent of each other, the docbase management system is well extendable, scalable and maintainable. | 06-18-2009 |
| 20090157993 | MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITY - A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity. | 06-18-2009 |
| 20090172334 | Data sorting device and method thereof - A data sorting device and a method thereof are disclosed, wherein the data sorting device includes plural storage modules and an enabling controller. Moreover, each storage module has a falling edge-triggered register and a rising edge-triggered register, and each storage module receives a serial data in response to the rising edge of clock and the falling edge of clock. Furthermore, the enabling controller is connected with each storage module for enabling each storage module by sequence turns in response to the trigger of the rising edge of clock. | 07-02-2009 |
| 20090198941 | Computer system with addressable storage medium - A computer system with an addressable medium is disclosed. The computer system comprises an addressable medium subsystem, a microprocessor and at least one input/output device. The addressable medium subsystem includes: a control logic which has a control circuit with an address table for storing a plurality of addresses, and an access logic with a storage medium layer and an electromagnetic induction circuit. The electromagnetic induction circuit includes a plurality of coils and a plurality of rods. Each rod is surrounded by one of the coils and corresponds to one of a plurality of regions on the storage medium layer. The access logic controls the coils to access the data stored on the regions for the control logic. Each region corresponds to one of the addresses on the address table. The microprocessor and the input/output device electrically couple with the control logic. Both the microprocessor accesses instructions for executing and the input/output device accesses data via the control logic. | 08-06-2009 |
| 20090222637 | ON-DIE TERMINATION CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - On-die termination control circuit of semiconductor memory device includes a counter configured to count an external clock to output a first code, and to count an internal clock to output a second code, a transfer controller configured to determine whether to transfer the first code and the second code in response to a first termination command and a normal termination controller configured to compare the first code and the second code with each other to determine enabling/disabling timings of a termination operation in response to a second termination command. | 09-03-2009 |
| 20090276597 | MEMORY CONTROLLER-ADAPTIVE 1T/2T TIMING CONTROL - Circuits, methods, and apparatus that adaptively control 1T and 2T timing for a memory controller interface. An embodiment of the present invention provides a first memory interface as well as an additional memory interface, each having a number of address and control lines. The address and control lines of the redundant memory interface may be individually enabled and disabled. If a line in the additional interface is enabled, it and its corresponding line in the first interface drive a reduced load and may operate at the higher 1T data rate. If a line in the additional interface is disabled, then its corresponding line in the first interface drives a higher load and may operate at the slower 2T data rate. In either case, the operating speed of the interface may also be considered in determining whether each line operates with 1T or 2T timing. | 11-05-2009 |
| 20090287897 | CONTROL OF ACCESS TO AN EXTERNAL STORAGE DEVICE - The control device has a fetching unit, a virtual drive creation unit, and an access control unit. The fetching unit fetches, from the external storage device, attribute information relating to data stored in the external storage device. The virtual drive creation unit creates, in the control device, a virtual drive for storing the fetched attribute information. The access control unit controls access to the virtual drive and the external storage device. When an instruction relating to the attribute information is input, the access control unit accesses the virtual drive to fetch the attribute information. When an instruction to read the data from the external storage device is input, the access control unit accesses the external storage device to reads the data. When an instruction to write new data to the external storage device is input, the access control unit accesses the external storage device to write the new data. | 11-19-2009 |
| 20090300314 | MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA - Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface. | 12-03-2009 |
| 20090319744 | Digital Television, Memory Controller, and Method for Controlling Access of a Memory Device - A digital television, a memory controller and a method for controlling access of a memory device are provided. The digital television comprises the memory device and the memory controller. The memory controller comprises a storage buffer and a clock adjustment device. The storage buffer buffers a data read from the memory device according to a reference clock source. The clock adjustment device provides the reference clock source and determines whether to adjust the reference clock source in response to the data. The method comprises steps of: providing a reference clock source; buffering a data read from the memory device according to the reference clock source; and determining whether to adjust the reference clock source in response to the data. | 12-24-2009 |
| 20090319745 | SYSTEM AND METHOD FOR AN ASYNCHRONOUS DATA BUFFER HAVING BUFFER WRITE AND READ POINTERS - A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made. | 12-24-2009 |
| 20100011182 | Techniques For Scheduling Requests For Accessing Storage Devices Using Sliding Windows - A system includes a storage device and a scheduler. The scheduler determines if deadlines of requests for accessing the storage device fall within first and second sliding windows. The scheduler issues requests that are in the first sliding window in a first order of execution and requests that are in the second sliding window in a second order of execution. | 01-14-2010 |
| 20100030993 | Memory Access Control Device, Memory Access Control Method, Data Storage Method and Memory Access Control Program - An access control device which increases memory access efficiency to data stored in a memory according to the present invention comprises a plurality of groups of the memory, divides and stores the data in different memory areas of the plurality of groups of the memory distinguished based on the predetermined bits of an access address to the plurality of groups of the memory, and accesses the data stored in the different memory areas of the plurality of groups of the memory simultaneously in the same clock cycle of access to the memory. | 02-04-2010 |
| 20100058018 | Memory Scheduler for Managing Internal Memory Operations - An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller. | 03-04-2010 |
| 20100070730 | MINIMIZING MEMORY ACCESS CONFLICTS OF PROCESS COMMUNICATION CHANNELS - A system and method for minimizing cache conflicts and synchronization support for generated parallel tasks within a compiler framework. A compiler comprises library functions to generate a queue for parallel applications and divides it into windows. A window may be sized to fit within a first-level cache of a processor. Application code with producer and consumer patterns within a loop construct has these patterns split into producer and consumer tasks. Within a producer task loop, a function call is placed for a push operation that modifies a memory location within a producer sliding window without a check for concurrent accesses. A consumer task loop has a similar function call. At the time a producer or consumer task is ready to move, or slide, to an adjacent window, its corresponding function call determines if the adjacent window is available. | 03-18-2010 |
| 20100088483 | DETECTION CIRCUIT FOR MIXED ASYNCHRONOUS AND SYNCHRONOUS MEMORY OPERATION - A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation. | 04-08-2010 |
| 20100122059 | Memory Command Delay Balancing In A Daisy-Chained Memory Topology - A methodology for a daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. With such ability to predict command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM may also be programmed to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response thereat, and, hence, to better manage further processing of the response. | 05-13-2010 |
| 20100138625 | RECORDING MEDIUM STORING UPDATE PROCESSING PROGRAM FOR STORAGE SYSTEM, UPDATE PROCESSING METHOD, AND STORAGE SYSTEM - A reading and writing control unit has a synchronous mode for directly writing write data in storage devices and an asynchronous mode for accumulating the write data in a cache memory and writing the accumulated write data in the storage devices. A synchronization and asynchronization instructing unit instructs whether the data writing is to be performed in the synchronous mode and the asynchronous mode. A process control unit switches the reading and writing control unit, which is set in the asynchronous mode, to the synchronous mode. The process control unit issues an end instruction to cause the process to end service processing in a state in which the write data output by the process is directly written in the storage device. The process control unit starts service processing of the new process after the process ends the service processing and notifies an end result when the processing ends. | 06-03-2010 |
| 20100146237 | MEMORY DEVICE, MEMORY SYSTEM, AND ACCESS TIMING ADJUSTING METHOD IN MEMORY SYSTEM - A memory device ( | 06-10-2010 |
| 20100169603 | METHOD OF PROVIDING TO A PROCESSOR AN ESTIMATED COMPLETION TIME OF A STORAGE OPERATION - A method of performing a storage operation includes: receiving a storage command, estimating the completion time of the associated storage operation, and providing the estimated completion time to a processor. | 07-01-2010 |
| 20100268906 | HIGH BANDWIDTH MEMORY INTERFACE - This invention describes an improved high bandwidth chip-to-chip interface for memory devices, which is capable of operating at higher speeds, while maintaining error free data transmission, consuming lower power, and supporting more load. Accordingly, the invention provides a memory subsystem comprising at least two semiconductor devices; a main bus containing a plurality of bus lines for carrying substantially all data and command information needed by the devices, the semiconductor devices including at least one memory device connected in parallel to the bus; the bus lines including respective row command lines and column command lines; a clock generator for coupling to a clock line, the devices including clock inputs for coupling to the clock line; and the devices including programmable delay elements coupled to the clock inputs to delay the clock edges for setting an input data sampling time of the memory device. | 10-21-2010 |
| 20100281231 | HIERARCHICAL MEMORY ARBITRATION TECHNIQUE FOR DISPARATE SOURCES - A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream. | 11-04-2010 |
| 20100293352 | SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device proposed in the present invention comprises the buffer control circuit which, when writing the data, controls the data input buffer so that the data from the same timing as the clock when the writing command is input is written in the activated memory bank, and which, when reading the data, controls the data output buffer so that the data with the read latency of more than 3 clock cycles after when the reading command is input is read from the activated memory bank. | 11-18-2010 |
| 20100306493 | SYSTEM, METHOD, AND COMPUTER-READABLE MEDIUM FOR OPTIMIZED DATA STORAGE AND MIGRATION IN A DATABASE SYSTEM - A system, method, and computer-readable medium that facilitate optimized data storage and migration are provided. Storage device zones are tested and assigned respective speed quality ratings. The frequency with which data is accessed within the system may be periodically monitored and a corresponding access frequency quantifier assigned to the data is updated accordingly. The data access frequency quantifier may be associated with a storage device zone speed quality rating. The association between data access frequency quantifiers and the storage device zone speed quality ratings may be made in a hierarchical association such that quantifiable differentials may be ascertained between a particular access frequency quantifier and a storage device zone speed quality rating. In this manner, when no storage zone having a speed quality rating that is associated with data having a particular access frequency quantifier is available for storage of the data, a storage zone having a speed quality rating more proximate the speed quality rating associated with the access frequency quantifier may be identified for migration of the data for storage thereby. | 12-02-2010 |
| 20100325380 | PORT PACKET QUEUING - A port queue includes a first memory portion having a first memory access time and a second memory portion having a second memory access time. The first memory portion includes a cache row. The cache row includes a plurality of queue entries. A packet pointer is enqueued in the port queue by writing the packet pointer in a queue entry in the cache row in the first memory. The cache row is transferred to a packet vector in the second memory. A packet pointer is dequeued from the port queue by reading a queue entry from the packet vector stored in the second memory. | 12-23-2010 |
| 20110016282 | SYNCHRONOUS MEMORY READ DATA CAPTURE - A method of snap-shot data training to determine the optimum timing of the DQS enable signal in a single read operation is provided. This is accomplished by first writing a Gray code count sequence into the memory and then reading it back in a single burst. The controller samples the read burst at a fixed interval from the time the command was issued to determine the loop-around delay. A simple truth table lookup determines the optimum DQS enable timing for normal reads. Advantageously, during normal read operations, the first positive edge of the enabled DQS signal is used to sample a counter that is enabled every time a command is issued. If the counter sample changes, indicating timing drift has occurred, the DQS enable signal can be adjusted to compensate for the drift and maintain a position centered in the DQS preamble. This technique can also be applied to a system that uses the iterative approach to determining DQS enable timing on power up. Another embodiment of the invention is a simple, low latency clock domain crossing circuit based on the DQS latched sample of the counter. | 01-20-2011 |
| 20110035564 | TECHNIQUE TO PERFORM MEMORY DISAMBIGUATION - A memory access management technique. More particularly, at least one embodiment of the invention relates to a technique to issue loads to a memory ahead of older store operations corresponding to the same target address. | 02-10-2011 |
| 20110055509 | CONTROL COMPONENT FOR CONTROLLING A DELAY INTERVAL WITHIN A MEMORY COMPONENT - Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device. | 03-03-2011 |
| 20110087853 | Storage Device, Substrate, Liquid Container, System and Control Method of Storage Device - A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that outputs a clock for access control for performing access control of a read/write of the nonvolatile storage section, and performs access control of the read/write to the nonvolatile storage section, and a masking process section that performs the masking process of a reset signal on the basis of the clock for access control from the access control section, and supplies the reset signal after the masking process to the access control section. | 04-14-2011 |
| 20110138145 | PARALLEL NESTED TRANSACTIONS IN TRANSACTIONAL MEMORY - Various technologies and techniques are disclosed for supporting parallel nested transactions in a transactional memory system. Multiple closed nested transactions are created for a single parent transaction, and the closed nested transactions are executed concurrently as parallel nested transactions. Various techniques are used to ensure effects of the parallel nested transactions are hidden from other transactions outside the parent transaction until the parent transaction commits. For example, versioned write locks are used with parallel nested transactions. When a transactional memory word changes from a write lock to a versioned write lock, an entry is made in a global versioned write lock map to store a pointer to a write log entry that the versioned write lock replaced. When the versioned write lock is encountered during transaction processing, the global versioned write lock map is consulted to translate the versioned write lock to the pointer to the write log entry. | 06-09-2011 |
| 20110153974 | SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE - A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller. | 06-23-2011 |
| 20110167237 | MULTI-BANK MEMORY ACCESSES USING POSTED WRITES - Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access. | 07-07-2011 |
| 20110185145 | SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a semiconductor storage device comprises nonvolatile memories, memory controllers connected to the nonvolatile memories, and an arbitration module. The arbitration module is configured to control a timing of permitting one of operations of program, erase, and read of the memory controllers. | 07-28-2011 |
| 20110191564 | Hierarchical Organization Of Large Memory Blocks - A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency. | 08-04-2011 |
| 20110208939 | MEMORY ACCESS SYSTEM AND MEMORY ACCESS CONTROL METHOD - The memory access system includes first to fourth memories and a memory controller. The memory controller accesses blocks in a first block group respectively stored in the first and second memories by supplying the first and second unique addresses different from each other at a first timing of activating a first chip select signal, and accesses blocks in a second block group respectively stored in the third and fourth memories by supplying the first and second unique addresses different from each other at a second timing of activating a second chip select signal. | 08-25-2011 |
| 20110213944 | SYNCHRONIZATION SYSTEM AND RELATED INTEGRATED CIRCUIT - A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency. | 09-01-2011 |
| 20110302385 | MEMORY DEVICE SYNCHRONIZATION - A memory controller includes first and second output modules for driving first and second data, respectively, to be written to a memory device. The memory controller also includes a clock module for providing an internal clock signal and a timing control module for producing a first and second timing control signals. The first and second timing control signals are supplied to the first and second output modules, respectively. | 12-08-2011 |
| 20120036335 | Timing control circuit - A timing control circuit comprises at least three current control units coupled in parallel between a first circuit and a second circuit node. The current control units each have an active mode and an inactive mode. The current control units are responsive to a timing trigger event to pass current whose magnitude is dependent on how many of the current control units are in the active mode. The current control units comprise a plurality of groups. Current control units within a same group are responsive to a change in a bit of a control value corresponding to that group to switch together between the active and inactive modes, such that the magnitude of the current is dependent on which of the groups are in the active mode. The signal timing in the associated circuit is varied in dependence on the magnitude of the current. | 02-09-2012 |
| 20120079228 | DIGITAL COUNTER SEGMENTED INTO SHORT AND LONG ACCESS TIME MEMORY - A method performed in a memory controller for maintaining segmented counters split into primary and secondary memories, the primary memory faster. Events occur that require incrementing one of the segmented counters and the memory controller responds by incrementing a corresponding primary part in the primary memory. Each time a primary part is rolling over the memory controller determines that a secondary part should be updated. Also, the memory controller periodically determines that the secondary part of a segmented counter should be opportunistically updated. The opportunistic update is based on a probability function and a random number. The secondary part includes at least all of bits of the segmented counter not in the primary part and is stored in the secondary memory. Each time an update to the secondary part occurs, both the secondary part and primary part of the segmented counter must be updated. | 03-29-2012 |
| 20120102287 | ORDERING A PLURALITY OF WRITE COMMANDS ASSOCIATED WITH A STORAGE DEVICE - A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being START known by the device. Further, the plurality of write commands are ordered in the determined order. | 04-26-2012 |
| 20120117352 | Docbase management system and implementing method thereof - The present invention discloses a docbase management system, including a first module, adapted to parse a received invocation from an application and generate an execution plan which comprises operations on physical storage; a second module, adapted to execute the execution plan to schedule a third module to execute the operations on physical storage in the execution plan; and the third module, adapted to execute the operations on physical storage in the execution plan under the scheduling of the second module. Since the implementation of the docbase management system is divided into hierarchies, and the hierarchies are independent of each other, the docbase management system is well extendable, scalable and maintainable. | 05-10-2012 |
| 20120151171 | PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY - A memory system, having indeterminate read data latency, that includes a memory controller and one or more hub devices. The memory controller is configured for receiving data transfers via an upstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting a frame start indicator. The data frame includes an identification tag that is utilized by the memory controller to associate the data frame with a corresponding read instruction issued by the memory controller. The one or more hub devices are in communication with the memory controller in a cascade interconnect manner via the upstream channel and a downstream channel. Each hub device is configured for receiving the data transfers via the upstream channel or the downstream channel and for determining whether all or a subset of the data transfers include a data frame by detecting the frame start indicator. | 06-14-2012 |
| 20120151172 | PROVIDING FRAME START INDICATION IN A MEMORY SYSTEM HAVING INDETERMINATE READ DATA LATENCY - A method for providing frame start indication that includes receiving a data transfer via a channel in a memory system. The receiving is in response to a request, and at an indeterminate time relative to the request. It is determined whether the data transfer includes a frame start indicator. The data transfer and “n” subsequent data transfers are captured in response to determining that the data transfer includes a frame start indicator. The data transfer and the “n” subsequent data transfers make up a data frame, where “n” is greater than zero. | 06-14-2012 |
| 20120173836 | Dynamic Frequency Memory Control - A memory controller ( | 07-05-2012 |
| 20120185663 | Memory Interface Converter - A digital system is provided with a memory interface converter to couple a memory device that understands a type of command protocol to a memory controller that generates a different type of command protocol. The memory interface converter includes a first memory interface configured to couple to a host controller memory interface having a first signal protocol and a second memory interface configured to couple to one or more memory devices having a different second signal protocol. A decoder is configured to decode commands received on a command input port and to convert the received commands into commands for a command output port. A state machine is configured to emulate memory states according to the first signal protocol, and another state machine is configured to emulate memory controller states according to the second signal protocol. | 07-19-2012 |
| 20120185664 | Synchronous Global Controller for Enhanced Pipelining - The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse | 07-19-2012 |
| 20120198194 | Multi-Bank Memory Accesses Using Posted Writes - Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data of write accesses, reducing delays between successive write and read accesses. Memory devices that interface with these computer circuits use posted write accesses to effectively return the modified relative timing to its original timing before processing the write access. | 08-02-2012 |
| 20120210089 | MEMORY COMMAND DELAY BALANCING IN A DAISY-CHAINED MEMORY TOPOLOGY - A daisy-chained memory topology wherein, in addition to the prediction of the timing of receipt of a response from a memory module (DIMM), the memory controller can effectively predict when a command sent by it will be executed by the addressee DIMM. By programming DIMM-specific command delay in the DIMM's command delay unit, the command delay balancing methodology according to the present disclosure “normalizes” or “synchronizes” the execution of the command signal across all DIMMs in the memory channel. By predicting command execution timing, the memory controller can efficiently control power profile of all the DRAM devices (or memory modules) on a daisy-chained memory channel. A separate DIMM-specific response delay unit in the DIMM is programmeable to provide DIMM-specific delay compensation in the response path, further allowing the memory controller to accurately ascertain the timing of receipt of a response. | 08-16-2012 |
| 20120226882 | STORAGE SYSTEM, STORAGE CONTROL APPARATUS, AND STORAGE CONTROL METHOD - In a storage system a write processing section writes data, of ejection object data, which is stored in a storage apparatus to an ejection portable record medium. A read processing section reads out data, of the ejection object data, which is not stored in the storage apparatus at the time of an ejection request being made from portable record mediums contained in a store section, and stores the data in the storage apparatus as data to be written by the write processing section. An ejection process control section controls timing at which the write processing section begins writing on the basis of an amount of the data, of the ejection object data, which is stored in the storage apparatus and an amount of remaining data, of the ejection object data, which is to be read out by the read processing section from the portable record mediums. | 09-06-2012 |
| 20120226883 | MANAGEMENT APPARATUS - According to an embodiment a management apparatus includes: a stream storage configured to store a stream constituted by a plurality of pages; a trace information storage configured to store trace information in each stream, a receiving unit configured to receive a request to write the pages constituting the stream; and a management unit. The management unit refers to the trace information; writes the page into the stream storage when the write rule indicates that the page is to be written in the stream storage; writes the page into the temporary storage when the write rule indicates that the page is to be written in the temporary storage; and writes the page that has been written in the temporary storage into the stream storage in units of extents at a predetermined timing. | 09-06-2012 |
| 20120226884 | SIGNAL RESTORATION CIRCUIT, LATENCY ADJUSTMENT CIRCUIT, MEMORY CONTROLLER, PROCESSOR, COMPUTER, SIGNAL RESTORATION METHOD, AND LATENCY ADJUSTMENT METHOD - A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal. | 09-06-2012 |
| 20120239898 | MEMORY SYSTEM WITH INDEPENDENTLY ADJUSTABLE CORE AND INTERFACE DATA RATES - An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value. | 09-20-2012 |
| 20120246434 | SYSTEM AND METHOD FOR DECODING COMMANDS BASED ON COMMAND SIGNALS AND OPERATING STATE - A system and method for decoding command signals that includes a command decoder configured to generate internal control signals to perform an operation based on the command signals and an operating state. The same combination of command signals can request different commands depending on the operating state. A command is selected from a first set of operations according to the command signals when the memory system is in a first operating state and a command is selected from a second set of operations according to the command signals when the memory system is in a second operating state. | 09-27-2012 |
| 20120260057 | COUNTER ARCHITECTURE FOR ONLINE DVFS PROFITABILITY ESTIMATION - A counter architecture and a corresponding method are provided for estimating a profitability value of DVFS for a unit of work running on a computing device. The counter architecture and the corresponding method are arranged for dividing total execution time for executing a unit of work on the computing device into a pipelined fraction subject to clock frequency and a non-pipelined fraction due to off-chip memory accesses, and for estimating the DVFS profitability value from the pipelined and the non-pipelined fraction. | 10-11-2012 |
| 20120290810 | Memory Access Latency Metering - Memory transactions that are issued just in time have deterministic response delay. By measuring an actual delay and comparing it to an expected delay a memory scheduler can determine whether it is issuing transaction requests too early and can thereby automatically adapt the issue of transaction requests by delaying future transaction requests to be just in time. | 11-15-2012 |
| 20120303921 | DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY - A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. | 11-29-2012 |
| 20120324193 | Systems and Methods for DQS Gating - Systems and methods are provided for timing read operations with a memory device. A system for timing read operations with a memory device includes a gating circuit configured to receive a timing signal from the memory device. The gating circuit is further configured to pass through the timing signal as a filtered timing signal during a gating window. The gating window is generated by the gating circuit based on a control signal. The system further includes a timing control circuit configured to generate the control signal after receiving a read request from a memory controller. The timing control circuit is further configured to adjust the control signal to account for temporal variations in the timing signal from the memory device. | 12-20-2012 |
| 20130007399 | ADJUSTING THE TIMING OF SIGNALS ASSOCIATED WITH A MEMORY SYSTEM - A system and method are provided for adjusting the timing of signals associated with a memory system. A memory controller is provided. Additionally, at least one memory module is provided. Further, at least one interface circuit is provided, the interface circuit capable of adjusting timing of signals associated with one or more of the memory controller and the at least one memory module. | 01-03-2013 |
| 20130013878 | Levelization of Memory Interface for Communicating with Multiple Memory Devices - In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices. | 01-10-2013 |
| 20130013879 | MEMORY CONTROL DEVICE, MEMORY DEVICE, AND MEMORY CONTROL METHOD - The memory control device according to the present invention includes a command generating unit which divides the memory access request issued by the master into access commands each of which is for one of the memory devices, a command issuing units which issue each of the access commands to the memory devices, a data control unit which switches data between a master and memories, and the command generating unit switch between control for outputting an identical physical address to the memory units and control for outputting different physical addresses to the memory devices, depending on when the physical addresses of the memory devices are identical and when the physical addresses of the memory devices are different, each of the memory devices corresponds to one of the divided access commands. | 01-10-2013 |
| 20130031326 | DEVICES, METHODS, AND SYSTEMS SUPPORTING ON UNIT TERMINATION - The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry. | 01-31-2013 |
| 20130103917 | EFFICIENT COMMAND MAPPING SCHEME FOR SHORT DATA BURST LENGTH MEMORY DEVICES - An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer system perform a method of requesting data from the memory device. This method comprises receiving a plurality of commands for the memory device from the command bus, the memory device clocked by a clock. At least one command of the plurality of commands includes a first command and a second command within a single clock cycle of said clock. At least one of the first command and second command is a data access command. The first command is executed during a first clock cycle and the second command is executed during a second subsequent clock cycle. | 04-25-2013 |
| 20130111175 | METHODS AND APPARATUS TO CONTROL GENERATION OF MEMORY ACCESS REQUESTS | 05-02-2013 |
| 20130111176 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT | 05-02-2013 |
| 20130145117 | COORDINATING WRITE SEQUENCES IN A DATA STORAGE SYSTEM - According to one aspect of the present disclosure, a system and technique for coordinating write sequences in a data storage system includes a processor configured to receive from a primary device, responsive to the primary device receiving a request to write to primary storage, a request for a sequence number. The system also includes a sequence generator configured to: generate a current sequence number for the write; generate a first identifier indicating an identity of secondary devices writing to secondary storage based on the current sequence number; generate a second identifier indicating an identity of secondary devices writing to secondary storage based on the current sequence number and a previous sequence number; transmit the current sequence number and the second identifier to the primary device; and transmit the current sequence number and the first identifier to the secondary devices writing to secondary storage based on the previous sequence number. | 06-06-2013 |
| 20130159657 | MEMORY CONTROLLER WITH FAST REACQUISITION OF READ TIMING TO SUPPORT RANK SWITCHING - Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory controller performs the fast timing reacquisition by adjusting a data delay line coupled to a clock path associated with a control loop, wherein the control loop controls a data clock which is used to receive read data at the memory controller. | 06-20-2013 |
| 20130166870 | VOLTAGE AND TIMING CALIBRATION METHOD USED IN MEMORY SYSTEM - A voltage and timing calibration method used in a memory system. A memory controller adjusts timing and voltages of the controller and voltages of a memory buffer according to data returned by the buffer based on timing and voltages at a memory controller side of the buffer, to calibrate timing and voltages between the controller and controller side. According to data read by the buffer from a memory chip unit on the basis of timing and voltages at a memory chip side of the buffer, the controller adjusts the timing and voltage at the chip side and the voltage of the chip unit; or the buffer adjusts the timing and voltage at the chip side and the voltage of the chip unit, to calibrate the timing and voltage between the chip side and chip unit. Therefore, hardware resources of the buffer can be saved and the circuit can be simplified. | 06-27-2013 |
| 20130179658 | SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES - A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing. | 07-11-2013 |
| 20130198477 | MANAGING REMOTE DATA REPLICATION - Various systems, processes, and products may be used to manage remote replication of data. In particular implementations, a system, process, and product for managing remote replication of data may include the ability to receive writes from an external system, request an ordered index for the writes, and send the writes to at least one storage system. The system, process, and product may also include the ability to receive writes from the at least one storage system, receive ordered indexes for the writes from the external system and the at least one storage system, and store the writes based on the indexes. | 08-01-2013 |
| 20130212349 | LOAD THRESHOLD CALCULATING APPARATUS AND LOAD THRESHOLD CALCULATING METHOD - A load threshold calculating apparatus includes a computer that acquires for a second storage device having a lower response performance to access requests than a first storage device, a required maximum response time for response to a read request; substitutes the maximum response time into a model expressing for the second storage device, a response time to the read request, the response time increasing exponentially with an increase in read requests and according to an exponent denoting the number of read requests to the second storage device per unit time, to calculate a value indicative of the number of read requests in a case of the maximum response time; calculates based on the calculated value and the number of the memory areas in the second storage device, an upper limit value of the number of read requests to a memory area per unit time; and outputs the upper limit value. | 08-15-2013 |
| 20130275709 | METHODS FOR READING DATA FROM A STORAGE BUFFER INCLUDING DELAYING ACTIVATION OF A COLUMN SELECT - Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time. | 10-17-2013 |
| 20130283001 | SEMICONDUCTOR DEVICE THAT BURST-OUTPUTS READ DATA - Disclosed herein is a device that includes: a data terminal; a plurality of memory banks; and a control circuit configured to control a data transfer between the data terminal and the memory banks. The control circuit is configured to set a read latency in response to a burst length. | 10-24-2013 |
| 20130297906 | METHOD AND APPARATUS FOR BATCHING MEMORY REQUESTS - A memory controller includes a batch unit, a batch scheduler, and a memory command scheduler. The batch unit includes a plurality of source queues for receiving memory requests from a plurality of sources. Each source is associated with a selected one of the source queues. The batch unit is operable to generate batches of memory requests in the source queues. The batch scheduler is operable to select a batch from one of the source queues. The memory command scheduler is operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller. | 11-07-2013 |
| 20130305008 | MEMORY OPERATION TIMING CONTROL METHOD AND MEMORY SYSTEM USING THE SAME - A method of controlling operation timing of memory devices included in a storage apparatus and a memory system including the method. The method includes adjusting operation timing such that a number of memory devices that simultaneously perform operations is below a reference value according to a host request, and issuing operations according to the adjusted operation timing and transferring the issued operations to the memory devices. | 11-14-2013 |
| 20130318321 | BUFFER CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A buffer control circuit of a semiconductor memory apparatus includes a delay unit configured to determine delay amounts for a command in response to a plurality of command latency signals, delay the command according to a clock, and generate a plurality of delayed signals; and a buffer control signal generation unit configured to receive the plurality of command latency signals and the plurality of delayed signals, and generate a buffer control signal. | 11-28-2013 |
| 20130326184 | MEMORY APPARATUS - A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data. | 12-05-2013 |
| 20130326185 | MEMORY POWER TOKENS - Techniques are described for controlling availability of memory. As memory write operations are processed, the contents of memory targeted by the write operations are read and compared to the data to be written. The availability of the memory for subsequent write operations is controlled based on the outcomes of the comparing. How many concurrent write operations are being executed may vary according to the comparing. In one implementation, a pool of tokens is maintained based on the comparing. The tokens represent units of power. When write operations require more power, for example when they will alter the values of more cells in PCM memory, they draw (and eventually return) more tokens. The token pool can act as a memory-availability mechanism in that tokens must be obtained for a write operation to be executed. When and how many tokens are reserved or recycled can vary according to implementation. | 12-05-2013 |
| 20130332689 | Techniques For Reducing A Rate Of Data Transfer To At Least A Portion Of Memory - A system, method, and computer program product are provided for reducing a rate of data transfer to at least a portion of memory. In operation, a rate of degradation of at least a portion of memory associated with a drive is determined. Furthermore, a rate of data transfer to the at least a portion of the memory is reduced, based on the determined rate of degradation. | 12-12-2013 |
| 20130346721 | MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES - A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied. | 12-26-2013 |
| 20130346722 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 12-26-2013 |
| 20140006743 | QoS-Aware Scheduling | 01-02-2014 |
| 20140013070 | DYNAMIC MEMORY PERFORMANCE THROTTLING - Dynamic memory performance throttling. An embodiment of a memory device includes a memory stack including coupled memory elements; the memory elements including multiple ranks, the plurality of ranks including a first rank and a second rank, and a logic device including a memory controller. The memory controller is to determine an amount of misalignment between data signals relating to a read request for the first rank and a read request for the second rank, and, upon determining that misaligment between the first rank and the second rank is greater than a threshold, the memory controller is to insert a time shift between a data signal for the first rank and a data signal for the second rank. | 01-09-2014 |
| 20140019703 | MEMORY ACCESS SYSTEM - A memory access system may be used to relay data between an electronic device and external memory. The memory access system may include write buffers which may receive and write information from the electronic device to the external memory. The memory access system may also include read buffers which may gather data from the external memory and send it to a main processing component of the electronic device for processing. The memory access system may be configured so that the main processing component of the electronic device may gather data from the write buffers of the memory access system when a condition is satisfied. | 01-16-2014 |
| 20140032871 | TRACKING MECHANISM FOR WRITING TO A MEMORY CELL - A circuit includes a tracking write circuit and a write circuit. Various write signals of the write circuit are generated based on tracking signals of the tracking write circuit. The write signals are used in a write operation of a memory cell. | 01-30-2014 |
| 20140040587 | Power Savings Apparatus and Method for Memory Device Using Delay Locked Loop - Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle. | 02-06-2014 |
| 20140059318 | MEMORY TIMING OPTIMIZATION USING PATTERN BASED SIGNALING MODULATION - According to some embodiments, a method and apparatus are provided to determine a worst-case setup and hold bit pattern stream associated with a load on a bus, and determine a time shift to apply to an incoming bit pattern being conveyed relative to a DLL associated with the load. | 02-27-2014 |
| 20140068218 | STORAGE DEVICE AND COMMUNICATION METHOD - According to one embodiment, a storage device includes a queue, an interface unit, a selection unit and a delay unit. The interface unit exclusively executes command receiving processing of storing commands from a host in the queue and data transmission processing with the host. The selection unit selects one command from the commands stored in the queue. The delay unit delays a second timing at which data transmission processing for the selected command is started based on a first timing at which the command receiving processing is executed last. When a new command is not received between the first timing and the second timing, the interface unit starts the data transmission processing for the selected command at the second timing. When the new command is received between the first timing and the second timing, the interface unit executes command receiving processing for the new command. | 03-06-2014 |
| 20140089620 | SYSTEM AND METHOD FOR CONTROLLING MEMORY COMMAND DELAY - A system with a processor in communication with a memory controller in communication with a plurality of memory devices wherein one of the plurality of memory devices is interposed between the memory controller and the remaining plurality of memory devices. By programming command delay in the memory controller, the command delay coordinates the execution of the command signal across all memory devices. The processor provides control signals to the memory controller that, in response, decodes the control signals and determines the mode of operation of one or more of the memory devices. The processor is also in communication with storage media and stores data in or retrieves data from the storage media. | 03-27-2014 |
| 20140122822 | APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES - Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation. | 05-01-2014 |
| 20140149708 | DATA STRUCTURE PRODUCT AND METHOD FOR INTERFACE TRANSMISSION - The present invention discloses an interface transmission method including: enabling a first command string including a first sub-command to be transmitted to a storage device from a processing device during a first period; enabling a second command string including a second sub-command to be transmitted to the storage device from the processing device during a second period, wherein the first sub-command and the second sub-command constitute a command; when the command is a write command, enabling a write data string to be transmitted to the storage device from the processing device during a third period, wherein the write data string includes write data; and when the command is a read command, enabling a read data string to be transmitted to the processing device from the storage device during the third period, wherein the read data string includes read data. | 05-29-2014 |
| 20140164726 | SYSTEM-ON-CHIP HAVING SPECIAL FUNCTION REGISTER AND OPERATING METHOD THEREOF - Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled. | 06-12-2014 |
| 20140173240 | MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT - A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request. | 06-19-2014 |
| 20140189277 | STORAGE CONTROLLER SELECTING SYSTEM, STORAGE CONTROLLER SELECTING METHOD, AND RECORDING MEDIUM - A storage controller selecting system includes a time information storage unit, a receiver, and a processor. The time information storage unit is configured to store internal processing time information for each of a plurality of storage controllers. The internal processing time information for each individual storage controller relates to an internal processing time taken for processing performed within the individual storage controller in response to an access request to a logical volume. The receiver is configured to receive a creation request for requesting creation of a new logical volume. The processor is configured to select a certain storage controller from among the plurality of storage controllers according to the internal processing time information, and to cause the certain storage controller to create the new logical volume. | 07-03-2014 |
| 20140195764 | MEMORY DEVICE HAVING AN ADAPTABLE NUMBER OF OPEN ROWS - A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row. | 07-10-2014 |
| 20140215175 | EFFICIENT SUSPEND-RESUME OPERATION IN MEMORY DEVICES - A method includes executing a first memory access operation in a memory. A progress indication, which is indicative of a progress of execution of the first memory access operation, is obtained from the memory. Based on the progress indication, a decision is made whether to suspend the execution of the first memory access operation in order to execute a second memory access operation. | 07-31-2014 |
| 20140237207 | METHOD AND SYSTEM FOR ENHANCED PERFORMANCE IN SERIAL PERIPHERAL INTERFACE - A method of conducting an operation in an integrated circuit having a plurality of memory cells includes receiving an operating command for the memory cells and receiving a first address segment associated with the memory cells in at least one clock cycle after receiving the operating command. The method further includes receiving a first performance enhancement indicator in at least one clock cycle after ending the first address segment while before starting to transfer data, for determining whether an enhanced operation is to be performed. | 08-21-2014 |
| 20140258666 | MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA - Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface. | 09-11-2014 |
| 20140281325 | SYNCHRONIZATION AND ORDER DETECTION IN A MEMORY SYSTEM - Embodiments relate to out-of-synchronization detection and out-of-order detection in a memory system. One aspect is a system that includes a plurality of channels, each providing communication with a memory buffer chip and a plurality of memory devices. A memory control unit is coupled to the plurality of channels. The memory control unit is configured to perform a method that includes receiving frames on two or more of the channels. The memory control unit identifies alignment logic input in each of the received frames and generates a summarized input to alignment logic for each of the channels of the received frames based on the alignment logic input. The memory control unit adjusts a timing alignment based on a skew value per channel. Each of the timing adjusted summarized inputs is compared. Based on a mismatch between at least two of the timing adjusted summarized inputs, a miscompare signal is asserted. | 09-18-2014 |
| 20140281326 | DUAL ASYNCHRONOUS AND SYNCHRONOUS MEMORY SYSTEM - Embodiments relate to a dual asynchronous and synchronous memory system. One aspect is a system that includes a memory controller and a memory buffer chip coupled to the memory controller via a synchronous channel. The memory buffer chip includes a memory buffer unit configured to synchronously communicate with the memory controller in a nest domain, and a memory buffer adaptor configured to communicate with at least one memory interface port in a memory domain. The at least one memory interface port is operable to access at least one memory device. A boundary layer is connected to the nest domain and the memory domain, where the boundary layer is configurable to operate in a synchronous transfer mode between the nest and memory domains and to operate in an asynchronous transfer mode between the nest and memory domains. | 09-18-2014 |
| 20140281327 | SYSTEM AND METHOD TO DYNAMICALLY DETERMINE A TIMING PARAMETER OF A MEMORY DEVICE - A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter. | 09-18-2014 |
| 20140281328 | MEMORY INTERFACE OFFSET SIGNALING - A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths. | 09-18-2014 |
| 20140281329 | Priority Command Queues for Low Latency Solid State Drives - A method, apparatus, and system of a priority command queues for low latency solid state drives are disclosed. In one embodiment, a system of a storage system includes a command sorter to determine a target storage device for at least one of a solid state drive (SSD) command and a hard disk drive (HDD) command and to place the command in a SSD ready queue if the SSD command is targeted to a SSD storage device of the storage system and to place the HDD command to a HDD ready queue if the HDD command is targeted to an HDD storage device of the storage system, a SSD ready queue to queue the SSD command targeted to the SSD storage device, and a HDD ready queue to queue the HDD command targeted to the HDD storage device. | 09-18-2014 |
| 20140297986 | SEMICONDUCTOR MEMORY DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The semiconductor memory device includes an internal flag signal generator and an active information generator. The internal flag signal generator generates a plurality of internal flag signals which are selectively enabled when combination signals of bank address signals and row address signals supplied are inputted from an external device at least a predetermined number of times. The active information generator outputs a flag signal enabled when at least one of the plurality of internal flag signals is enabled in response to a start signal for extracting information on a number of times that a word line is activated and outputs a plurality of bank information signals according to the plurality of internal flag signals. The active information generator generates internal bank address signals and internal row address signals according to the plurality of internal flag signals to refresh a bank. | 10-02-2014 |
| 20140310494 | STORAGE CONTROL SYSTEM WITH DATA MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF - A storage control system, and a method of operation thereof, including: a recycle write queue for providing a recycle write; a host write queue for providing a host write; and a scheduler, coupled to the recycle write queue and the host write queue, for scheduling the recycle write and the host write for writing to a memory device. | 10-16-2014 |
| 20140310495 | COLLECTIVE MEMORY TRANSFER DEVICES AND METHODS FOR MULTIPLE-CORE PROCESSORS - This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory. | 10-16-2014 |
| 20140317373 | METHOD AND APPARATUS FOR MANAGING MEMORY - A method of managing a memory in an electronic device is provided that includes calculating an indication of remaining life of a memory component that is used as a swap space by the electronic device; and adjusting the use of the memory component as a swap space based on the indication of remaining life, wherein the adjusting includes one of: (i) reducing a rate at which data is swapped in and out of the memory component, and (ii) discontinuing the use of the memory component as a swap space. | 10-23-2014 |
| 20140331021 | MEMORY CONTROL APPARATUS AND METHOD - A memory control apparatus that minimizes memory bank collisions by rescheduling memory requests. The memory control apparatus includes a scheduler configured to, in response to at least two memory requests existing in a current cycle, schedule a plurality of elements included in the at least two memory requests based on information about memory banks determined for the plurality of elements; and a request generator configured to, in response to the scheduling of the plurality of elements by the scheduler, generate a scheduled memory request for the current cycle using at least one element in the at least two memory requests in order to prevent a memory bank collision. | 11-06-2014 |
| 20140337598 | MODULATION OF FLASH PROGRAMMING BASED ON HOST ACTIVITY - An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may include a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to (i) determine an amount of bandwidth used by the read/write operations, (ii) if the bandwidth is above a threshold value, process the read/write operations at a first speed, and (iii) if the bandwidth is below the threshold value, process the read/write operations at a second speed. | 11-13-2014 |
| 20140344544 | Marching Memory, A Bidirectional Marching Memory, A complex Marching Memory And A Computer System, Without The Memory Bottleneck - A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor. | 11-20-2014 |
| 20140359242 | MEMORY DEVICE WITH RELAXED TIMING PARAMETER ACCORDING TO TEMPERATURE, OPERATING METHOD THEREOF, AND MEMORY CONTROLLER AND MEMORY SYSTEM USING THE MEMORY DEVICE - A memory device used with a relaxed timing requirement specification according to temperatures, an operation method thereof, and a memory controller and a memory system using the memory device are provided. The memory device has a first timing characteristic at a first temperature and a second timing characteristic that is longer than the first timing characteristic at a second temperature. If a temperature of the memory device is higher than a reference temperature, the memory controller controls the first timing characteristic as a timing requirement specification of the memory device. If the temperature of the memory device is lower than the reference temperature, the memory controller controls the second timing characteristic as the timing requirement specification of the memory device. | 12-04-2014 |
| 20150012717 | MEMORY CONTROLLED DATA MOVEMENT AND TIMING - The present disclosure includes apparatuses, electronic device readable media, and methods for memory controlled data movement and timing. A number of electronic device readable media can store instructions executable by an electronic device to provide programmable control of data movement operations within a memory. The memory can provide timing control, independent of any associated processor, for interaction between the memory and the associated processor. | 01-08-2015 |
| 20150012718 | SYSTEM FOR COMPENSATING FOR DYNAMIC SKEW IN MEMORY DEVICES - A memory device includes a memory array, a memory controller, data lines connecting the memory array and the memory controller, and a delay compensation module. The delay compensation module includes a delay line that provides delayed clock signals, a look-up table that stores a mapping between predefined data bit patterns and corresponding propagation delays for each data line, and delay compensation logic modules corresponding to the data lines. The delay compensation logic modules receive data bit patterns carried by the data lines, select propagation delays based on the data bit patterns and the look-up table data, and delay the bits carried by corresponding ones of the data lines based on delayed clock signals corresponding to the propagation delays. | 01-08-2015 |
| 20150019831 | DUAL ASYNCHRONOUS AND SYNCHRONOUS MEMORY SYSTEM - A computer-system implemented method for dual asynchronous and synchronous memory operation in a memory subsystem includes establishing a synchronous channel between a memory controller and a memory buffer chip. A mode selector determines a reference clock source for a memory domain phase-locked loop of the memory buffer chip based on an operating mode of the memory buffer chip. An output of a nest domain phase-locked loop is provided as the reference clock source to the memory domain phase-locked loop in the memory buffer chip based on the operating mode being synchronous. The nest domain phase-locked loop is operable synchronous to a memory controller phase-locked loop of the memory controller. A separate reference clock is provided independent of the nest domain phase-locked loop as the reference clock to the memory domain phase-locked loop based on the operating mode being asynchronous. | 01-15-2015 |
| 20150067290 | MEMORY ACCESS TIME TRACKING IN DUAL-RAIL SYSTEMS - Disclosed are various apparatuses and methods for memory access time tracking in dual-rail systems. An apparatus may include a memory coupled to a first voltage rail and having a data output, a data circuit coupled to a second voltage rail and configured to receive the data output from the memory, and a timing circuit configured to adjust an access time of the memory based on a second voltage rail level. A method may include determining a voltage rail level of a data circuit, adjusting the access time of the memory based on the voltage rail level of the data circuit, outputting data from the memory, and receiving the output data by the data circuit. | 03-05-2015 |
| 20150067291 | CONTROLLER, MEMORY SYSTEM, AND METHOD - According to the embodiments, a controller includes an arbiter, a command fetch unit, and a processing unit. The arbiter executes a retrieval process. The retrieval process is a process of selecting a queue, to which a command is issued, out of plural queues by retrieval according to a round robin method. The command fetch unit fetches a command from the selected queue. The processing unit executes a process according to the fetched command to a memory chip. The arbiter manages a retrieval position. When a new command is issued to any one of the plural queues in an empty state in which there is no queue to which a command is issued, the arbiter has the retrieval position jump to the queue to which the new command is issued. | 03-05-2015 |
| 20150095605 | Latency-Aware Memory Control - A system, method and computer-readable storage device for accessing heterogeneous memory system, are provided. A memory controller schedules access of a command to a memory region in a set of memory regions based on an access priority associated with the command and where the set of memory regions have corresponding access latencies. The memory controller also defers access of the command to the set of memory regions using at least two queues and the access priority. | 04-02-2015 |
| 20150134926 | SYSTEMS AND METHODS FOR LOG COORDINATION - A storage module may be configured to perform log storage operations on a storage log maintained on a non-volatile storage medium. An I/O client may utilize storage services of the storage module to maintain an upper-level log. The storage module may be configured to coordinate log storage and/or management operations between the storage log and the upper-level log. The coordination may include adapting a segment size of the logs to reduce write amplification. The coordination may further include coordinating validity information between log layers, adapting log grooming operations to reduce storage recovery overhead, defragmenting upper-level log data within the storage address space, preventing fragmentation of upper-level log data, and so on. The storage module may coordinate log operations by use of log coordination messages communicated between log layers. | 05-14-2015 |
| 20150143069 | Managing Data Delivery - Methods and systems for managing data and/or operations on data such as content are disclosed. A method can comprise receiving data from a source, determining timing information associated with the source and automatically modifying a storage operation of data received from the source based upon the timing information. | 05-21-2015 |
| 20150317096 | APPARATUS, METHOD AND SYSTEM FOR MEMORY DEVICE ACCESS WITH A MULTI-CYCLE COMMAND - Techniques and mechanisms for determining a timing of a command to access a memory device resource. In an embodiment, a multi-cycle command which is exchanged from a memory controller to a memory device, wherein the multi-cycle command indicates an access to a bank of the memory device. Timing of the one or more other commands is controlled, based on the multi-cycle command, to enforce a time delay parameter which describes an operational constraint of the memory device. In another embodiment, timing of one or more commands is determined with reference to a beginning of a last cycle of a multi-cycle command. | 11-05-2015 |
| 20150356008 | METHOD FOR ACCESS TO ALL THE CELLS OF A MEMORY AREA FOR PURPOSES OF WRITING OR READING DATA BLOCKS IN SAID CELLS - A method for access to all cells in a memory area for purposes of writing or reading data blocks in the cells may include, for each access time (Ti with i=0 to N) to the cells in the memory area to be accessed, a process of determining the address (ADRj, with j=0 to N) of the cell of the memory area to be accessed at the access time (Ti), an address (ADRj) determined for an access time Ti not being once again determined for another access time (Tk, k≠j). The process of determining each address (ADRj) may be a pseudorandom process. The method may be used, for example, in any type of card, chip card, SIM card, etc., which includes a processing unit, such as a microcontroller, for manipulating cryptographic data serving to identify and/or authenticate a user of such a card. | 12-10-2015 |
| 20150363106 | MEMORY SYSTEM AND ELECTRONIC DEVICE - An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet. | 12-17-2015 |
| 20160085444 | SELECTABLE MEMORY ACCESS TIME - The present disclosure relates to selectable memory access time. An apparatus includes a memory controller. The memory controller is configured to select a memory access time interval duration parameter based, at least in part, on a memory address identifier, in response to receiving a memory access request; to adjust the selected memory access time interval duration parameter based, at least in part, on a current operating temperature; and perform a requested memory access operation on a memory array, a duration of the memory access operation related to the adjusted memory access time interval duration parameter. | 03-24-2016 |
| 20160124647 | MEMORY SYSTEM AND METHOD OF OPERATING SAME USING PROGRAM ORDER INFORMATION - A method of operating a memory system includes managing program order information of the memory device based on program order stamps (POSs) indicating relative temporal relationships between program operations performed in relation to a plurality of memory groups included in the memory device, and controlling operations directed to the plurality of memory groups in response to the program order information. | 05-05-2016 |
| 20160124648 | Apparatus and Method for Managing Memory - An apparatus for managing a memory having a plurality of command/address pins is provided. The apparatus includes a command generating module and a control module. The command generating module generates a set of target commands. The set of target commands include a plurality of command groups. Each of the command groups corresponds to at least one command/address pin of the plurality of command/address pins. It is known that the memory accesses the set of target commands from the plurality of command/address pins at a target time point. The control module controls the command groups to have different transition times prior to the target time points when the command groups are transmitted on the plurality of command/address pins. | 05-05-2016 |
| 20160133306 | MEMORY DEVICE HAVING AN ADAPTABLE NUMBER OF OPEN ROWS - A memory device comprises a memory array, at least one row address buffer, a set of row data buffers, a row decoder, an array of sense amplifiers, and a demultiplexer. The memory array comprises data elements organized into rows and columns. Each of the rows is addressable by a row address. Each of the data elements in each of the rows is addressable by a column address. The at least one row address buffer holds a selected row address of a set of successive selected row addresses. The set of row data buffers holds respective contents of selected rows that correspond to the set of successive selected row addresses. The row decoder decodes the selected row address to access a selected row. The array of sense amplifier reads the selected row and transmits content of the selected row to one of the row data buffers through the demultiplexer, and writes the content of the selected row back to the selected row. | 05-12-2016 |
| 20160196073 | Memory Module Access Method and Apparatus | 07-07-2016 |
| 20160203848 | MEMORY SIGNAL BUFFERS AND MODULES SUPPORTING VARIABLE ACCESS GRANULARITY | 07-14-2016 |
