Class / Patent application number | Description | Number of patent applications / Date published |
711134000 | Combined replacement modes | 24 |
20080235458 | METHOD FOR TRACKING OF NON-RESIDENT PAGES - Embodiments of the present invention provide methods and systems for efficiently tracking evicted or non-resident pages. For each non-resident page, a first hash value is generated from the page's metadata, such as the page's mapping and offset parameters. This first hash value is then used as an index to point one of a plurality of circular buffers. Each circular buffer comprises an entry for a clock pointer and entries that uniquely represent non-resident pages. The clock pointer points to the next page that is suitable for replacement and moves through the circular buffer as pages are evicted. In some embodiments, the entries that uniquely represent non-resident pages are a hash value that is generated from the page's inode data. | 09-25-2008 |
20080282038 | Data Processing Apparatus that Provides Parallel Access to Multi-Dimensional Array of Data Values - An array of data values, such as an image of pixel values, is stored in a main memory ( | 11-13-2008 |
20090055593 | STORAGE SYSTEM COMPRISING FUNCTION FOR CHANGING DATA STORAGE MODE USING LOGICAL VOLUME PAIR - A storage system writes a data element stored in a primary volume to a secondary volume constituting a volume pair with the primary volume in accordance with a selected storage mode, which is a data storage mode selected from a plurality of types of data storage modes. This storage system is provided with a function for switching the above-mentioned selected storage mode from a currently selected data storage mode to a different type of data storage mode. | 02-26-2009 |
20090113134 | Method and Cache Control Circuit for Replacing Cache Lines Using Alternate PLRU Algorithm and Victim Cache Coherency State - A method and a cache control circuit for replacing a cache line using an alternate pseudo least-recently-used (PLRU) algorithm with a victim cache coherency state, and a design structure on which the subject cache control circuit resides are provided. When a requirement for replacement in a congruence class is identified, a first PLRU cache line for replacement and an alternate PLRU cache line for replacement in the congruence class are calculated. When the first PLRU cache line for replacement is in the victim cache coherency state, the alternate PLRU cache line is picked for use. | 04-30-2009 |
20090164734 | MULTIPLE CONCURRENT SYNC DEPENDENCIES IN AN OUT-OF-ORDER STORE QUEUE - A method, system and processing device for retiring data entries held within a store queue (STQ). The STQ of a processor cache is modified to receive and process several types of data entries including: non-synchronized (non-sync), thread of execution synchronized (thread-sync), and all thread of execution synchronized (all-thread-sync). The task of storing data entries, from the STQ out to memory or an input/output device, is modified to increase the effectiveness of the cache. The modified STQ allows non-sync, thread-sync, and all-thread-sync instructions to coexist in the STQ regardless of the thread of execution. Stored data entries, or stores are deterministically selected for retirement, according to the data entry type. | 06-25-2009 |
20090172291 | MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS - A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data. | 07-02-2009 |
20090210628 | Computer Cache System With Stratified Replacement - Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction. | 08-20-2009 |
20090282196 | FIRST IN FIRST OUT EVICTION IMPLEMENTATION - Methods for a treatment of cached objects are described. In one embodiment, management of a region of a cache is configured with an eviction policy plug-in. The eviction policy plug-in includes an eviction timing component and a sorting component, with the eviction timing component including code to implement an eviction timing method, and the eviction timing method to trigger eviction of an object from the region of cache. The sorting component includes code to implement a sorting method to identify an object that is eligible for eviction in the region of cache. The sorting method involves identifying an object that has been cached in the region of cache for a longer time period than other objects that are cached in the cache region. | 11-12-2009 |
20100023699 | System and Method for Usage Analyzer of Subscriber Access to Communications Network - A system and a method are described, whereby a data cache enables the realization of an efficient design of a usage analyzer for monitoring subscriber access to a communications network. By exploiting the speed advantages of cache memory, as well as adopting innovative data loading and retrieval choices, significant performance improvements in the time required to access the necessary data records can be realized. | 01-28-2010 |
20100191916 | Optimizing A Cache Back Invalidation Policy - A method and a system for utilizing less recently used (LRU) bits and presence bits in selecting cache-lines for eviction from a lower level cache in a processor-memory sub-system. A cache back invalidation (CBI) logic utilizes LRU bits to evict only cache-lines within a LRU group, following a cache miss in the lower level cache. In addition, the CBI logic uses presence bits to (a) indicate whether a cache-line in a lower level cache is also present in a higher level cache and (b) evict only cache-lines in the lower level cache that are not present in a corresponding higher level cache. However, when the lower level cache-line selected for eviction is also present in any higher level cache, CBI logic invalidates the cache-line in the higher level cache. The CBI logic appropriately updates the values of presence bits and LRU bits, following evictions and invalidations. | 07-29-2010 |
20110099333 | MECHANISM FOR EFFECTIVELY CACHING STREAMING AND NON-STREAMING DATA PATTERNS - A method and apparatus for efficiently caching streaming and non-streaming data is described herein. Software, such as a compiler, identifies last use streaming instructions/operations that are the last instruction/operation to access streaming data for a number of instructions or an amount of time. As a result of performing an access to a cache line for a last use instruction/operation, the cache line is updated to a streaming data no longer needed (SDN) state. When control logic is to determine a cache line to be replaced, a modified Least Recently Used (LRU) algorithm is biased to select SDN state lines first to replace no longer needed streaming data. | 04-28-2011 |
20120047331 | SYSTEMS AND METHODS FOR MANAGING AN UPLOAD OF FILES IN A SHARED CACHE STORAGE SYSTEM - Systems and methods for managing a storage device are disclosed. Generally, in a host to which a storage device is operatively coupled, wherein the storage device includes a cache for storing one or more discardable files, a file is identified to be uploaded to an external location. A determination is made whether sufficient free space exists in the cache to pre-stage the file for upload to the external location and the file is stored in the cache upon determining that sufficient free space exists in the cache to pre-stage the file for upload to the external location, wherein pre-stating prepares a file for opportunistically uploading such file in accordance with an uploading policy. | 02-23-2012 |
20120079206 | METHOD, APPARATUS, PROXY SERVER, AND SYSTEM FOR SELECTING CACHE REPLACEMENT POLICIES - Embodiments of the present invention provide a method, an apparatus, and a proxy server for selecting cache replacement policies to reduce manual participation and switch cache replacement policies automatically. The method includes: obtaining statistical data of multiple cache replacement policies that are running simultaneously; and switching, according to an event of policy decision for cache replacement policies and the statistical data, an active cache replacement policy to a cache replacement policy that complies with a policy decision requirement. The automatic switching of cache replacement policies lowers the technical requirements on administrators. In addition, in the operation process of a proxy cache, a cache replacement policy that is applicable to a current scenario and meets a performance expectation of a user can be selected automatically, so as to make the technical solution feature good adaptability. Compared with the existing solution in which only a cache replacement policy is used throughout, the technical solution of the present invention can improve the performance of the proxy cache. | 03-29-2012 |
20130138892 | DRAM CACHE WITH TAGS AND DATA JOINTLY STORED IN PHYSICAL ROWS - A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption. | 05-30-2013 |
20130318305 | Method and Apparatus for Optimal Cache Sizing and Configuration for Large Memory Systems - A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem. | 11-28-2013 |
20130339622 | CACHE COHERENCY PROTOCOL FOR ALLOWING PARALLEL DATA FETCHES AND EVICTION TO THE SAME ADDRESSABLE INDEX - A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class. | 12-19-2013 |
20130339623 | CACHE COHERENCY PROTOCOL FOR ALLOWING PARALLEL DATA FETCHES AND EVICTION TO THE SAME ADDRESSABLE INDEX - A technique for cache coherency is provided. A cache controller selects a first set from multiple sets in a congruence class based on a cache miss for a first transaction, and places a lock on the entire congruence class in which the lock prevents other transactions from accessing the congruence class. The cache controller designates in a cache directory the first set with a marked bit indicating that the first transaction is working on the first set, and the marked bit for the first set prevents the other transactions from accessing the first set within the congruence class. The cache controller removes the lock on the congruence class based on the marked bit being designated for the first set, and resets the marked bit for the first set to an unmarked bit based on the first transaction completing work on the first set in the congruence class. | 12-19-2013 |
20140089595 | UTILITY AND LIFETIME BASED CACHE REPLACEMENT POLICY - Embodiments of the invention describe an apparatus, system and method for utilizing a utility and lifetime based cached replacement policy as described herein. For processors having one or more processor cores and a cache memory accessible via the processor core(s), embodiments of the invention describe a cache controller to determine, for a plurality of cache blocks in the cache memory, an estimated utility and lifetime of the contents of each cache block, the utility of a cache block to indicate a likelihood of use its contents, the lifetime of a cache block to indicate a duration of use of its contents. Upon receiving a cache access request resulting in a cache miss, said cache controller may select one of the cache blocks to be replaced based, at least in part, on one of the estimated utility or estimated lifetime of the cache block. | 03-27-2014 |
20140095799 | DIFFERENTIATING CACHE RELIABILITY TO REDUCE MINIMUM ON-DIE VOLTAGE - Systems and methods may provide for determining whether a memory access request is error-tolerant, and routing the memory access request to a reliable memory region if the memory access request is error-tolerant. Moreover, the memory access request may be routed to an unreliable memory region if the memory access request is error-tolerant. In one example, use of the unreliable memory region enables a reduction in the minimum operating voltage level for a die containing the reliable and unreliable memory regions. | 04-03-2014 |
20140129778 | Multi-Port Shared Cache Apparatus - An apparatus for use in telecommunications system comprises a cache memory shared by multiple clients and a controller for controlling the shared cache memory. A method of controlling the cache operation in a shared cache memory apparatus is also disclosed. The apparatus comprises a cache memory accessible by a plurality of clients and a controller configured to allocate cache lines of the cache memory to each client according to a line configuration. The line configuration comprises, for each client, a maximum allocation of cache lines that each client is permitted to access. The controller is configured to, in response to a memory request from one of the plurality of clients that has reached its maximum allocation of cache lines, allocate a replacement cache line to the client from cache lines already allocated to the client when no free cache lines in the cache are available. | 05-08-2014 |
20140136791 | MANAGING DATA WITHIN A CACHE - A system and method for managing data within a cache is described. In sonic example embodiments, the system identifies and/or tracks consumers of data located within a cache, and maintains the data within the cache based on determining whether there is an active consumer of the data. | 05-15-2014 |
20140164709 | VIRTUAL MACHINE FAILOVER - Disclosed is a computer system ( | 06-12-2014 |
20140215160 | METHOD OF USING A BUFFER WITHIN AN INDEXING ACCELERATOR DURING PERIODS OF INACTIVITY - A method of using a buffer within an indexing accelerator during periods of inactivity, comprising flushing indexing specific data located in the buffer, disabling a controller within the indexing accelerator, handing control of the buffer over to a higher level cache, and selecting one of a number of operation modes of the buffer. An indexing accelerator, comprising a controller and a buffer communicatively coupled to the controller, in which, during periods of inactivity, the controller is disabled and a buffer operating mode among a number of operating modes is chosen under which the buffer will be used. | 07-31-2014 |
20150106570 | CACHE METHOD AND CACHE APPARATUS - A cache apparatus stores part of a plurality of accessible data blocks into a cache area. A calculation part calculates, for each pair of data blocks of the plurality of data blocks, an expected value of the number of accesses made after one of the data blocks is accessed until the other of the data blocks is accessed, on the basis of a probability that when each of the plurality of data blocks is accessed, each data block that is likely to be accessed next is accessed next. When a data block is read from outside the cache area, a determination part determines a data block to be discarded from the cache area, on the basis of the expected value of the number of accesses made after the read data block is accessed until each of the plurality of data blocks is accessed. | 04-16-2015 |