Entries |
Document | Title | Date |
20080215818 | STRUCTURE FOR SILENT INVALID STATE TRANSITION HANDLING IN AN SMP ENVIRONMENT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line. | 09-04-2008 |
20080222362 | Method and Apparatus for Execution of a Process - Techniques are provided for enabling execution of a process employing a cache Method steps can include obtaining a first probability of accessing a given artifact in a state S | 09-11-2008 |
20080263283 | System and Method for Tracking Changes in L1 Data Cache Directory - Method, system and computer program product for tracking changes in an L1 data cache directory. A method for tracking changes in an L1 data cache directory determines if data to be written to the L1 data cache is to be written to an address to be changed from an old address to a new address. If it is determined that the data to be written is to be written to an address to be changed, a determination is made if the data to be written is associated with the old address or the new address. If it is determined that the data is to be written to the new address, the data is allowed to be written to the new address following a prescribed delay after the address to be changed is changed. The method is preferably implemented in a system that provides a Store Queue (STQU) design that includes a Content Addressable Memory (CAM)-based store address tracking mechanism that includes early and late write CAM ports. The method eliminates time windows and the need for an extra copy of the L1 data cache directory. | 10-23-2008 |
20080282037 | Method and apparatus for controlling cache - A cache controller controls at least one cache. The cache includes ways including a plurality of blocks that stores therein entry data. A writing unit writes degradation data to a failed block. The degradation data indicates that the failed block is in a degradation state. A reading unit reads entry data from a block. A determining unit determines, if the entry data obtained by the reading unit includes the degradation data, that the block is in the degradation state. | 11-13-2008 |
20080288723 | STORAGE DEVICE AND STORAGE DEVICE DATA LIFE CYCLE CONTROL METHOD - A storage device including a control part which performs control by extracting a life tag specifying a retention term during which the data is to be retained in the second volume having the quicker access time than the first volume, the control part managing the retention term of the corresponding data as specified by the life tag, and an elapsed term which has elapsed since the corresponding data was stored. A storage part manages update segment control information, and when the elapsed term of certain data exceeds the retention term of the certain data, the storage part nullifies the certain data in the second volume. | 11-20-2008 |
20080294847 | Cache control device and computer-readable recording medium storing cache control program - A cache control device controlling a cache memory having ways based on an access request includes an error number count memory unit that counts the total number of errors occurred in response to the access request regardless of in which way they occur, a degeneration information memory unit that stores cache line degeneration information indicating degeneration of a specific cache line, a degeneration information writing unit that writes, when the counted number of errors reaches a predetermined upper limit number, the cache line degeneration information into the degeneration information memory unit for a cache line, error in which causes the number to reach the predetermined upper limit number, and a replace control unit that performs, in response to a replace request to the cache line corresponding to the cache line degeneration information stored in the degeneration information memory unit, a replace control to exclude the cache line from replace candidates. | 11-27-2008 |
20080301373 | TECHNIQUE FOR CACHING DATA TO BE WRITTEN TO MAIN MEMORY - A memory apparatus having a cache memory including cache segments, and memorizing validity data indicative of whether or not each of the sectors contained in each cache segment is a valid sector inclusive of valid data; and a cache controlling component for controlling access to the cache memory. The cache controlling component includes a detecting component for detecting, when writing a cache segment back to the main memory, areas having consecutive invalid sectors by accessing validity data corresponding to the cache segment, and a write-back controlling component issuing a read command to the main memory, the read command being for reading data into each area detected, making the area a valid sector, and writing the data in the cache segment back to the main memory. | 12-04-2008 |
20080313407 | LATENCY-AWARE REPLACEMENT SYSTEM AND METHOD FOR CACHE MEMORIES - A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency. | 12-18-2008 |
20080320226 | Apparatus and Method for Improved Data Persistence within a Multi-node System - Improved access to retained data useful to a system is accomplished by managing data flow through cache associated with the processor(s) of a multi-node system. A data management facility operable with the processors and memory array directs the flow of data from the processors to the memory array by determining the path along which data evicted from a level of cache close to one of the processors is to return to a main memory and directing evicted data to be stored, if possible, in a horizontally associated cache. | 12-25-2008 |
20080320227 | Cache memory device and cache memory control method - A cache memory device that includes a cache which stores data and tag information specifying an address of stored data, includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection by the detection unit, a memory unit that stores an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search by the search unit, and a control unit that requests an external unit to replace data with a use of the address stored by the memory unit. | 12-25-2008 |
20090006761 | Cache pollution avoidance - Embodiments of the present invention are directed to a scheme in which information as to the future behavior of particular software is used in order to optimize cache management and reduce cache pollution. Accordingly, a certain type of data can be defined as “short life data” by using knowledge of the expected behavior of particular software. Short life data can be a type of data which, according to the ordinary expected operation of the software, is not expected to be used by the software often in the future. Data blocks which are to be stored in the cache can be examined to determine if they are short life data blocks. If the data blocks are in fact short life data blocks they can be stored only in a particular short life area of the cache. | 01-01-2009 |
20090019227 | Method and Apparatus for Refetching Data - Methods and apparatus for refetching data to store in a cache are disclosed. According to one aspect of the present invention, a method includes identifying a speculative set that identifies at least a first element that is associated with a cache. The first element has at least a first representation in the cache that is suitable for updating. The method also includes issuing a request to obtain the first element from a data source, opening a channel to the data source, obtaining the first element from the data source using the channel, and closing the channel. Finally, the method includes updating the first representation associated with the first element in the cache. | 01-15-2009 |
20090024800 | METHOD AND SYSTEM FOR USING UPPER CACHE HISTORY INFORMATION TO IMPROVE LOWER CACHE DATA REPLACEMENT - A system for managing data in a plurality of storage locations. In response to a least recently used algorithm wanting to move data from a cache to a storage location, an aging table is searched for an associated entry for the data. In response to finding the associated entry for the data in the aging table, an indicator is enabled on the data. In response to determining that the indicator is enabled on the data, the data is kept in the cache despite the least recently used algorithm wanting to move the data to the storage location. | 01-22-2009 |
20090037661 | Cache mechanism for managing transient data - A system and method are provided for managing transient data in cache memory. The method accepts a segment of data and stores the segment in a cache line. In response to accepting a read-invalidate command for the cache line, the segment is both read from the cache line and the cache line made invalid. If, prior to accepting the read-invalidate command, the segment in the cache line is modified, the modified segment is not stored in a backup storage memory as a result of subsequently accepting the read-invalidate command. In one aspect, the segment is initially identified as transient data, and the read-invalidate command is used in response to identifying the segment as transient data. | 02-05-2009 |
20090070533 | Content network global replacement policy - This invention is related to content delivery systems and methods. In one aspect of the invention, a content provider controls a replacement process operating at an edge server. The edge server services content providers and has a data store for storing content associated with respective ones of the content providers. A content provider sets a replacement policy at the edge server that controls the movement of content associated with the content provider, into and out of the data store. In another aspect of the invention, a content delivery system includes a content server storing content files, an edge server having cache memory for storing content files, and a replacement policy module for managing content stored within the cache memory. The replacement policy module can store portions of the content files at the content server within the cache memory, as a function of a replacement policy set by a content owner. | 03-12-2009 |
20090083492 | COST-CONSCIOUS PRE-EMPTIVE CACHE LINE DISPLACEMENT AND RELOCATION MECHANISMS - A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment. | 03-26-2009 |
20090113132 | PREFERRED WRITE-MOSTLY DATA CACHE REPLACEMENT POLICIES - A computer-implemented method of cache replacement includes steps of: determining whether each cache block in a cache memory is a read or a write block; augmenting metadata associated with each cache block with an indicator of the type of access; receiving an access request resulting in a cache miss, the cache miss indicating that a cache block will need to be replaced; examining the indicator in the metadata of each cache block for determining a probability that said cache block will be replaced; and selecting for replacement the cache block with the highest probability of replacement. | 04-30-2009 |
20090113133 | Synchronous Memory Having Shared CRC and Strobe Pin - A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC | 04-30-2009 |
20090157971 | Integration of Secure Data Transfer Applications for Generic IO Devices - Techniques are presented for sending an application instruction from a hosting digital appliance to a portable medium, where the instruction is structured as one or more units whose size is a first size, or number of bytes. After flushing the contents of a cache, the instruction is written to the cache, where the cache is structured as logical blocks having a size that is a second size that is larger (in terms of number of bytes) than the first size. In writing the instruction (having a command part and, possibly, a data part), the start of the instruction is aligned with one of the logical block boundaries in the cache and the instruction is padded out with dummy data so that it fills an integral number of the cache blocks. When a response from a portable device to an instruction is received at a hosting digital appliance, the cache is similarly flushed prior to receiving the response. The response is then stored to align with a logical block boundary of the cache. | 06-18-2009 |
20090157972 | Hash Optimization System and Method - A computer implemented method, apparatus and program product automatically optimizes hash function operation by recognizing when a first hash function results in an unacceptable number of cache misses, and by dynamically trying another hash function to determine which hash function results in the most cache hits. In this manner, hardware optimizes hash function operation in the face of changing loads and associated data flow patterns. | 06-18-2009 |
20090157973 | Storage controller for handling data stream and method thereof - A storage controller for handling data stream having data integrity field (DIF) and method thereof. The storage controller comprises a host-side I/O controller for receiving a data stream from a host entity, a host-side I/O controller for connecting to a physical storage device, and, a central processing circuitry having at least one DIF I/O interface for handling DIF data so as to reduce the number of memory access to the main memory of the storage controller. | 06-18-2009 |
20090164733 | APPARATUS AND METHOD FOR CONTROLLING THE EXCLUSIVITY MODE OF A LEVEL-TWO CACHE - A method of controlling the exclusivity mode of a level-two cache includes generating level-two cache exclusivity control information at a processor in response to an exclusivity mode indicator, and utilizing the level-two cache exclusivity control information to configure the exclusivity mode of the level-two cache. | 06-25-2009 |
20090172290 | Replacing stored content to make room for additional content - The storage of items, such as media items, in a playback device may be managed automatically without user intervention in some embodiments. An algorithm, based on heuristics, may predict which items are most likely to be used or played in the future and, based on that determination, may select the least likely to be used items for replacement. In addition, replacement may be affected by the size of space needed for additional storage versus the size of particular candidates for replacement. | 07-02-2009 |
20090193195 | CACHE THAT STORES DATA ITEMS ASSOCIATED WITH STICKY INDICATORS - Data items are stored in a cache of the storage system, where the data items are for a snapshot volume. Sticky indicators are associated with the data items in the cache, where the sticky indicators delay removal of corresponding data items from the cache. Data items of the cache are sacrificed according to a replacement algorithm that takes into account the sticky indicators associated with the data items. | 07-30-2009 |
20090204765 | DATA BLOCK FREQUENCY MAP DEPENDENT CACHING - A method for increasing the performance and utilization of cache memory by combining the data block frequency map generated by data de-duplication mechanism and page prefetching and eviction algorithms like Least Recently Used (LRU) policy. The data block frequency map provides weight directly proportional to the frequency count of the block in the dataset. This weight is used to influence the caching algorithms like LRU. Data blocks that have lesser frequency count in the dataset are evicted before those with higher frequencies, even though they may not have been the topmost blocks for page eviction by caching algorithms. The method effectively combines the weight of the block in the frequency map and its eviction status by caching algorithms like LRU to get an improved performance and utilization of the cache memory. | 08-13-2009 |
20090204766 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR HANDLING ERRORS IN A CACHE WITHOUT PROCESSOR CORE RECOVERY - A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetched data is received from a higher-level cache into a low level cache of the processor. Upon determining that the fetched data failed an error check indicating that the fetched data is corrupted, the method includes requesting an execution pipeline to discontinue processing and flush its contents, and initiating a clean up sequence, which includes sending an invalidation request to the low level cache causing the low level cache to remove lines associated with the corrupted data, and requesting the execution pipeline to restart. The execution pipeline accesses a copy of the requested data from a higher-level storage location. | 08-13-2009 |
20090216954 | APPARATUS, SYSTEM, AND METHOD FOR SELECTING A SPACE EFFICIENT REPOSITORY - An apparatus, system, and method are disclosed for selecting a space efficient repository. A cache receives write data. A destage module destages the data sequentially to a coarse grained repository such as a stride level repository and destages a directory entry for the data to a coarse grained directory such as a stride level directory if the data satisfies a repository policy. In addition, the destage module destages the data to a fine grained repository such as a track level repository overwriting an existing data instance and destages the directory entry to a fine grained directory such as a track level directory if the data does not satisfy the repository policy. | 08-27-2009 |
20090222626 | Systems and Methods for Cache Line Replacements - A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier configured to identify a cache line for replacement. The system also includes a control logic configured to determine a value of the identifier selected from an incrementer, a cache maintenance instruction, or remains the same. | 09-03-2009 |
20090254710 | DEVICE AND METHOD FOR CONTROLLING CACHE MEMORY - A cache memory control device according to an embodiment of the present invention comprises: a refill counter that counts a refill request, and a cache-capacity determining unit that determines cache capacity. The cache-capacity determining unit transmits a cache-capacity-decrease command signal to the cache memory when a count value is equal to or smaller than a first threshold value or is smaller than the first threshold value, and the cache-capacity determining unit transmits a cache-capacity-increase command signal to the cache memory when the count value is equal to or larger than a second threshold value, which is larger than the first threshold value, or when the count value is larger than the second threshold value. | 10-08-2009 |
20090271574 | METHOD FOR IMPROVING FREQUENCY-BASED CACHING ALGORITHMS BY MAINTAINING A STABLE HISTORY OF EVICTED ITEMS - The invention provides a method for improving frequency-based caching algorithms by maintaining a stable history of evicted items. One embodiment involves a process for caching data in a cache memory including logical pages including, upon detecting that a first page is being evicted from the cache memory, performing an addition process by adding metadata of the first page to a stable history list. Upon detecting a cache miss for a second page, if the stable history list contains metadata for the second page, then removing the second page metadata from the stable history list and applying a promotion determination for the second page to determine a priority value for the second page metadata and placing the second page in the cache memory based on the priority data. Upon detecting that metadata of a third page is to be evicted from the stable history list, applying an eviction determination to evict metadata of the third page from the stable history list based on a predetermined caching rule. | 10-29-2009 |
20090271575 | CACHE MEMORY, SYSTEM, AND METHOD OF STORING DATA - A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way. | 10-29-2009 |
20090300289 | Reducing back invalidation transactions from a snoop filter - In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed. | 12-03-2009 |
20090313438 | DISTRIBUTED CACHE ARRANGEMENT - Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache.) | 12-17-2009 |
20100023698 | Enhanced Coherency Tracking with Implementation of Region Victim Hash for Region Coherence Arrays - A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA. | 01-28-2010 |
20100030972 | Device, system and method of accessing data stored in a memory. - Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the pointer from the detected entry. Other embodiments are described and claimed. | 02-04-2010 |
20100037026 | Cache Refill Control - A method and a device are disclosed for a cache memory refill control. | 02-11-2010 |
20100057994 | DEVICE AND METHOD FOR CONTROLLING CACHES - Device and method for controlling caches, comprising a decoder configured to decode additional information of datasets retrievable from a memory, wherein the decoded additional information is configured to control whether particular ones of the datasets are to be stored in a cache. | 03-04-2010 |
20100057995 | CONTENT REPLACEMENT AND REFRESH POLICY IMPLEMENTATION FOR A CONTENT DISTRIBUTION NETWORK - A method for replacing, refreshing, and managing content in a communication network is provided. The method defines an object policy mechanism that applies media replacement policy rules to defined classes of stored content objects. The object policy mechanism may classify stored content objects into object groups or policy targets. The object policy mechanism may also define metric thresholds and event triggers as policy conditions. The object policy mechanism may further apply replacement policy algorithms or defined policy actions against a class of stored content objects. The media replacement policy rules are enforced at edge content storage repositories in the communication network. A computing device for carrying out the method, and a method for creating, reading, updating, and deleting policy elements and managing policy engine operations, are also provided. | 03-04-2010 |
20100077152 | PRIMARY-SECONDARY CACHING SCHEME TO ENSURE ROBUST PROCESSING TRANSITION DURING MIGRATION AND/OR FAILOVER - Scores are maintained usable by a behavioral targeting service. Each of a plurality of scoring engine partitions is provided events (first events) for at least one of the particular non-overlapping subsets of the users, and at least one particular scoring engine partition is also provided events (second events) for at least an additional one of said particular non-overlapping subsets of the users. The event indications are processed to determine updated scoring data indicative of behavior of the users represented by the detected events relative to the at least one online service and the updated scoring data are written to a persistent scoring engine storage. The particular scoring engine provides updated scores to the persistent scoring engine storage according to a first writeback caching scheme for updated scores determined from the first events and according to a second writeback caching scheme for updated scores determined from the second events. The time-to-live parameters are controlled for the first writeback caching scheme independently of controlling time-to-live parameters for the second writeback caching scheme. | 03-25-2010 |
20100082907 | System For And Method Of Data Cache Managment - The present invention provides a system for and a method of data cache management. In accordance with an embodiment, of the present invention, a method of cache management is provided. A request for access to data is received. A sample value is assigned to the request, the sample value being randomly selected according to a probability distribution. The sample value is compared to another value. The data is selectively stored in the cache based on results of the comparison. | 04-01-2010 |
20100138613 | Data Caching - The invention relates to a method for improving caching efficiency in a computing device. It utilises metadata, that describes attributes of the data to which it relates, to determine an appropriate caching strategy for the data. The caching strategy may be based on the type of the data, and/or on the expected access of the data. | 06-03-2010 |
20100153650 | Victim Cache Line Selection - A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order. | 06-17-2010 |
20100153651 | Efficient use of memory and accessing of stored records - Memory is used, including by receiving at a processor an indication that a first piece of metadata associated with a set of backup data is required during a block based backup and/or restore. The processor is used to retrieve from a metadata store a set of metadata that includes the first piece of metadata and one or more additional pieces of metadata included in the metadata store in an adjacent location that is adjacent to a first location in which the first piece of metadata is stored in the metadata store, without first determining whether the one or more additional pieces of metadata are currently required. The retrieved set of metadata is stored in a cache. | 06-17-2010 |
20100161905 | Latency Reduction for Cache Coherent Bus-Based Cache - In one embodiment, a system comprises a plurality of agents coupled to an interconnect and a cache coupled to the interconnect. The plurality of agents are configured to cache data. A first agent of the plurality of agents is configured to initiate a transaction on the interconnect by transmitting a memory request, and other agents of the plurality of agents are configured to snoop the memory request from the interconnect. The other agents provide a response in a response phase of the transaction on the interconnect. The cache is configured to detect a hit for the memory request and to provide data for the transaction to the first agent prior to the response phase and independent of the response. | 06-24-2010 |
20100235582 | METHOD AND MECHANISM FOR DELAYING WRITING UPDATES TO A DATA CACHE - A novel and useful mechanism and method for writing data updates to a data cache subsystem of a storage controller. Updates received by the storage controller requiring storage allocation on a repository volume are delayed prior to being written to the data cache subsystem. The delay is based on the storage utilization of the repository volume. As the utilization of the repository volume increases, the cache write delay increases, thereby limiting the possibility that there will still be any updates in the data cache subsystem waiting to be destaged to the repository volume when the repository volume is fully utilized. When the repository volume is fully utilized all writes to the data cache of updates that will cause destage of tracks in the repository volume are stopped, thereby causing an infinite delay. | 09-16-2010 |
20100235583 | ADAPTIVE DISPLAY CACHING - Apparatus, systems, and methods may operate to send a window copy message including changed window identification information to a remote node when metadata associated with a changed foreground window at a local node has been cached, and otherwise, to locally cache the window metadata and send the window metadata and window pixel data to the remote node. When a preselected minimum bandwidth connection is not available between the local node and the remote node, additional operations may include sending a rectangle paint message including changed rectangle identification information to the remote node when rectangle metadata associated with a changed rectangle of a designated minimum size at the local node has been cached, and otherwise, to locally cache the rectangle metadata and send the rectangle metadata and rectangle pixel data to the remote node. Additional apparatus, systems, and methods are disclosed. | 09-16-2010 |
20100250857 | CACHE CONTROLLING APPARATUS, INFORMATION PROCESSING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM ON OR IN WHICH CACHE CONTROLLING PROGRAM IS RECORDED - A technique for managing a cache memory for temporarily retaining data read out from a main memory so as to be used by a processing section is disclosed. The cache memory is managed using a tag memory and utilized by a write-through method. The cache controlling apparatus includes a supervising section adapted to supervise accessing time to the cache memory, and a refreshing section adapted to read out data on one or more cache lines of the cache memory from the main memory again in response to a result of the supervision by the supervising section and retain the read out data into the cache memory. | 09-30-2010 |
20100262785 | Method and System for an Extensible Caching Framework - Systems and methods which provide an extensible caching framework are disclosed. These systems and methods may provide a caching framework which can evaluate individual parameters of a request for a particular piece of content. Modules capable of evaluating individual parameters of an incoming request may be added and removed from this framework. When a request for content is received, parameters of the request can be evaluated by the framework and a cache searched for responsive content based upon this evaluation. If responsive content is not found in the cache, responsive content can be generated and stored in the cache along with associated metadata and a signature formed by the caching framework. This signature may aid in locating this content when a request for similar content is next received. | 10-14-2010 |
20100281222 | CACHE SYSTEM AND CONTROLLING METHOD THEREOF - A cache system and a method for controlling the cache system are provided. The cache system includes a plurality of caches, a buffer module, and a migration selector. Each of the caches is accessed by a corresponding processor. Each of the caches includes a plurality of cache sets and each of the cache sets includes a plurality of cache lines. The buffer module is coupled to the caches for receiving and storing data evicted due to conflict miss from a source cache line of a source cache set of a source cache among the caches. The migration selector is coupled to the caches and the buffer module. The migration selector selects, from all the cache sets, a destination cache set of a destination cache among the caches according to a predetermined condition and causing the evicted data to be sent from the buffer module to the destination cache set. | 11-04-2010 |
20100281223 | SELECTIVELY SECURING DATA AND/OR ERASING SECURE DATA CACHES RESPONSIVE TO SECURITY COMPROMISING CONDITIONS - Techniques are generally described for methods, systems, data processing devices and computer readable media configured to decrypt data to be stored in a data cache when a particular condition indicative of user authentication or data security has occurred. The described techniques may also be arranged to terminate the storage of decrypted data in the cache when a particular condition that may compromise the security of the data is detected. The describe techniques may further be arranged to erase the decrypted data stored in the cache when a particular condition that may compromise the security of the data is detected. | 11-04-2010 |
20100293335 | Cache Management - A method for cache management in an environment based on Common Information Model is described. Cache elements in the cache are associated with a time attribute and historical data. Cache elements having a time attribute lying in a certain range are polled for from the server and updated at predetermined time points. A new time attribute is calculated for each cache element based on its historical data and this new time attribute assists in adapting the polling frequency for the cache element to its importance and change characteristics. Asynchronous notifications from the server preempt the polling based on the time attribute for a cache element and instead, polling for the cache element is based on the asynchronous notification. A system for cache management includes a client and a server, the client having a cache that is managed based on each cache element's importance and change characteristics. | 11-18-2010 |
20100293336 | SYSTEM AND METHOD OF INCREASING CACHE SIZE - A system and method for increasing cache size is provided. Generally, the system contains a storage device having storage blocks therein and a memory. A processor is also provided, which is configured by the memory to perform the steps of: categorizing storage blocks within the storage device as within a first category of storage blocks if the storage blocks that are available to the system for storing data when needed; categorizing storage blocks within the storage device as within a second category of storage blocks if the storage blocks contain application data therein; and categorizing storage blocks within the storage device as within a third category of storage blocks if the storage blocks are storing cached data and are available for storing application data if no first category of storage blocks are available to the system. | 11-18-2010 |
20100325361 | METHOD FOR CONTROLLING CACHE - A computer-implemented method, apparatus, and computer program-product for controlling cache. The method includes the steps of assigning a value corresponding to a transaction to a memory object that is created while a computer application is processing the transaction; adding the assigned value as a transaction flag value to a flag area of a cache array in accordance with the storage of the memory object in the cache; registering the corresponding transaction flag value as a victim candidate at the completion of the transaction; and in response to eviction of a cache line, preferentially evicting a cache line having the transaction flag value registered as the victim candidate. | 12-23-2010 |
20100325362 | System and Method For Providing Conditional access to Server-based Applications From Remote Access Devices - Systems and methods are provided for providing users at remote access devices with conditional access to server-based applications. Requests for access to server-based applications (e.g., requests to launch or obtain data associated with the server-based applications) by remote access devices may be prevented or allowed based on device compliance with one or more policies including whether data-retention prevention code can be downloaded to and operational on the remote access devices. The data-retention prevention code may be used to both determine whether data can be automatically deleted from a cache or file directory at the remote access device and to delete potentially retention-sensitive data once the data is downloaded to the remote access device from the server-based application. | 12-23-2010 |
20110004730 | CACHE MEMORY DEVICE, PROCESSOR, AND CONTROL METHOD FOR CACHE MEMORY DEVICE - A cache memory device that connects an instruction controlling unit outputting a memory access request for requesting data and a storage device storing data, the cache memory device including: a data memory unit that holds data for each cache line, a tag memory unit that holds, for each cache line linked with a cache line of the data memory unit, tag addresses specifying storage positions of data covered by the memory access request at the storage device and status data indicating states of the data of the data memory unit corresponding to the tag addresses, a search unit that searches for a cache line of the tag memory unit corresponding to an index address included in the memory access request, a comparison unit that compares a tag address held in the found cache line of the tag memory unit and a tag address included in the memory access request and, when the two do not match, detects a “cache miss” and reads out the status information of the found cache line, and a controlling unit that, when the comparison unit detects a cache miss, requests data covered by the memory access request to the storage device and, when the cache line storing the data requested at the storage device is not present in the data memory unit, stops the supply of a clock to the data memory unit based on the status information of the cache line that the comparison unit read out. | 01-06-2011 |
20110010505 | RESOURCE MANAGEMENT CACHE TO MANAGE RENDITIONS - A resource management cache of a computing device receives a request for an item. The item may include any type of content, such as an image or a video. A rendition for the item is determined. The item may be stored in a plurality of renditions for retrieval. The resource management cache can send one or more requests to one or more sources for the rendition. The sources may include remote sources and also a local source. If a source responds with an indication the rendition is available, the rendition is sent to and received at the computing device. If no sources respond with an indication the rendition is available, the resource management cache may send a message asking if a source can generate the rendition from another rendition of the item. The rendition may be generated and it is sent to and received at the resource management cache. | 01-13-2011 |
20110016276 | SYSTEM AND METHOD FOR CACHE MANAGEMENT - Aspects of the invention relate to improvements to the Least Recently Used (LRU) cache replacement method. Weighted LRU (WLRU) and Compact Weighted LRU (CWLRU) are CPU cache replacement methods that have superior hit rates to LRU replacement for programs with poor locality, such as network protocols and applications. WLRU assigns weights to cache lines and makes replacement decision by comparing weights. When a cache line is first brought into the cache, it is assigned an initial weight. Weights of cache lines in WLRU increase when hit and decrease when not hit. Weights in WLRU also have upper limits, and the weight of a cache line never increases beyond the upper limit. CWLRU is a more space-efficient implementation of WLRU. Compared to WLRU, CWLRU uses fewer bits per cache line to store the weight. | 01-20-2011 |
20110055488 | HORIZONTALLY-SHARED CACHE VICTIMS IN MULTIPLE CORE PROCESSORS - A processor includes multiple processor core units, each including a processor core and a cache memory. Victim lines evicted from a first processor core unit's cache may be stored in another processor core unit's cache, rather than written back to system memory. If the victim line is later requested by the first processor core unit, the victim line is retrieved from the other processor core unit's cache. The processor has low latency data transfers between processor core units. The processor transfers victim lines directly between processor core units' caches or utilizes a victim cache to temporarily store victim lines while searching for their destinations. The processor evaluates cache priority rules to determine whether victim lines are discarded, written back to system memory, or stored in other processor core units' caches. Cache priority rules can be based on cache coherency data, load balancing schemes, and architectural characteristics of the processor. | 03-03-2011 |
20110060881 | Asynchronous Cache Refresh for Systems with a Heavy Load - A method and system to refresh a data entry in a cache before the data entry expires. The system includes a client computing system coupled to a server via a network connection. In response to a request for data access, the client computing system locates a data entry in a cache and determines whether the data entry in the cache has exceeded a refresh timeout since a last update of the data entry. If the data entry in the cache has exceeded the refresh timeout, the client computing system retrieves the data entry found in the cache in response to the request without waiting for the data entry to be refreshed, and requests a refresh of the data entry from the server via the network connection. | 03-10-2011 |
20110087844 | CONTENT NETWORK GLOBAL REPLACEMENT POLICY - This invention is related to content delivery systems and methods. In one aspect of the invention, a content provider controls a replacement process operating at an edge server. The edge server services content providers and has a data store for storing content associated with respective ones of the content providers. A content provider sets a replacement policy at the edge server that controls the movement of content associated with the content provider, into and out of the data store. In another aspect of the invention, a content delivery system includes a content server storing content files, an edge server having cache memory for storing content files, and a replacement policy module for managing content stored within the cache memory. The replacement policy module can store portions of the content files at the content server within the cache memory, as a function of a replacement policy set by a content owner. | 04-14-2011 |
20110113201 | GARBAGE COLLECTION IN A CACHE WITH REDUCED COMPLEXITY - Garbage collection associated with a cache with reduced complexity. In an embodiment, a relative rank is computed for each cache item based on relative frequency of access and relative non-idle time of cache entry compared to other entries. Each item having a relative rank less than a threshold is considered a suitable candidate for replacement. Thus, when a new item is to be stored in a cache, an entry corresponding to an identified item is used for storing the new item. | 05-12-2011 |
20110119449 | APPLICATION INFORMATION CACHE - A request for application information can be received from an application running in a process. The application information can be requested from an information repository, and received back from the repository in a first format. The application information can be converted to a second format, and passed to the application in the second format. In addition, the application information can be saved in the second format in a cache in the process. Also, when application information has been cached in response to a request for the information for a first user object, and a subsequent request for the application information for a second user object is received, it can be determined whether the second user object is authorized to access the application information. If so, then the application information can be fetched from the cache and returned for use by the second user object. | 05-19-2011 |
20110131379 | PROCESSOR AND METHOD FOR WRITEBACK BUFFER REUSE - A processor may include a writeback configured to perform a first writeback operation to store corresponding writeback data back to a lower-level memory upon eviction of the writeback data, and a writeback buffer configured to store the writeback data after the writeback data has been evicted from the writeback cache and before the writeback data has been sent to the lower-level memory. After the writeback data has been sent from the writeback buffer to the lower-level memory, and before the lower-level memory has acknowledged completion of the first writeback operation, the writeback cache may perform a second writeback operation to store different writeback data in the writeback buffer in response to eviction of the different writeback data, such that a total size of the writeback data for the concurrently outstanding writeback operations exceeds a total size of writeback data that the writeback buffer is capable of concurrently storing. | 06-02-2011 |
20110138129 | CACHE MANAGEMENT FOR A NUMBER OF THREADS - The illustrative embodiments provide a method, a computer program product, and an apparatus for managing a cache. A probability of a future request for data to be stored in a portion of the cache by a thread is identified for each of the number of threads to form a number of probabilities. The data is stored with a rank in a number of ranks in the portion of the cache responsive to receiving the future request from the thread in the number of threads for the data. The rank is selected using the probability in the number of probabilities for the thread. | 06-09-2011 |
20110138130 | PROCESSOR AND METHOD OF CONTROL OF PROCESSOR - A processor includes: a processing unit that has a first unit; a second unit that holds part of the data held by the first unit; a third unit that receives from the processing unit a first request including first attribute information for obtaining a first logical value and a second request including second attribute information for obtaining a second logical value and that holds the first request until receiving a completion notification of the first request or holds the second request until receiving a completion notification of the second request; and a control unit that receives the first and second requests from the third unit and, replaces the first attribute information by the second attribute information when data of the addresses corresponding to the first and second request are not in the second unit, and supplies the completion notification for the second request to the first unit. | 06-09-2011 |
20110138131 | Probabilistic Offload Engine For Distributed Hierarchical Object Storage Devices - A method and system having a probabilistic offload engine for distributed hierarchical object storage devices is disclosed. According to one embodiment, a system comprises a first storage system and a second storage system in communication with the first storage system. The first storage system and the second storage system are key/value based object storage devices that store and serve objects. The first storage system and the second storage system execute a probabilistic algorithm to predict access patterns. The first storage system and the second storage system execute a probabilistic algorithm to predict access patterns and minimize data transfers between the first storage system and the second storage system. | 06-09-2011 |
20110153949 | DELAYED REPLACEMENT OF CACHE ENTRIES - A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry. | 06-23-2011 |
20110153950 | Cache memory, cache memory system, and method program for using the cache memory - A cache memory includes: a plurality of MSHRs (Miss Status/Information Holding Registers); a memory access identification unit that identifies a memory access included in an accepted memory access request; and a memory access association unit that associates a given memory access with the MSHR that is used when the memory access turns out to be a cache miss and determines, on the basis of the association, a candidate for the MSHR that is used by the memory access identified by the access identification unit. | 06-23-2011 |
20110161597 | Combined Memory Including a Logical Partition in a Storage Memory Accessed Through an IO Controller - A computer system having a combined memory. A first logical partition of the combined memory is a main memory region in a storage memory. A second logical partition of the combined memory is a direct memory region in a main memory. A memory controller comprising a storage controller is configured to receive a memory access request including a real address from a processor, determine whether the real address is for the first logical partition or for the second logical partition. If the address is for the first logical partition the storage controller communicates with an IO controller in the storage memory to service the memory access request. If the address is for the direct memory region, the memory controller services the memory access request in a conventional manner. | 06-30-2011 |
20110179227 | CACHE MEMORY AND METHOD FOR CACHE ENTRY REPLACEMENT BASED ON MODIFIED ACCESS ORDER - A cache memory and method for controlling the cache memory. The cache memory selects, from an access address, a unique set from among a plurality of sets, each access set including a plurality of cache entries. Each cache entry holds unit data for caching. The cache memory holds, for each of the cache entries, order data that indicates an access order of the cache entries in each set, and replaces a cache entry that is oldest in the access order. The cache memory modifies the order data regardless of an actual access order, and selects, based on the modified order data, a cache entry to be replaced. | 07-21-2011 |
20110191544 | Data Storage and Access - A data cache wherein contents of the cache are arranged and organised according to a hierarchy. When a member of a first hierarchy is accessed, all contents of that member are copied to the cache. The cache may be arranged according to folders which contain data or blocks of data. A process for caching data using such an arrangement is also provided for. | 08-04-2011 |
20110197032 | CACHE COORDINATION BETWEEN DATA SOURCES AND DATA RECIPIENTS - A data recipient configured to access a data source may exhibit improved performance by caching data items received from the data source. However, the cache may become stale unless the data recipient is informed of data source updates. Many subscription mechanisms are specialized for the particular data recipient and/or data source, which may cause an affinity of the data recipient for the data source, thereby reducing scalability of the data sources and/or data recipients. A cache synchronization service may accept requests from data recipients to subscribe to the data source, and may promote cache freshness by notifying subscribers when particular data items are updated at the data source. Upon detecting an update of the data source involving one or more data items, the cache synchronization service may request each subscriber of the data source to remove the stale cached representation of the updated data item(s) from its cache. | 08-11-2011 |
20110197033 | Cache Used Both as Cache and Staging Buffer - In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled. | 08-11-2011 |
20110231613 | REMOTE STORAGE CACHING - Disclosed is a storage system. A network interface device (NIC) receives network storage commands from a host. The NIC may cache the data to/from the storage commands in a solid-state disk. The NIC may respond to future network storage command by supplying the data from the solid-state disk rather than initiating a network transaction. | 09-22-2011 |
20110238919 | CONTROL OF PROCESSOR CACHE MEMORY OCCUPANCY - Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described. | 09-29-2011 |
20110307666 | DATA CACHING METHOD - Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged. | 12-15-2011 |
20110320730 | NON-BLOCKING DATA MOVE DESIGN - A mechanism for data buffering is provided. A portion of a cache is allocated as buffer regions, and another portion of the cache is designated as random access memory (RAM). One of the buffer regions is assigned to a processor. A data block is stored to the one of the buffer regions of the cache according an instruction of the processor. The data block is stored from the one of the buffer regions of the cache to the memory. | 12-29-2011 |
20110320731 | ON DEMAND ALLOCATION OF CACHE BUFFER SLOTS - Dynamic allocation of cache buffer slots includes receiving a request to perform an operation that requires a storage buffer slot, the storage buffer slot residing in a level of storage. The dynamic allocation of cache buffer slots also includes determining availability of the storage buffer slot for the cache index as specified by the request. Upon determining the storage buffer slot is not available, the dynamic allocation of cache buffer slots includes evicting data stored in the storage buffer slot, and reserving the storage buffer slot for data associated with the request. | 12-29-2011 |
20120011323 | MEMORY SYSTEM AND MEMORY MANAGEMENT METHOD INCLUDING THE SAME - A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors. | 01-12-2012 |
20120036326 | EFFICIENTLY SYNCHRONIZING WITH SEPARATED DISK CACHES - In a method of synchronizing with a separated disk cache, the separated cache is configured to transfer cache data to a staging area of a storage device. An atomic commit operation is utilized to instruct the storage device to atomically commit the cache data to a mapping scheme of the storage device. | 02-09-2012 |
20120047330 | I/O EFFICIENCY OF PERSISTENT CACHES IN A STORAGE SYSTEM - A system and method are disclosed for improving the efficiency of a storage system. At least one application-oriented property is associated with data to be stored on a storage system. Based on the at least one application-oriented property, a manner of implementing at least one caching function in the storage system is determined. Data placement and data movement are controlled in the storage system to implement the at least one caching function. | 02-23-2012 |
20120079205 | METHOD AND APPARATUS FOR REDUCING PROCESSOR CACHE POLLUTION CAUSED BY AGGRESSIVE PREFETCHING - A method and apparatus for controlling a first and second cache is provided. A cache entry is received in the first cache, and the entry is identified as having an untouched status. Thereafter, the status of the cache entry is updated to accessed in response to receiving a request for at least a portion of the cache entry, and the cache entry is subsequently cast out according to a preselected cache line replacement algorithm. The cast out cache entry is stored in the second cache according to the status of the cast out cache entry. | 03-29-2012 |
20120084513 | CIRCUIT AND METHOD FOR DETERMINING MEMORY ACCESS, CACHE CONTROLLER, AND ELECTRONIC DEVICE - A memory access determination circuit includes a counter that switches between a first reference value and a second reference value in accordance with a control signal to generate a count value based on the first reference value or the second reference value. A controller performs a cache determination based on an address that corresponds to the count value and outputs the control signal in accordance with the cache determination. A changing unit changes the second reference value in accordance with the cache determination. | 04-05-2012 |
20120102270 | Methods and Apparatuses for Idle-Prioritized Memory Ranks - Embodiments of an apparatus to reduce memory power consumption are presented. In one embodiment, the apparatus comprises a cache memory, a memory, and a control unit. In one embodiment, the memory includes a plurality of memory ranks. The control unit is operable to select one or more memory ranks among the plurality of memory ranks to be idle-prioritized memory ranks such that access frequency to the idle-prioritized memory ranks is reduced. | 04-26-2012 |
20120102271 | CACHE MEMORY SYSTEM AND CACHE MEMORY CONTROL METHOD - The number of ways of address arrays ( | 04-26-2012 |
20120131280 | SYSTEMS AND METHODS FOR BACKING UP STORAGE VOLUMES IN A STORAGE SYSTEM - Systems and methods for backing up storage volumes are provided. One system includes a primary side, a secondary side, and a network coupling the primary and secondary sides. The secondary side includes first and second VTS including a cache and storage tape. The first VTS is configured to store a first portion of a group of storage volumes in its cache and migrate the remaining portion to its storage tape. The second VTS is configured to store the remaining portion of the storage volumes in its cache and migrate the first portion to its storage tape. One method includes receiving multiple storage volumes from a primary side, storing the storage volumes in the cache of the first and second VTS, migrating a portion of the storage volumes from the cache to storage tape in the first VTS, and migrating a remaining portion of the storage volumes from the cache to storage tape in the second VTS. | 05-24-2012 |
20120151149 | Method and Apparatus for Caching Prefetched Data - A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache entries stored in the data cache comprises data that has been loaded using fetch ahead (FA); associating an identifier with each cache entry in the subset of cache entries, the identifier indicating whether the cache entry comprises data that has been loaded using FA; and implementing a cache replacement policy for controlling replacement of at least a given cache entry in the data cache with a new cache entry as a function of the identifier associated with the given cache entry. | 06-14-2012 |
20120159078 | Protecting Data During Different Connectivity States - Aspects of the subject matter described herein relate to data protection. In aspects, during a backup cycle, backup copies may be created for files that are new or that have changed since the last backup. If external backup storage is not available, the backup copies may be stored in a cache located on the primary storage. If backup storage is available, the backup copies may be stored in the backup storage device and backup copies that were previously stored in the primary storage may be copied to the backup storage. The availability of the backup storage may be detected and used to seamlessly switch between backing up files locally and remotely as availability of the backup storage changes. | 06-21-2012 |
20120166732 | CONTENT CACHING DEVICE, CONTENT CACHING METHOD, AND COMPUTER READABLE MEDIUM - A first acquisition unit acquires each of the resources defined by the scenario, from locations depending on identifiers of the resources. A judging unit judge, when a resource having same identifier and structure as the resource acquired is existent in the cache storage, erases the resource, the identifier thereof, and the receipt time information from the cache storage, and when not existent, stores the acquired resource in association with the identifier thereof and the receipt time information of the bookmark instruction, in the cache storage. A second acquisition, when the identifiers of the resources specified by a first scenario are existent in the cache storage, acquires the resources from the cache storage according to the receipt time information corresponding to the first scenario and identifiers of the resources, and when not existent, acquires the resources from a location depending on the identifiers. | 06-28-2012 |
20120179875 | USING EPHEMERAL STORES FOR FINE-GRAINED CONFLICT DETECTION IN A HARDWARE ACCELERATED STM - A method and apparatus for fine-grained filtering in a hardware accelerated software transactional memory system is herein described. A data object, which may have an arbitrary size, is associated with a filter word. The filter word is in a first default state when no access, such as a read, from the data object has occurred during a pendancy of a transaction. Upon encountering a first access, such as a first read, from the data object, access barrier operations including an ephemeral/private store operation to set the filter word to a second state are performed. Upon a subsequent/redundant access, such as a second read, the access barrier operations are elided to accelerate the subsequent access, based on the filter word being set to the second state to indicate a previous access occurred. | 07-12-2012 |
20120185650 | CACHE DEVICE, DATA MANAGEMENT METHOD, PROGRAM, AND CACHE SYSTEM - A deleted cache determining part determines a cache data which is to be deleted from a data storing part in a case where a sum of a data amount of a data which is recorded to the data storing part and a data amount of a cache data which is stored to the data storing part and a data amount of a buffer data which is stored to the storing part is equal to or more than a predetermined threshold, and an accumulated data control part deletes the cache data which is determined by the deleted cache determining part from the data storing part. | 07-19-2012 |
20120191918 | TECHNIQUES FOR DIRECTORY SERVER INTEGRATION - Techniques for directory server integration are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for directory server integration comprising setting one or more parameters determining a range of permissible expiration times for a plurality of cached directory entries, creating, in electronic storage, a cached directory entry from a directory server, assigning a creation time to the cached directory entry, and assigning at least one random value to the cached directory entry, the random value determining an expiration time for the cached directory entry within the range of permissible expiration times, wherein randomizing the expiration time for the cached directory entry among the range of permissible expiration times for a plurality of cached directory entries reduces an amount of synchronization required between cache memory and the directory server at a point in time. | 07-26-2012 |
20120198173 | ROUTER AND MANY-CORE SYSTEM - According to one embodiment, a router manages routing of a packet transferred between a plurality of cores and at least one of cache memories to which the cores can access. The router includes an analyzer, a packet memory and a controller. The analyzer determines whether the packet is a read-packet or a write-packet. The packet memory stores at least part of the write-packet issued by one of the cores. The controller stores cache data of the write-packet and a cache address in the packet memory when the analyzer determines that the packet is the write-packet. The cache address indicates an address in which the cache data is stored. The controller outputs the cache data stored in the packet memory to the core issuing a read-request as a response data corresponding to the read packet when the analyzer determines that the packet is the read-packet and the cache address corresponding to the read-request is stored in the packet memory. | 08-02-2012 |
20120198174 | APPARATUS, SYSTEM, AND METHOD FOR MANAGING EVICTION OF DATA - An apparatus, system, and method are disclosed for managing eviction of data. A cache write module stores data on a non-volatile storage device sequentially using a log-based storage structure having a head region and a tail region. A direct cache module caches data on the non-volatile storage device using the log-based storage structure. The data is associated with storage operations between a host and a backing store storage device. An eviction module evicts data of at least one region in succession from the log-based storage structure starting with the tail region and progressing toward the head region. | 08-02-2012 |
20120203972 | MEMORY MANAGEMENT FOR OBJECT ORIENTED APPLICATIONS DURING RUNTIME - Memory management for object oriented applications during run time includes loading an object oriented application into a computer memory. The object oriented application includes a plurality of nodes in a classification tree, the nodes including key value pairs. The nodes are aggregated in the classification tree by a computer. The aggregating includes eliminating redundant keys and creating a composite node. The composite node is loaded into the computer memory. The plurality of nodes in the classification tree are removed from the computer memory in response to loading the composite node into the computer memory. | 08-09-2012 |
20120203973 | SELECTIVE CACHE-TO-CACHE LATERAL CASTOUTS - A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line. | 08-09-2012 |
20120215985 | CACHE AND A METHOD FOR REPLACING ENTRIES IN THE CACHE - A processor is provided. The processor including a cache, the cache having a plurality of entries, each of the plurality of entries having a tag array and a data array, and a remapper configured to create at least one identifier, each identifier being unique to a process of the processor, and to assign a respective identifier to the tag array for the entries related to a respective process, the remapper further configured to determine a replacement value for the entries related to each identifier. | 08-23-2012 |
20120221798 | Computer Cache System With Stratified Replacement - Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction. | 08-30-2012 |
20120233408 | INTELLIGENT WRITE CACHING FOR SEQUENTIAL TRACKS - Write caching for sequential tracks is performed by a processor device in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit. If a first track is determined to be sequential, and an earlier track is also determined to be sequential, a temporal bit associated with the earlier track is cleared to allow for destage of data of the earlier track. If a temporal bit for one of a plurality of additional tracks in one of a plurality of strides in a modified cache is determined to be not set, a stride associated with the one of the plurality of additional tracks is selected for a destage operation. If the NVS exceeds a predetermined storage threshold, a predetermined one of the plurality of strides is selected for the destage operation. | 09-13-2012 |
20120246411 | CACHE EVICTION USING MEMORY ENTRY VALUE - Embodiments are directed to efficiently determining which cache entries are to be evicted from memory and to incorporating a probability of reuse estimation in a cache entry eviction determination. A computer system with multiple different caches accesses a cache entry. The computer system determines an entry cost value for the accessed cache entry. The entry cost value indicates an amount of time the computer system is slowed down by to load the cache entry into cache memory. The computer system determines an opportunity cost value for the computing system caches. The opportunity cost value indicates an amount of time by which the computer system is slowed down while performing other operations that could have used the cache entry's cache memory space. Upon determining that the entry cost value is lower than the opportunity cost value, the computer system probabilistically evicts the cache entry from cache memory. | 09-27-2012 |
20120254547 | MANAGING METADATA FOR DATA IN A COPY RELATIONSHIP - Provided are a computer program product, system, and method for managing metadata for data in a copy relationship copied from a source storage to a target storage. Information is maintained on a copy relationship of source data in the source storage and target data in the target storage. The source data is copied from the source storage to the cache to copy to target data in the target storage indicated in the copy relationship. Target metadata is generated for the target data comprising the source data copied to the cache. An access request to requested target data comprising the target data in the cache is processed and access is provided to the requested target data in the cache. A determination is made as to whether the requested target data in the cache has been destaged to the target storage. The target metadata for the requested target data in the target storage is discarded in response to determining that the requested target data in the cache has not been destaged to the target storage. | 10-04-2012 |
20120260043 | FABRICATING KEY FIELDS - Exemplary methods, computer systems, and computer program products for fabricating key fields by a processor device in a computer environment are provided. In one embodiment, the computer environment is configured for, as an alternative to reading Count-Key-Data (CKD) data in order to change the key field, providing a hint to fabricate a new key field, thereby overwriting a previous key field and updating the CKD data. | 10-11-2012 |
20120260044 | SYSTEMS AND METHODS FOR DESTAGING STORAGE TRACKS FROM CACHE - A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes writing data to the plurality of storage tracks and incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes scan each of the storage tracks in each of multiple scan cycles, decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count. | 10-11-2012 |
20120272009 | METHODS AND APPARATUS FOR HANDLING A CACHE MISS - In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided. | 10-25-2012 |
20120278558 | Structure-Aware Caching - Techniques for structure-aware caching are provided. The techniques include decomposing a response from an origin server into one or more independently addressable objects, using a domain specific language to navigate the response to identify the one or more addressable objects and create one or more access paths to the one or more objects, and selecting a route to an object by navigating an internal structure of a cached object to discover one or more additional independently addressable objects. | 11-01-2012 |
20120297140 | EXPANDABLE DATA CACHE - A method and system for cache management in a storage device is disclosed. A portion of unused memory in the storage device is used for temporary data cache so that two levels of cache may be used (such as a permanent data cache and a temporary data cache). The storage device may manage the temporary data cache in order to maintain clean entries in the temporary data cache. In this way, the storage area associated with the temporary data cache may be immediately reclaimed and retasked for a different purpose without the need for extraneous copy operations. | 11-22-2012 |
20120297141 | IMPLEMENTING TRANSACTIONAL MECHANISMS ON DATA SEGMENTS USING DISTRIBUTED SHARED MEMORY - Systems, Methods, and Computer Program Products are provided for implementing transactional mechanisms by a plurality of procedures on data segments by using distributed shared memory (DSM) agents in a clustered file system (CFS). A new data segment is allocated and an associated cache data segment and metadata data segments, which are allocated for the new data segment and loaded into a cache and modified during the allocating of the new data segment, are added to a list of data segments modified within an associated transaction. The DSM agents assign an exclusive permission to the new data segment. | 11-22-2012 |
20120303902 | APPARATUS AND METHOD FOR MANAGING DATA STORAGE - An apparatus for controlling a log-structured data storage system, operable with a first log-structured data storage area for storing data, comprises a metadata storage component for controlling the first log-structured data storage area and comprising a second log-structured data storage area for storing metadata; and means for nesting the second log-structured data storage area for storing metadata within the first log-structured data storage area. The apparatus may further comprise at least a third log-structured data storage area for storing further metadata, and means for nesting the at least a third log-structured data storage area within the second log-structured data storage area. | 11-29-2012 |
20120311269 | NON-UNIFORM MEMORY-AWARE CACHE MANAGEMENT - An apparatus is disclosed for caching memory data in a computer system with multiple system memories. The apparatus comprises a data cache for caching memory data. The apparatus is configured to determine a retention priority for a cache block stored in the data cache. The retention priority is based on a performance characteristic of a system memory from which the cache block is cached. | 12-06-2012 |
20120324169 | INFORMATION PROCESSING DEVICE AND METHOD, AND PROGRAM - Provided is an information processing device including a holding portion of a cache link that is formed such that, when clusters are recorded on a predetermined recording medium by a FAT file system and a FAT formed by link information of the clusters is also recorded on the predetermined recording medium by the system, an entry is arranged for each of the clusters located at a predetermined interval, the entry being formed by information including the link information extracted from the FAT, an information update portion that, when updating the cache link after data is additionally written to the clusters on the recording medium, updates the information for an update target entry among entries forming the cache link, and a configuration conversion portion that removes the update target entry updated from an original position in the cache link, and connects it to an endmost position of the cache link. | 12-20-2012 |
20130007371 | Browser Storage Management - Browser storage management techniques are described. In one or more implementations, inputs are received at a computing device that specify maximum aggregate sizes of application and database caches, respectively, of browser storage to be used to locally store data at the computing device. For example, the inputs may be provided using a policy, by an administrator of the computing device, and so on. The maximum aggregate sizes are set of application and database caches, respectively, of browser storage at the computing device to the sizes specified by the inputs. | 01-03-2013 |
20130007372 | MANAGEMENT OF WRITE CACHE USING STRIDE OBJECTS - Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each of a plurality of strides in a modified cache, wherein the multi-update bit is adapted to indicate a corresponding stride is part of at least one track in a working set that refers to a group of frequently updated tracks. The plurality of strides are scanned based on a schedule to identify tracks for destaging. An operation to destage is performed on a selected track identified during the scanning, if the multi-update bit of a selected stride on the selected track is set to indicate the selected track is part of the working set and if the NVS is about 90% full or greater. | 01-03-2013 |
20130013865 | DEDUPLICATION OF VIRTUAL MACHINE FILES IN A VIRTUALIZED DESKTOP ENVIRONMENT - Techniques for deduplication of virtual machine files in a virtualized desktop environment are described, including receiving data into a page cache, the data being received from a virtual machine and indicating a write operation, and deduplicating the data in the page cache prior to committing the data to storage, the data being deduplicated in-band and in substantially real-time. | 01-10-2013 |
20130024622 | EVENT-DRIVEN REGENERATION OF PAGES FOR WEB-BASED APPLICATIONS - Systems and methods for invalidating and regenerating pages. In one embodiment, a method can include detecting content changes in a content database including various objects. The method can include causing an invalidation generator to generate an invalidation based on the modification and communicating the invalidation to a dependency manager. A cache manager can be notified that pages in a cache might be invalidated based on the modification via a page invalidation notice. In one embodiment, a method can include receiving a page invalidation notice and sending a page regeneration request to a page generator. The method can include regenerating the cached page. The method can include forwarding the regenerated page to the cache manager replacing the cached page with the regenerated page. In one embodiment, a method can include invalidating a cached page based on a content modification and regenerating pages which might depend on the modified content. | 01-24-2013 |
20130042073 | Hybrid Automatic Repeat Request Combiner and Method for Storing Hybrid Automatic Repeat Request Data - The invention provides a method for storing hybrid automatic repeat request (HARQ) data, the method including: when receiving new data of a coded block, a HARQ processor writing the new data into a high rate buffer memory (Cache) and a channel decoder; the Cache writing the new data into a data memory of the Cache or an external memory; and when receiving retransmitted data of the coded block, the HARQ processor obtaining a previous data corresponding to the retransmitted data from the data memory of the Cache or the external memory through the Cache, combining the retransmitted data and the previous data, and writing the combined data to the Cache and the channel decoder; the Cache writing the combined data into the data memory of the Cache or the external memory. The invention also provides a HARQ combiner. | 02-14-2013 |
20130061001 | SYSTEM REFRESH IN CACHE MEMORY - System refresh in a cache memory that includes generating a refresh time period (RTIM) pulse at a centralized refresh controller of the cache memory and activating a refresh request at the centralized refresh controller based on generating the RTIM pulse. The refresh request is associated with a single cache memory bank of the cache memory. A refresh grant is received and transmitted to a bank controller. The bank controller is associated with and localized at the single cache memory bank of the cache memory. | 03-07-2013 |
20130138891 | ALLOCATION ENFORCEMENT IN A MULTI-TENANT CACHE MECHANISM - Systems and methods for cache optimization are provided. The method comprises monitoring cache access rate for a plurality of cache tenants sharing same cache mechanism having an amount of data storage space, wherein a first cache tenant having a first cache size is allocated a first cache space within the data storage space, and wherein a second cache tenant having a second cache size is allocated a second cache space within the data storage space. The method further comprises determining cache profiles for at least the first cache tenant and the second cache tenant according to data collected during the monitoring; analyzing the cache profiles for the plurality of cache tenants to determine an expected cache usage model for the cache mechanism; and analyzing the cache usage model and factors related to cache efficiency or performance for the one or more cache tenants to dictate one or more occupancy constraints. | 05-30-2013 |
20130145099 | Method, System and Server of Removing a Distributed Caching Object - The present disclosure discloses a method, a system and a server of removing a distributed caching object. In one embodiment, the method receives a removal request, where the removal request includes an identifier of an object. The method may further apply consistent Hashing to the identifier of the object to obtain a Hash result value of the identifier, locates a corresponding cache server based on the Hash result value and renders the corresponding cache server to be a present cache server. In some embodiments, the method determines whether the present cache server is in an active status and has an active period greater than an expiration period associated with the object. Additionally, in response to determining that the present cache server is in an active status and has an active period greater than the expiration period associated with the object, the method removes the object from the present cache server. By comparing an active period of a located cache server with an expiration period associated with an object, the exemplary embodiments precisely locate a cache server that includes the object to be removed and perform a removal operation, thus saving the other cache servers from wasting resources to perform removal operations and hence improving the overall performance of the distributed cache system. | 06-06-2013 |
20130145100 | MANAGING METADATA FOR DATA IN A COPY RELATIONSHIP - Provided is a method for managing metadata for data in a copy relationship copied from a source storage to a target storage. Information is maintained on a copy relationship of source data in the source storage and target data in the target storage. The source data is copied from the source storage to the cache to copy to target data in the target storage indicated in the copy relationship. Target metadata is generated for the target data comprising the source data copied to the cache. An access request to requested target data comprising the target data in the cache is processed and access is provided to the requested target data in the cache. The target metadata for the requested target data in the target storage is discarded in response to determining that the requested target data in the cache has not been destaged to the target storage. | 06-06-2013 |
20130151784 | DYNAMIC PRIORITIZATION OF CACHE ACCESS - Some embodiments of the inventive subject matter are directed to determining that a memory access request results in a cache miss and determining an amount of cache resources used to service cache misses within a past period in response to determining that the memory access request results in the cache miss. Some embodiments are further directed to determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed a threshold. In some embodiments, the threshold corresponds to reservation of a given amount of cache resources for potential cache hits. Some embodiments are further directed to rejecting the memory access request in response to the determining that servicing the memory access request would increase the amount of cache resources used to service cache misses within the past period to exceed the threshold. | 06-13-2013 |
20130151785 | DIRECTORY REPLACEMENT METHOD AND DEVICE - The present invention provides a directory replacement method and device. An HA receives a data access request including a first address from a first CA, if a designated storage where a directory is located is entirely occupied by the directory, and a first directory entry corresponding to the first address is not in the directory, the HA selects a second directory entry from the directory, deletes it and adds the first directory entry into the directory; before the HA replaces the directory entry in the directory, no matter what status (for example, I status, S status or A status) a share status of a cache line corresponding to an address in the directory entry to be replaced is, the HA does not need to request a corresponding CA to perform an invalidating operation on data, but directly replaces the directory entry in the directory, thereby improving replacement efficiency. | 06-13-2013 |
20130159630 | SELECTIVE CACHE FOR INTER-OPERATIONS IN A PROCESSOR-BASED ENVIRONMENT - The present invention provides embodiments of methods and apparatuses for selective caching of data for inter-operations in a heterogeneous computing environment. One embodiment of a method includes allocating a portion of a first cache for caching for two or more processing elements and defining a replacement policy for the allocated portion of the first cache. The replacement policy restricts access to the first cache to operations associated with more than one of the processing elements. | 06-20-2013 |
20130173862 | METHOD FOR CLEANING CACHE OF PROCESSOR AND ASSOCIATED PROCESSOR - A method for cleaning a cache of a processor includes: generating a specific command according to a request, wherein the specific command includes an operation command, a first field and a second field; obtaining an offset and a starting address according to the first field and the second field; selecting a specific segment from the cache according to the starting address and the offset; and cleaning data stored in the specific segment. | 07-04-2013 |
20130191598 | DEVICE, SYSTEM AND METHOD OF ACCESSING DATA STORED IN A MEMORY - Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the point from the detected entry. Other embodiments are described and claimed. | 07-25-2013 |
20130198460 | INFORMATION PROCESSING DEVICE, MEMORY MANAGEMENT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - An information processing device includes a memory and a processor coupled to the memory, wherein the processor executes a process comprising selecting data included in a same file as deletion target data from the memory when deleting the data cached in the memory at the caching from the memory and deleting the deletion target data and the data selected at the selecting, from the memory. | 08-01-2013 |
20130198461 | MANAGING TRACK DISCARD REQUESTS TO INCLUDE IN DISCARD TRACK MESSAGES - Provided is a method for managing track discard requests. A backup copy of a track in a cache is maintained in a cache backup device. A track discard request is generated to discard tracks in the cache backup device removed from the cache. Track discard requests are queued in a discard track queue. If a predetermined number of track discard requests are queued in the discard track queue while processing in a discard multi-track mode, one discard multiple tracks message is sent to the cache backup device indicating the tracks indicated in the queued predetermined number of track discard requests to instruct the cache backup device to discard the tracks indicated in the discard multiple tracks message. If a predetermined number of periods of inactivity while processing in the discard multi-track mode, processing the track discard requests is switched to a discard single track mode. | 08-01-2013 |
20130205093 | MANAGEMENT OF POINT-IN-TIME COPY RELATIONSHIP FOR EXTENT SPACE EFFICIENT VOLUMES - A storage controller receives a request to establish a point-in-time copy operation by placing a space efficient source volume in a point-in-time copy relationship with a space efficient target volume, wherein subsequent to being established the point-in-time copy operation is configurable to consistently copy the space efficient source volume to the space efficient target volume at a point in time. A determination is made as to whether any track of an extent is staging into a cache from the space efficient target volume or destaging from the cache to the space efficient target volume. In response to a determination that at least one track of the extent is staging into the cache from the space efficient target volume or destaging from the cache to the space efficient target volume, release of the extent from the space efficient target volume is avoided. | 08-08-2013 |
20130219124 | EFFICIENT DISCARD SCANS - A plurality of tracks is examined for meeting criteria for a discard scan. In lieu of waiting for a completion of a track access operation, at least one of the plurality of tracks is marked for demotion. An additional discard scan may be subsequently performed for tracks not previously demoted. The discard and additional discard scans may proceed in two phases. | 08-22-2013 |
20130227220 | Data Storage Device and Method of Managing a Cache in a Data Storage Device - A data storage device is provided. The data storage device includes a data storage medium having a plurality of data blocks, a cache having a plurality of cache blocks, wherein each cache block is identified by a cache block address, a cache control memory including a memory element for each data block configured to store the cache block address of the cache block in which data of the data block is written. | 08-29-2013 |
20130254489 | SYSTEMS AND METHODS FOR CACHE LINE REPLACEMENT - A computer readable storage medium includes instructions that, when executed by a processor, cause the processor to receive an index value included in a cache invalidate by index instruction, an encoded way value, and an incrementer output value. The instructions further cause the processor to assign the index value as an identifier value in response to receiving the cache invalidate by index instruction. The identifier value indicates a cache line for replacement. | 09-26-2013 |
20130254490 | DELAYED REPLACEMENT OF TLB ENTRIES - A cache entry replacement unit can delay replacement of more valuable entries by replacing less valuable entries. When a miss occurs, the cache entry replacement unit can determine a cache entry for replacement (“a replacement entry”) based on a generic replacement technique. If the replacement entry is an entry that should be protected from replacement (e.g., a large page entry), the cache entry replacement unit can determine a second replacement entry. The cache entry replacement unit can “skip” the first replacement entry by replacing the second replacement entry with a new entry, if the second replacement entry is an entry that should not be protected (e.g., a small page entry). The first replacement entry can be skipped a predefined number of times before the first replacement entry is replaced with a new entry. | 09-26-2013 |
20130254491 | CONTROLLING A PROCESSOR CACHE USING A REAL-TIME ATTRIBUTE - A processor device has a cache, and a cache controller that manages the replacement of a number of cache lines in the cache, in accordance with a replacement policy. A storage location is to be configured to define a memory map having a cacheable region, an un-cacheable region, and a real time region. Upon a cache miss of an address that lies in the real time region, the cache controller responds by loading content at the address into a cache line, and then prevents the cache line from aging as would a cache line that is in the cacheable region. Other embodiments are also described and claimed. | 09-26-2013 |
20130262773 | INFORMATION PROCESSING APPARATUS AND CONTROL METHOD OF INFORMATION PROCESSING APPARATUS - An information processing apparatus includes a first arithmetic processing unit, a second arithmetic processing unit that is connected to a main storage, and a third arithmetic processing unit. The first arithmetic processing unit includes a cache memory that retains therein data. The second arithmetic processing unit includes a processing unit that notifies, when a read request for the data from the third arithmetic processing unit is not being executed when the replacement request is received, the first arithmetic processing unit of a completion notification indicating that the data has been written back to the main storage and the replacement process is completed and that notifies, when the read request is being executed when the replacement request is received, the first arithmetic processing unit of the completion notification after the read request has ended. | 10-03-2013 |
20130262774 | METHOD AND APPARATUS TO MANAGE OBJECT BASED TIER - Exemplary embodiments provide a technique to manage object based tier to improve allocation of media to unallocated area. In one embodiment, a method of allocating an area of a logical volume to an unallocated area of a virtual volume for a write command comprises: calculating an object location of an object based on the write command and an object allocation information, the write command containing a virtual volume name and a virtual volume address of a virtual volume; selecting a tier from a plurality of tiers based on the calculated object location and an object and tier definition information; selecting a media type from a plurality of media types based on the selected tier and a tier and media definition information; and selecting a logical volume from a plurality of logical volumes based on the virtual volume specified by the write command, the object allocation information, a pool information, and the selected media type. | 10-03-2013 |
20130268734 | CACHE HANDLING IN A DATABASE SYSTEM - Embodiments relate to cache handling in a database system. An aspect includes controlling operations of a set of caches in the database system and determining whether a value of a cache quality parameter of a first cache out of the set of caches meets a cache image creation criterion relating to the first cache. Moreover, an aspect includes selecting at least one cache entry from the first cache, if a value of a related cache entry parameter meets a cache entry criterion, and if the value of the cache quality parameter of the first cache exceeds the predefined value of the cache image creation criterion, and creating a cache image based on the selected at least one cache entry and storing the cache image for further use. | 10-10-2013 |
20130275684 | ACCESSING AND MANAGING CODE TRANSLATIONS IN A MICROPROCESSOR - In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries. | 10-17-2013 |
20130290641 | ELASTIC CACHING FOR JAVA VIRTUAL MACHINES - A mechanism is provided for managing memory of a runtime environment executing on a virtual machine. The mechanism includes an elastic cache made of objects within heap memory of the runtime environment. When the runtime environment and virtual machine are not experiencing memory pressure from a hypervisor, the objects of the elastic cache may be used to temporarily store application-level cache data from applications running within the runtime environment. When memory pressure from the hypervisor is exerted, the objects of the elastic cache are re-purposed to inflate a memory balloon within heap memory of the runtime environment. | 10-31-2013 |
20130297881 | PERFORMING ZERO-COPY SENDS IN A NETWORKED FILE SYSTEM WITH CRYPTOGRAPHIC SIGNING - A method and system for sending data in a file system that uses cryptographic signatures to protect data integrity. A computer system calculates a signature based on the content of a page of a memory. The memory is shared by processes that run on the computer system. The computer system write-protects the page while the page is used for calculation of the signature. When a first process attempts to modify the page, a page fault is triggered. In response to the page fault, the content of the page in memory is copied to a new page in the memory. The new page is accessible by the processes. Access to the page by the first process is redirected to the new page. Subsequent to the page fault, access to the page by the second process is also redirected to the new page. | 11-07-2013 |
20130297882 | CACHE MEMORY DEVICE, CONTROL UNIT OF CACHE MEMORY, INFORMATION PROCESSING APPARATUS, AND CACHE MEMORY CONTROL METHOD - A cache memory device including a cache memory that includes a plurality of entries and includes at least one block including data and a status representing a status of the data for each entry and a control unit that performs replacement of the data on each block of the cache memory, wherein the control unit includes a counter that counts the number of replacements by which the data is replaced in each entry for each entry and a switching unit that switches a replacement scheme of the data according to the number of replacements. | 11-07-2013 |
20130297883 | EFFICIENT SUPPORT OF SPARSE DATA STRUCTURE ACCESS - Method and apparatus to efficiently organize data in caches by storing/accessing data of varying sizes in cache lines. A value may be assigned to a field indicating the size of usable data stored in a cache line. If the field indicating the size of the usable data in the cache line indicates a size less than the maximum storage size, a value may be assigned to a field in the cache line indicating which subset of the data in the field to store data is usable data. A cache request may determine whether the size of the usable data in a cache line is equal to the maximum data storage size. If the size of the usable data in the cache line is equal to the maximum data storage size the entire stored data in the cache line may be returned. | 11-07-2013 |
20130326148 | BUCKET-BASED WEAR LEVELING METHOD AND APPARATUS - A method for memory management is provided for a memory including a plurality of pages. The method comprises assigning in-use pages to in-use buckets according to use counts. The in-use buckets include a low in-use bucket for a lowest range of use counts, and a high in-use bucket for a highest range of use counts. The method comprises assigning free pages to free buckets according to use counts. The free buckets include a low free bucket for a lowest range of use counts, and a high free bucket for a highest range of use counts. The method maintains use counts for in-use pages. On a triggering event for a current in-use page, the method determines whether the use count of the current in-use page exceeds a hot swap threshold, and if so moves data in the current in-use page to a lead page in the low free bucket. | 12-05-2013 |
20130339617 | AUTOMATIC PATTERN-BASED OPERAND PREFETCHING - Embodiments relate to automatic pattern-based operand prefetching. An aspect includes receiving, by prefetch logic in a processor, an operand cache miss from a pipeline of the processor. Another aspect includes determining that an entry in a history table corresponding to the operand cache miss exists based on an instruction address of the operand cache miss. Yet another aspect includes, based on determining that the entry corresponding to the operand cache miss exists in the history table, issuing a prefetch instruction for a second operand based on the determined entry in the history table, and writing the determined entry into a miss buffer. | 12-19-2013 |
20130339618 | AVOIDING ABORTS DUE TO ASSOCIATIVITY CONFLICTS IN A TRANSACTIONAL ENVIRONMENT - Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set. | 12-19-2013 |
20130339619 | SYSTEM FOR REDUCING MEMORY LATENCY IN PROCESSOR - A method for reducing memory latency in a processor includes identifying an independent instruction (or cache miss instruction) and corresponding dependent instructions from a re-circulating issue window (RIW) when a cache miss is encountered. The cache miss instruction and corresponding dependent instructions are moved to a re-circulating issue buffer (RIB) and moved back to the RIW from the RIB for processing when the cache miss is resolved. | 12-19-2013 |
20130339620 | Providing Cache Replacement Notice Using a Cache Miss Request - A computing device has an interface and a processor. The interface is configured to receive a cache miss request from a cache memory, and the processor is configured to identify data that is being removed from the cache memory based at least in part on information obtained from the cache miss request. In another embodiment, a computing device has a memory, a first interface, a processor, and a second interface. The processor is configured to generate a cache miss request when it is determined that data identified in a cache request received through the first interface is not stored in the memory, and the second interface is configured to send the cache miss request to a cache memory. The cache miss request optionally includes an indication of the data identified in the cache request and an indication of a portion of the cached data that is being removed from the memory. | 12-19-2013 |
20130339621 | ADDRESS RANGE PRIORITY MECHANISM - Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a process using a virtual address of the data. The requested data may be assigned a priority by a component in a computer system called an address range priority assigner (ARP). The ARP may assign a particular priority to the requested data if the virtual address of the requested data is within a particular range of virtual addresses. The particular priority assigned may be high priority and the particular range of virtual addresses may be smaller than a cache's capacity. | 12-19-2013 |
20130346700 | SYSTEMS AND METHODS FOR MANAGING MEMORY - A method of accessing data in a shared-memory, parallel-processing computing system, comprises, on a first processing unit, receiving a reference for a data structure stored in a memory and a first value of a generation attribute associated with the data structure, waiting to receive an exclusive lock on the data structure, obtaining an exclusive lock on the data structure, receiving a second value of a second generation attribute associated with the data structure; and accessing the data structure only if the first generation attribute value and the second generation attribute value are identical. | 12-26-2013 |
20140006717 | SIGNATURE BASED HIT-PREDICTING CACHE | 01-02-2014 |
20140019687 | METHOD FOR INCREASING CACHE SIZE - A method for increasing storage space in a system containing a block data storage device, a memory, and a processor is provided. Generally, the processor is configured by the memory to tag metadata of a data block of the block storage device indicating the block as free, used, or semifree. The free tag indicates the data block is available to the system for storing data when needed, the used tag indicates the data block contains application data, and the semifree tag indicates the data block contains cache data and is available to the system for storing application data type if no blocks marked with the free tag are available to the system. | 01-16-2014 |
20140025899 | Efficiently Updating and Deleting Data in a Data Storage System - A method of storing data is disclosed. The method is performed on a data storage server having one or more processors and memory storing one or more programs for execution by the one or more processors. The data storage server receives a first and second data request, the requests including a first and second range of one or more keys and an associated first and second value respectively. The data storage server identifies one or more overlap points associated with the first range and the second range. For each of the overlap points, the data storage server then creates data items including ranges of keys, the ranges of each data item including one or more keys that are either: (a) the keys between a terminal key of the first or second range and the overlap point, or (b) the keys between two adjacent overlap points. | 01-23-2014 |
20140025900 | Combined Transparent/Non-Transparent Cache - In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion. | 01-23-2014 |
20140032849 | CACHE MANAGER FOR SEGMENTED MULTIMEDIA AND CORRESPONDING METHOD FOR CACHE MANAGEMENT - The invention concerns a cache manager ( | 01-30-2014 |
20140040559 | SYSTEM AND METHOD OF CACHING INFORMATION - A system and method is provided wherein, in one aspect, a currently-requested item of information is stored in a cache based on whether it has been previously requested and, if so, the time of the previous request. If the item has not been previously requested, it may not be stored in the cache. If the subject item has been previously requested, it may or may not be cached based on a comparison of durations, namely (1) the duration of time between the current request and the previous request for the subject item and (2) for each other item in the cache, the duration of time between the current request and the previous request for the other item. If the duration associated with the subject item is less than the duration of another item in the cache, the subject item may be stored in the cache. | 02-06-2014 |
20140047187 | ADJUSTMENT OF THE NUMBER OF TASK CONTROL BLOCKS ALLOCATED FOR DISCARD SCANS - A controller receives a request to perform a release space operation. A determination is made that a new discard scan has to be performed on a cache, in response to the received request to perform the release space operation. A determination is made as to how many task control blocks are to be allocated to the perform the new discard scan, based on how many task control blocks have already been allocated for performing one or more discard scans that are already in progress. | 02-13-2014 |
20140047188 | Method and Multi-Core Communication Processor for Replacing Data in System Cache - A method for replacing data in a system cache includes obtaining, by the system cache, an access statistics value corresponding to each piece of header data in the system cache, wherein the access statistics value corresponding to the header data represents a difference of the predetermined number of access times of the header data minus the number of times that the header data has been accessed by central processing units (CPUs); obtaining, by the system cache according to the access statistics value corresponding to each piece of header data, header data to be transferred; and transferring, by the system cache, the header data, which is to be transferred, to an external memory. | 02-13-2014 |
20140052924 | Selective Memory Scrubbing Based on Data Type - A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache). | 02-20-2014 |
20140059297 | SYSTEM CACHE WITH STICKY ALLOCATION - Methods and apparatuses for implementing a system cache within a memory controller. Multiple requesting agents may allocate cache lines in the system cache, and each line allocated in the system cache may be associated with a specific group ID. Also, each line may have a corresponding sticky state which indicates if the line should be retained in the cache. The sticky state is determined by an allocation hint provided by the requesting agent. When a cache line is allocated with the sticky state, the line will not be replaced by other cache lines fetched by any other group IDs. | 02-27-2014 |
20140068194 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND CONTROL METHOD OF PROCESSOR - A processor is includes cache memory; an arithmetic processing section that a load request loading an object data stored at a memory to the cache memory; a cache control part patent a process corresponding to the received load request; a memory management part which requests the object data corresponding to the request from the cache control part and header information containing information indicating whether or not the object data is a latest for the memory, and receives the header information responded by the memory; and a data management part that manages a write control of the data to the cache memory, and receives the object data responded by the memory based on the request. The requested data is transmitted from the memory to the data management part held by a CPU node without being intervened by the memory management part. | 03-06-2014 |
20140068195 | METHOD TO INCREASE PERFORMANCE OF NON-CONTIGUOUSLY WRITTEN SECTORS - A method of managing data in a cache upon a cache write operation includes determining a number of non-contiguously written sectors on a track in the cache and comparing the number with a threshold number. If the number exceeds the threshold number, a full background stage operation is issued to fill the non-contiguously written sectors with unmodified data from a storage medium and the full track is then destaged. A corresponding system includes a cache manager module operating on the storage subsystem. Upon a determination that a cache write operation on a track has taken place, the cache manager module determines a number of non-contiguously written sectors on the track, compares the number with a predetermined threshold number, issues a background stage operation to fill the non-contiguously written sectors with unmodified data from a storage medium if the number exceeds the threshold number, and then destages the full track. | 03-06-2014 |
20140075122 | DURABLE TRANSACTIONS WITH STORAGE-CLASS MEMORY - A system for conducting memory transactions includes a non-volatile main memory and a memory buffer including a plurality of cache lines. Each of the cache lines includes content and one or more bits signifying whether a memory transaction corresponding to the content of the cache line has been performed to completion and whether the content of the cache line matches content of a corresponding location of the non-volatile main memory. When the one or more bits of a cache line of the plurality of cache lines signifies that the transaction has been performed to completion and the content of the cache line does not match the content of the corresponding location of the non-volatile memory, access to modify the content of the cache line is restricted until the content of the cache line is written to the corresponding location of the non-volatile main memory. | 03-13-2014 |
20140075123 | Concurrent Control For A Page Miss Handler - In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed. | 03-13-2014 |
20140082292 | EFFICIENT CACHE VOLUME SIT SCANS - A processor, operable in a computing storage environment, allocates portions of a Scatter Index Table (SIT) disproportionately between a larger portion dedicated for meta data tracks, and a smaller portion dedicated for user data tracks, and processes a storage operation through the disproportionately allocated portions of the SIT using an allocated number of Task Control Blocks (TCB). | 03-20-2014 |
20140082293 | Store Buffer for Transactional Memory - Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation. | 03-20-2014 |
20140082294 | MANAGEMENT OF DESTAGE TASKS WITH LARGE NUMBER OF RANKS - A processor, operable in a computing storage environment, for each rank in a storage management device in the computing storage environment, allocates a lower maximum count, and a higher maximum count, of Task Control Blocks (TCBs) to be implemented for performing a storage operation, and performs the storage operation using up to the lower maximum count of TCBs, yet only allows those TCBs above the lower maximum count to be allocated for performing the storage operation satisfying at least one criterion. | 03-20-2014 |
20140089592 | SYSTEM CACHE WITH SPECULATIVE READ ENGINE - Methods and apparatuses for processing speculative read requests in a system cache within a memory controller. To expedite a speculative read request, the request is sent on parallel paths through the system cache. A first path goes through a speculative read engine to determine if the speculative read request meets the conditions for accessing memory. A second path involves performing a tag lookup to determine if the data referenced by the request is already in the system cache. If the speculative read request meets the conditions for accessing memory, the request is sent to a miss queue where it is held until a confirm or cancel signal is received from the tag lookup mechanism. | 03-27-2014 |
20140089593 | RECOVERING FROM DATA ERRORS USING IMPLICIT REDUNDANCY - Some implementations disclosed herein provide techniques and arrangements for recovery of data stored in memory shared by a number of processors through information stored in a cache directory. A core of a processor may initiate access (e.g., read or write) to particular data located in a first cache that is accessible to the core. In response to detecting an error associated with accessing the particular data, a location in the processor that includes the particular data may be identified and the particular data may be copied from the location to the first cache. | 03-27-2014 |
20140089594 | DATA PROCESSING METHOD, CACHE NODE, COLLABORATION CONTROLLER, AND SYSTEM - The present invention provides a data processing method based on a cache node group for data caching, where each cache node in the group includes a local replacement-allowable data storage space for storing data accessed by a local client and a collaborative replacement-allowable data storage space for storing data content accessed by a non-local client. By using the data processing method to process data content stored in the local replacement-allowable data storage space and the collaborative replacement-allowable data storage space of the cache node, the clients can obtain data more accurately and directly during access to the cache node, thereby meeting different requirements for local optimization of the cache node. | 03-27-2014 |
20140095797 | Cache Memory Having Enhanced Performance And Security Features - Methods for accessing, storing and replacing data in a cache memory are provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory. | 04-03-2014 |
20140095798 | Protecting Data During Different Connectivity States - Aspects of the subject matter described herein relate to data protection. In aspects, during a backup cycle, backup copies may be created for files that are new or that have changed since the last backup. If external backup storage is not available, the backup copies may be stored in a cache located on the primary storage. If backup storage is available, the backup copies may be stored in the backup storage device and backup copies that were previously stored in the primary storage may be copied to the backup storage. The availability of the backup storage may be detected and used to seamlessly switch between backing up files locally and remotely as availability of the backup storage changes. | 04-03-2014 |
20140108735 | MANAGING A CACHE FOR STORING ONE OR MORE INTERMEDIATE PRODUCTS OF A COMPUTER PROGRAM - A method, program product and a system is provided for managing a cache. The method includes analyzing at least an intermediate product of a computer program. The intermediate product is produced by the computer program in response to a set of control inputs. The method also includes determining a resource measure associated with the first intermediate product and determining a resource measure value for the first intermediate product using a first set of control inputs> The first intermediate product is stored in the cache upon determination that the resource measure value exceeds a predetermined resource threshold. | 04-17-2014 |
20140115258 | SYSTEM AND METHOD FOR MANAGING A DEDUPLICATION TABLE - Implementations described and claimed herein provide systems and methods for allocating and managing resources for a deduplication table. In one implementation, an upper limit to an amount of memory allocated to a deduplication table is established. The deduplication table has one or more checksum entries, and each checksum entry is associates a checksum with unique data. A new checksum entry corresponding to new unique data is prevented from being added to the deduplication table where adding the new checksum entry will cause the deduplication table to exceed a size limit. The new unique data has a checksum that is different from the checksums in the one or more checksum entries in the deduplication table. | 04-24-2014 |
20140129776 | STORE REPLAY POLICY - A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided. | 05-08-2014 |
20140129777 | SYSTEMS AND METHODS FOR DYNAMIC DATA STORAGE - A data caching method is performed to receive an instruction to operate based on a specific data set; determine whether the specific data set is cached in its memory; when the specific data set is not cached in the memory, determine a plurality of attributes for a plurality of data sets currently stored in the memory, determine whether these attributes satisfy data caching criteria for storing the specific data set, and furthermore, when the data caching criteria are not satisfied, select at least one of the plurality of data sets according to a data replacement rule, delete at least a portion of the selected data set from the memory, and download the specific data set from a remote source; operate the specific data set according to the user instruction; and store at least a portion of the specific data set in the memory. | 05-08-2014 |
20140136788 | Deleting Records In A Multi-Level Storage Architecture Without Record Locks - The multi-level storage system and method of deleting first level storage structure pages or records without record locks. The method includes determining whether a record to be deleted from the first level storage structure has any uncommitted write operation, and if the record has an uncommitted write operation, the record is kept in the first level storage structure. Record-moved version information is added to the record to designate the record being moved from the first level storage structure to the second level storage structure. Data change operations are executed for the record based on the record-moved version information without waiting until the record's movement from the first level storage structure to the second level storage structure finishes. | 05-15-2014 |
20140136789 | HOST SIDE DEDUPLICATION - One or more techniques and/or systems are provided for performing host side deduplication. Host side deduplication may be performed upon writeable data within a write request received at a host computing device configured to access data stored by a storage server. The host side deduplication may be performed at the host computing device to determine whether the writeable data is already stored by the storage server based upon querying a host side cache comprising data stored by a storage server and/or a data structure comprising unique signatures of data stored by the storage server. If the writeable data is stored by the storage server, then a deduplication notification excluding the writeable data may be sent to the storage server, otherwise a write command comprising the writeable data may be sent. Accordingly, unnecessary network traffic of redundant data already stored by the storage server may be reduced. | 05-15-2014 |
20140136790 | SYSTEMS AND METHODS FOR DESTAGING STORAGE TRACKS FROM CACHE - A system includes a cache and a processor coupled to the cache. The cache stores data in multiple storage tracks and each storage track includes an associated multi-bit counter. The processor is configured to perform the following method. One method includes incrementing the multi-bit counter on each respective storage track a predetermined amount each time the processor writes to a respective storage track. The method further includes decrementing each multi-bit counter each scan cycle, and destaging each storage track including a zero count. | 05-15-2014 |
20140143500 | FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER - A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address. | 05-22-2014 |
20140149672 | SELECTIVE RELEASE-BEHIND OF PAGES BASED ON REPAGING HISTORY IN AN INFORMATION HANDLING SYSTEM - An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred. | 05-29-2014 |
20140149673 | LOW LATENCY DATA EXCHANGE - According to one embodiment, a method for exchanging data in a system that includes a main processor in communication with an active memory device is provided. The method includes a processing element in the active memory device receiving an instruction from the main processor and receiving a store request from a thread running on the main processor, the store request specifying a memory address associated with the processing element. The method also includes storing a value provided in the store request in a queue in the processing element and the processing element performing the instruction using the value from the queue. | 05-29-2014 |
20140149674 | Performance and Energy Efficiency While Using Large Pages - Technologies are described herein for improving performance and energy efficiency in a computing system while using a large memory page size. Some example technologies may configure a main memory of the computing system to include a page-to-chunk table and a data area. The page-to-chunk table may include multiple entries such as a first entry. The first entry may correspond to a page that is made up of multiple chunks. The first entry may include pointers to the multiple chunks stored in the data area. | 05-29-2014 |
20140149675 | SELECTIVE RELEASE-BEHIND OF PAGES BASED ON REPAGING HISTORY IN AN INFORMATION HANDLING SYSTEM - An information handling system (IHS) includes an operating system with a release-behind component that determines which file pages to release from a file cache in system memory. The release-behind component employs a history buffer to determine which file pages to release from the file cache to create room for a current page access. The history buffer stores entries that identify respective pages for which a page fault occurred. For each identified page, the history buffer stores respective repage information that indicates if a repage fault occurred for such page. The release-behind component identifies a candidate previous page for release from the file cache. The release-behind component checks the history buffer to determine if a repage fault occurred for that entry. If so, then the release-behind component does not discard the candidate previous page from the cache. Otherwise, the release-behind component discards the candidate previous page if a repage fault occurred. | 05-29-2014 |
20140149676 | BACKGROUND MEMORY VALIDATION FOR GAMING DEVICES - Various embodiments are directed to a gaming device including a background memory validation system. The background memory validation system includes a background kernel thread that validates read-only pages on the gaming device. Additionally, the background kernel thread also minimizes potential timing problems because this process only validates page content in memory that is fully-loaded and functional. | 05-29-2014 |
20140156940 | Mechanism for Page Replacement in Cache Memory - A mechanism for page replacement for cache memory is disclosed. A method of the disclosure includes referencing an entry of a data structure of a cache in memory to identify a stored value of an eviction counter, the stored value of the eviction counter placed in the entry when a page of a file previously stored in the cache was evicted from the cache, determining a refault distance of the page of the file based on a difference between the stored value of the eviction counter and a current value of the eviction counter, and adjusting a ratio of cache lists maintained by the processing device to track pages in the cache, the adjusting based on the determined refault distance. | 06-05-2014 |
20140156941 | Tracking Non-Native Content in Caches - The described embodiments include a cache with a plurality of banks that includes a cache controller. In these embodiments, the cache controller determines a value representing non-native cache blocks stored in at least one bank in the cache, wherein a cache block is non-native to a bank when a home for the cache block is in a predetermined location relative to the bank. Then, based on the value representing non-native cache blocks stored in the at least one bank, the cache controller determines at least one bank in the cache to be transitioned from a first power mode to a second power mode. Next, the cache controller transitions the determined at least one bank in the cache from the first power mode to the second power mode. | 06-05-2014 |
20140156942 | Shared Virtual Memory Between A Host And Discrete Graphics Device In A Computing System - In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed. | 06-05-2014 |
20140181409 | METHOD AND SYSTEM FOR QUEUE DESCRIPTOR CACHE MANAGEMENT FOR A HOST CHANNEL ADAPTER - A method for managing a queue descriptor cache of a host channel adaptor (HCA) includes obtaining a queue descriptor from memory. The queue descriptor includes data describing a queue and the memory is located in a host system. The method further includes storing a copy of the queue descriptor in the queue descriptor cache of the HCA. The HCA accesses the copy of the queue descriptor to obtain the plurality of data, accesses the queue using the data, and updates the data to reflect the access to the queue. The method further includes calculating, using the data, a value corresponding to utilization of the queue, comparing the value against a threshold, fetching, if the value exceeds the threshold, a new copy of the queue descriptor from memory, and replacing the copy of the queue descriptor in the queue descriptor cache with the new copy obtained from the memory. | 06-26-2014 |
20140181410 | MANAGEMENT OF CACHE SIZE - In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached. | 06-26-2014 |
20140181411 | PROCESSING DEVICE WITH INDEPENDENTLY ACTIVATABLE WORKING MEMORY BANK AND METHODS - A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented. | 06-26-2014 |
20140181412 | MECHANISMS TO BOUND THE PRESENCE OF CACHE BLOCKS WITH SPECIFIC PROPERTIES IN CACHES - A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition. | 06-26-2014 |
20140189245 | MERGING EVICTION AND FILL BUFFERS FOR CACHE LINE TRANSACTIONS - A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer. | 07-03-2014 |
20140195739 | ZERO-COPY CACHING - Caching of an immutable buffer that has its data and address prevented from changing during the lifetime of the immutable buffer. A first computing entity maintains a cache of the immutable buffer and has a strong reference to the immutable buffer. So long as any entity has a strong reference to the immutable buffer, the immutable buffer is guaranteed to continue to exist for the duration of the strong reference. A second computing entity communicates with the first computing entity to obtain a strong reference to the immutable buffer and thereafter read data from the immutable buffer. Upon reading the data from the cache, the second computing entity demotes the strong reference to a weak reference to the immutable buffer. A weak reference to the immutable buffer does not guarantee that the immutable buffer will continue to exist for the duration of the weak reference. | 07-10-2014 |
20140201454 | Methods And Systems For Pushing Dirty Linefill Buffer Contents To External Bus Upon Linefill Request Failures - Methods and systems are disclosed for recovering dirty linefill buffer data upon linefill request failures. When a linefill request failure occurs and the linefill buffer has been marked as dirty, such as due to a system bus failure, the contents of the linefill buffer are pushed back to the system bus. The dirty data within the linefill buffer can then be used to update the external memory. The disclosed embodiments are useful for a wide variety of applications, including those requiring low data failure rates. | 07-17-2014 |
20140201455 | METHOD FOR INCREASING CACHE SIZE - A method for increasing storage space in a system containing a block data storage device, a memory, and a processor is provided. Generally, the processor is configured by the memory to tag metadata of a data block of the block storage device indicating the block as free, used, or semifree. The free tag indicates the data block is available to the system for storing data when needed, the used tag indicates the data block contains application data, and the semifree tag indicates the data block contains cache data and is available to the system for storing application data type if no blocks marked with the free tag are available to the system. | 07-17-2014 |
20140201456 | Control Of Processor Cache Memory Occupancy - Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described. | 07-17-2014 |
20140208036 | PERFORMING STAGING OR DESTAGING BASED ON THE NUMBER OF WAITING DISCARD SCANS - A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether more than a threshold number of discard scans are waiting to be performed. The controller avoids satisfying the request to perform the staging or the destaging operations or a read hit with respect to the area of the cache, in response to determining that more than the threshold number of discard scans are waiting to be performed. | 07-24-2014 |
20140237189 | COMPRESSION STATUS BIT CACHE AND BACKING STORE - One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data. | 08-21-2014 |
20140237190 | MEMORY SYSTEM AND MANAGEMENT METHOD THEROF - A memory system having multiple memory layers is provided. The memory system includes an upper memory layer and an intermediate memory layer comprising a first sub-memory consisting of a nonvolatile memory and a second sub-memory consisting of a volatile memory in a parallel structure positioned below the upper memory layer, and a memory management unit that controls operations of the upper memory layer and the intermediate memory layer. The intermediate memory layer is referred by the upper memory layer, and the memory management unit stores data meeting a predetermined condition among data stored in the second sub-memory into the first sub-memory in advance when a user device comprising the memory system is operating in a normal mode. | 08-21-2014 |
20140244935 | STORAGE SYSTEM CAPABLE OF MANAGING A PLURALITY OF SNAPSHOT FAMILIES AND METHOD OF SNAPSHOT FAMILY BASED READ - A method for a snapshot family based reading of data units from a storage system, the method comprises: receiving a read request for reading a requested data entity, searching in a cache memory of the storage system for a matching cached data entity, if not finding the matching cached data entity then: searching for one or more relevant data entity candidates stored in the storage system; selecting, out of the one or more relevant data entity candidates, a selected relevant data entity that has a content that has a highest probability, out of contents of the one or more relevant data entity candidates, to be equal to the content of the requested data entity; and responding to the read request by sending the selected relevant data entity. | 08-28-2014 |
20140250273 | RE-BUILDING MAPPING INFORMATION FOR MEMORY DEVICES - Memory modules and methods of operating memory modules re-build mapping information from data read from last valid physical pages. Corruption of mapping information is detected. A last valid physical page associated with logical data blocks is read. Mapping information is obtained from the data read from the last valid physical page, and mapping information is re-built using the mapping information obtained from the last valid pages. | 09-04-2014 |
20140258635 | INVALIDATING ENTRIES IN A NON-COHERENT CACHE - Techniques are provided for performing an invalidate operation in a non-coherent cache. In response to receiving an invalidate instruction, a cache unit only invalidates cache entries that are associated with invalidation data. In this way, a separate invalidate instruction is not required for each cache entry that is to be invalidated. Also, cache entries that are not to be invalidated remain unaffected by the invalidate operation. A cache entry may be associated with invalidation data if an address of the corresponding data item is in a particular set of addresses. The particular set of addresses may have been specified as a result of an invalidation instruction specified in code that is executing on a processor that is coupled to the cache. | 09-11-2014 |
20140258636 | CRITICAL-WORD-FIRST ORDERING OF CACHE MEMORY FILLS TO ACCELERATE CACHE MEMORY ACCESSES, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS - Critical-word-first reordering of cache fills to accelerate cache memory accesses, and related processor-based systems and methods are disclosed. In this regard in one embodiment, a cache memory is provided. The cache memory comprises a data array comprising a cache line, which comprises a plurality of data entry blocks configured to store a plurality of data entries. The cache memory also comprises cache line ordering logic configured to critical-word-first order the plurality of data entries into the cache line during a cache fill, and to store a cache line ordering index that is associated with the cache line and that indicates the critical-word-first ordering of the plurality of data entries in the cache line. The cache memory also comprises cache access logic configured to access each of the plurality of data entries in the cache line based on the cache line ordering index for the cache line. | 09-11-2014 |
20140281250 | Systems and Methods for Performing Data Recovery in a Memory System - Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page. | 09-18-2014 |
20140281251 | METHOD AND APPARATUS FOR CACHE LINE STATE UPDATE IN SECTORED CACHE WITH LINE STATE TRACKER - Technologies for tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array can be performed. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. | 09-18-2014 |
20140281252 | STATEMENT CACHE AUTO-TUNING - Disclosed are methods and apparatuses that implement automatic resizing of statement caches in response to cache metrics. One embodiment provides an approach for periodically calculating a session eligibility index for each session cache, wherein the session eligibility index indicates the priority level of the session cache for resizing, and selecting and resizing one or more cache sessions based at least in part on the session eligibility index. | 09-18-2014 |
20140281253 | DYNAMICALLY REMOVING ENTRIES FROM AN EXECUTING QUEUE - According to an embodiment, a computer-implemented method for control block management is provided. The computer-implemented method includes placing one or more control blocks in a queue for execution by a computer hardware device. The computer-implemented method also includes allocating a purge flag in each of the control blocks. The purge flag instructs the computer hardware device to skip execution of the corresponding control block. | 09-18-2014 |
20140281254 | Semiconductor Chip With Adaptive BIST Cache Testing During Runtime - A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries. | 09-18-2014 |
20140281255 | PAGE STATE DIRECTORY FOR MANAGING UNIFIED VIRTUAL MEMORY - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140281256 | FAULT BUFFER FOR RESOLVING PAGE FAULTS IN UNIFIED VIRTUAL MEMORY SYSTEM - A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping. | 09-18-2014 |
20140289474 | OPERATION PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS - An operation processing apparatus connected with another operation processing apparatus includes an operation processing unit configured to perform an operation process using first data administered by the own operation processing apparatus and second data administered by another operation processing apparatus and acquired from another operation processing apparatus, and a control unit configured to include a setting unit which sets the operation processing unit to an operating state or a non-operating state and a cache memory which holds the first data and the second data, wherein when the setting unit sets the operation processing unit to the operating state and the second data is evicted from the cache memory, the control unit sends to another operation processing apparatus the evicted data and a request which is a trigger for storing the evicted data in a cache memory in another operation processing apparatus. | 09-25-2014 |
20140289475 | CACHE MEMORY DEVICE, INFORMATION PROCESSING DEVICE, AND CACHE MEMORY CONTROL METHOD - A cache memory device includes: a processor; and a main memory and a cache memory coupled to the processer, wherein the processor executes a process includes: obtaining a first address in the main memory; obtaining a first index that indicates a first cache index of the cache memory by a hash function; storing a first tag of the first address in the first cache index; generating a second address, a second tag; obtaining by the hash function a second index that indicates a second cache index of the cache memory; changing the second index so that the second index and the first index match and storing the second tag with a third index that is indicated by the changed second index in the cache memory and in a way that is different from the way in which the tag of the first address is stored. | 09-25-2014 |
20140289476 | CACHING AND DEDUPLICATION OF DATA BLOCKS IN CACHE MEMORY - A storage system comprises a cache for caching data blocks and storage devices for storing blocks. A storage operating system may deduplicate sets of redundant blocks on the storage devices based on a deduplication requirement. Blocks in cache are typically deduplicated based on the deduplication on the storage devices. Sets of redundant blocks that have not met the deduplication requirement for storage devices and have not been deduplicated on the storage devices and cache are targeted for further deduplication processing. Sets of redundant blocks may be further deduplicated based on their popularity (number of accesses) in cache. If a set of redundant blocks in cache is determined to have a combined number of accesses being greater than a predetermined threshold number of accesses, the set of redundant blocks is determined to be “popular.” Popular sets of redundant blocks are selected for deduplication in cache and the storage devices. | 09-25-2014 |
20140304476 | MAINTAINING CACHE CONSISTENCY IN A CACHE FOR CACHE EVICTION POLICIES SUPPORTING DEPENDENCIES - For maintaining consistency for a cache that contains dependent objects in a computing environment, object dependencies for cached objects are managed by defining and maintaining object dependency lists for each one of the cached objects for identifying objects upon which the cached objects are dependent. Maintaining cache consistency for 2 types of cache eviction policies is supported by maintaining an object dependency lists for each one of the cached objects for identifying objects dependent upon the cached object. Each of the objects in an object dependency list is updated when the object is updated. | 10-09-2014 |
20140304477 | OBJECT LIVENESS TRACKING FOR USE IN PROCESSING DEVICE CACHE - A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy. | 10-09-2014 |
20140310476 | BUCKETIZED MULTI-INDEX LOW-MEMORY DATA STRUCTURES - Systems and methods for generating and storing a data structure for maintaining cache supporting compression and cache-wide deduplication, including generating data structures with fixed size memory regions configured to hold multiple signatures as keys, wherein the number of the fixed size memory regions is bounded. A first mapping is generated from short-length signatures to a storage location and a quantized length measure on a cache storage device; and unused contiguous regions on the cache device are allocated. Metadata and cache page content is retrieved using a single input/output operation; a correctness of a full value of hash functions of uncompressed cache page content is validated; a second mapping is generated from short-length signatures to entries in the first mapping; and verification of whether the cached page content corresponds to a full-length original logical block address using the metadata is performed. | 10-16-2014 |
20140317354 | ELECTRONIC DEVICE, DATA CACHING SYSTEM AND METHOD - A data caching system applied in an electronic device is provided. The electronic device includes a processor, a cache, a main storage. Data stored in the cache is assigned with a weight value to present times that the data has been read. The data caching system includes a receiving module receiving requests for reading data from the processor. A reading module reads data according to the reading requests, and determines whether a requested data is stored in the cache. A weight value calculating module calculates the weight value, of the requested data that is stored in the cache. The weight value calculating module plus one to the weight value of the requested data when the requested data is read. If the cache is full, the data whose weight value is equal to zero is randomly selected to be cleared from the cache to release space. | 10-23-2014 |
20140331011 | SYSTEMS AND METHODS FOR INSTANTANEOUS CLONING - Techniques to clone a writeable data object in non-persistent memory are disclosed. The writeable data object is stored in a storage structure in non-persistent memory that corresponds to a portion of a persistent storage. The techniques enable cloning of the writeable data object without having to wait until the writeable data object is saved to the persistent storage and without needing to quiesce incoming operations (e.g., reads and writes) to the writeable data object. | 11-06-2014 |
20140344524 | ADAPTIVE OVER-PROVISIONING IN MEMORY SYSTEMS - A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead. | 11-20-2014 |
20140365731 | Systems and Methods for Cache Management for Universal Serial Bus Systems - Systems and methods are provided for cache management. An example system includes a cache and a cache-management component. The cache includes a plurality of cache lines corresponding to a plurality of device endpoints, a device endpoint including a portion of a universal-serial-bus (USB) device. The cache-management component is configured to receive first transfer request blocks (TRBs) for data transfer involving a first device endpoint and determine whether a cache line in the cache is assigned to the first device endpoint. The cache-management component is further configured to, in response to no cache line in the cache being assigned to the first device endpoint, determine whether the cache includes an empty cache line that contains no valid TRBs, and in response to the cache including an empty cache line, assign the empty cache line to the first device endpoint and store the first TRBs to the empty cache line. | 12-11-2014 |
20140372703 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR WARMING A CACHE FOR A TASK LAUNCH - A system, method, and computer program product for warming a cache for a task launch is described. The method includes the steps of receiving a task data structure that defines a processing task, extracting information stored in a cache warming field of the task data structure, and, prior to executing the processing task, generating a cache warming instruction that is configured to load one or more entries of a cache storage with data fetched from a memory. | 12-18-2014 |
20140379987 | DYNAMIC MEMORY PAGE POLICY - Mechanisms for predicting whether a memory access may be a page hit or a page miss and applying different page policies (e.g., an open page policy or a close page policy) based on the prediction are disclosed. A counter may be used to determine a hit rate (e.g., a percentage or a ratio of the number of memory accesses that are page hits). The processing device may apply different page policies based on the hit rate. A memory access history (that includes data indicating a sequence or list of memory accesses) may be used to identify a counter from a plurality of counters. The processing device may apply different page policies based on the value of the counter (e.g., based on whether the counter is greater than a threshold). | 12-25-2014 |
20140379988 | CACHE DESTAGING FOR VIRTUAL STORAGE DEVICES - Some implementations may include a virtual storage system to which data is written. The virtual storage system may include a cache and multiple hard drives. Multiple queues may be associated with the multiple hard drives such that each hard drive of the multiple hard drives has a corresponding queue of the multiple queues. A set of candidate rows may be selected from the cache. For each candidate row in the set of candidate rows, destination hard drives may be identified. Each candidate row may be placed in queues corresponding to the destination hard drives. Two or more candidate rows from the multiple queues may be written substantially contemporaneously (e.g., in parallel) to two or more destination hard drives. | 12-25-2014 |
20140379989 | COHERENT ATTACHED PROCESSOR PROXY HAVING HYBRID DIRECTORY - A coherent attached processor proxy (CAPP) includes transport logic having a first interface configured to support communication with a system fabric of a primary coherent system and a second interface configured to support communication with an attached processor (AP) that is external to the primary coherent system and that includes a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. The CAPP further includes one or more master machines that initiate memory access requests on the system fabric of the primary coherent system on behalf of the AP, one or more snoop machines that service requests snooped on the system fabric, and a CAPP directory having a precise directory having a plurality of entries each associated with a smaller data granule and a coarse directory having a plurality of entries each associated with a larger data granule. | 12-25-2014 |
20150026408 | CACHE MEMORY SYSTEM AND METHOD OF OPERATING THE SAME - A cache memory system and a method of operating the cache memory system are provided. The cache memory system includes: an address buffer for receiving address bits including a cache address and a tag address from the outside or externally; a cache memory including a memory array, the cache memory outputting, from a row of the memory array which the cache address designates, a plurality of pieces of tag data and a plurality of pieces of cache data corresponding to the plurality of pieces of tag data; and a register configured to temporarily store a data set including the plurality of pieces of cache data output from the cache memory. | 01-22-2015 |
20150026409 | DEFERRED RE-MRU OPERATIONS TO REDUCE LOCK CONTENTION - Data operations, requiring a lock, are batched into a set of operations to be performed on a per-core basis. A global lock for the set of operations is periodically acquired, the set of operations is performed, and the global lock is freed so as to avoid excessive duty cycling of lock and unlock operations in the computing storage environment. | 01-22-2015 |
20150032966 | SYSTEM AND METHOD FOR APPLICATION LEVEL CACHING - The disclosure generally relates to methods and systems for application level caching and more particularly to dynamically applying caching policies to a software application. In one embodiment, an application level caching method, comprising: monitoring, using a utility executed by a processor, run-time data access operations corresponding to an application; identifying, using the processor, at least one characteristic associated with the run-time data access operations; triggering, using the processor, a caching rule based on the at least one characteristic associated with the run-time data access operations; and providing, using the processor, a memory access instruction according to the caching rule. | 01-29-2015 |
20150039835 | System and Method of Hinted Cache Data Removal - The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver, a priority controller, and a data scrubber. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data transfer request includes a request to discard a portion of data based upon the pointers generated by the hinting driver. If the priority controller determines that data transfer request includes a request to discard a portion of data, the data scrubber locates and removes the portion of data from the cache memory so that the cache memory is freed from invalid data (e.g. data associated with a deleted file). | 02-05-2015 |
20150058575 | PRECHARGE DISABLE USING PREDECODED ADDRESS - A memory can be a sum addressed memory (SAM) that receives, for each read access, two address values (e.g. a base address and an offset) having a sum that indicates the entry of the memory to be read (the read entry). A decoder adds the two address value to identify the read entry. Concurrently, a predecode module predecodes the two address values to identify a set of entries (e.g. two different entries) at the memory, whereby the set includes the entry to be read. The predecode module generates a precharge disable signal to terminate precharging at the set of entries which includes the entry to he read. Because the precharge disable signal is based on predecoded address information, it can be generated without waiting for a full decode of the read address entry. | 02-26-2015 |
20150058576 | HARDWARE MANAGED COMPRESSED CACHE - A computing element, system, and method for implementing control structures for a compressed cache in hardware. Embodiments provide a first engine configured to allocate and deallocate virtual memory pages and physical memory pages from pools of available pages to store received data to the compressed cache, a second engine configured to compress received data and store the compressed data. Embodiments also provide for embedding data within the virtual and physical memory pages to indicate page size, type, and data compression. | 02-26-2015 |
20150067264 | METHOD AND APPARATUS FOR MEMORY MANAGEMENT - In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction. | 03-05-2015 |
20150081978 | Dynamic Sizing of Memory Caches - Disclosed are cache management apparatus and methods. A mobile device can include a global cache manager (GCM), a processor, and a storage medium. The GCM can manage a cache for an application of the mobile device. The storage medium can store instructions that, upon the processor's execution, cause the mobile device to perform functions. The functions can include: receiving an indication of a triggering event related to memory allocated for the application; the GCM responsively determining an amount of memory allocated to the application; the GCM determining whether a memory limit for the application is within a threshold amount of being exceeded by the amount of memory allocated to the application; and responsive to determining that the memory limit for the application is within the threshold amount of being exceeded, instructing the application to cease utilization of a portion of memory allocated to the cache. | 03-19-2015 |
20150089146 | CONDITIONAL PAGE FAULT CONTROL FOR PAGE RESIDENCY - The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault. | 03-26-2015 |
20150095582 | Method for Specifying Packet Address Range Cacheability - A method for specifying packet address range cacheability is provided. The method includes passing a memory allocation request from an application running on a network element configured to implement packet forwarding operations to an operating system of a network element, the memory allocation request including a table ID associated with an application table to be stored using the memory allocation. The method also includes allocating a memory address range by the operating system to the application in response to the memory allocation request, and inserting an entry in a cacheability register, the entry including the table ID included in the memory allocation request and the memory address range allocated in response to the memory allocation request. | 04-02-2015 |
20150095583 | DATA PROCESSING SYSTEM WITH CACHE LINEFILL BUFFER AND METHOD OF OPERATION - When data in first and second requests from a processor does not reside in cache memory, a first data element responsive to the second request is received by a cache controller from an external memory module after a first data element responsive to the first request and before the second data element responsive to the first request. Ownership of a linefill buffer is assigned to the first request when the first data element responsive to the first request is received. Ownership of the linefill buffer is re-assigned to the second request when the first data element responsive to the second request is received after the first data element responsive to the first request is received. | 04-02-2015 |
20150100735 | Enhancing Lifetime of Non-Volatile Cache by Reducing Intra-Block Write Variation - A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a set, the set containing a memory block associated with a physical block address. A mapping from a logical address to the physical address of the block is also maintained. The method shifts the mapping based on the value of the write count and writes data to the block based on the mapping. | 04-09-2015 |
20150100736 | HARDWARE MANAGED COMPRESSED CACHE - A computing element, system, and method for implementing control structures for a compressed cache in hardware. Embodiments provide a first engine configured to allocate and deallocate virtual memory pages and physical memory pages from pools of available pages to store received data to the compressed cache, a second engine configured to compress received data and store the compressed data. Embodiments also provide for embedding data within the virtual and physical memory pages to indicate page size, type, and data compression. | 04-09-2015 |
20150113222 | Read and Write Requests to Partially Cached Files - Aspects of the invention are provided to support partial file caching on a file system block boundary. All read requests are converted so that offset and count are aligned on a block boundary. Data associated with read requests is first satisfied from local cache, with cache misses supported with a call to persistent or remote system. Similarly, for a write request, any partial blocks are aligned to the block boundary. Data associated with the write request is performed on local cache and placed in a queue for replay to the persistent or remote system. | 04-23-2015 |
20150113223 | SYSTEMS AND METHODS FOR ADAPTIVE RESERVE STORAGE - A storage layer may over-provision physical storage resources of a storage medium by reserving a portion of the full physical storage capacity of the storage medium for use as reserve capacity. The reserve capacity may be used to prevent write stall conditions and/or for grooming operations, such as storage recovery, refresh, and the like. A reserve module may be configured to adapt the reserve capacity in accordance with, inter alia, operating conditions on the storage layer. The reserve module may be configured to dynamically modify the storage capacity available through the storage layer. A cache layer configured to cache data of a backing store on the storage layer, may be configured to add and/or remove cache entries in response to changes in the reserve capacity. | 04-23-2015 |
20150121013 | CACHE LONGEVITY DETECTION AND REFRESH - A web server cache performs verification of cached computational results by storing a computed function result as a cached value in a cache, and upon receiving a subsequent invocation of the function, examining a duration of the value in the cache. The web server compares, if the duration exceeds a staleness detection threshold, a result of a subsequent execution of the function to the cached value in response to the subsequent invocation by recomputing, a result from execution of the function for validating the cached value, and flags an error if the duration exceeds the staleness detection threshold and the result differs from the cached value. Alternatively, the method returns, if the duration of the cache value is within the staleness detection threshold, the cache value as the result of the subsequent invocation. | 04-30-2015 |
20150127913 | EFFICIENT PROCESSING OF CACHE SEGMENT WAITERS - For a plurality of input/output (I/O) operations waiting to assemble complete data tracks from data segments, a process, separate from a process responsible for the data assembly into the complete data tracks, is initiated for waking a predetermined number of the waiting I/O operations. | 05-07-2015 |
20150143052 | MANAGING FAULTY MEMORY PAGES IN A COMPUTING SYSTEM - Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert. | 05-21-2015 |
20150143053 | SYSTEM AND METHOD FOR IMPROVED STORAGE REQUEST HANDLING IN HOST-SIDE CACHES - A system and method of improved storage request handling in host-side caches includes a host-side cache with a cache controller, a plurality of request queues, and a cache memory. The cache controller is configured to receive a storage request, assign a priority to the storage request based on a queuing policy, insert the storage request into a first request queue selected from the plurality of request queues based on the assigned priority, extract the storage request from the first request queue when the storage request is a next storage request to fulfill based on the assigned priority, forward the storage request to a storage controller, and receive a response to the storage request from the storage controller. The queuing policy is implemented using a rule-based policy engine. In some embodiments, the cache controller is further configured to update one or more monitoring metrics based on processing of the storage request. | 05-21-2015 |
20150143054 | Managing Faulty Memory Pages In A Computing System - Managing faulty memory pages in a computing system, including: tracking, by a page management module, a number of errors associated with a memory page; determining, by the page management module, whether the number of errors associated with the memory page exceeds a predetermined threshold; responsive to determining that the number of errors associated with the memory page exceeds the predetermined threshold, attempting, by the page management module, to retire the memory page; determining, by the page management module, whether the memory page has been successfully retired; and responsive to determining that the memory page has not been successfully retired, generating, by the page management module, a predictive failure alert. | 05-21-2015 |
20150149728 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device may include a first address cache configured to store a physical address of a semiconductor memory device and a write count associated with the physical address, an address monitor configured to update the physical address and the write count in the first address cache based on a received write request, and an arbiter configured to store a write address and write data associated with the write request in a write cache in response to a command from the address monitor, wherein the command generated by the address monitor is based on whether an update is made to the physical address and the write count in first address cache. | 05-28-2015 |
20150331805 | OPERATING A FIFO MEMORY - The present invention concerns a method of operating a first-in first-out memory ( | 11-19-2015 |
20150356025 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system including a processor core and a cache control unit is disclosed. The processor core is capable of being coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data. Further, the cache control unit is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information. The cache control unit is also configured to fill the data from the first memory to the second memory based on the track corresponding to the segment of instructions after execution of an instruction last updating the base register used by the at least one instruction accessing the data. | 12-10-2015 |
20150356026 | Cache Memory Having Enhanced Performance and Security Features - A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory. | 12-10-2015 |
20150363323 | NON-VOLATILE MEMORY WRITE MECHANISM - A system includes a memory buffer to cache a non-volatile memory. The non-volatile memory stores a plurality of valid and obsolete variables in a plurality of valid and obsolete regions, respectively. The system further includes a journal region to track movement of valid variables and valid regions within the memory buffer utilizing alternating pairs of structure pointers to indicate at least portions of the plurality of valid and obsolete regions indicative of from where and to where the valid variables move during a write event. | 12-17-2015 |
20150363325 | IDENTIFICATION OF LOW-ACTIVITY LARGE MEMORY PAGES - Large pages that may impede memory performance in computer systems are identified. In operation, mappings to selected large pages are temporarily demoted to mappings to small pages and accesses to these small pages are then tracked. For each selected large page, an activity level is determined based on the tracked accesses to the small pages included in the large page. By strategically selecting relatively low activity large pages for decomposition into small pages and subsequent memory reclamation while restoring the mappings to relatively high activity large pages, memory consumption is improved, while limiting performance impact attributable to using small pages. | 12-17-2015 |
20150363326 | IDENTIFICATION OF LOW-ACTIVITY LARGE MEMORY PAGES - Large pages that may impede memory performance in computer systems are identified. In operation, mappings to selected large pages are temporarily demoted to mappings to small pages and accesses to these small pages are then tracked. For each selected large page, an activity level is determined based on the tracked accesses to the small pages included in the large page. By strategically selecting relatively low activity large pages for decomposition into small pages and subsequent memory reclamation while restoring the mappings to relatively high activity large pages, memory consumption is improved, while limiting performance impact attributable to using small pages. | 12-17-2015 |
20150363331 | STORAGE CONTROL DEVICE AND METHOD OF CONTROLLING STORAGE CONTROL DEVICE - To improve response performance of a storage control device. A storage control device | 12-17-2015 |
20150370628 | EMPLOYING INTERMEDIARY STRUCTURES FOR FACILITATING ACCESS TO SECURE MEMORY - The present application is directed to employing intermediary structures for facilitating access to secure memory. A secure driver (SD) may be loaded into the device to reserve a least a section of memory in the device as a secure page cache (SPC). The SPC may protect application data from being accessed by other active applications in the device. Potential race conditions may be avoided through the use of a linear address manager (LAM) that maps linear addresses (LAs) in an application page table (PT) to page slots in the SPC. The SD may also facilitate error handling in the device by reconfiguring VEs that would otherwise be ignored by the OS. | 12-24-2015 |
20150370720 | USING CUCKOO MOVEMENT FOR IMPROVED CACHE COHERENCY - Example implementations of the present disclosure are directed to handling the eviction of a conflicting cuckoo entry while reducing performance degradation resulting. In example implementations, when an address is replacing another address, the evicted address does not necessarily map to the same places as the new address. Example implementations attempt to conduct a run through of the cache coherent directory with the new entry such that the evicted address can find an empty entry in the directory and fill the empty entry. | 12-24-2015 |
20150378924 | EVICTING CACHED STORES - A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries. | 12-31-2015 |
20150378928 | MANAGING READ TAGS IN A TRANSACTIONAL MEMORY - Managing cache evictions during transactional execution of a process. Based on initiating transactional execution of a memory data accessing instruction, memory data is fetched from a memory location, the memory data to be loaded as a new line into a cache entry of the cache. Based on determining that a threshold number of cache entries have been marked as read-set cache lines, determining whether a cache entry that is a read-set cache line can be replaced by identifying a cache entry that is a read-set cache line for the transaction that contains memory data from a memory address within a predetermined non-conflict address range. Then invalidating the identified cache entry of the transaction. Then loading the fetched memory data into the identified cache entry, and then marking the identified cache entry as a read-set cache line of the transaction. | 12-31-2015 |
20150378934 | CONTEXT BASED CACHE EVICTION - A method, medium, and system to receive a request to add a resource to a cache, the resource including a data object and a context item key associated with the resource and uniquely identifying a context of use referenced by the context item key; determine whether the resource is stored in the cache; store, in response to the determination that the resource is not stored in the cache, the resource in the cache; and add the context item key of the resource stored in the cache to a record of reference list of resources. | 12-31-2015 |
20160019167 | SOCIAL CACHE - Various embodiments relating to a social cache replacement policy are described. The techniques of the present invention disclosed utilize social network properties to guide a cache replacement policy executed by a social networking platform system. In one embodiment, a method is provided for determining a queue location to cache a data item based on a popularity score computed from social network properties. In one embodiment, a method is provided for computing the popularity score by incorporating a user's social network properties and the user's friends' social network properties. In embodiments, the popularity score may be computed using a plurality of social network properties, which may include social network properties associated with (i) the user, (ii) the consumer(s), and/or (iii) the data item(s). In embodiments, a plurality of popularity scores are maintained in a user-score database, where the plurality of popularity scores are periodically updated using historical data. | 01-21-2016 |
20160041910 | CACHE OPTIMIZATION - A system and method for management and processing of resource requests at cache server computing devices is provided. Cache server computing devices segment content into an initialization fragment for storage in memory and one or more remaining fragments for storage in a media having higher latency than the memory. Upon receipt of a request for the content, a cache server computing device transmits the initialization fragment from the memory, retrieves the one or more remaining fragments, and transmits the one or more remaining fragments without retaining the one or more remaining fragments in the memory for subsequent processing. | 02-11-2016 |
20160041926 | BALANCED CACHE FOR RECENTLY FREQUENTLY USED DATA - The disclosure of the present invention presents a method and system for efficiently maintaining an object cache to a maximum size by number of entries, whilst providing a means of automatically removing cache entries when the cache attempts to grow beyond its maximum size. The method for choosing which entries should be removed provides for a balance between least recently used and least frequently used policies. A flush operation is invoked only when the cache size grows beyond the maximum size and removes a fixed percentage of entries in one pass. | 02-11-2016 |
20160043977 | DATA DEDUPLICATION AT THE NETWORK INTERFACES - A method for data deduplication during execution of an application on a plurality of computing nodes, including: generating, by a first processor in a first computing node executing the application, a first message to process application data owned by a second computing node executing the application; receiving, by a first network interface (NI) of the first computing node, the first message; extracting, by the first NI, a first key from the first message; determining, by the first NI, the first key is not a duplicate; and placing, by the first NI and in response to the first key not being a duplicate, the first message on a network connecting the first computing node to the second computing node. | 02-11-2016 |
20160055087 | SYSTEM AND METHOD FOR MANAGING CACHE REPLACEMENTS - A system and method for managing cache replacements and a memory subsystem incorporating the system or the method. In one embodiment, the system includes: ( | 02-25-2016 |
20160062903 | METHOD AND SYSTEM FOR CACHE MANAGEMENT - Machine logic (for example, software) for cache management. comprising cache management method includes the following operations: determining, in response to a cache entry is created, a category for the cache entry; and determining a predicted time point of an invalidation event associated with the category, wherein occurrence of the invalidation event will cause invalidation of catching entries of the category; setting a valid period of the cache entry based on the predicted time point. | 03-03-2016 |
20160062904 | ALLOCATION ENFORCEMENT IN A MULTI-TENANT CACHE MECHANISM - Cache optimization. Cache access rates for tenants sharing the same cache are monitored to determine an expected cache usage. Factors related to cache efficiency or performance dictate occupancy constraints. A request to increase cache space allocated to a first tenant is received. If there is a second cache tenant for which reducing its cache size by the requested amount will not violate the occupancy constraints for the second cache tenant, its cache is decreased by the requested amount and allocated to satisfy the request. Otherwise, the first cache size is increased by allocating the amount of data storage space to the first cache tenant without deallocating the same amount of data storage space allocated to another cache tenant from among the plurality of cache tenants. | 03-03-2016 |
20160062916 | CIRCUIT-BASED APPARATUSES AND METHODS WITH PROBABILISTIC CACHE EVICTION OR REPLACEMENT - Selection logic can be used to select between a set of cache lines that are candidates for eviction from a cache. For each cache line in the set of cache lines, a relative probability that the cache line will result in a hit can be calculated based upon: past reuse behavior for the cache line; and hit rates for reuse distances. Based upon the relative probabilities for the set of cache lines, a particular cache line can be selected from the set of cache lines for eviction. | 03-03-2016 |
20160070645 | ALLOCATION ENFORCEMENT IN A MULTI-TENANT CACHE MECHANISM - Cache optimization. Cache access rates for tenants sharing the same cache are monitored to determine an expected cache usage. Factors related to cache efficiency or performance dictate occupancy constraints. A request to increase cache space allocated to a first tenant is received. If there is a second cache tenant for which reducing its cache size by the requested amount will not violate the occupancy constraints for the second cache tenant, its cache is decreased by the requested amount and allocated to satisfy the request. Otherwise, the first cache size is increased by allocating the amount of data storage space to the first cache tenant without deallocating the same amount of data storage space allocated to another cache tenant from among the plurality of cache tenants. | 03-10-2016 |
20160070654 | EVICTING CACHED STORES - A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines an eviction request setting for evicting the one or more existing store cache entries. | 03-10-2016 |
20160077969 | CACHE MEMORY SYSTEM AND OPERATING METHOD THEREOF - A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons, and an update controller configured to, in response to the cache miss being determined, determine, as an update candidate, a piece among pieces of cache data included in the set and corresponding to the pieces of the tag data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data. | 03-17-2016 |
20160092372 | READ CACHE MANAGEMENT IN MULTI-LEVEL CELL (MLC) NON-VOLATILE MEMORY - A method includes reading memory pages from a non-volatile memory that holds at least first memory pages having a first bit significance and second memory pages having a second bit significance, different from the first bit significance. At least some of the read memory pages are cached in a cache memory. One or more of the cached memory pages are selected for eviction from the cache memory, in accordance with a selection criterion that gives eviction preference to the memory pages of the second bit significance over the memory pages of the first bit significance. The selected memory pages are evicted from the cache memory. | 03-31-2016 |
20160098353 | METHODS AND SYSTEMS FOR MEMORY DE-DUPLICATION - Provided are methods and systems for de-duplicating cache lines in physical memory by detecting cache line data patterns and building a link-list between multiple physical addresses and their common data value. In this manner, the methods and systems are applied to achieve de-duplication of an on-chip cache. A cache line filter includes one table that defines the most commonly duplicated content patterns and a second table that saves pattern numbers from the first table and the physical address for she duplicated cache line. Since a cache line duplicate can be detected during a write operation, each write can involve table lookup and comparison. If there is a hit in the table, only the address is saved instead of the entire data string. | 04-07-2016 |
20160098356 | HARDWARE-ASSISTED MEMORY COMPRESSION MANAGEMENT USING PAGE FILTER AND SYSTEM MMU - Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages (“hot” and “cold” pages, respectively) so that inactive pages can be compressed prior to the occurrence of a page fault. The methods and systems are designed to achieve, among other things, lower cost, longer battery life, and faster user response. Whereas existing approaches for memory management are based on pixel or frame buffer compression, the methods and systems provided focus on the CPU's program (e.g., generic data structure). Focusing on hardware-accelerated memory compression to offload CPU translates higher power efficiency (e.g., ASIC is approximately 100× lower power than CPU) and higher performance (e.g., ASIC is approximately 10× faster than CPU), and also allows for hardware-assisted memory management to offload OS/kernel, which significantly increases response time. | 04-07-2016 |
20160110293 | SYSTEMS AND METHODS FOR INVALIDATING DIRECTORY OF NON-HOME LOCATIONS WAYS - Systems and methods for invalidating a way of a directory for non-home locations (DNHL) set that stores an identifier of a home location of an address is disclosed. As a part of a method, a request to store data in a location of a special cache that is being tracked by the way of the DNHL set is accessed, it is determined if an address stored in the location of the special cache is stored in a non-home location, a DNHL set is identified that tracks the location of the special cache if the address is not stored in a non-home location, and a set and way of the location of the special cache is compared with a set and way identifier stored in each way of the DNHL set. The way of the DNHL set that stores a matching set and way identifier is invalidated. | 04-21-2016 |
20160110294 | METHODS AND SYSTEMS FOR TRACKING ADDRESSES STORED IN NON-HOME CACHE LOCATIONS - Systems and methods for tracking addresses stored in non-home locations in a cache. A method includes determining if an address that is to be stored in a cache is to be stored in a non-home location, determining if a directory has a location available for storing an identifier of the non-home location and if one or more locations of the directory are available for storing an identifier of the non-home location, storing an identifier of the non-home location in one of the one or more locations of the directory. The method further includes invalidating a non-home location in the cache that corresponds to one of the one or more locations of the directory, if none of the one or more locations of the directory are available for storing an identifier of the non-home location, and storing an identifier of the non-home location in the one of the one or more locations. | 04-21-2016 |
20160117259 | STORAGE MANAGEMENT METHOD, STORAGE MANAGEMENT SYSTEM, COMPUTER SYSTEM, AND PROGRAM - A storage management method and the like for managing a hierarchical storage are provided. A storage management method is provided for managing a hierarchical storage including a lower storage tier, and a higher storage tier having higher speed than the lower storage tier, on a computer system including at least one computer. This storage management method includes a step of causing the computer system to copy a target data item from the higher storage tier to the lower storage tier, and a step of causing the system to determine whether or not to delete the entity of the data item on the higher storage tier having been subjected to the copying based on a time required for reading the copy of the data item. | 04-28-2016 |
20160140054 | METHOD AND SYSTEM FOR DETERMINING FIFO CACHE SIZE - Described herein are methods, systems and machine-readable media for simulating a FIFO cache using a Bloom filter ring, which includes a plurality of Bloom filters arranged in a circular log. New elements are registered in the Bloom filter at the head of the circular log. When the Bloom filter at the head of the circular log is filled to its capacity, membership information associated with old elements in the Bloom filter at the tail of the circular log is evicted (simulating FIFO cache behavior), and the head and tail of the log are advanced. The Bloom filter ring is used to determine cache statistics (e.g., cache hit, cache miss) of a FIFO cache of various sizes. In response to simulation output specifying cache statistics for FIFO cache of various sizes, a FIFO cache is optimally sized. | 05-19-2016 |
20160162413 | Application Startup Page Fault Management in a Hardware Multithreading Environment - A method, system and computer-usable medium are disclosed for startup page fault management improves application startup performance by assigning startup tasks to a hardware thread 0 across plural processing cores in a simultaneous multithreading environment to provide more rapid processing of processor bound page faults. I/O bound page faults are flagged to associated with predetermined cache locations to improve data and text first reference page-in I/O response. | 06-09-2016 |
20160170875 | MANAGED RUNTIME CACHE ANALYSIS | 06-16-2016 |
20160188491 | APPARATUS AND METHOD FOR ASYNCHRONOUS TILE-BASED RENDERING CONTROL - An apparatus and method are described for asynchronous tile-based rendering control. In one embodiment of the invention, there is a delay between when the graphics driver queues the GPU commands for rendering and when the GPU begins executing. During this delay, the graphics driver receives additional information or data about whether cache evictions may be inhibited. As such, it allows the graphics driver to defer the cache eviction control of its render cache until it has this extra information. By doing so, it reduces the memory bandwidth required for rendering 3D graphics applications and in turn reduces the power consumption of the GPU. | 06-30-2016 |
20160202936 | DATA MANAGEMENT ON MEMORY MODULES | 07-14-2016 |
20180024938 | ALLOCATING PHYSICAL PAGES TO SPARSE DATA SETS IN VIRTUAL MEMORY WITHOUT PAGE FAULTING | 01-25-2018 |
20220138111 | BLOCK DEVICE INTERFACE USING NON-VOLATILE PINNED MEMORY - A method comprising: receiving, at a block device interface, an instruction to write data, the instruction comprising a memory location of the data; copying the data to pinned memory; performing, by a vector processor, one or more invertible transforms on the data; and writing the data from the pinned memory to one or more storage devices asynchronously; wherein the pinned memory of the data corresponds to a location in pinned memory, the pinned memory being accessible by the vector processor and one or more other processors. | 05-05-2022 |