| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708670000 | Addition/subtraction | 58 |
| 20090216826 | GENERALIZED PROGRAMMABLE COUNTER ARRAYS - A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel counters. Resulting operands are then summed using a standard Ripple Carry Adder to produce the final result. The GPCA consists of a linear arrangement of identical compressor slices (CSlice). | 08-27-2009 |
| 20090265410 | Packed add-subtract operation in a microprocessor - A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided. | 10-22-2009 |
| 20090271465 | CONFIGURABLE HYBRID ADDER CIRCUITRY - Hybrid adder circuitry is provided for integrated circuits such as programmable integrated circuits. The hybrid adder may combine the capabilities of multiple adder architectures. Hybrid adders may include carry select and carry ripple adder circuits. The adder circuits may be combined using a carry look-ahead architecture. Adder functionality may be implemented using the resources of logic regions on the programmable integrated circuits. Each logic region may include combinatorial logic such as look-up table logic and register circuitry. The hybrid adder circuitry may receive input words to be added from the combinatorial circuitry and may produce corresponding arithmetic sum output signals to the register circuitry. | 10-29-2009 |
| 20100030836 | Adder, Synthesis Device Thereof, Synthesis Method, Synthesis Program, and Synthesis Program Storage Medium - A conventional multi-input adder has a problem that only either the number of stages of operation blocks or the number of half adders and full adders can be reduced. | 02-04-2010 |
| 20100030837 | COMBINED ADDER CIRCUIT ARRAY AND/OR PLANE - A method of modifying a group of full adder circuits to compute a Boolean function of a set number of input bits, each full adder circuit having first and second data inputs, a data output, a carry input and a carry output, the full adder circuits being interconnected so as to form a carry chain. The method comprises the steps of setting the first input of each full adder circuit to a same fixed value, connecting each respective input bit of the set number of input bits to the second input of a respective one of the full adder circuits and using the output of the carry chain of the array of full adder circuits as the result of the Boolean function. | 02-04-2010 |
| 20100049779 | SHARED PARALLEL ADDER TREE FOR EXECUTING MULTIPLE DIFFERENT POPULATION COUNT OPERATIONS - A shared parallel adder tree for executing multiple different population count operations on a single datum includes a number of carry-save adders (CSAs) and/or half adders (HAs), arranged in rows, where certain CSAs and HAs are dedicated to a single population count operation, while other CSAs and HAs are shared among two or more population count operations. The datum is applied to the first row in the tree. Partial sums of the number of ones at various locations within the tree are routed to certain CSAs and/or HAs “down” the tree to propagate the particular population count operations. Carry-propagate adders generate at least a portion of the final sum of the number of ones in certain population count operations. An “AND” operation on a particular number of the bits in the datum provides the high order bit of the resulting sum of the particular population count operation. | 02-25-2010 |
| 20100250641 | INFORMATION PROCESSING DEVICE, ARITHMETIC PROCESSING METHOD, AND ELECTRONIC APPARATUS - An information processing device includes: plural input registers including a first input register and a second input register; an added value register; a first adding unit that performs addition processing for stored data of the first input register and stored data of the second input register; a second adding unit that performs addition processing for connected data, which is obtained by connecting the stored data of the first input register and the stored data of the second input register, and stored data of the added value register; and plural output registers in which a processing result of the first adding unit or the second adding unit is stored, wherein in each of given execution cycles, the first adding unit stores a processing result of the first adding unit in any one of the plural output registers and the second adding unit stores a processing result of the second adding unit in any one of the plural output registers. | 09-30-2010 |
| 20100274831 | COMPUTING DEVICE, CALCULATING METHOD, AND PROGRAM PRODUCT - A computing device includes: a deciding unit which, in computation of values of nodes on a lattice in a direction where a value of m representing a horizontal axis coordinate of the lattice increases, decides dummy nodes to be added to m=n−1, so as to enable values of nodes on m=n to be calculated by adding the dummy nodes to m=n−1 and executing a vector operation through the use of the SIMD function by using values of nodes on m=n−1 and values of the added dummy nodes; an adding unit adding the dummy nodes decided by the deciding unit to m=n−1; and a calculating unit calculating the values of the nodes present on m=n by executing the vector operation through the use of the SIND function by using the values of the nodes on m=n−1 and the values of the dummy nodes added by the adding unit. | 10-28-2010 |
| 20100306302 | TECHNIQUE FOR DETERMINING IF A LOGICAL SUM OF A FIRST OPERAND AND A SECOND OPERAND IS THE SAME AS A THIRD OPERAND - A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings. | 12-02-2010 |
| 20110093518 | NEAR OPTIMAL CONFIGURABLE ADDER TREE FOR ARBITRARY SHAPED 2D BLOCK SUM OF ABSOLUTE DIFFERENCES (SAD) CALCULATION ENGINE - Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network. | 04-21-2011 |
| 20110238721 | ADDER CIRCUIT AND XIU-ACCUMULATOR CIRCUIT USING THE SAME - A Xiu-accumulator circuit including N cascaded adders is provided. Each adder includes two registers, wherein one register stores an addition result information and the other register stores a carry-in information. Respective addition result information from respective adder is further fed back to itself for accumulation. The carry-in information outputted from a previous stage adder is fed to a next stage adder at a next clock cycle. After N clock cycles, the carry-in information outputted from the first stage adder is fed to the last stage adder. | 09-29-2011 |
| 20130007086 | METHOD OF OPTIMIZING COMBINATIONAL CIRCUITS - A method of simplifying a combinational circuit establishes an initial combinational circuit operable to calculate a set of target signals. A quantity of multiplication operations performed in a first portion of the initial combinational circuit is reduced to create a first, simplified combinational circuit. The first portion includes only multiplication operations and addition operations. A quantity of addition operations performed in a second portion of the first, simplified combinational circuit is reduced to create a second, simplified combinational circuit. The second portion includes only addition operations. Also, the second, simplified combinational circuit is operable to calculate the target signals using fewer operations than the initial combinational circuit. | 01-03-2013 |
| 20130080495 | SOFTWARE RECONFIGURABLE DIGITAL PHASE LOCK LOOP ARCHITECTURE - A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle. | 03-28-2013 |
| 20130297667 | OSBS subtractor Accelerator - The OSBS Subtractor Accelerator will enable the subtraction operation to simultaneously subtract all Bits of a data set, where: no ripple affect, no complement operations; therefore no multiple additions, no multiple moves, no temporary storage and no multiple instruction steps are required. In stand alone (pure) format the required time is six propagation delays to perform a subtraction operation. Beside the pure format a distributed or grouped format is available; which is dividing both input operands into groups. This grouped configuration also performs a parallel operation on the bits and on the groups in the same time. However, it needs nine propagation delays to execute a subtraction operation (including the first and second XOR gates); regardless it is a 16, 32 or 64 bit subtractor. It uses considerably less number of components than the pure configuration, and none of the integrated circuits have more than 5 input pins. | 11-07-2013 |
| 20140280429 | Efficient Hardware Structure For Sorting/Adding Multiple Inputs Assigned To Different Bins - In one embodiment, a four-input, four-output bin adder is disclosed. The bin adder comprises a two-by-three, multi-stage, cascaded array of two-input, two-output adder circuits. Each of the bin-adder input signals comprises a numeric data value and an associated address, and the bin adder is adapted to add together (a.k.a. accumulate) the numeric values of only those inputs signals having addresses that are the same. In particular, the inputs and outputs of the two-input, two-output adder circuits are connected together in such a way that each input signal is compared to every other input signal, in a round-robin configuration. If the associated addresses match, then the input signals' numeric data values are added (i.e., accumulated) and output as a single signal comprising the sum of the numeric data values and the common address. | 09-18-2014 |
| 20150052181 | PARAMETER GENERATING DEVICE AND METHOD - The present invention discloses a parameter generating device and the method thereof to generate a parameter for circuit operation in which the parameter corresponds to an N degree polynomial of a characteristic curve while said N is a positive integer. The parameter generating device comprises: a storage circuit to store at least N+1 initial values that are determined by a start value and a unit variation amount; and an parameter calculating circuit, coupled to the storage circuit, to carry out addition calculation for at least [(K−1)×N+1] time(s) if a multiple K is positive or subtraction calculation for at least −K×N time(s) if the multiple K is negative, so as to generate the aforementioned parameter, wherein the multiple K is derived from a difference divided by the unit variation amount while the difference is a current value minus the start value. | 02-19-2015 |
| 708671000 | Comparison | 4 |
| 20080263123 | Method and system for determining a minimum number and a penultimate minimum number in a set of numbers - There is provided a system for determining a minimum number and a penultimate minimum number in a set of numbers. According to one embodiment, the system includes a first comparator module configured to receive a first subset of the set of numbers and to compare the first subset to determine a first minimum number and a first penultimate minimum number. The system also includes a second comparator module configured to receive a second subset of the set of numbers and to compare the second subset to determine a second minimum number and a second penultimate minimum number. The system further includes a third comparator module configured to receive and compare the first and second minimum numbers and the first and second penultimate minimum numbers to determine the minimum number and the penultimate minimum number in the set of numbers. | 10-23-2008 |
| 20090172070 | Single Clock Cycle First Order Limited Accumulator for Supplying Weighted Corrections - A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle. | 07-02-2009 |
| 20140040342 | HIGH SPEED ADD-COMPARE-SELECT CIRCUIT - In described embodiments, a trellis decoder includes a memory including a set of registers; and an add-compare-select (ACS) module including at least two ACS layer modules coupled in series and configured to form a feedback loop with carry components in a single clock cycle, wherein the ACS layer module includes at least two branch metrics represented by a plurality of bits and adders configured to generate a plurality of state metrics using carry-save arithmetic, and a plurality of multiplexers configured to perform a selection of a maximum state metric in carry-save arithmetic stored in memory as the carry components. A method of performing high speed ACS operation is disclosed. | 02-06-2014 |
| 20160019028 | CHECKING ARITHMETIC COMPUTATIONS - Checking correctness of computations. An arithmetic logic unit circuit provides a computation result as a first number. The computation result is increased by a constant as a second number by the arithmetic logic unit circuit. A sum of the first number and the constant is compared to the second number, and an error is reported, if the comparing operation does not indicate an equal result. | 01-21-2016 |
| 708672000 | Incrementation/decrementation | 2 |
| 20130290393 | Expanded Scope Incrementer - An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word. | 10-31-2013 |
| 20150324170 | BINARY ARRAY WITH LSB DITHERING IN A CLOSED LOOP SYSTEM - A binary array system and method for operating an electrical system are disclosed. The binary array system includes a binary counter configured to output a number of bit values through a number of bit outputs. Each of the bit values are output through a corresponding one of the bit outputs. The system includes a number of binary array elements. Each of the binary array elements is coupled to a corresponding one of the bit outputs and is configured to provide a unit value based on one of the bit values output through the corresponding one of the bit outputs. The binary array system also includes a controller coupled to the binary counter that is configured to set the bit values of the binary counter. | 11-12-2015 |
| 708680000 | Decimal | 2 |
| 20120078993 | Reduced-Level Two's Complement Arithmetic Unit - A processor includes a two's complement arithmetic unit that reduces a level of complexity in the critical path by eliminating the addition of the “1” to the carry in of the two's complement arithmetic unit. To execute a subtraction instruction using two's complement arithmetic, the subtraction as disclosed herein is performed in accordance with the identity “A−B=not (not (A)+B),” where A is a first operand and B is a second operand that is to be subtracted from A. Accordingly, the addition of the “1” term into the carry in is eliminated, and reduces a level of complexity that would otherwise slow down and/or limit the speed at which a subtraction instruction can be performed. | 03-29-2012 |
| 20140149481 | Decimal Multi-Precision Overflow and Tininess Detection - An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory area. The boundary indicator indicates whether a collective result generated from the intermediate results is within a boundary precision value. | 05-29-2014 |
| 708683000 | Coded decimal | 2 |
| 20100146031 | Direct Decimal Number Tripling in Binary Coded Adders - The digital propagate, digit generate, sum+0, and sum+1 terms used in typical carry-propagate adders are generated directly off the multiplicand. During the direct generation, the logic takes into account that each digit will be tripled and if each digit's next less significant digit is greater than 4. Using this technique, the generation of the multiplicand is significantly faster and uses less circuitry. | 06-10-2010 |
| 20140115023 | BID TO BCD/DPD CONVERTERS - A method and system for binary to binary coded decimal (BCD) conversion. The conversion includes: obtaining a binary input vector; generating, by a binary/BCD hardware converter, a plurality of BCD vectors based on the binary input vector; and calculating a BCD output vector based on the plurality of BCD vectors. | 04-24-2014 |
| 708700000 | Binary | 32 |
| 20090077155 | HIGH SPEED ADDER DESIGN FOR A MULTIPLY-ADD BASED FLOATING POINT UNIT - A method is provided for improving a high-speed adder for Floating-Point Units (FPU) in a given computer system. The improved adder utilizes a compound incrementer, a compound adder, a carry network, an adder control/selector, and series of multiplexers (muxes). The carry network performs the end-around-carry function simultaneously to and independent of other required functions optimizing the functioning of the adder. Also, the use of a minimum number of muxes is also utilized to reduce mux delays. | 03-19-2009 |
| 20090248781 | METHOD AND DEVICE FOR DYNAMICALLY VERIFYING A PROCESSOR ARCHITECTURE - A method and device may be useful for dynamically verifying a processor architecture at runtime. The checker may more efficiently and cheaply verify at least some of the functionality provided by the execution unit of the processor architecture. The checker may verify operations such as addition, subtraction, multiplication, and division. | 10-01-2009 |
| 20090313315 | N-digit subtraction unit, N-digit subtraction module, N-digit addition unit and N-digit addition module - Provided are N-digit addition and subtraction units and N-digit addition and subtraction modules in which borrowing and carrying are not propagated in modules having basic digits. In the units and modules, an output pattern of results of addition and subtraction is predicted based on a relation between an augend and an addend and a relation between a minuend and a subtrahend, respectively, thereby preventing borrowing and carrying from being propagated in modules having basic digits. | 12-17-2009 |
| 20100057825 | METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION FOR A MODULO ADDER FOLLOWED BY SATURATION CONCURRENT MESSAGE PROCESSING - A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A′, B′) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A′, B′) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit ( | 03-04-2010 |
| 20110153709 | DELAY OPTIMAL COMPRESSOR TREE SYNTHESIS FOR LUT-BASED FPGAS - A compressor tree synthesis algorithm, named DOCT, which guarantees the delay optimal implementation in LUT-based FPGAs. Given a targeted K-input LUT architecture, DOCT firstly derives a finite set of prime patterns as essential building blocks. Then, it shows that a delay optimal compressor tree can always be constructed by those derived prime patterns via integer linear programming (ILP). Without loss of delay optimality, a post-processing procedure is invoked to reduce the number of demanded LUTs for the generated compressor tree design. DOCT has been evaluated over a broad set of benchmark circuits. The DOCT reduces the depth of the compressor tree and the number of LUTs based on the modern 8-input LUT-based FPGA architecture. | 06-23-2011 |
| 20120047194 | COMPARING DATA SAMPLES REPRESENTED BY CHARACTERISTIC FUNCTIONS - According to certain embodiments, a first characteristic function representing a first set of samples and a second characteristic function representing a second set of samples are generated. The first characteristic function and the second characteristic function are transformed to a first arithmetic function and a second arithmetic function, respectively. A first hash code and a second hash code are calculated from the first arithmetic function and the second arithmetic function, respectively. If the first hash code equals the second hash code, the first set of samples and the second set of samples are designated as equivalent; otherwise, the first set of samples and the second set of samples are designated as not equivalent. | 02-23-2012 |
| 20120124120 | ADDER - According to an embodiment, an adder includes first and second wave computing units and a threshold wave computing unit. Each of the first and second wave computing units includes a pair of first input sections, a first wave transmission medium having a continuous film including a magnetic body connected to the first input sections, and a first wave detector outputting a result of computation by spin waves induced in the first wave transmission medium by the signals corresponding to the two bit values. The threshold wave computing unit includes a plurality of third input sections, a third wave transmission medium having a continuous film including a magnetic body connected to the third input sections, and a third wave detector a result of computation by spin waves induced in the third wave transmission medium. | 05-17-2012 |
| 20120265797 | MONTGOMERY MULTIPLICATION METHOD - Disclosed is a method of modular multiplication of two L-bit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2 | 10-18-2012 |
| 20120311009 | HYBRID ADDER USING DYNAMIC AND STATIC CIRCUITS - A hybrid adder may include static partial sum circuits that operate to generate partial sums of operands, where each operand may be divided into groups that include multiple bits. A first subset of the static partial sum circuits may generate a partial sum of a corresponding group of the two or more operands assuming a carry in of 0 to the corresponding group, and a second subset may similarly assume a carry in of 1 to the corresponding group. The adder may further include a dynamic carry tree circuit that generates arithmetic carry signals, where each of the arithmetic carry signals corresponds to a respective group of sum bits. The adder may further include a multiplexer that, during operation, selects each of the groups of sum bits from either of the first or the second subsets of static partial sum circuits dependent upon corresponding ones of the arithmetic carry signals. | 12-06-2012 |
| 20130311534 | DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION - A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary ( | 11-21-2013 |
| 20140214913 | ADDER CAPABLE OF SUPPORTING ADDITION AND SUBTRACTION OF UP TO N-BIT DATA AND METHOD OF SUPPORTING ADDITION AND SUBTRACTION OF A PLURALITY OF DATA TYPE USING THE ADDER - An adder for supporting multiple data types by controlling a carry propagation is provided. The adder includes a plurality of first addition areas configured to receive pieces of incoming operand data, wherein each of the plurality of first addition areas includes a predetermined unit number of bits, and a plurality of second addition areas configured to receive pieces of control data based on a type of the operand data and an operation type, wherein the plurality of second addition areas are alternately arranged between the plurality of first addition areas. | 07-31-2014 |
| 708702000 | Field-Effect transistor (FET) | 1 |
| 20150019610 | FULL ADDER CIRCUIT - A full adder circuit includes a first logical operation unit suitable for outputting an inverse of the second input signal and a first output signal corresponding to either a second input signal or the inverse of the second input signal in response to a first input signal, a second logical operation unit suitable for outputting an inverse of the first output signal and a sum signal corresponding to either the first output signal or the inverse of the first output signal in response to a carry input signal, and a third logical operation unit suitable for outputting a carry output signal in response to the inverse of the second input signal, the first output signal, the inverse of the first output signal, and the sum signal. | 01-15-2015 |
| 708703000 | Gate functional level | 1 |
| 20080256165 | Full-Adder Modules and Multiplier Devices Using the Same - A full-adder module ( | 10-16-2008 |
| 708706000 | Parallel | 19 |
| 20090070400 | CARRY-SELECT ADDER - A carry select adder to add two binary addends to produce a binary sum. In a first section a first addition block adds 6-bit addend slices having 3-bit lower-half and higher-half slices. A first adder block receives and adds the lower-half slices and outputs an adder-carry-out and a 3-bit lower-half value. A zero-carry-loaded second adder block receives and adds the higher-half slices and outputs a 4-bit zero-related intermediate-value. A one-carry-loaded third adder block receives and adds the higher-half slices and outputs a 4-bit one-related intermediate-value. A 4-bit multiplexer then passes either the zero-related intermediate-value or the one-related intermediate-value as a 1-bit section-carry-out and a 3-bit higher-half value based on the adder-carry-out, wherein the higher-half value and the lower-half value form a 6-bit sum slice corresponding to the 6-bit addend slices. | 03-12-2009 |
| 20130117345 | PARALLEL SELF-TIMER ADDER (PASTA) - A parallel self-timed adder (PASTA) is disclosed. It is based on recursive formulation and uses only half adders for performing multi-bit binary addition. Theoretically the operation is parallel for those bits that do not need any carry chain propagation. Thus the new approach attains logarithmic performance without any special speed-up circuitry or look-ahead schema. The corresponding CMOS implementation of the design along with completion detection unit is also presented. The design is regular and does not have any practical limitations of fan-ins or fan-outs or complex interconnections. Thus it is more suitable for adoption in fast adder implementation in high-performance processors. The performance of the implementation is tested using SPICE circuit simulation tool by linear technology. Simulation results show its superiority over cascaded circuit adders. A constant time carry propagation is also achieved using the proposed implementation by tuning the CMOS parameters. | 05-09-2013 |
| 20140324937 | METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER - A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit, adding the inputs using a parallel structure, wherein the parallel structure is optimized to accelerate the addition by utilizing a characteristic that the inputs are one bit each, and transmitting the resulting outputs to a subsequent stage. | 10-30-2014 |
| 708707000 | Carry-ripple | 2 |
| 20090265411 | CRYPTOGRAPHIC AUTHENTICATION APPARATUS, SYSTEMS AND METHODS - Apparatus, systems, and methods send an interrogation command from an interrogation and timing apparatus to a timed identification (TID) apparatus. The TID apparatus receives the interrogation command, performs a series of logical operations to calculate a response, and returns the response within a maximum length of time established by the interrogation and timing apparatus. The interrogation and timing apparatus confirms that the length of time between sending the interrogation command and receiving the response is within the maximum length of time and that the response is correct. If so, the TID apparatus is authenticated. Additional embodiments are disclosed and claimed. | 10-22-2009 |
| 20090327388 | STATIC LOGIC LING ADDER - In general, in one aspect, the disclosure describes a prefix tree adder. The adder may be used to add two strings of bits or multiply a string of bits by 3. First group carry generate and propagate signals are calculated directly from inputs to the adder using Ling equations and static logic. The previously calculated group carry generate and propagate signals are propagated through the adder to calculate additional group carry generate and propagate signals. A conditional summer receives a plurality of inputs for the bits and calculates multiple sums for the bits. The conditional summer selects an appropriate sum for the bits based on carry signals utilized as control signals. The number of delay stages required to calculate the sum is LOG | 12-31-2009 |
| 708708000 | Carry-save adders | 5 |
| 20080281897 | Universal execution unit - Methods and apparatus are described for an execution unit. A method includes receiving an instruction and one or more operands, determining a plurality of program bits and one or more sets of pluralities of select input bits, based on the instruction and the one or more operands, determining a plurality of extra adder input bits, based on the instruction and the one or more operands, determining a plurality of multiplexer output bits, based on the plurality of program bits and the one or more sets of pluralities of select input bits, determining one or more carry-save adder tree outputs, based on the plurality of multiplexer output bits and the plurality of extra adder input bits, determining a carry-propagate adder sum output, based on the one or more carry-save adder tree output; and determining the result of the instruction on the one or more operands, based on the carry-propagate adder sum output. An apparatus includes a finite state machine comprising an instruction input, a plurality of operand inputs, a plurality of outputs, a plurality of extra adder inputs, a result output, and condition code output flags, an array of multiplexers coupled to the plurality of outputs and comprising a plurality of multiplexer outputs, a carry-save adder tree coupled to the plurality of multiplexer outputs and coupled to the extra adder inputs and comprising a plurality of carry-save adder tree outputs coupled to the finite state machine, and a carry-propagate adder coupled to the plurality of carry-save adder tree outputs and comprising a plurality of carry-propagate adder outputs coupled to the finite state machine. | 11-13-2008 |
| 20090063609 | Static 4:2 Compressor with Fast Sum and Carryout - In one embodiment, a compressor circuit has a carry-in input and input bits a, b, c, and d. The compressor circuit comprises a first multiplexor (mux) coupled to receive a value of input bit a and a complement of the value of input bit a as inputs and a value of the input bit b as a first selection control. The first mux has a first output. Coupled to receive a value of input bit c and a complement of the value of input bit c as inputs and a value of the input bit d as a second selection control, a second mux has a second output. A third mux is coupled to receive the first output and a complement of the first output as inputs and the second output as a third selection control, and the third mux has a third output. The fourth mux, coupled to receive a value of the third output and a complement of a value of the third output as inputs and the carry-in input as a fourth selection control, has a fourth output which is a sum output of the compressor circuit. In another embodiment, a processor comprises an arithmetic unit comprising a plurality of the compressor circuits arranged in two or more levels of compressor circuits. By making use of the redundancy available in the compressor outputs, the carry logic may be more efficient than previous designs. Additionally, a fast sum generation (e.g. 3 two input XOR delays) may be implemented. | 03-05-2009 |
| 20130179483 | Technique for Optimization and Re-Use of Hardware In the Implementation of Instructions Used in Viterbi and Turbo Decoding, Using Carry and Save Arithmetic - The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic. | 07-11-2013 |
| 20130179484 | Efficient Technique for Optimal Re-Use of Hardware In the Implementation of Instructions Used in Viterbi, Turbo and LPDC Decoders - Low density parity check (LDPC) decoding can be mapped to a class of DSP instructions called MINST. The MINST class of instructions significantly enhance the efficiency of LDPC decoding by merging several of the functions required by LDPC decoders into a single MINST instruction. This invention is an efficient implementation of the MINST class of instructions using a configurable three input arithmetic logic unit. The carry output results of the three input arithmetic logic unit enable permit boundary decisions in a range determination required by the MINST instruction. The preferred embodiment employs 2's complement arithmetic and carry-save adder logic. This invention allows reuse of hardware required to implement MAX* functions in LDPC functions. | 07-11-2013 |
| 20130275485 | Technique for Optimization and Re-Use of Hardware in the Implementation of Instructions Used in Viterbi and Turbo Decoding, Using Carry Save Arithmetic - The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2−b2+c2) with (x2+y2+z2); and (a3+b3−c3) with (x3+y3+z3); implementing an efficient method of computing (a4−b4−c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic. | 10-17-2013 |
| 708710000 | Carry look-ahead | 6 |
| 20080228847 | N Bit Adder and Corresponding Adding Method - An n bit adder includes first computing circuit with 2n inputs for receiving n values of bits of first and second binary numbers and an additional input for receiving an input carry digit. The first computing circuit elaborates from each of the n pairs of bit values of the same significance, a carry digit propagating signal and diagonal generation signals. The adder further including: an estimating circuit performing a first estimation of each coefficient of the number resulting from the sum of the first and second numbers, by using the complement of the corresponding bit of significance of the first number; a second computing circuit, elaborating a set of correcting signals based on the propagating signals and the diagonal generation signals; a correcting block applying to each estimated value of bit of significance k of the sum, k+1 corrections using the correcting signals, and delivering n bits of the sum. | 09-18-2008 |
| 20090112963 | METHOD TO PERFORM A SUBTRACTION OF TWO OPERANDS IN A BINARY ARITHMETIC UNIT PLUS ARITHMETIC UNIT TO PERFORM SUCH A METHOD - A method, circuit apparatus, and a design structure on which the circuit resides, is provided to perform a subtraction of two operands in a binary arithmetic unit by subdividing two operands into groups of equal numbers of bits, generating, by appropriate arithmetic operations, pairs of intermediate results for the particular groups of bits of the two operands comprising the same bit positions, respectively. A first intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘0’ and a second intermediate result of each pair of intermediate results is generated under the assumption of a carry-in of ‘1’. The correct intermediate result of each particular pair of intermediate results from each group of bits is selected, and the result of the subtraction of the two operands is generated by an appropriate merging of the selected correct intermediate results. | 04-30-2009 |
| 20090138537 | Address generating circuit and semiconductor memory device - An address generating circuit includes a first carry look-ahead circuit for performing an operation using an inputted first carry and a first address and outputting a first output address and a first output carry respectively as a first operation result, a second carry look-ahead circuit for performing an operation using a carry fixed to 0 and a second address and outputting a second output address and a second output carry respectively as a second operation result, a third carry look-ahead circuit for performing an operation using a carry fixed to 1 and the second address and outputting a third output address and a third output carry respectively as a third operation result, and a first select circuit for selecting either of the second and third operation results based on the first output carry and outputting the selected operation result. | 05-28-2009 |
| 20090187617 | Carry look-ahead circuit and carry look-ahead method - A carry look-ahead circuit generates a generate output for generating a carry, from a plurality of inverted generate inputs and a plurality of inverted propagate inputs to peer bits of a first operand and a second operand including a plurality of bits. The carry look-ahead circuit includes a circuit that receives the inverted generate inputs excluding the inverted generate input of a most significant bit among the inverted generate inputs and the inverted propagate inputs and generates an inverted pseudo generate signal of the generate output; and a circuit that receives the inverted generate input of the most significant bit among the inverted generate inputs and the inverted pseudo generate signal and outputs the generate output. | 07-23-2009 |
| 20120259908 | FAST CARRY LOOKAHEAD CIRCUITS - A fast lookahead carry adder includes adder logic and lookahead carry-path logic coupled to the adder logic. The carry path logic has a main carry path, a carry entrance path and a carry exit path, the carry entrance path separate from the carry exit path. | 10-11-2012 |
| 20140006470 | Carry Look-Ahead Adder with Generate Bits and Propagate Bits Used for Column Sums | 01-02-2014 |
| 708714000 | Conditional sums | 3 |
| 20090132631 | METHOD OF FORCING 1's AND INVERTING SUM IN AN ADDER WITHOUT INCURRING TIMING DELAY - A summing circuit for an adder decodes control signals to determine that the result should be manipulated, and generates a half-sum output which is used to produce a manipulated result based on the control signals. The half-sum output is combined with a previous carry bit to complete the sum operation. The control signals can invert the adder result, or force the result to be all 1's. These functions can be effectuated in a 3-way multiplexer that combines the operand inputs and control signals. For inversion, two separate logic circuits produce true and complement half-sums in parallel, and the appropriate half-sum is selected for the half-sum output. For a result of all 1's, a force_1 control signal pulls the half-sum output node to electrical ground and the final output is manipulated by gating the carry signals with the force_1 signal. The two functions are implemented without introducing additional delay. | 05-21-2009 |
| 20090204659 | N-BIT ADDER AND CORRESPONDING ADDITION METHOD - An adder is provided for adding input signals including first and second binary input numbers, with N bits each. The adder includes a determination circuit capable of determining the bits of the sum of the input signals. The determination circuit includes an estimating circuit including estimating blocks connected in series, each estimating block being capable of estimating each bit of the sum, and a correction circuit capable of generating a correction signal so as to correct each estimated bit of the sum after each estimate. Each correction signal of an estimated bit rank i of the sum is generated using the last rank i−1 estimated and corrected bit of the sum, the correction signal of said last rank i−1 bit, and the last estimated and corrected rank i−2 bit of the sum. | 08-13-2009 |
| 20100036902 | M-BIT RACE DELAY ADDER AND METHOD OF OPERATION - There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, A | 02-11-2010 |
