| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708550000 | Compensation for finite word length | 12 |
| 708551000 | Round off or truncation | 10 |
| 20090100122 | SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS - Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention. | 04-16-2009 |
| 20090172067 | METHODS AND APPARATUS FOR IMPLEMENTING A SATURATING MULTIPLIER - Methods and apparatus are provided for implementing an efficient saturating multiplier associated with addition and subtraction logic. The result of the multiplier is saturated before accumulating. The result of the multiplier can be stored in a result register in unsaturated form. The output of the result register can then be saturated and provided to addition and subtraction logic to allow efficient implementation of a saturating multiplier. | 07-02-2009 |
| 20100125620 | ARITHMETIC PROCESSING DEVICE AND METHODS THEREOF - A device and methods are disclosed for communicating an unrounded result from one arithmetic calculation for use in a second, subsequent calculation. For example, an unrounded result of a first calculation can be forwarded to provide a multiplier, a multiplicand or an addend operand for the subsequent operation. The operand can be forwarded to the input of the same fused multiply addition module (FMAM) that supplied the result, or to another FMAM, and do so without regard to the precision of the forwarded operand, the precision of the subsequent operation, or the native precision of the FMAM. | 05-20-2010 |
| 20100131580 | APPARATUS AND METHODS FOR HARDWARE-EFFICIENT UNBIASED ROUNDING - A system and method for unbiased rounding away from, or toward, zero comprising apparatus for truncating N bits from an original M bit input number thereby to provide a M−N bit number, and apparatus for adding the equivalent value of ‘½’ to the M−N bit number unless the input number is negative, or positive, respectively, and the N truncated bits represent exactly ½. | 05-27-2010 |
| 20120215825 | EFFICIENT MULTIPLICATION TECHNIQUES - Techniques are disclosed that involve the multiplication of values. For instance, a plurality of partial products may be calculated from a first operand and a second operand. This calculating bypasses calculating partial products having corresponding shift values that are less than a shift threshold value. These partial products are summed to produce a summed product. In turn, the summed product is truncated into a final product having a final precision. This final precision may be a shared precision employed by multiple processing units (e.g., algorithmic units in a graphics or display processing pipeline). | 08-23-2012 |
| 20120311008 | SMART ROUNDING SUPPORTING PSYCHOLOGICAL PRICING - Pricing values may be automatically computed by converting a base price with a predefined price ending based on predetermined rounding rules. A base price may be adjusted employing a rounding syntax and two pricing points, one for a rounding lower limit the other for rounding upper limit. Based on a comparison of a portion of the price computed with the rounding syntax, the adjusted (or sales) price may be computed reflecting a desired pricing strategy such as a psychological pricing strategy. | 12-06-2012 |
| 20130007085 | Method and Apparatus For Performing Lossy Integer Multiplier Synthesis - A method is provided for deriving an RTL a logic circuit performing a multiplication as the sum of addends operation with a desired rounding position. In this, an error requirement to meet for the design rounding position is derived. For each of the CCT and the VCT implementation a number columns to discard is derived and a constant to include in the sum addends. For an LMS implementation, a number of columns to discard is derived. After discarding the columns and including the constants as appropriate, an RTL representation of the sum of addends operation is derived for each of the CCT, VCT and LMS implementations and a logic circuit synthesized for each of these. The logic circuit which gives the best implementation is selected for manufacture. | 01-03-2013 |
| 20140181170 | ARITHMETIC CIRCUIT AND ARITHMETIC METHOD - According to one embodiment, an arithmetic circuit includes follows. The arithmetic unit performs an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits. The rounding preprocessor performs an OR operation on lower (m−k) bits of the first value to generate a second value of 1 bit. The register stores a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value. The rounding postprocessor calculates a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and adds the carry bit value to upper n bits of the third value. | 06-26-2014 |
| 20150039665 | DATA PROCESSING APPARATUS AND METHOD FOR PERFORMING A NARROWING-AND-ROUNDING ARITHMETIC OPERATION - A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N| 02-05-2015 | |
| 20150379526 | TRACKING AND LINKING MOBILE DEVICE ACTIVITY - Methods for tracking mobile devices with increased accuracy include generating a first time-dependent identifier. Generating the first time-dependent identifier includes device information, location information, and time information identified for the device and for a request by the device to visit a third-party content supplier in association with a redirection instruction. One or more embodiments monitor additional activity by a plurality of client devices for a second time-dependent identifier. Because both identifiers are time dependent, if the identifiers match, one or more embodiments can determine that the client device has performed an action at the third-party content supplier in association with the redirection instruction with an improved probability of accuracy. | 12-31-2015 |
| 708552000 | Overflow or underflow | 2 |
| 708553000 | Prediction | 2 |
| 20090043835 | METHOD FOR EFFICIENT AND RELIABLE COMPUTATION OF RESULTS FOR MATHEMATICAL FUNCTIONS - A method is provided for efficient computation of reliable results for mathematical functions. The method may include an interface, a control module, and an error module. The interface receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical function varies with respect to the values for the arguments. The control module determines whether executing the mathematical function using the plurality of arguments will produce a result within the range of computable results. The error module aborts the mathematical function call prior to initiating execution of the mathematical function in response to determining that the values for the plurality of arguments produce a result outside the range of computable results. | 02-12-2009 |
| 20130151579 | APPARATUSES AND RELATED METHODS FOR OVERFLOW DETECTION AND CLAMPING WITH PARALLEL OPERAND PROCESSING - A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis. | 06-13-2013 |
