| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708530000 | Error detection or correction | 10 |
| 20080215661 | WAVEFORM CORRECTION APPARATUS AND WAVEFORM CORRECTION METHOD - This disclosure concerns a waveform corrector comprising a first portion calculating an offset value of an intermediate value between a maximum value and a minimum value of a signal with respect to a reference value; a second portion calculating an actual amplitude of the signal by subtracting the offset value from the maximum value or the minimum value; a third portion generating a first correction signal by subtracting the offset value from the digital signal; a fourth portion subtracting a value obtained by shifting a figure of the actual amplitude from the actual amplitude so that the actual amplitude converges into a reference amplitude; and a fifth portion subtracting a value obtained by shifting the first correction signal by an amount identical to a shift amount of the actual amplitude from the first correction signal so that the first correction signal converges into a second correction signal. | 09-04-2008 |
| 20080313253 | OPERATION CIRCUIT FOR MODIFIED EUCLIDEAN ALGORITHM IN HIGH-SPEED REED-SOLOMON DECODER AND METHOD OF IMPLEMENTING THE MODIFIED EUCLIDEAN ALGORITHM - Provided are an operation circuit for a modified Euclidean algorithm in a high-speed Reed-Solomon (RS) decoder and a method of implementing the modified Euclidean algorithm. Since a finite state machine (FSM) for generating a stop signal and an FSM for generating a control signal that controls a swap operation, a shift operation, and a polynomial operation for each basic cell of the modified Euclidean algorithm are used, an area-efficient RS decoder can be realized without using a conventional degree computation unit for comparing and calculating degrees. | 12-18-2008 |
| 20090112961 | ERROR-CORRECTING METHOD USED IN DATA TRANSMISSION AND DECODING - An error-correcting method used in decoding data transmission is disclosed. The error-correcting method is used for analyzing an error receiving data received from a receiving terminal and comprises: providing a first calculating formula for manipulation of the receiving data to generate the first sum; providing a second calculating formula for manipulation of the receiving data to generate the second sum; identifying the error position of the receiving data according to the result of dividing the second sum by the first sum. | 04-30-2009 |
| 20120197956 | CALCULATING UNIT FOR REDUCING AN INPUT NUMBER WITH RESPECT TO A MODULUS - A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number. | 08-02-2012 |
| 20120239720 | EFFICIENT AND RELIABLE COMPUTATION OF RESULTS FOR MATHEMATICAL FUNCTIONS - For efficient computation of results for mathematical functions, a method receives a mathematical function call. The call includes a plurality of arguments for which a range of computable results for the mathematical function of the function call varies with respect to the values for the arguments. The method determines whether executing the mathematical function using the plurality of arguments will produce a result within the range of computable results. The method further aborts the mathematical function call prior to initiating execution of the mathematical function in response to determining that the values for the plurality of arguments produce a result outside the range of computable results. | 09-20-2012 |
| 20120278374 | Decimal Floating-Point Quantum Exception Detection - A system and method for detecting decimal floating point data processing exceptions. A processor accepts at least one decimal floating point operand and performs a decimal floating point operation on the at least one decimal floating point operand to produce a decimal floating point result. A determination is made as to whether the decimal floating point result fails to maintain a preferred quantum. The preferred quantum indicates a value represented by a least significant digit of a significand of the decimal floating point result. An output is provided, in response to the determining that the decimal floating point result fails to maintain the preferred quantum, indicating an occurrence of a quantum exception. A maskable exception can be generated that is immediately trapped or later detected to control conditional processing. | 11-01-2012 |
| 20140059105 | ACCURACY CONFIGURABLE ADDERS AND METHODS - A preferred method of accuracy configuration with an approximate adder receives two input operands and generates a first approximate adder output with a plurality of sub-adders having a first accuracy under a first condition. Error detection and correction is selectively enabled to generate a next approximate adder output having a second accuracy that is higher than the first accuracy under a second condition. In preferred embodiments, a pipelined architecture provides selectable stages and the enablement of each successive stage provides a high level of accuracy. Power gated control can achieve enablement of error correction stages to conserve power. | 02-27-2014 |
| 708531000 | Parity check | 2 |
| 20100030835 | Variable Node Processing Unit - A variable node processing unit with N+1 inputs, having at least a first bank of two-input adders and a separate last bank of two-input adders, where the banks of adders are disposed in series. | 02-04-2010 |
| 20130254252 | Variable Node Processing Unit - A low-density parity check min-sum decoder including a variable node processing unit having N+1 inputs. A first bank of N+1 two-input adders each have an associated output, and at least one of the N+1 inputs go to more than two of the adders of the first bank. A second bank of N two-input adders has no adders in common with the first bank. At least one of the adders of the first bank provides its associated output to more than one adder of the second bank. The banks of adders are disposed in series. A sign module outputs a sign value produced from one of the inputs and an output from one of the adders of the second bank. N+1 outputs are provided, where one of the outputs is the sign value. | 09-26-2013 |
| 708532000 | Residue code | 1 |
| 20100036901 | MODULUS-BASED ERROR-CHECKING TECHNIQUE - During a method, a modulus circuit determines a modulus base p of a first number and a modulus base p of a second number. Also, the modulus circuit performs the operation using the modulus base p of the first number and the modulus base p of the second number, and calculates a modulus base p of the result of the operation involving the first number and the second number. Next, the modulus circuit compares the result of the operation carried out on the modulus base p of the first number and the modulus base p of the second number with the modulus base p of the operation performed on the first number and the second number to identify potential errors associated with the operation. Moreover, the modulus circuit repeats the method to identify additional potential errors associated with the operation, where the determining and calculating operations are repeated using moduli base q. | 02-11-2010 |
