| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708316000 | Having multiplexing | 12 |
| 20080250093 | Method and Apparatus for Filtering Multiple Channels of Signals - To reduce chip size and lower cost by using a method of multiplexing a device to filter a plurality of signals, the present invention provides an apparatus for filtering the plurality of signals, comprising: a group of storage units, for storing the plurality of signals, wherein the group of storage units comprises a plurality of storage units, each of which is used to store corresponding signal segments in each signal and output the stored signal segments in a predefined order; and a processing module, for weighting and combining the output signals from the group of storage units, to obtain a plurality of filtered signals corresponding to the multiple channels of signals. The group of storage units may further comprise a group of combining units, for combining output signal segments from the storage units to be processed with a same weight value. The present invention further provides the corresponding method for filtering a plurality of signals. With the method and apparatus of the present invention, the filter size may be reduced significantly and the cost may be lowered. | 10-09-2008 |
| 20080288567 | FIR FILTER PROCESS AND FIR FILTER ARRANGEMENT - The present invention relates to a FIR filter process ( | 11-20-2008 |
| 20090327385 | Filter Structure and Method for Filtering an Input Signal - The invention relates to a method and filter structure for filtering an input signal, which is applied to an input ( | 12-31-2009 |
| 20100169401 | FILTER FOR NETWORK INTRUSION AND VIRUS DETECTION - Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result. | 07-01-2010 |
| 20110113082 | SIGNAL FILTERING AND FILTER DESIGN TECHNIQUES - Signal filtering and filter design techniques are disclosed. An interconnection circuit switchably couples an input and an output of an element that is operable to perform a signal filtering operation on a signal received at the input so as to provide a filtered signal at the output. This enables the element to be used to implement a series of cascaded signal filtering operations. An iterative filter design method and a data structure that enables control of the element and/or the interconnection circuit are also disclosed. According to another aspect of the invention, an element is operable to perform any of multiple signal filtering operations on a received input signal. Controlled selection of respective sets of filter parameters associated with the multiple signal filtering operations enables the element to be used to implement the signal filtering operations in parallel filtering paths. | 05-12-2011 |
| 20120110051 | Reconfigurable Digital Signal Filter Processor - A reconfigurable digital signal filter processing unit for use in a communication device is provided. The reconfigurable filters processor can implement different filter topologies to adapt to a range or wireless technology characteristics. The reconfigurable filter processor comprises a plurality of filter blocks whose inputs can be selected based on the desired configuration of the filter. Each filter block applies a transfer function to a received signal to achieve a desired filtering function. | 05-03-2012 |
| 20130013658 | USE OF LINE CHARACTERIZATION TO CONFIGURE PHYSICAL LAYERED DEVICES - A method of optimizing filter performance through monitoring channel characteristics is provided. A signal enters a channel and a receiver receives the signal. The receiver includes a FIR filter to remove near-end transmitted interference and recover a far-end desired signal. The filter has storage elements configured as a shift registers to move the signal, multipliers to multiply the signal by a filter coefficient, an intermittent summer to combine the multiplied results into a replica of an interfering signal, a final summer to remove the replica from the receiver signal to provide direct and indirect monitoring of the signal, where direct monitoring includes time or frequency monitoring, and indirect monitoring includes monitoring signal to noise ratio, error magnitude or bit error rate. The filter is optimized according to monitoring and includes reducing a dynamic range, reducing bits of precision, reducing linearity, the filter, and reallocating the filter. | 01-10-2013 |
| 20130110898 | APPARATUS FOR SIGNAL PROCESSING | 05-02-2013 |
| 20130339415 | LATENCY COMPENSATION - Systems and methods for latency compensation are disclosed. In one embodiment, a computer-based system for latency compensation in a dynamic system comprises a processor and logic instructions stored in a tangible computer-readable medium coupled to the processor which, when executed by the processor, configure the processor to receive at least first parameter data from a first sensor and second parameter data from a second sensor, direct the at least first parameter data and the second parameter data into a combining filter, receive additional parameter data about the dynamic system from at least one additional sensor, construct a model of latency effects on the first parameter data and the second parameter data, and use the model of latency effects to compensate for latency-based differences in the first parameter data and the second parameter data. | 12-19-2013 |
| 20150074160 | S12 TX FIR ARCHITECTURE - A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers. | 03-12-2015 |
| 20150381147 | CONFIGURABLE GENERIC FILTER HARDWARE BLOCK AND METHODS - A configurable generic filter hardware block and corresponding methods are provided. A configurable generic filter hardware block comprises a plurality of multipliers; a plurality of adders; and one or more multiplexers, wherein the configurable generic filter hardware block is configured using a header data structure, the header data structure comprises a pointer to a memory location storing a plurality of input samples, a pointer to a memory location storing a plurality of output samples and a coefficient selection control value. The configurable generic filter hardware block is optionally invoked by a convolution instruction in one or more of a vector processor and a state machine. An exemplary Generic Filter Iteration comprises loading input samples; selecting coefficients; convolving the input samples and the selected coefficients and storing output samples. Each Generic Filter Iteration has a corresponding header data structure. The header data structures are optionally stored sequentially in memory and processed in a single loop. | 12-31-2015 |
| 20160020753 | Generation of High-Rate Sinusoidal Sequences - Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus. | 01-21-2016 |
