| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708313000 | Decimation/interpolation | 46 |
| 20080208941 | Interpolation Process Circuit - There are included a three-tap FIR calculating part ( | 08-28-2008 |
| 20080243980 | Coupling Simulations With Filtering - Systems, techniques, and machine-readable instructions for coupling simulations with filtering. In one aspect, a method is for coupling simulations with filtering of data. The method includes generating a first visual rendition of a first collection of display data and a second visual rendition of a second collection of display data, receiving user input changing a variable rendered in the second visual rendition, and representing an impact of the change to the variable on the first visual rendition of the first collection of display data. The second collection of display data is a product of filtering the first collection of display data. | 10-02-2008 |
| 20080243981 | Method and apparatus for accelerating processing of adaptive finite impulse response filtering - Finite impulse response filtering is achieved by broadcasting to at least one compute unit an instruction having a plurality of data samples, a conditional field associated with each compute unit, and a set of operator values for operating on each data sample; providing a function of each the data sample in accordance with an associated set of operator values identified by the conditional field; and combining the functions to obtain an intermediate finite impulse response of the data samples. | 10-02-2008 |
| 20080275930 | CONVOLUTION OPERATION CIRCUIT - There is provided a convolution operation circuit that performs a convolution operation on a provided digital signal. The convolution operation circuit includes a data dividing section that generates a plurality of divided data obtained by dividing respective amplitude data of the digital signal into a plurality of bit areas, an arithmetic section that performs a predetermined convolution operation on the respective divided data of the respective amplitude data in a time-sharing mode and outputs the result, and a coupling section that couples the divided data output from the arithmetic section for each of the amplitude data. | 11-06-2008 |
| 20090037505 | INTERPOLATING CUBIC SPLINE FILTER AND METHOD - A filter for high speed digital signal processing. In one embodiment the filter includes a linear, phase-B, interpolating cubic spline filter having a pre-filter section and an interpolating post-filter section. The pre-filter section may be formed to implement any one of a 1-4-1 cubic spline function, a 2-5-2 cubic spline function or a 1-2-1 cubic spline function. The post-filter may be formed using a plurality of running average filters arranged in a cascade (i.e., serial) fashion. The filter can be constructed using significantly fewer independent component parts for a given level of pass band and stop band performance criteria, as compared with a conventional finite impulse response (FIR) filter. The filter is thus ideally suited for implementation with very large scale integration (VLSI) technology, and in a wide variety of electronic devices where high speed digital filtering is required. | 02-05-2009 |
| 20090070395 | INTERPOLATION FUNCTION GENERATION CIRCUIT - An interpolation function generation circuit is formed by cascade connecting a first FIR filter ( | 03-12-2009 |
| 20090077149 | ASYNCHRONOUS SAMPLING RATE CONVERSION - Asynchronous sampling rate converter using multistage oversampling with final stage polyphase filter coefficients approximated by polynomials of the filter index. The approximation polynomial coefficients occupy smaller memory than the polyphase filter coefficients being approximated. | 03-19-2009 |
| 20090112957 | System and methods for data sample decimation and display of scanning probe microscope images - Methods, systems and components for producing a scanning probe microscope (SPM) image. One method embodiment includes receiving sample data from a scanning probe microscope wherein said sample data comprises data sample many times per pixel of the SPM image to be displayed; selecting at least one decimation scheme from a plurality of different decimation schemes, for decimating the sample data to provide a single data value per pixel; and decimating the sample data, using the at least one selected decimation scheme. A method of decimating sample data scanned along scan lines from a surface of an object to be imaged includes at least temporarily storing multiple adjacent scan lines of the sample data prior to decimating at least a portion of the sample data; correlating adjacent samples of the sample data; and selecting a decimation scheme different from a decimation scheme previously selected to be applied to sample data within a pixel pertaining to an image to be formed from the sample data, when correlating provides results in which a value from one line of comparison is different from a value from another line of comparison by at least a predetermined value, but otherwise maintaining the previously selected decimation scheme for decimating the sample data pertaining to that pixel. | 04-30-2009 |
| 20090177726 | METHOD FOR PROCESSING A DIGITAL INPUT SIGNAL IN A DIGITAL DOMAIN AND DIGITAL FILTER CIRCUIT FOR PROCESSING A DIGITAL INPUT SIGNAL - The invention relates to a method for processing a digital input signal (x(i)) in a digital domain, comprising: -sampling a wideband of input frequencies of said digital input signal (x(i)) with a sampling frequency (fs), which decimates with a decimation factor (D), -linear shaping said sampled input frequencies with a configurable delay, -producing an output signal (y(i)) containing said linear shaped input frequencies, wherein the output signal (y(i)) has the same sampling frequency (fs) as said input signal (x(i)). | 07-09-2009 |
| 20090187615 | DIGITAL FILTER - Provided is a digital filter for radio communication processing capable of dynamically modifying the characteristic and simultaneously processing a plurality of systems. In the digital filter, calculation core groups ( | 07-23-2009 |
| 20090198753 | Data processing method by passage between different sub-band domains - The invention concerns data processing by passage between different subband domains, of a first number L to a second number M of subband components. After determining a third number K, least common multiple between the first number L and the second number M: a) if K is different from L, it consists in arranging in blocs, by a serial/parallel conversion, an input vector X(z) to, obtain p | 08-06-2009 |
| 20090292753 | FIR FILTER APPARATUS, AUDIO APPARATUS AND FIR FILTER PROGRAM - A coefficient compensating unit | 11-26-2009 |
| 20100088355 | EXTRACTING MULTIPLE CLASSIFIED ADAPTIVE DECIMATION FILTERS - A plurality of initial decimation filters are concatenated into an initial combined decimation filter. The initial decimation filters are assigned to a plurality of classes which associate the initial decimation filters with regions of an image to be predicted. An input signal is generated from the initial combined decimation filter and is weighted with a plurality of prediction filters. A correlation matrix and an observation vector are generated for the initial combined decimation filter from the input signal. An optimized combined decimation filter is extracted from the correlation matrix and observation vector. The optimized filter comprises a plurality of optimized decimation filters. The optimized combined decimation filter is de-concatenated into the plurality of optimized decimation filters. | 04-08-2010 |
| 20100121897 | Filter Block for Compensating Droop in a Frequency Response of a Signal - The invention may provide a method and filter block for compensating droop in a frequency response of a signal. The filter block may include a decimator, which decimates a high frequency input signal to a set frequency output signal. The set frequency can be, for example, the Nyquist frequency for the input signal. Further, the filter block may include a droop compensator that compensates the droop in the frequency response of the output signal from the decimator. The droop compensator may be made using recursive filters, as opposed to large tap FIR filters, which may result in less memory consumption and decreased power consumption. | 05-13-2010 |
| 20100146026 | SUB-BAND SIGNAL PROCESSING - An apparatus for sub-band processing of an input signal includes an analysis filter bank, signal processors and a synthesis filter bank. The analysis filter bank includes first and second signal branches for decomposing the input signal into two sub-band signals. The first signal branch includes a decimation filter connected upstream of a down-sampling unit and a basis filter. The second branch includes an all-pass filter and a subtractor that is connected downstream of the all-pass filter and the basis filter in the first signal branch via an up-sampling unit and a subsequent interpolation filter. At least one of the decimation filter and the interpolation filter is an infinite impulse response filter, and the all-pass filter has a phase response that compensates for a phase response of at least one of the decimation filter and the interpolation filter. | 06-10-2010 |
| 20100174768 | DIGITAL SIGNAL PROCESSING CIRCUIT AND METHOD COMPRISING BAND SELECTION - A digital signal processing circuit comprises a band selector ( | 07-08-2010 |
| 20100179977 | SAMPLED FILTER WITH FINITE IMPULSE RESPONSE - The invention relates to sampled filters with finite impulse response, or FIR filters. | 07-15-2010 |
| 20100198898 | PASSIVE SWITCHED-CAPACITOR FILTERS CONFORMING TO POWER CONSTRAINT - Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner. | 08-05-2010 |
| 20100217790 | METHOD AND APPARATUS FOR DIGITAL UP-DOWN CONVERSION USING INFINITE IMPULSE RESPONSE FILTER - A method and an apparatus for digital up-down conversion using an Infinite Impulse Response (IIR) filter are provided. The method for digital up-down conversion for frequency conversion in a mobile communication system using plural frequency converts, includes IIR-filtering, by a magnitude response IIR filter having the same magnitude response as in Finite Impulse Response (FIR) filtering, an input signal and a stable filter coefficient calculated according to a Levinson polynomial; and receiving, by the magnitude response IIR filter, the IIR filtered signal, and performing IIR filtering by a phase compensation IIR filter having a filter coefficient compensating for a non-linear phase to a linear phase. | 08-26-2010 |
| 20100235420 | Desensitized Filters with Droop Correction - A method and system for the design and implementation of desensitized digital filters with droop correction. The desensitized digital filter includes a first filter configured to receive an input signal, a decimator or upsampler, and a modified desensitized half-band filter. The first filter introduces droop into the passband of the desensitized digital filter. The desensitized half-band filter has a transfer function F(z)=K(1+z | 09-16-2010 |
| 20100293214 | Method and System for Finite Impulse Response (FIR) Digital Filtering - A method for finite impulse response (FIR) digital filtering is provided that includes generating a frequency domain sample block from an input sample block of length L, adding the computed frequency domain sample block to a reverse time-ordered set of previously generated frequency domain sample blocks as a newest frequency domain sample block, computing a spectral multiplication of each of K newest frequency domain sample blocks in the reverse time-ordered set with a corresponding frequency domain filter block in a time-ordered set of K frequency domain filter blocks of a FIR filter, adding the K results of the K spectral multiplications to generate an output spectral block, inverse transforming the output spectral block to generate a time domain output block, and outputting L filtered output samples from the time domain output block. | 11-18-2010 |
| 20100332577 | METHOD AND DEVICE FOR IMPROVING THE PASSBAND OF A PHYSICAL SYSTEM - The invention relates to the improvement of the passband of physical systems. Use is made of a finite impulse response filter which is calculated in the following manner, on the basis of the behavior (observed or known) of the physical system: the impulse response a(t) of the physical system according to a temporal or spatial variable is determined; an impulse response b(t) of similar form but compressed according to the scale of the variable t in a ratio n and expanded in amplitude in the same ratio is calculated sample by sample, and the coefficients of a finite impulse response filter able to provide at its output the signal b(t) when the signal a(t) is applied to its input are calculated. This finite impulse response filter is incorporated into the physical system, preferably at the output, so as to improve the passband thereof in the ratio n. | 12-30-2010 |
| 20110004647 | OFFSET-FREE SINC INTERPOLATOR AND RELATED METHODS - An offset free sinc interpolating filter includes differentiators operating at a first sampling frequency, integrators operating at a second sampling frequency and one or more coefficient multipliers. The coefficient multipliers multiply a received value with a constant coefficient value to generate an output value. The differentiators, integrators and coefficient multipliers can be operatively coupled to each other, either directly or through other components such as adders and delay elements, or by a combination of the two. In operation, an input signal is provided to the sinc interpolating filter at the first sampling frequency. The input signal is processed by the differentiators, integrators and coefficient multipliers to generate an output signal at the second sampling frequency. Once the output signal is generated, the integrators are reset before the next input cycle begins. | 01-06-2011 |
| 20110022649 | DIGITAL AUDIO PROCESSING SYSTEM AND METHOD - A method includes receiving first data corresponding to a first signal sampled at a first sample rate, decimating the first data to provide a second signal sampled at a second sample rate, and recovering a pilot signal from the second signal. The method also includes evaluating the pilot signal to determine an error value, where the error value is based on a comparison of a sample of the pilot signal to zero. The method also includes adjusting the second sample rate based on the error value. | 01-27-2011 |
| 20110035427 | PIXEL SENSOR CONVERTERS AND ASSOCIATED APPARATUS AND METHODS - There is described a pixel sensor converter for an image sensor array. In particular, a pixel sensor converter comprising: a delta-sigma converter comprising a modulator and a decimator. In some examples, the modulator is configured to be in communication with a detector, such as a photo-detector, and is configured to sample an analogue signal received from a detector at a particular sampling rate. The modulator is further configured to provide a bit stream of a particular bit rate. The provided bit stream corresponds to a sampled analogue signal. The decimator is in communication with the modulator, and is configured to receive and modify a bit stream provided from the modulator in order to provide a digital output signal. The provided digital output signal is representative of an analogue signal received at the modulator, but having a reduced bit rate than a corresponding bit stream provided by the modulator. | 02-10-2011 |
| 20110040818 | DISCRETE TIME LOWPASS FILTER - A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal. | 02-17-2011 |
| 20110060783 | DECIMATION FILTER - A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module. | 03-10-2011 |
| 20110087716 | MULTI-RATE FILTER BANK - A multi-rate filter bank including an anti-aliasing filter, a plurality of multiplier block modules, a folding block, and a data composer is disclosed. The anti-aliasing filter receives an anti-aliasing input signal. The multiplier block modules receive an original signal and sequentially generate a plurality of processed signals. The multiplier block modules also receive a plurality of block input signals and a select signal. Each of the multiplier block modules is configured into a decimation block or an expanding anti-aliasing filter according to the select signal. The folding block receives the select signal and a folding input signal and generates a folding block output signal. The data composer receives and composes the folding block output signal and the outputs of the multiplexer block modules and the anti-aliasing filter and generates an anti-aliasing filter output signal. | 04-14-2011 |
| 20110087717 | METHOD FOR DECIMATION OF IMAGES - In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process. | 04-14-2011 |
| 20110087718 | METHOD FOR DECIMATION OF IMAGES - In the case of printing at high addressability, where the cell size is smaller than the spot size, an image can be decimated in a manner that will limit the large accumulation of printed material. The proper decimation of the image will depend on the spot size, the physics of drop coalescence and the addressability during printing. A simple method of using concentric decimation is disclosed herein to enable this process. | 04-14-2011 |
| 20110131265 | ELECTRONIC HARDWARE RESOURCE MANAGEMENT IN VIDEO PROCESSING - Apparatus and methods for electronic hardware resource management in video processing are provided. A hybrid filter is controllable to apply either Finite Impulse Response (FIR) filtering or Infinite Impulse Response (IIR) filtering for vertical filtering of a video image during a resizing process. A scale factor by which the video image is to be resized in the resizing process is determined, and the hybrid filter is controlled to apply FIR filtering for the vertical filtering where the determined scale factor satisfies a first condition relative to a threshold value S | 06-02-2011 |
| 20110145310 | METHOD FOR UPDATING AN ENCODER BY FILTER INTERPOLATION - A method for updating the processing capacity of an encoder or decoder to use a modulated transform having a size greater than a predetermined initial size is provided, particularly, where the encoders or decoders are for storing an initial prototype filter defined by an ordered set of initial size coefficients. A step is provided for constructing a prototype filter of a size greater than the initial size to implement the modulated transform of the greater size by inserting at least one coefficient between two consecutive coefficients of the initial prototype filter. | 06-16-2011 |
| 20110153705 | METHOD AND APPARATUS FOR A FINITE IMPULSE RESPONSE FILTER - A finite impulse response filter comprises an input formatter, a plurality of sample registers, a plurality of coefficient registers, an arithmetic unit, a multiply accumulate unit, a crosspoint switch, an interpolator, a control unit, and an output formatter. The input formatter separates the in-phase portion of a complex-number discrete-time sample from the quadrature portion. The sample registers store a plurality of discrete-time samples. The coefficient registers store a plurality of coefficients. The arithmetic unit adds two of the discrete-time samples to create a sum. The multiply accumulate unit includes a multiplier that multiplies the sum by a coefficient to create a product, an adder that adds the product to a sum of products, and a register that stores the sum of products. The crosspoint switch allows communication between the first and second plurality of registers and the arithmetic unit and the multiply accumulate unit. The interpolator inserts a desired number of zeros into the time-sampled data stream to adjust the time-sampled data stream to an increasing sampling rate. The control unit controls the settings of the crosspoint switch, the arithmetic unit, and the multiply accumulate unit. The output formatter combines the in-phase sum of products and the quadrature sum of products to create a filtered complex-number discrete-time sample. | 06-23-2011 |
| 20110231466 | TIME-DIVISION DECIMATION FILTER BANK AND TIME-DIVISION DECIMATION FILTERING METHOD - A time-division (TD) decimation filter bank includes two decimation filter units. The first decimation filter unit operates at a system clock and receives a first-stage input data string. Each data in the first-stage input data string has a first part data and second part data. During the odd clock periods, the first part data are filtered and decimated in frequency. During the even clock periods, the second part data are filtered and decimated in frequency. The second decimation filter unit operates at the system clock and 2 | 09-22-2011 |
| 20120041995 | Multi-Branch Rate Change Filter - The present invention relates to a rate change filter having multiple branches. The multi-branch rate change filter of the present invention achieves higher effective output rates by processing the input sample stream in two or more parallel filter branches with offset states. | 02-16-2012 |
| 20120166506 | Measuring Sum of Squared Current - A modulator can be configured to sense a change in current flow in a circuit and to generate an oversampled, noise-shaped signal. A first decimation filter is coupled to the modulator and is configured to generate instantaneous current data at a first data rate. The instantaneous current data can be input into a multiplier circuit. The output of the multiplier circuit (the instantaneous current data squared) can be input to a second decimation filter. The second decimation filter can be configured to generate a sum of the squared current data at a second data rate. The sum of the squared current data can be used by an application (e.g., battery power management) to compute power measurements or for other purposes. | 06-28-2012 |
| 20120185524 | Multi-Rate Implementation Without High-Pass Filter - A filtering method approximates a target Finite Impulse Response (FIR) (or transversal) filter and reduces computational requirements by eliminating high pass filtering required by known multi-rate filters. An input signal is copied into two identical signals and processed in parallel by a full-rate path, and by a reduced-rate path. Parallel filters are computed and applied in each path, the reduced-rate signal is up-sampled, and the two signals summed. The high pass filter required by known multi-rate filters is eliminated and the low pass filter in the prior art is implicit in a down sampling. Linear phase FIR filters are used for down and up sampling, resulting in constant group delay. Added benefits include the option of zero added latency through the filtering and the constant group delay added to the target FIR. The user may choose criteria such as minimum resolution in each band. | 07-19-2012 |
| 20120203812 | METHOD AND APPARATUS FOR GENERATING SIGNAL HAVING CONVERTED SAMPLING RATE IN COMMUNICATION SYSTEM - A method of generating a signal having a converted sampling rate in a communication system is provided. The method includes selecting effective input samples among S number of input samples included in an input stream corresponding to an input sampling rate, generating a filter coefficient set including filter coefficients having a length of a second tap, the filter coefficients having the length of the second tap being generated by dividing a filter coefficient having a length of a first tap configuring a low-pass filter into the filter coefficients having the length of the second tap corresponding to a number of selected effective input samples, selecting filter coefficients corresponding to each of the effective input samples among the filter coefficients included in the filter coefficient set, and outputting output samples having an output sampling rate which is converted from the input sampling rate. | 08-09-2012 |
| 20120246210 | METHOD AND APPARATUS FOR ADAPTIVE CONTROL OF THE DECIMATION RATIO IN ASYNCHRONOUS SAMPLE RATE CONVERTERS - An asynchronous sample rate converter prevents the folding back of a signal in the passband of an input sample rate into the passband of the output sample by adaptively controlling the decimation rate. The ASRC includes an adaptive decimation rate controller that selectably controls a decimation filter based on the ratio of the input sampling rate to the output sampling rate. By adaptively controlling the decimation rate in the ASRC, a significant amount of area and power is saved. | 09-27-2012 |
| 20120254272 | MULTI-STANDARD MULTI-RATE FILTER - A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter. | 10-04-2012 |
| 20130066934 | SEMICONDUCTOR DEVICE - To variably change the filter characteristic of a decimation filter in accordance with a sampling rate. A decimation filter | 03-14-2013 |
| 20140012888 | Systems and Methods for Filter Initialization and Tuning - Various embodiments of the present invention provide systems and methods for data filter tuning. As an example, a method for filter tuning is disclosed that includes: providing a tunable filter having an operation filter and a calibration filter; applying a low frequency test input to the operation filter in place of an input signal to yield a first filter output; calculating a low frequency magnitude value corresponding to the first filter output; applying a high frequency test input to the operation filter in place of an input signal to yield a second filter output; calculating a high frequency magnitude value corresponding to the second filter output; modifying a tuning factor of the calibration filter when a ratio of the high frequency magnitude value and the low frequency magnitude value is outside of a defined range; and storing the tuning factor of the calibration filter when the ratio of the high frequency magnitude value and the low frequency magnitude value is within the defined range. | 01-09-2014 |
| 20140101218 | DECIMATION FILTER - A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module. | 04-10-2014 |
| 20150318840 | SEMICONDUCTOR DEVICE INCLUDING A DECIMATION FILTER THAT PERFORMS PREDETERMINED FILTERING - An electric-power meter device includes a sensor which detects an electric energy and which outputs an analog signal with 50 Hz to 60 Hz, and a microcomputer which includes an analog-to-digital converter which, based on a delta-sigma modulation scheme, converts the input analog signal provided from the sensor to a digital signal based on a required sampling rate to output the digital signal, a central processing unit that performs data processing based on the digital signal converted by the analog-to-digital converter, and a timer unit that outputs a trigger signal in a cycle corresponding to the required sampling rate. The analog-to-digital converter includes a delta-sigma modulator and a decimation filter. | 11-05-2015 |
| 20150333733 | Low Delay Modulated Filter Bank - The document relates to modulated sub-sampled digital filter banks, as well as to methods and systems for the design of such filter banks. In particular, the present document proposes a method and apparatus for the improvement of low delay modulated digital filter banks. The method employs modulation of an asymmetric low-pass prototype filter and a new method for optimizing the coefficients of this filter. Further, a specific design for a 64 channel filter bank using a prototype filter length of 640 coefficients and a system delay of 319 samples is given. The method substantially reduces artifacts due to aliasing emerging from independent modifications of subband signals, for example when using a filter bank as a spectral equalizer. The method is preferably implemented in software, running on a standard PC or a digital signal processor (DSP), but can also be hardcoded on a custom chip. The method offers improvements for various types of digital equalizers, adaptive filters, multiband companders and spectral envelope adjusting filter banks used in high frequency reconstruction (HFR) or parametric stereo systems. | 11-19-2015 |
| 20160182014 | POLYPHASE DECIMATION FIR FILTERS AND METHODS | 06-23-2016 |
