| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708301000 | Tapped delay line | 10 |
| 20090150468 | DIGITAL FILTER - A FIR filter ( | 06-11-2009 |
| 20110307536 | DIGITAL FILTER - The digital filter is connected to an upstream analog unit, changes bit data outputs corresponding to analog computation results every N clock pulse, operates in accordance with a clock in synchronization of the analog unit, and removes noise from the bit data output from the analog unit, the digital filter including an Nth-order sinc filter having a cascade of N sinc filters, each acquiring a moving average of a sample, and a moving average filter having a tap number of K connected to the output of the Nth-order sinc filter. | 12-15-2011 |
| 20110307537 | DIGITAL FILTER - A digital filter has a plurality of filters, wherein each filter performs coefficient multiplication and delay processing for an input signal and an output signal, obtains the output signal from the input signal, and includes a plurality of coefficient multipliers for multiplying a signal by a predetermined coefficient. The digital filter also includes a plurality of delay circuits for delaying a signal, and an adder for adding a plurality of signals. A first RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the first filter and stores delay data for the delay circuit of the second filter. A second RAM stores a plurality of sets of coefficient data for a plurality of coefficient multipliers of the second filter and stores delay data for the delay circuit of the first filter. | 12-15-2011 |
| 20120143935 | FILTER DEVICE AND METHOD FOR PROVIDING A FILTER DEVICE - The invention relates to a filter device ( | 06-07-2012 |
| 20120166505 | S12 TX FIR ARCHITECTURE - A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers. | 06-28-2012 |
| 20120173601 | Configurable Filter Using a Transmission Line as a Delay Line - Methods and systems for a configurable finite impulse response (FIR) filter using a transmission line as a delay line are disclosed and may include selectively coupling one or more taps of a multi-tap transmission line to configure delays for one or more finite impulse response (FIR) filters to enable transmission and/or reception of signals. The delays may be configured based on a location of the one or more selectively coupled taps on the multi-tap transmission line. The FIR filters, which may include one or more stages, may be impedance matched to the selectively coupled taps. The multi-tap transmission line may be integrated on the chip, or a package to which the chip is coupled. The multi-tap transmission line may include a microstrip structure or a coplanar waveguide structure, and may include ferromagnetic material. The distortion of signals in the chip may be compensated utilizing the FIR filters. | 07-05-2012 |
| 20120226728 | ADAPTIVE SIGNAL PROCESSING - An adaptive low pass filtering process with a filter delay D | 09-06-2012 |
| 20140201254 | Delay Fabric Apparatus and Delay Line - A fabric for delaying digital signals in continuous time has an array of node filters. Inputs of filters in the first column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form an output signal of the filter. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other rows of the array. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements. A delay line is constructed by combining a phase generator and a fabric, where the phase generator splits a digital input signal in multiple incrementally delayed versions for the fabric inputs. | 07-17-2014 |
| 20160006416 | Semi-Analog FIR Filter With High Impedance State - A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that the signal to an impedance element is the same as the previous value, then the driver of that impedance element is “turned off” or goes into a high impedance state, so that no current flows through that impedance element, and it no longer contributes to the filter output. Alternatively, if the impedance elements are the same between two adjacent taps of the delay line, the driver of one of those impedance elements may be turned off or go into a high impedance state. The technique may be particularly useful in differential output filters. Turning off a driver effectively removes the attached impedance element from the filter and reduces current flow and power consumption, thus extending battery life in mobile devices. | 01-07-2016 |
| 20160182015 | FRACTIONAL AND INTEGER RATIO POLYPHASE INTERPOLATION FILTER | 06-23-2016 |
