Class / Patent application number | Description | Number of patent applications / Date published |
708230000 | Multifunctional | 57 |
20080243976 | MULTIPLY AND MULTIPLY AND ACCUMULATE UNIT - The present invention relates to a multiply apparatus and a method for multiplying a first operand consisting of na bits and a second operand consisting of nx bits. In one embodiment the multiply apparatus comprising a CSA (CSA) unit with nx rows each comprising na AND gates for calculating a single bit product of two single bit input values and adder cells for adding results of a preceding row to a following row and a last output row for outputting a carry vector and a sum vector, and logic circuitry for selectively inverting the single bit products at the most significant position of the nx−1 first rows and at the na−1 least significant positions of the output row in response to a first configuration signal before inputting the selectively inverted single bit products to respective adder cells for switching the CSA unit selectively between processing of signed two's complement operands and unsigned operands in response to the first configuration signal. In one embodiment the method comprising outputting a carry vector and a sum vector, and adding the carry vector and the sum vector provided by the output row of the CSA unit via a CPA unit consisting of a row of na full adder cells, wherein the carry input of the CPA unit is coupled to receive a first configuration signal to switch between processing of signed and unsigned two's complement operands. | 10-02-2008 |
20080263115 | Very long arithmetic logic unit for security processor - An arithmetic and logic unit carries out arithmetic or logic operations on long operands. The unit comprises: an operation unit having a processing location, and configured for carrying out processing on bits at the processing location, the processing comprising any of a plurality of pre-defined arithmetic or logical operations, the processes being defined for a first number of bits determined by the operand word length; a fetch and write unit comprising direct memory access circuitry for fetching a second number of bits of operand data by direct access from an external memory and for writing results to memory, the second number being set by a predetermined memory access width; the second number being smaller than said operand word length, and the direct memory access circuitry being configured to deliver said second number of bits directly to the processing location without aggregation prior to processing. The fetch and write unit is controllable to carry out fetch operations for a further second number of bits of the long operand while a current part of the operand is being processed in said operation unit, thereby to hide memory access latency. | 10-23-2008 |
20080281891 | Parallel Computation Structures to Enhance Signal-Quality, Using Arithmetic or Statistical Averaging - Parallel hardware computation structures for integrated-circuit arithmetic and statistical signal averaging are described herein as an invention that is applicable to broad systems applications where a variety of analog-to-digital and digital-to-analog data interfaces occur. Signal values are improved to accommodate signal reconstruction of high quality and at high frequencies. The computation efficiency of the parallel hardware structures makes them useful in a broad set of applications where signal data is being converted from one electronics domain to another—in particular, from the analog domain to the digital domain and the reverse. Important application areas include video processing, music studios, telecommunications, voice communication and support systems, and information technology in general. | 11-13-2008 |
20090077144 | METHOD AND APPARATUS FOR PERFORMING FINITE FIELD CALCULATIONS - In general terms, the invention provides a finite field engine and methods for operating on elements in a finite field. The finite field engine provides finite field sub-engines suitable for any finite field size requiring a fixed number of machine words. The engine reuses these engines, along with some general purpose component or specific component providing modular reduction associated with the exact reduction (polynomial or prime) of a specific finite field. The engine has wordsized suitable code capable of adding, subtracting, multiplying, squaring, or inverting finite field elements, as long as the elements are representable in no more than the given number of words. The wordsized code produces unreduced values. Specific reduction is then applied to the unreduced value, as is suitable for the specific finite field. In this way, fast engines can be produced for many specific finite fields, without duplicating the bulk of the engine instructions (program). | 03-19-2009 |
20090240753 | METHOD, HARDWARE PRODUCT, AND COMPUTER PROGRAM PRODUCT FOR USING A DECIMAL FLOATING POINT UNIT TO EXECUTE FIXED POINT INSTRUCTIONS - A decimal floating point (DFP) unit is used to execute fixed point instructions. Two or more operands are accepted, wherein each operand is in a packed binary coded decimal (BCD) format. Any invalid BCD formats are detected by checking the operands for any invalid BCD codes. It is determined if an exception flag exists and, if so, outputting the flag; it is determined if a condition code exists and, if so, outputting the code. An operation is performed on the two or more operands to generate a result; wherein the operation takes place directly on BCD data, thus using the DFP unit to perform a BCD operation; appending a result sign to the result of the operation; and providing the result of the operation and the appended result sign as a result output in a packed BCD format. | 09-24-2009 |
20100023569 | METHOD FOR COMPUTERIZED ARITHMETIC OPERATIONS - A method of computing arithmetic operations more efficiently than the conventional Arithmetic Logic Unit (ALU) is disclosed. By encoding both operands from Binary Coded Decimal (BCD) codes (0000, to 1001) into decimal digits (0 to 9), inputting them in the GerTh's™ look-up tables, which are made of an array of AND gates, the invention finds the answer more efficiently. This method finds the result in fewer steps than a traditional ALU by reducing the repetitive calculation steps and logic gates required. And this new method makes the unsolvable computerized binary floating-point multiplications and divisions back to the solvable GerTh's computerized decimal digits' (0-9) elementary arithmetic operations. | 01-28-2010 |
20100036898 | COMPUTING MODULE FOR EFFICIENT FFT AND FIR HARDWARE ACCELERATOR - A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the FIR mode, one real output is generated. The hardware accelerator may switch from FFT mode to FIR mode using three multiplexers. All FIR components may be utilized in FFT mode. Registers may be added to provide pipelining support. The hardware accelerator may support multiple numerical-representation systems. | 02-11-2010 |
20100205235 | M-SEQUENCE GENERATOR, PROVIDING METHOD THEREOF, AND RANDOM ERROR GENERATING DEVICE IN WHICH M-SEQUENCE GENERATOR IS USED - An M-sequence generator includes EXCLUSIVE-OR gates feeding back pieces of bit data from m number of series registers to the registers in response to a clock. A period of a cyclic group {(α | 08-12-2010 |
20110010406 | Programmable Logic Systems and Methods Employing Configurable Floating Point Units - A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z. | 01-13-2011 |
20110060782 | Hardware Implementation of a Galois Field Multiplier - An embodiment of the invention provides a method of operating a Galois field multiplier in a processor. An n bit multiplier and an n bit multiplicand are received during a first group of one or more clock cycles. An (2n−1) bit product is calculated based on the n bit multiplicand and the n bit multiplier. The (2n−1) bit product is stored in a first memory element during the first group of one or more clock cycles. An n bit polynomial value is received during a second group of one or more clock cycles. During the second group of one or more clock cycles, the (2n−1) bit product is divided by the n bit polynomial value producing an n bit result. The n bit result is stored in a second memory element during the second group of one or more clock cycles. | 03-10-2011 |
20120036172 | Expanded Scope Incrementor - An incrementor circuit and method for incrementing is provided that computes an output data word by increasing an input data word magnitude by one of several integer values. The incrementor circuit includes a mode increment signal circuit providing a designation of one of the integer values for increasing the input data word magnitude. A single constant incrementor is connected to the mode increment signal circuit and the input data word and provides an intermediate sum by selectively adding a constant to the input data word. A multiplex circuit logically combines selected input data word bit position values with the mode increment signal circuit designation forming logical bit position values and directs selected input data word bit position values, selected logical bit position values, and selected bit position values of the intermediate sum to form the output data word. | 02-09-2012 |
20120150933 | METHOD AND DATA PROCESSING UNIT FOR CALCULATING AT LEAST ONE MULTIPLY-SUM OF TWO CARRY-LESS MULTIPLICATIONS OF TWO INPUT OPERANDS, DATA PROCESSING PROGRAM AND COMPUTER PROGRAM PRODUCT - Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus. | 06-14-2012 |
20120173598 | APPARATUS AND METHOD FOR DIVISION OF A GALOIS FIELD BINARY POLYNOMIAL - An apparatus and method for processing a division of a binary polynomial are provided. The apparatus includes a plurality of exclusive OR (XOR) operators that may perform a selective XOR operation with respect to a conditional bit of a dividend polynomial. The plurality of XOR operators may perform selective XOR operations in parallel and accordingly, a division of a binary polynomial may be rapidly performed. | 07-05-2012 |
20120233230 | DOUBLE-CLOCKED SPECIALIZED PROCESSING BLOCK IN AN INTEGRATED CIRCUIT DEVICE - Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products. | 09-13-2012 |
20130013656 | THREE-TERM PREDICTIVE ADDER AND/OR SUBTRACTER - A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2 | 01-10-2013 |
20130024488 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes an arithmetic device that includes a first storage unit that stores first device-control information for deciding an arithmetic processing to be executed next to an arithmetic processing currently being executed by an arithmetic device and a timing at which the arithmetic processing to be executed next to the arithmetic processing currently being executed by the arithmetic device is executed; and the arithmetic device that includes a second storage unit that stores second device-control information for deciding a content of an operation contained in an arithmetic processing. The control device reads out the first device-control information, and determines whether a decision start condition defined for each arithmetic processing is satisfied by using the first device-control information, the decision start condition being a condition on which the arithmetic processing to be executed next to the arithmetic processing currently being executed is decided. | 01-24-2013 |
20130054662 | METHODS OF USING GENERALIZED ORDER DIFFERENTIATION AND INTEGRATION OF INPUT VARIABLES TO FORECAST TRENDS - Disclosed are methods and apparatuses to generate a forecast based on generalized differentiation or integration, including but not limited to non-integer or variable order differentiation or integration. | 02-28-2013 |
20130191426 | Merged Floating Point Operation Using a Modebit - A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output. | 07-25-2013 |
20130282780 | Method and Apparatus to Perform Floating Point Operations - A method of subtracting floating-point numbers includes determining whether a first sign associated with a first floating-point number is unequal to a second sign associated with a second floating-point number, determining whether a first exponent associated with the first floating-point number is less than a second exponent associated with the second floating-point number, negating a first mantissa associated with the first floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent, and adding the first mantissa to a second mantissa associated with the second floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent. Embodiments of a corresponding computer-readable medium and device are also provided. | 10-24-2013 |
20150088948 | HYBRID ARCHITECTURE FOR SIGNAL PROCESSING - Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data. | 03-26-2015 |
20160062752 | METHOD, PROGRAM, AND SYSTEM FOR CODE OPTIMIZATION - Method, program and system for code optimization. A sign assignment instruction with identically sized packed decimal format input and output operands is detected where the sign assignment instruction assigns a value of zero to a packed decimal data value input operand having a value of negative zero. If the input operand to the sign assignment instruction does not result from an add or subtract operation, or the value of the input operand is not greater than a value prior to that operation, the possibility that the value of the input operand of the sign assignment instruction is negative zero is checked when the input operand and the output operand have identical addresses. An instruction is generated and inserted for executing the sign assignment instruction only when there is the possibility that the operand value is negative zero. | 03-03-2016 |
20160092170 | LOW AREA FULL ADDER WITH SHARED TRANSISTORS - A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum. | 03-31-2016 |
20160132295 | EFFICIENT IMPLEMENTATION OF A MULTIPLIER/ACCUMULATOR WITH LOAD - This invention is multiply-accumulate circuit supporting a load of the accumulator. During multiply-accumulate operation a partial product generator forms partial produces from the product inputs. An adder tree sums the partial product and the accumulator value. The sum is stored back in the accumulator overwriting the prior value. During load operation an input gate forces one of the product inputs to all 0's. Thus the partial product generator generates partial products corresponding to a zero product. The adder tree adds this zero product to the external load value. The sum, which corresponds to the external load value is stored back in the accumulator overwriting the prior value. A multiplexer at the side input of the adder tree selects the accumulator value for normal operation or the external load value for load operation. | 05-12-2016 |
708231000 | Microprocessor | 4 |
20090055455 | MICROPROCESSOR - A microprocessor has an instruction decode portion, a register file, a complex operation unit, and a data storage position determining mechanism. The complex operation unit performs complex operation, including complex multiplication, using first and second complex number data supplied from the register file based on an instruction decoded by the instruction decode portion, and outputs the result of the complex operation toward the register file. Furthermore, the data storage position determining mechanism determines the storage positions of the real part and imaginary part of output data of the complex operation unit in the register file such that the storage order of the real part and imaginary part of the output data in the register file is consistent with the storage orders of the real parts and imaginary parts of the first and second complex number data. | 02-26-2009 |
20100332573 | PROCESSING UNIT - A processing unit computes a trigonometric function, for decrease the number of instructions and improve throughput. In a floating point multiply-add circuit, an OR circuit, a selector and an EOR circuit are disposed, and an expansion point and expansion function of the Taylor series expansion of the trigonometric function are computed using a first trigonometric function operation auxiliary instruction for defining the operation of rd=(rs | 12-30-2010 |
20110004644 | DYNAMIC FLOATING POINT REGISTER PRECISION CONTROL - Apparatus and methods are provided to perform floating point operations that are adaptive to the precision formats of input operands. The apparatus includes adaptive conversion logic and a tagged register file. The adaptive conversion logic receives the input operands, where each of the input operands is of a corresponding precision. The adaptive conversion logic also records the corresponding precision for use in subsequent floating point operations. The tagged register file is coupled to the adaptive conversion logic. The tagged register file stores the each of the input operands, and stores the corresponding precision and furthermore associates the corresponding precision with the each of the input operands. The subsequent floating point operations are performed at a precision level according to the corresponding precision. | 01-06-2011 |
20110231462 | SYSTEMS AND METHODS FOR SOLVING COMPUTATIONAL PROBLEMS - Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits. | 09-22-2011 |
708232000 | Array of elements (e.g., AND/OR array, etc.) | 6 |
20090077145 | Reconfigurable arithmetic unit - A reconfigurable arithmetic circuit including a matrix having a plurality of partial product mask cells arranged in rows and columns, where rows and columns have incrementing arithmetic weights assigned, each partial product mask cell including a gate implementing a logical AND function of its inputs to provide an output, and a programmable memory cell connected to furnish input to the gate, a plurality of horizontally oriented conductors each connected to furnish input to the gates of the partial product mask cells of a row, and a plurality of diagonally oriented conductors each connected to furnish input to the gates of the partial product mask cells along the diagonal of increasing arithmetic weight of rows and columns, and a compression circuit receiving inputs from the gates of the partial product mask cells of the matrix, and furnishing outputs providing conventional arithmetic compression of its inputs in carry-saved format. | 03-19-2009 |
20090106337 | Serial Adder Based On "No-Carry" Addition - The invention, based on an original addition algorithm for adding two binary numbers, a and b, and disclosed in the body of this application, is a schematic diagram of a serial, synchronous, digital adder, with circuitry which exemplifies an unusual procedure for calculating the carry at any bit pair, a | 04-23-2009 |
20100070548 | UNIVERSAL GALOIS FIELD MULTIPLIER - An apparatus including a multiplier circuit and a multiplexing circuit. The multiplier circuit may be configured to multiply a first multiplicand and a second multiplicand based on a programmable base value and generate a plurality of intermediate values, each intermediate value representing a result of the multiplication reduced by a respective irreducible polynomial. The multiplexing circuit may be configured to generate an output in response to the plurality of intermediate values received from the multiplier circuit and the programmable base value. | 03-18-2010 |
20110106869 | Method of Addition with Multiple Operands, Corresponding Adder and Computer Program Product - A method is provided for adding binary numbers, each of N bits, based on an accumulation mechanism which, for each iteration of index i+1 with I>0, generates an estimation signal U | 05-05-2011 |
20110231463 | METHODS AND APPARATUSES FOR FLEXIBLE AND HIGH PERFORMANCE DIGITAL SIGNAL PROCESSING - A Signal Processing Engine (SPE) includes circuitry for generating a selectable forward tap and a selectable reverse tap from a forward delay chain and a reverse delay chain, respectively. An add/subtract unit arithmetically combines the selectable forward tap and the selectable reverse tap to generate an intermediate output. A multiplier combines the intermediate output and a coefficient output from a circular coefficient buffer to generate a multiply result. Another adder/subtractor combines the multiply result with a second term including a processed input or an accumulator feedback by bypassing, adding, or subtracting the second term with the multiply result to generate an accumulator output. The accumulator output may be delayed a programmable number of clock cycles to generate a processed output. In some embodiments, the SPE is coupled to programmable logic blocks forming a programmable logic array through a programmable SPE routing block. | 09-22-2011 |
20110231464 | STATE MACHINE AND GENERATOR FOR GENERATING A DESCRIPTION OF A STATE MACHINE FEEDBACK FUNCTION - An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream. | 09-22-2011 |
708233000 | Pipeline | 4 |
20080294706 | Novel Adder Structure with Midcycle Latch for Power Reduction - A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input ( | 11-27-2008 |
20110202586 | CONFIGURABLE IC'S WITH DUAL CARRY CHAINS - Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. In some embodiments, at least a first logic circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. Also, in some embodiments, each particular tile further has a set of configurable input-select circuits for receiving inputs and configurably supplying a sub-set of the received inputs to the configurable logic circuits in the particular tile. At least a first input select circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement, where the direction connection is for supplying a signal to the first input select circuit. In some embodiments, several logic circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. In some embodiments, several input select circuits of the first tile have at least one direct connection with at least one circuit of another tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement. | 08-18-2011 |
20120066279 | Techniques for Use with Automated Circuit Design and Simulations - An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output node and carry node. The input node corresponds to a function input term, the output node corresponds to an output term of the function and the carry node corresponds to a carry value to a following logical structure in the series of logical structures. | 03-15-2012 |
20150012578 | SYSTEMS AND METHODS FOR COMPUTING MATHEMATICAL FUNCTIONS - Mathematical functions are computed in a single pipeline performing a polynomial approximation (e.g. a quadratic approximation, or the like); and one or more data tables corresponding to at least one of the RCP, SQRT, EXP or LOG functions operable to be coupled to the single pipeline according to one or more opcodes; wherein the single pipeline is operable for computing at least one of RCP, SQRT, EXP or LOG functions according to the one or more opcodes. SIN and COS are also computed using the pipeline according to the approximation ((−1)̂IntX)*Sin(π*Min(FracX, 1.0−FracX)/Min(FracX, 1.0−FracX). A pipline portion approximates Sin(π*FracX) using tables and interpolation and a subsequent stage multiplies this approximation by FracX. For input arguments of x close 1.0. LOG2(x−1)/(x−1) is computed using a first pipeline portion using tables and interpolation and subsequently multiplied by (x−1). A DIV operation may also be performed with input arguments scaled up to avoid underflow as needed. | 01-08-2015 |
708234000 | Parallel bit input of operand | 1 |
20110153702 | MULTIPLICATION OF A VECTOR BY A PRODUCT OF ELEMENTARY MATRICES - A method, system and computer program product to improve multiplication of a vector by a product of elementary matrices. The method includes, for example, receiving an input vector and determining, by at least one computer processor, which intermediate resultants of a matrix vector product between the input vector and a plurality of elementary matrices can be performed in parallel. At least some of the intermediate resultants may be calculated in parallel by a plurality of computer processors if they are not dependent on the pending product resultant of the input vector and one or more of the elementary matrices. | 06-23-2011 |
708235000 | Uses look-up table | 16 |
20100228808 | Restrained Vector Quantisation - The invention relates to a method for generating a dictionary for the vector quantisation of a signal. Said method comprises a step ( | 09-09-2010 |
20100318592 | Multiplicative Division Circuit With Reduced Area - The technology is a division circuit with decreased circuit area. An embodiment includes an integrated circuit implementing multiplicative division of a dividend input and a divisor input. The integrated circuit includes a lookup table circuit and multiplier circuits. The lookup table circuit providing an approximation of a reciprocal of a divisor input. The multiplier circuits receive the approximation and refine a quotient output of the dividend input and a divisor input. At least one of the multiplier circuits is a squaring circuit implementing multiplication with a reduced number of intermediate partial products. The reduced number of intermediate partial products prevent the squaring circuit from multiplication of any two unequal numbers and limiting the squaring circuit to multiplication of a same number by the same number. | 12-16-2010 |
20110119320 | DYNAMIC FILTERING DEVICE AND METHOD THEREOF - A dynamic filtering device includes a variation detector, a coefficient generator and a filter. The cut-off frequency of the filter is dynamically adjusted according to variations of an input signal. A higher signal-to-noise ratio is obtained when a finger moves in slow motion and its response time is reduced when the finger moves in fast motion, therefore improving the response time and the noise immunity of the filter. | 05-19-2011 |
20110231465 | Residue Number Systems Methods and Apparatuses - A method for performing reconstruction using a residue number system includes selecting a set of moduli. A reconstruction coefficient is estimated based on the selected set of moduli. A reconstruction operation is performed using the reconstruction coefficient. | 09-22-2011 |
20110238718 | LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS - A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out. | 09-29-2011 |
20110270903 | DIGITAL FRACTIONAL INTEGRATOR - A method and apparatus for fractional digital integration of an input signal is provided, the input signal including a time series of numerical values and the method or apparatus including applying the input signal time series to one input of a two-input summer at a time I, providing an output of the summer to a delay register at time I, providing an output of the delay register from time i−1 to a two-input multiplier, providing an output of the multiplier to the summer at time I, using a resettable counter to determine a value i and index a lookup table with i to provide the indexed value of the lookup table as an input to the multiplier, and obtaining an output signal time series from the output of the summer. | 11-03-2011 |
20120179734 | METHOD AND APPARATUS FOR DISCRETE COSINE TRANSFORM/INVERSE DISCRETE COSINE TRANSFORM - Discrete cosine transform/inverse discrete cosine transform method and device are provided. The discrete cosine transform/inverse discrete cosine transform method includes: generating a table index for only an input value other than 0 (zero) out of input values of coordinates in an input block; | 07-12-2012 |
20120311005 | METHOD AND APPARATUS FOR SOLVING DISCRETE LOGARITHM PROBLEM USING PRE-COMPUTATION TABLE - A method and apparatus for computing a discrete logarithm using a pre-computation table are provided. The method includes previously generating the pre-computation table consisting of chains of function values obtained by applying an iterating function to a predetermined number of initial values having a generator of the cyclic group as a base and having different exponents; and if a function value obtained by applying the iterating function to a value having a target element as a base and having an exponent is identical to a function value stored in the pre-computation table, computing the discrete logarithm of the target element by using exponent information of the two function values. | 12-06-2012 |
20130024489 | METHOD FOR FAST CALCULATION OF THE BEGINNING OF PSEUDO RANDOM SEQUENCES FOR LONG TERM EVOLUTION - An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate pseudo-random sequences in response to a first m-sequence and a second m-sequence, where the first m-sequence is initialized with a pre-calculated constant and the second m-sequence is initialized based on a pre-defined initial sequence and a table of pre-calculated values indicating which components of the initial sequence participate in initializing the second m-sequence. The second circuit may be configured to store the table of pre-calculated values. | 01-24-2013 |
20130185345 | ALGEBRAIC PROCESSOR - An algebraic processor as part of a wireless telecommunication system, including pre-computed Look Up Tables (LUT), used for computing a number of different functions using linear interpolation. Preferably, the step of computing is implemented in a multiplier-accumulator having a SIMD structure. | 07-18-2013 |
20130262540 | Transcendental and Non-Linear Components Using Series Expansion - In an embodiment, hardware implementing a transcendental or other non-linear function is based on a series expansion of the function. For example, a Taylor series expansion may be used as the basis. One or more of the initial terms of the Taylor series may be used, and may be implemented in hardware. In some embodiments, modifications to the Taylor series expansion may be used to increase the accuracy of the result. In one embodiment, a variety of bit widths for the function operands may be acceptable for use in a given implementation. A methodology for building a library of series-approximated components for use in integrated circuit design is provided which synthesizes the acceptable implementations and tests the results for accuracy. A smallest (area-wise) implementation which produces a desired level of accuracy may be selected as the library element. | 10-03-2013 |
20130262541 | Method and circuitry for square root determination - A method, performed by a processor, of determining a square root using a single processor cycle per iteration is described. The method includes, in a single cycle: obtaining, from a stored lookup table, a quotient digit and a square of the quotient digit; retrieving a current solution; and determining a new solution using the current solution and the quotient digit. Circuitry configured to perform the method is described. | 10-03-2013 |
20140040334 | DATA PROCESSING APPARATUS AND METHOD FOR REDUCING THE SIZE OF A LOOKUP TABLE - A data processing apparatus is provided with lookup table circuitry for receiving from the processing circuitry an n-bit input data value, and for returning to the processing circuitry an output data value. The lookup table circuitry provides a plurality of entries identifying possible input data values and corresponding output data values, with the plurality of entries being less than 2 | 02-06-2014 |
20140207838 | METHOD, APPARATUS AND SYSTEM FOR EXECUTION OF A VECTOR CALCULATION INSTRUCTION - Techniques and mechanisms for executing a vector instruction with a processor. In an embodiment, a vector definition instruction is executed to perform operations associated with setting a first vector as a reference vector, the operations resulting in vector multiplication information being stored in a look-up table. In another embodiment, a vector multiplication instruction is subsequently executed to perform a vector multiplication calculation based on the vector multiplication information stored in the look-up table. | 07-24-2014 |
20160154767 | LOOKUP TABLE SHARING FOR MEMORY-BASED COMPUTING | 06-02-2016 |
20160161976 | LOOKUP TABLE SHARING FOR MEMORY-BASED COMPUTING - Methods and systems for memory-based computing include combining multiple operations into a single lookup table and combining multiple memory-based operation requests into a single read request. Operation result values are read from a multi-operation lookup table that includes result values for a first operation above a diagonal of the lookup table and includes result values for a second operation below the diagonal. Numerical inputs are used as column and row addresses in the lookup table and the requested operation determines which input corresponds to the column address and which input corresponds to the row address. Multiple operations are combined into a single request by combining respective members from each operation into respective inputs an reading an operation result value from a lookup table to produce a combined result output. The combined result output is separated into a plurality of individual result outputs corresponding to the plurality of requests. | 06-09-2016 |
708236000 | More than two operands | 3 |
20100235417 | CIRCUIT AND METHOD CONVERTING BOOLEAN AND ARITHMETIC MASKS - A circuit for converting Boolean and arithmetic masks includes “m” converting units, wherein m is an integer greater than 1. Each of the m converting unit includes; a first converting unit configured to receive first bits of input data, output one of the first bits as a first output bit, perform an XOR operation with respect to at least part of the first bits, and output an XOR operation result as a first intermediate result bit to a next converting unit in a sequence of converting unit ranging between 2 and n−1 | 09-16-2010 |
20110185000 | Method for carry estimation of reduced-width multipliers - A low-error reduced-width multiplier is provided by the present invention. The multiplier can dynamically compensate the truncation error. The compensation value is derived by the dependencies among the multiplier partial products, and thus, can be analyzed according to the multiplication type and the multiplier input statistics. | 07-28-2011 |
20140379770 | Secured Comparison Method of Two Operands and Corresponding Device - A first operation of comparison of the first initial operand with the second initial operand uses at least one comparison operator in such a way as to obtain a first final result word. A second operation of comparison of the second initial operand with the first initial operand uses the at least one comparison operator in such a way as to obtain a second final result word. Another operation checks the values of the bits of the two final result words in relation to a part at least of r combinations of reference values taken from possible combinations of values of these two final result words. These reference combinations represent a valid result of comparison of the two operands including an equality, a relationship of inferiority and a relationship of superiority between the two operands. | 12-25-2014 |